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Staging: comedi: ni_65xx.c: fix insn_bits shift calculation.
[net-next-2.6.git] / drivers / staging / comedi / drivers / ni_65xx.c
CommitLineData
5211d97c
JG		 1/*
2 comedi/drivers/ni_6514.c
3 driver for National Instruments PCI-6514
4
5 Copyright (C) 2006 Jon Grierson <jd@renko.co.uk>
6 Copyright (C) 2006 Frank Mori Hess <fmhess@users.sourceforge.net>
7
8 COMEDI - Linux Control and Measurement Device Interface
9 Copyright (C) 1999,2002,2003 David A. Schleef <ds@schleef.org>
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26/*
27Driver: ni_65xx
28Description: National Instruments 65xx static dio boards
29Author: Jon Grierson <jd@renko.co.uk>, Frank Mori Hess <fmhess@users.sourceforge.net>
30Status: testing
31Devices: [National Instruments] PCI-6509 (ni_65xx), PXI-6509, PCI-6510, PCI-6511,
32 PXI-6511, PCI-6512, PXI-6512, PCI-6513, PXI-6513, PCI-6514, PXI-6514, PCI-6515,
33 PXI-6515, PCI-6516, PCI-6517, PCI-6518, PCI-6519, PCI-6520, PCI-6521, PXI-6521,
34 PCI-6528, PXI-6528
35Updated: Wed Oct 18 08:59:11 EDT 2006
36
37Based on the PCI-6527 driver by ds.
38The interrupt subdevice (subdevice 3) is probably broken for all boards
39except maybe the 6514.
40
41*/
42
43/*
44 Manuals (available from ftp://ftp.natinst.com/support/manuals)
45
46 370106b.pdf 6514 Register Level Programmer Manual
47
48 */
49
50#define _GNU_SOURCE
51#define DEBUG 1
52#define DEBUG_FLAGS
25436dc9 53#include <linux/interrupt.h>
5211d97c
JG		 54#include "../comedidev.h"
55
56#include "mite.h"
57
58#define NI6514_DIO_SIZE 4096
59#define NI6514_MITE_SIZE 4096
60
61#define NI_65XX_MAX_NUM_PORTS 12
62static const unsigned ni_65xx_channels_per_port = 8;
63static const unsigned ni_65xx_port_offset = 0x10;
64
65static inline unsigned Port_Data(unsigned port)
66{
67 return 0x40 + port * ni_65xx_port_offset;
68}
0a85b6f0 69
5211d97c
JG		 70static inline unsigned Port_Select(unsigned port)
71{
72 return 0x41 + port * ni_65xx_port_offset;
73}
0a85b6f0 74
5211d97c
JG		 75static inline unsigned Rising_Edge_Detection_Enable(unsigned port)
76{
77 return 0x42 + port * ni_65xx_port_offset;
78}
0a85b6f0 79
5211d97c
JG		 80static inline unsigned Falling_Edge_Detection_Enable(unsigned port)
81{
82 return 0x43 + port * ni_65xx_port_offset;
83}
0a85b6f0 84
5211d97c
JG		 85static inline unsigned Filter_Enable(unsigned port)
86{
87 return 0x44 + port * ni_65xx_port_offset;
88}
89
90#define ID_Register 0x00
91
92#define Clear_Register 0x01
93#define ClrEdge 0x08
94#define ClrOverflow 0x04
95
96#define Filter_Interval 0x08
97
98#define Change_Status 0x02
99#define MasterInterruptStatus 0x04
100#define Overflow 0x02
101#define EdgeStatus 0x01
102
103#define Master_Interrupt_Control 0x03
104#define FallingEdgeIntEnable 0x10
105#define RisingEdgeIntEnable 0x08
106#define MasterInterruptEnable 0x04
107#define OverflowIntEnable 0x02
108#define EdgeIntEnable 0x01
109
0a85b6f0
MT		 110static int ni_65xx_attach(struct comedi_device *dev,
111 struct comedi_devconfig *it);
da91b269 112static int ni_65xx_detach(struct comedi_device *dev);
139dfbdf 113static struct comedi_driver driver_ni_65xx = {
68c3dbff
BP		 114 .driver_name = "ni_65xx",
115 .module = THIS_MODULE,
116 .attach = ni_65xx_attach,
117 .detach = ni_65xx_detach,
5211d97c
JG		 118};
119
125edf55
BP		 120struct ni_65xx_board {
121
5211d97c
JG		 122 int dev_id;
123 const char *name;
124 unsigned num_dio_ports;
125 unsigned num_di_ports;
126 unsigned num_do_ports;
127 unsigned invert_outputs:1;
125edf55
BP		 128};
129
130static const struct ni_65xx_board ni_65xx_boards[] = {
5211d97c 131 {
0a85b6f0
MT		 132 .dev_id = 0x7085,
133 .name = "pci-6509",
134 .num_dio_ports = 12,
135 .invert_outputs = 0},
68c3dbff 136 {
0a85b6f0
MT		 137 .dev_id = 0x1710,
138 .name = "pxi-6509",
139 .num_dio_ports = 12,
140 .invert_outputs = 0},
68c3dbff 141 {
0a85b6f0
MT		 142 .dev_id = 0x7124,
143 .name = "pci-6510",
144 .num_di_ports = 4},
68c3dbff 145 {
0a85b6f0
MT		 146 .dev_id = 0x70c3,
147 .name = "pci-6511",
148 .num_di_ports = 8},
68c3dbff 149 {
0a85b6f0
MT		 150 .dev_id = 0x70d3,
151 .name = "pxi-6511",
152 .num_di_ports = 8},
68c3dbff 153 {
0a85b6f0
MT		 154 .dev_id = 0x70cc,
155 .name = "pci-6512",
156 .num_do_ports = 8},
68c3dbff 157 {
0a85b6f0
MT		 158 .dev_id = 0x70d2,
159 .name = "pxi-6512",
160 .num_do_ports = 8},
68c3dbff 161 {
0a85b6f0
MT		 162 .dev_id = 0x70c8,
163 .name = "pci-6513",
164 .num_do_ports = 8,
165 .invert_outputs = 1},
68c3dbff 166 {
0a85b6f0
MT		 167 .dev_id = 0x70d1,
168 .name = "pxi-6513",
169 .num_do_ports = 8,
170 .invert_outputs = 1},
68c3dbff 171 {
0a85b6f0
MT		 172 .dev_id = 0x7088,
173 .name = "pci-6514",
174 .num_di_ports = 4,
175 .num_do_ports = 4,
176 .invert_outputs = 1},
68c3dbff 177 {
0a85b6f0
MT		 178 .dev_id = 0x70CD,
179 .name = "pxi-6514",
180 .num_di_ports = 4,
181 .num_do_ports = 4,
182 .invert_outputs = 1},
68c3dbff 183 {
0a85b6f0
MT		 184 .dev_id = 0x7087,
185 .name = "pci-6515",
186 .num_di_ports = 4,
187 .num_do_ports = 4,
188 .invert_outputs = 1},
68c3dbff 189 {
0a85b6f0
MT		 190 .dev_id = 0x70c9,
191 .name = "pxi-6515",
192 .num_di_ports = 4,
193 .num_do_ports = 4,
194 .invert_outputs = 1},
68c3dbff 195 {
0a85b6f0
MT		 196 .dev_id = 0x7125,
197 .name = "pci-6516",
198 .num_do_ports = 4,
199 .invert_outputs = 1},
68c3dbff 200 {
0a85b6f0
MT		 201 .dev_id = 0x7126,
202 .name = "pci-6517",
203 .num_do_ports = 4,
204 .invert_outputs = 1},
68c3dbff 205 {
0a85b6f0
MT		 206 .dev_id = 0x7127,
207 .name = "pci-6518",
208 .num_di_ports = 2,
209 .num_do_ports = 2,
210 .invert_outputs = 1},
68c3dbff 211 {
0a85b6f0
MT		 212 .dev_id = 0x7128,
213 .name = "pci-6519",
214 .num_di_ports = 2,
215 .num_do_ports = 2,
216 .invert_outputs = 1},
68c3dbff 217 {
0a85b6f0
MT		 218 .dev_id = 0x71c5,
219 .name = "pci-6520",
220 .num_di_ports = 1,
221 .num_do_ports = 1,
222 },
5211d97c 223 {
0a85b6f0
MT		 224 .dev_id = 0x718b,
225 .name = "pci-6521",
226 .num_di_ports = 1,
227 .num_do_ports = 1,
228 },
5211d97c 229 {
0a85b6f0
MT		 230 .dev_id = 0x718c,
231 .name = "pxi-6521",
232 .num_di_ports = 1,
233 .num_do_ports = 1,
234 },
5211d97c 235 {
0a85b6f0
MT		 236 .dev_id = 0x70a9,
237 .name = "pci-6528",
238 .num_di_ports = 3,
239 .num_do_ports = 3,
240 },
5211d97c 241 {
0a85b6f0
MT		 242 .dev_id = 0x7086,
243 .name = "pxi-6528",
244 .num_di_ports = 3,
245 .num_do_ports = 3,
246 },
5211d97c
JG		 247};
248
b6ac1613 249#define n_ni_65xx_boards ARRAY_SIZE(ni_65xx_boards)
0a85b6f0 250static inline const struct ni_65xx_board *board(struct comedi_device *dev)
5211d97c
JG		 251{
252 return dev->board_ptr;
253}
0a85b6f0 254
5211d97c
JG		 255static inline unsigned ni_65xx_port_by_channel(unsigned channel)
256{
257 return channel / ni_65xx_channels_per_port;
258}
0a85b6f0
MT		 259
260static inline unsigned ni_65xx_total_num_ports(const struct ni_65xx_board
261 *board)
5211d97c
JG		 262{
263 return board->num_dio_ports + board->num_di_ports + board->num_do_ports;
264}
265
266static DEFINE_PCI_DEVICE_TABLE(ni_65xx_pci_table) = {
0a85b6f0
MT		 267 {
268 PCI_VENDOR_ID_NATINST, 0x1710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
269 PCI_VENDOR_ID_NATINST, 0x7085, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
270 PCI_VENDOR_ID_NATINST, 0x7086, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
271 PCI_VENDOR_ID_NATINST, 0x7087, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
272 PCI_VENDOR_ID_NATINST, 0x7088, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
273 PCI_VENDOR_ID_NATINST, 0x70a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
274 PCI_VENDOR_ID_NATINST, 0x70c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
275 PCI_VENDOR_ID_NATINST, 0x70c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
276 PCI_VENDOR_ID_NATINST, 0x70c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
277 PCI_VENDOR_ID_NATINST, 0x70cc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
278 PCI_VENDOR_ID_NATINST, 0x70CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
279 PCI_VENDOR_ID_NATINST, 0x70d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
280 PCI_VENDOR_ID_NATINST, 0x70d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
281 PCI_VENDOR_ID_NATINST, 0x70d3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
282 PCI_VENDOR_ID_NATINST, 0x7124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
283 PCI_VENDOR_ID_NATINST, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
284 PCI_VENDOR_ID_NATINST, 0x7126, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
285 PCI_VENDOR_ID_NATINST, 0x7127, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
286 PCI_VENDOR_ID_NATINST, 0x7128, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
287 PCI_VENDOR_ID_NATINST, 0x718b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
288 PCI_VENDOR_ID_NATINST, 0x718c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
289 PCI_VENDOR_ID_NATINST, 0x71c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, {
290 0}
5211d97c
JG		 291};
292
293MODULE_DEVICE_TABLE(pci, ni_65xx_pci_table);
294
47c30a2c 295struct ni_65xx_private {
5211d97c
JG		 296 struct mite_struct *mite;
297 unsigned int filter_interval;
298 unsigned short filter_enable[NI_65XX_MAX_NUM_PORTS];
299 unsigned short output_bits[NI_65XX_MAX_NUM_PORTS];
300 unsigned short dio_direction[NI_65XX_MAX_NUM_PORTS];
47c30a2c
BP		 301};
302
0a85b6f0 303static inline struct ni_65xx_private *private(struct comedi_device *dev)
5211d97c
JG		 304{
305 return dev->private;
306}
307
6179e3e9 308struct ni_65xx_subdevice_private {
5211d97c 309 unsigned base_port;
6179e3e9
BP		 310};
311
0a85b6f0
MT		 312static inline struct ni_65xx_subdevice_private *sprivate(struct comedi_subdevice
313 *subdev)
5211d97c
JG		 314{
315 return subdev->private;
316}
0a85b6f0 317
6179e3e9 318static struct ni_65xx_subdevice_private *ni_65xx_alloc_subdevice_private(void)
5211d97c 319{
6179e3e9 320 struct ni_65xx_subdevice_private *subdev_private =
0a85b6f0 321 kzalloc(sizeof(struct ni_65xx_subdevice_private), GFP_KERNEL);
5211d97c
JG		 322 if (subdev_private == NULL)
323 return NULL;
324 return subdev_private;
325}
326
da91b269 327static int ni_65xx_find_device(struct comedi_device *dev, int bus, int slot);
5211d97c 328
0a85b6f0
MT		 329static int ni_65xx_config_filter(struct comedi_device *dev,
330 struct comedi_subdevice *s,
331 struct comedi_insn *insn, unsigned int *data)
5211d97c
JG		 332{
333 const unsigned chan = CR_CHAN(insn->chanspec);
334 const unsigned port =
0a85b6f0 335 sprivate(s)->base_port + ni_65xx_port_by_channel(chan);
5211d97c
JG		 336
337 if (data[0] != INSN_CONFIG_FILTER)
338 return -EINVAL;
339 if (data[1]) {
340 static const unsigned filter_resolution_ns = 200;
341 static const unsigned max_filter_interval = 0xfffff;
342 unsigned interval =
0a85b6f0
MT		 343 (data[1] +
344 (filter_resolution_ns / 2)) / filter_resolution_ns;
5211d97c
JG		 345 if (interval > max_filter_interval)
346 interval = max_filter_interval;
347 data[1] = interval * filter_resolution_ns;
348
349 if (interval != private(dev)->filter_interval) {
350 writeb(interval,
0a85b6f0
MT		 351 private(dev)->mite->daq_io_addr +
352 Filter_Interval);
5211d97c
JG		 353 private(dev)->filter_interval = interval;
354 }
355
356 private(dev)->filter_enable[port] |=
0a85b6f0 357 1 << (chan % ni_65xx_channels_per_port);
5211d97c
JG		 358 } else {
359 private(dev)->filter_enable[port] &=
0a85b6f0 360 ~(1 << (chan % ni_65xx_channels_per_port));
5211d97c
JG		 361 }
362
363 writeb(private(dev)->filter_enable[port],
0a85b6f0 364 private(dev)->mite->daq_io_addr + Filter_Enable(port));
5211d97c
JG		 365
366 return 2;
367}
368
0a85b6f0
MT		 369static int ni_65xx_dio_insn_config(struct comedi_device *dev,
370 struct comedi_subdevice *s,
371 struct comedi_insn *insn, unsigned int *data)
5211d97c
JG		 372{
373 unsigned port;
374
375 if (insn->n < 1)
376 return -EINVAL;
377 port = sprivate(s)->base_port +
0a85b6f0 378 ni_65xx_port_by_channel(CR_CHAN(insn->chanspec));
5211d97c
JG		 379 switch (data[0]) {
380 case INSN_CONFIG_FILTER:
381 return ni_65xx_config_filter(dev, s, insn, data);
382 break;
383 case INSN_CONFIG_DIO_OUTPUT:
384 if (s->type != COMEDI_SUBD_DIO)
385 return -EINVAL;
386 private(dev)->dio_direction[port] = COMEDI_OUTPUT;
387 writeb(0, private(dev)->mite->daq_io_addr + Port_Select(port));
388 return 1;
389 break;
390 case INSN_CONFIG_DIO_INPUT:
391 if (s->type != COMEDI_SUBD_DIO)
392 return -EINVAL;
393 private(dev)->dio_direction[port] = COMEDI_INPUT;
394 writeb(1, private(dev)->mite->daq_io_addr + Port_Select(port));
395 return 1;
396 break;
397 case INSN_CONFIG_DIO_QUERY:
398 if (s->type != COMEDI_SUBD_DIO)
399 return -EINVAL;
400 data[1] = private(dev)->dio_direction[port];
401 return insn->n;
402 break;
403 default:
404 break;
405 }
406 return -EINVAL;
407}
408
0a85b6f0
MT		 409static int ni_65xx_dio_insn_bits(struct comedi_device *dev,
410 struct comedi_subdevice *s,
411 struct comedi_insn *insn, unsigned int *data)
5211d97c
JG		 412{
413 unsigned base_bitfield_channel;
414 const unsigned max_ports_per_bitfield = 5;
415 unsigned read_bits = 0;
416 unsigned j;
417 if (insn->n != 2)
418 return -EINVAL;
419 base_bitfield_channel = CR_CHAN(insn->chanspec);
420 for (j = 0; j < max_ports_per_bitfield; ++j) {
2b49d7c4 421 const unsigned port_offset = ni_65xx_port_by_channel(base_bitfield_channel) + j;
5211d97c 422 const unsigned port =
2b49d7c4 423 sprivate(s)->base_port + port_offset;
5211d97c
JG		 424 unsigned base_port_channel;
425 unsigned port_mask, port_data, port_read_bits;
426 int bitshift;
427 if (port >= ni_65xx_total_num_ports(board(dev)))
428 break;
2b49d7c4 429 base_port_channel = port_offset * ni_65xx_channels_per_port;
5211d97c
JG		 430 port_mask = data[0];
431 port_data = data[1];
432 bitshift = base_port_channel - base_bitfield_channel;
433 if (bitshift >= 32 || bitshift <= -32)
434 break;
435 if (bitshift > 0) {
436 port_mask >>= bitshift;
437 port_data >>= bitshift;
438 } else {
439 port_mask <<= -bitshift;
440 port_data <<= -bitshift;
441 }
442 port_mask &= 0xff;
443 port_data &= 0xff;
444 if (port_mask) {
445 unsigned bits;
446 private(dev)->output_bits[port] &= ~port_mask;
447 private(dev)->output_bits[port] |=
0a85b6f0 448 port_data & port_mask;
5211d97c
JG		 449 bits = private(dev)->output_bits[port];
450 if (board(dev)->invert_outputs)
451 bits = ~bits;
452 writeb(bits,
0a85b6f0
MT		 453 private(dev)->mite->daq_io_addr +
454 Port_Data(port));
5f74ea14 455/* printk("wrote 0x%x to port %i\n", bits, port); */
5211d97c
JG		 456 }
457 port_read_bits =
0a85b6f0 458 readb(private(dev)->mite->daq_io_addr + Port_Data(port));
5f74ea14 459/* printk("read 0x%x from port %i\n", port_read_bits, port); */
5211d97c
JG		 460 if (bitshift > 0) {
461 port_read_bits <<= bitshift;
462 } else {
463 port_read_bits >>= -bitshift;
464 }
465 read_bits |= port_read_bits;
466 }
467 data[1] = read_bits;
468 return insn->n;
469}
470
70265d24 471static irqreturn_t ni_65xx_interrupt(int irq, void *d)
5211d97c 472{
71b5f4f1 473 struct comedi_device *dev = d;
34c43922 474 struct comedi_subdevice *s = dev->subdevices + 2;
5211d97c
JG		 475 unsigned int status;
476
477 status = readb(private(dev)->mite->daq_io_addr + Change_Status);
478 if ((status & MasterInterruptStatus) == 0)
479 return IRQ_NONE;
480 if ((status & EdgeStatus) == 0)
481 return IRQ_NONE;
482
483 writeb(ClrEdge | ClrOverflow,
0a85b6f0 484 private(dev)->mite->daq_io_addr + Clear_Register);
5211d97c
JG		 485
486 comedi_buf_put(s->async, 0);
487 s->async->events |= COMEDI_CB_EOS;
488 comedi_event(dev, s);
489 return IRQ_HANDLED;
490}
491
0a85b6f0
MT		 492static int ni_65xx_intr_cmdtest(struct comedi_device *dev,
493 struct comedi_subdevice *s,
494 struct comedi_cmd *cmd)
5211d97c
JG		 495{
496 int err = 0;
497 int tmp;
498
499 /* step 1: make sure trigger sources are trivially valid */
500
501 tmp = cmd->start_src;
502 cmd->start_src &= TRIG_NOW;
503 if (!cmd->start_src || tmp != cmd->start_src)
504 err++;
505
506 tmp = cmd->scan_begin_src;
507 cmd->scan_begin_src &= TRIG_OTHER;
508 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
509 err++;
510
511 tmp = cmd->convert_src;
512 cmd->convert_src &= TRIG_FOLLOW;
513 if (!cmd->convert_src || tmp != cmd->convert_src)
514 err++;
515
516 tmp = cmd->scan_end_src;
517 cmd->scan_end_src &= TRIG_COUNT;
518 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
519 err++;
520
521 tmp = cmd->stop_src;
522 cmd->stop_src &= TRIG_COUNT;
523 if (!cmd->stop_src || tmp != cmd->stop_src)
524 err++;
525
526 if (err)
527 return 1;
528
529 /* step 2: make sure trigger sources are unique and mutually compatible */
530
531 if (err)
532 return 2;
533
534 /* step 3: make sure arguments are trivially compatible */
535
536 if (cmd->start_arg != 0) {
537 cmd->start_arg = 0;
538 err++;
539 }
540 if (cmd->scan_begin_arg != 0) {
541 cmd->scan_begin_arg = 0;
542 err++;
543 }
544 if (cmd->convert_arg != 0) {
545 cmd->convert_arg = 0;
546 err++;
547 }
548
549 if (cmd->scan_end_arg != 1) {
550 cmd->scan_end_arg = 1;
551 err++;
552 }
553 if (cmd->stop_arg != 0) {
554 cmd->stop_arg = 0;
555 err++;
556 }
557
558 if (err)
559 return 3;
560
561 /* step 4: fix up any arguments */
562
563 if (err)
564 return 4;
565
566 return 0;
567}
568
0a85b6f0
MT		 569static int ni_65xx_intr_cmd(struct comedi_device *dev,
570 struct comedi_subdevice *s)
5211d97c 571{
2696fb57 572 /* struct comedi_cmd *cmd = &s->async->cmd; */
5211d97c
JG		 573
574 writeb(ClrEdge | ClrOverflow,
0a85b6f0 575 private(dev)->mite->daq_io_addr + Clear_Register);
5211d97c 576 writeb(FallingEdgeIntEnable | RisingEdgeIntEnable |
0a85b6f0
MT		 577 MasterInterruptEnable | EdgeIntEnable,
578 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
5211d97c
JG		 579
580 return 0;
581}
582
0a85b6f0
MT		 583static int ni_65xx_intr_cancel(struct comedi_device *dev,
584 struct comedi_subdevice *s)
5211d97c
JG		 585{
586 writeb(0x00,
0a85b6f0 587 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
5211d97c
JG		 588
589 return 0;
590}
591
0a85b6f0
MT		 592static int ni_65xx_intr_insn_bits(struct comedi_device *dev,
593 struct comedi_subdevice *s,
594 struct comedi_insn *insn, unsigned int *data)
5211d97c
JG		 595{
596 if (insn->n < 1)
597 return -EINVAL;
598
599 data[1] = 0;
600 return 2;
601}
602
0a85b6f0
MT		 603static int ni_65xx_intr_insn_config(struct comedi_device *dev,
604 struct comedi_subdevice *s,
605 struct comedi_insn *insn,
606 unsigned int *data)
5211d97c
JG		 607{
608 if (insn->n < 1)
609 return -EINVAL;
610 if (data[0] != INSN_CONFIG_CHANGE_NOTIFY)
611 return -EINVAL;
612
613 writeb(data[1],
0a85b6f0
MT		 614 private(dev)->mite->daq_io_addr +
615 Rising_Edge_Detection_Enable(0));
5211d97c 616 writeb(data[1] >> 8,
0a85b6f0
MT		 617 private(dev)->mite->daq_io_addr +
618 Rising_Edge_Detection_Enable(0x10));
5211d97c 619 writeb(data[1] >> 16,
0a85b6f0
MT		 620 private(dev)->mite->daq_io_addr +
621 Rising_Edge_Detection_Enable(0x20));
5211d97c 622 writeb(data[1] >> 24,
0a85b6f0
MT		 623 private(dev)->mite->daq_io_addr +
624 Rising_Edge_Detection_Enable(0x30));
5211d97c
JG		 625
626 writeb(data[2],
0a85b6f0
MT		 627 private(dev)->mite->daq_io_addr +
628 Falling_Edge_Detection_Enable(0));
5211d97c 629 writeb(data[2] >> 8,
0a85b6f0
MT		 630 private(dev)->mite->daq_io_addr +
631 Falling_Edge_Detection_Enable(0x10));
5211d97c 632 writeb(data[2] >> 16,
0a85b6f0
MT		 633 private(dev)->mite->daq_io_addr +
634 Falling_Edge_Detection_Enable(0x20));
5211d97c 635 writeb(data[2] >> 24,
0a85b6f0
MT		 636 private(dev)->mite->daq_io_addr +
637 Falling_Edge_Detection_Enable(0x30));
5211d97c
JG		 638
639 return 2;
640}
641
0a85b6f0
MT		 642static int ni_65xx_attach(struct comedi_device *dev,
643 struct comedi_devconfig *it)
5211d97c 644{
34c43922 645 struct comedi_subdevice *s;
5211d97c
JG		 646 unsigned i;
647 int ret;
648
649 printk("comedi%d: ni_65xx:", dev->minor);
650
c3744138
BP		 651 ret = alloc_private(dev, sizeof(struct ni_65xx_private));
652 if (ret < 0)
5211d97c
JG		 653 return ret;
654
655 ret = ni_65xx_find_device(dev, it->options[0], it->options[1]);
656 if (ret < 0)
657 return ret;
658
659 ret = mite_setup(private(dev)->mite);
660 if (ret < 0) {
661 printk("error setting up mite\n");
662 return ret;
663 }
664
665 dev->board_name = board(dev)->name;
666 dev->irq = mite_irq(private(dev)->mite);
667 printk(" %s", dev->board_name);
668
669 printk(" ID=0x%02x",
0a85b6f0 670 readb(private(dev)->mite->daq_io_addr + ID_Register));
5211d97c 671
c3744138
BP		 672 ret = alloc_subdevices(dev, 4);
673 if (ret < 0)
5211d97c
JG		 674 return ret;
675
676 s = dev->subdevices + 0;
677 if (board(dev)->num_di_ports) {
678 s->type = COMEDI_SUBD_DI;
679 s->subdev_flags = SDF_READABLE;
680 s->n_chan =
0a85b6f0 681 board(dev)->num_di_ports * ni_65xx_channels_per_port;
5211d97c
JG		 682 s->range_table = &range_digital;
683 s->maxdata = 1;
684 s->insn_config = ni_65xx_dio_insn_config;
685 s->insn_bits = ni_65xx_dio_insn_bits;
686 s->private = ni_65xx_alloc_subdevice_private();
687 if (s->private == NULL)
688 return -ENOMEM;
689 sprivate(s)->base_port = 0;
690 } else {
691 s->type = COMEDI_SUBD_UNUSED;
692 }
693
694 s = dev->subdevices + 1;
695 if (board(dev)->num_do_ports) {
696 s->type = COMEDI_SUBD_DO;
697 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
698 s->n_chan =
0a85b6f0 699 board(dev)->num_do_ports * ni_65xx_channels_per_port;
5211d97c
JG		 700 s->range_table = &range_digital;
701 s->maxdata = 1;
702 s->insn_bits = ni_65xx_dio_insn_bits;
703 s->private = ni_65xx_alloc_subdevice_private();
704 if (s->private == NULL)
705 return -ENOMEM;
706 sprivate(s)->base_port = board(dev)->num_di_ports;
707 } else {
708 s->type = COMEDI_SUBD_UNUSED;
709 }
710
711 s = dev->subdevices + 2;
712 if (board(dev)->num_dio_ports) {
713 s->type = COMEDI_SUBD_DIO;
714 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
715 s->n_chan =
0a85b6f0 716 board(dev)->num_dio_ports * ni_65xx_channels_per_port;
5211d97c
JG		 717 s->range_table = &range_digital;
718 s->maxdata = 1;
719 s->insn_config = ni_65xx_dio_insn_config;
720 s->insn_bits = ni_65xx_dio_insn_bits;
721 s->private = ni_65xx_alloc_subdevice_private();
722 if (s->private == NULL)
723 return -ENOMEM;
724 sprivate(s)->base_port = 0;
725 for (i = 0; i < board(dev)->num_dio_ports; ++i) {
2696fb57 726 /* configure all ports for input */
5211d97c 727 writeb(0x1,
0a85b6f0
MT		 728 private(dev)->mite->daq_io_addr +
729 Port_Select(i));
5211d97c
JG		 730 }
731 } else {
732 s->type = COMEDI_SUBD_UNUSED;
733 }
734
735 s = dev->subdevices + 3;
736 dev->read_subdev = s;
737 s->type = COMEDI_SUBD_DI;
738 s->subdev_flags = SDF_READABLE | SDF_CMD_READ;
739 s->n_chan = 1;
740 s->range_table = &range_unknown;
741 s->maxdata = 1;
742 s->do_cmdtest = ni_65xx_intr_cmdtest;
743 s->do_cmd = ni_65xx_intr_cmd;
744 s->cancel = ni_65xx_intr_cancel;
745 s->insn_bits = ni_65xx_intr_insn_bits;
746 s->insn_config = ni_65xx_intr_insn_config;
747
748 for (i = 0; i < ni_65xx_total_num_ports(board(dev)); ++i) {
749 writeb(0x00,
0a85b6f0 750 private(dev)->mite->daq_io_addr + Filter_Enable(i));
5211d97c
JG		 751 if (board(dev)->invert_outputs)
752 writeb(0x01,
0a85b6f0 753 private(dev)->mite->daq_io_addr + Port_Data(i));
5211d97c
JG		 754 else
755 writeb(0x00,
0a85b6f0 756 private(dev)->mite->daq_io_addr + Port_Data(i));
5211d97c
JG		 757 }
758 writeb(ClrEdge | ClrOverflow,
0a85b6f0 759 private(dev)->mite->daq_io_addr + Clear_Register);
5211d97c 760 writeb(0x00,
0a85b6f0 761 private(dev)->mite->daq_io_addr + Master_Interrupt_Control);
5211d97c
JG		 762
763 /* Set filter interval to 0 (32bit reg) */
764 writeb(0x00000000, private(dev)->mite->daq_io_addr + Filter_Interval);
765
5f74ea14
GKH		 766 ret = request_irq(dev->irq, ni_65xx_interrupt, IRQF_SHARED,
767 "ni_65xx", dev);
5211d97c
JG		 768 if (ret < 0) {
769 dev->irq = 0;
770 printk(" irq not available");
771 }
772
773 printk("\n");
774
775 return 0;
776}
777
da91b269 778static int ni_65xx_detach(struct comedi_device *dev)
5211d97c
JG		 779{
780 if (private(dev) && private(dev)->mite
0a85b6f0 781 && private(dev)->mite->daq_io_addr) {
5211d97c 782 writeb(0x00,
0a85b6f0
MT		 783 private(dev)->mite->daq_io_addr +
784 Master_Interrupt_Control);
5211d97c
JG		 785 }
786
787 if (dev->irq) {
5f74ea14 788 free_irq(dev->irq, dev);
5211d97c
JG		 789 }
790
791 if (private(dev)) {
792 unsigned i;
793 for (i = 0; i < dev->n_subdevices; ++i) {
794 if (dev->subdevices[i].private) {
795 kfree(dev->subdevices[i].private);
796 dev->subdevices[i].private = NULL;
797 }
798 }
799 if (private(dev)->mite) {
800 mite_unsetup(private(dev)->mite);
801 }
802 }
803 return 0;
804}
805
da91b269 806static int ni_65xx_find_device(struct comedi_device *dev, int bus, int slot)
5211d97c
JG		 807{
808 struct mite_struct *mite;
809 int i;
810
811 for (mite = mite_devices; mite; mite = mite->next) {
812 if (mite->used)
813 continue;
814 if (bus || slot) {
815 if (bus != mite->pcidev->bus->number ||
0a85b6f0 816 slot != PCI_SLOT(mite->pcidev->devfn))
5211d97c
JG		 817 continue;
818 }
819 for (i = 0; i < n_ni_65xx_boards; i++) {
820 if (mite_device_id(mite) == ni_65xx_boards[i].dev_id) {
821 dev->board_ptr = ni_65xx_boards + i;
822 private(dev)->mite = mite;
823 return 0;
824 }
825 }
826 }
827 printk("no device found\n");
828 mite_list_devices();
829 return -EIO;
830}
831
832COMEDI_PCI_INITCLEANUP(driver_ni_65xx, ni_65xx_pci_table);
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