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Staging: brcm80211: s/int32/s32/
[net-next-2.6.git] / drivers / staging / brcm80211 / brcmfmac / dhd_sdio.c
CommitLineData
cf2b4488
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <typedefs.h>
18#include <osl.h>
19#include <bcmsdh.h>
20
21#ifdef BCMEMBEDIMAGE
22#include BCMEMBEDIMAGE
23#endif /* BCMEMBEDIMAGE */
24
25#include <bcmdefs.h>
26#include <bcmutils.h>
27#include <bcmendian.h>
28#include <bcmdevs.h>
29
30#include <siutils.h>
31#include <hndpmu.h>
32#include <hndsoc.h>
33#ifdef DHD_DEBUG
34#include <hndrte_armtrap.h>
35#include <hndrte_cons.h>
36#endif /* DHD_DEBUG */
37#include <sbchipc.h>
38#include <sbhnddma.h>
39
40#include <sdio.h>
41#include <sbsdio.h>
42#include <sbsdpcmdev.h>
43#include <bcmsdpcm.h>
44
45#include <proto/ethernet.h>
46#include <proto/802.1d.h>
47#include <proto/802.11.h>
48
49#include <dngl_stats.h>
50#include <dhd.h>
51#include <dhd_bus.h>
52#include <dhd_proto.h>
53#include <dhd_dbg.h>
54#include <dhdioctl.h>
55#include <sdiovar.h>
56#include <siutils_priv.h>
57
58#ifndef DHDSDIO_MEM_DUMP_FNAME
59#define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
60#endif
61
62#define QLEN 256 /* bulk rx and tx queue lengths */
63#define FCHI (QLEN - 10)
64#define FCLOW (FCHI / 2)
65#define PRIOMASK 7
66
67#define TXRETRIES 2 /* # of retries for tx frames */
68
69#if defined(CONFIG_MACH_SANDGATE2G)
70#define DHD_RXBOUND 250 /* Default for max rx frames in
71 one scheduling */
72#else
73#define DHD_RXBOUND 50 /* Default for max rx frames in
74 one scheduling */
75#endif /* defined(CONFIG_MACH_SANDGATE2G) */
76
77#define DHD_TXBOUND 20 /* Default for max tx frames in
78 one scheduling */
79
80#define DHD_TXMINMAX 1 /* Max tx frames if rx still pending */
81
82#define MEMBLOCK 2048 /* Block size used for downloading
83 of dongle image */
84#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
85 biggest possible glom */
86
87/* Packet alignment for most efficient SDIO (can change based on platform) */
88#ifndef DHD_SDALIGN
89#define DHD_SDALIGN 32
90#endif
91#if !ISPOWEROF2(DHD_SDALIGN)
92#error DHD_SDALIGN is not a power of 2!
93#endif
94
95#ifndef DHD_FIRSTREAD
96#define DHD_FIRSTREAD 32
97#endif
98#if !ISPOWEROF2(DHD_FIRSTREAD)
99#error DHD_FIRSTREAD is not a power of 2!
100#endif
101
102/* Total length of frame header for dongle protocol */
103#define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
104#ifdef SDTEST
105#define SDPCM_RESERVE (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN)
106#else
107#define SDPCM_RESERVE (SDPCM_HDRLEN + DHD_SDALIGN)
108#endif
109
110/* Space for header read, limit for data packets */
111#ifndef MAX_HDR_READ
112#define MAX_HDR_READ 32
113#endif
114#if !ISPOWEROF2(MAX_HDR_READ)
115#error MAX_HDR_READ is not a power of 2!
116#endif
117
118#define MAX_RX_DATASZ 2048
119
120/* Maximum milliseconds to wait for F2 to come up */
121#define DHD_WAIT_F2RDY 3000
122
123/* Bump up limit on waiting for HT to account for first startup;
124 * if the image is doing a CRC calculation before programming the PMU
125 * for HT availability, it could take a couple hundred ms more, so
126 * max out at a 1 second (1000000us).
127 */
128#if (PMU_MAX_TRANSITION_DLY <= 1000000)
129#undef PMU_MAX_TRANSITION_DLY
130#define PMU_MAX_TRANSITION_DLY 1000000
131#endif
132
133/* Value for ChipClockCSR during initial setup */
134#define DHD_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
135 SBSDIO_ALP_AVAIL_REQ)
136#define DHD_INIT_CLKCTL2 (SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP)
137
138/* Flags for SDH calls */
139#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
140
141/* Packet free applicable unconditionally for sdio and sdspi. Conditional if
142 * bufpool was present for gspi bus.
143 */
144#define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
145 PKTFREE(bus->dhd->osh, pkt, FALSE);
146DHD_SPINWAIT_SLEEP_INIT(sdioh_spinwait_sleep);
147extern int dhdcdc_set_ioctl(dhd_pub_t *dhd, int ifidx, uint cmd, void *buf,
148 uint len);
149
150#ifdef DHD_DEBUG
151/* Device console log buffer state */
152typedef struct dhd_console {
153 uint count; /* Poll interval msec counter */
154 uint log_addr; /* Log struct address (fixed) */
155 hndrte_log_t log; /* Log struct (host copy) */
156 uint bufsize; /* Size of log buffer */
3fd79f7c 157 u8 *buf; /* Log buffer (host copy) */
cf2b4488
HP		 158 uint last; /* Last buffer read index */
159} dhd_console_t;
160#endif /* DHD_DEBUG */
161
162/* Private data for SDIO bus interaction */
163typedef struct dhd_bus {
164 dhd_pub_t *dhd;
165
166 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
167 si_t *sih; /* Handle for SI calls */
168 char *vars; /* Variables (from CIS and/or other) */
169 uint varsz; /* Size of variables buffer */
66cbd3ab 170 u32 sbaddr; /* Current SB window pointer (-1, invalid) */
cf2b4488
HP		 171
172 sdpcmd_regs_t *regs; /* Registers for SDIO core */
173 uint sdpcmrev; /* SDIO core revision */
174 uint armrev; /* CPU core revision */
175 uint ramrev; /* SOCRAM core revision */
66cbd3ab
GKH		 176 u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
177 u32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
cf2b4488 178
66cbd3ab
GKH		 179 u32 bus; /* gSPI or SDIO bus */
180 u32 hostintmask; /* Copy of Host Interrupt Mask */
181 u32 intstatus; /* Intstatus bits (events) pending */
cf2b4488
HP		 182 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
183 bool fcstate; /* State of dongle flow-control */
184
7d4df48e 185 u16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
cf2b4488
HP		 186 char *fw_path; /* module_param: path to firmware image */
187 char *nv_path; /* module_param: path to nvram vars file */
188 const char *nvram_params; /* user specified nvram params. */
189
190 uint blocksize; /* Block size of SDIO transfers */
191 uint roundup; /* Max roundup limit */
192
193 struct pktq txq; /* Queue length used for flow-control */
3fd79f7c
GKH		 194 u8 flowcontrol; /* per prio flow control bitmask */
195 u8 tx_seq; /* Transmit sequence number (next) */
196 u8 tx_max; /* Maximum transmit sequence allowed */
cf2b4488 197
3fd79f7c
GKH		 198 u8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
199 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
7d4df48e 200 u16 nextlen; /* Next Read Len from last header */
3fd79f7c 201 u8 rx_seq; /* Receive sequence number (expected) */
cf2b4488
HP		 202 bool rxskip; /* Skip receive (awaiting NAK ACK) */
203
204 void *glomd; /* Packet containing glomming descriptor */
205 void *glom; /* Packet chain for glommed superframe */
206 uint glomerr; /* Glom packet read errors */
207
3fd79f7c 208 u8 *rxbuf; /* Buffer for receiving control packets */
cf2b4488 209 uint rxblen; /* Allocated length of rxbuf */
3fd79f7c
GKH		 210 u8 *rxctl; /* Aligned pointer into rxbuf */
211 u8 *databuf; /* Buffer for receiving big glom packet */
212 u8 *dataptr; /* Aligned pointer into databuf */
cf2b4488
HP		 213 uint rxlen; /* Length of valid data in buffer */
214
3fd79f7c 215 u8 sdpcm_ver; /* Bus protocol reported by dongle */
cf2b4488
HP		 216
217 bool intr; /* Use interrupts */
218 bool poll; /* Use polling */
219 bool ipend; /* Device interrupt is pending */
220 bool intdis; /* Interrupts disabled by isr */
221 uint intrcount; /* Count of device interrupt callbacks */
222 uint lastintrs; /* Count as of last watchdog timer */
223 uint spurious; /* Count of spurious interrupts */
224 uint pollrate; /* Ticks between device polls */
225 uint polltick; /* Tick counter */
226 uint pollcnt; /* Count of active polls */
227
228#ifdef DHD_DEBUG
229 dhd_console_t console; /* Console output polling support */
230 uint console_addr; /* Console address from shared struct */
231#endif /* DHD_DEBUG */
232
233 uint regfails; /* Count of R_REG/W_REG failures */
234
235 uint clkstate; /* State of sd and backplane clock(s) */
236 bool activity; /* Activity flag for clock down */
3e26416e
GKH		 237 s32 idletime; /* Control for activity timeout */
238 s32 idlecount; /* Activity timeout counter */
239 s32 idleclock; /* How to set bus driver when idle */
240 s32 sd_divisor; /* Speed control to bus driver */
241 s32 sd_mode; /* Mode control to bus driver */
242 s32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
cf2b4488
HP		 243 bool use_rxchain; /* If dhd should use PKT chains */
244 bool sleeping; /* Is SDIO bus sleeping? */
245 bool rxflow_mode; /* Rx flow control mode */
246 bool rxflow; /* Is rx flow control on */
247 uint prev_rxlim_hit; /* Is prev rx limit exceeded
248 (per dpc schedule) */
249 bool alp_only; /* Don't use HT clock (ALP only) */
250/* Field to decide if rx of control frames happen in rxbuf or lb-pool */
251 bool usebufpool;
252
253#ifdef SDTEST
254 /* external loopback */
255 bool ext_loop;
3fd79f7c 256 u8 loopid;
cf2b4488
HP		 257
258 /* pktgen configuration */
259 uint pktgen_freq; /* Ticks between bursts */
260 uint pktgen_count; /* Packets to send each burst */
261 uint pktgen_print; /* Bursts between count displays */
262 uint pktgen_total; /* Stop after this many */
263 uint pktgen_minlen; /* Minimum packet data len */
264 uint pktgen_maxlen; /* Maximum packet data len */
265 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
266 uint pktgen_stop; /* Number of tx failures causing stop */
267
268 /* active pktgen fields */
269 uint pktgen_tick; /* Tick counter for bursts */
270 uint pktgen_ptick; /* Burst counter for printing */
271 uint pktgen_sent; /* Number of test packets generated */
272 uint pktgen_rcvd; /* Number of test packets received */
273 uint pktgen_fail; /* Number of failed send attempts */
7d4df48e 274 u16 pktgen_len; /* Length of next packet to send */
cf2b4488
HP		 275#endif /* SDTEST */
276
277 /* Some additional counters */
278 uint tx_sderrs; /* Count of tx attempts with sd errors */
279 uint fcqueued; /* Tx packets that got queued */
280 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
281 uint rx_toolong; /* Receive frames too long to receive */
282 uint rxc_errors; /* SDIO errors when reading control frames */
283 uint rx_hdrfail; /* SDIO errors on header reads */
284 uint rx_badhdr; /* Bad received headers (roosync?) */
285 uint rx_badseq; /* Mismatched rx sequence number */
286 uint fc_rcvd; /* Number of flow-control events received */
287 uint fc_xoff; /* Number which turned on flow-control */
288 uint fc_xon; /* Number which turned off flow-control */
289 uint rxglomfail; /* Failed deglom attempts */
290 uint rxglomframes; /* Number of glom frames (superframes) */
291 uint rxglompkts; /* Number of packets from glom frames */
292 uint f2rxhdrs; /* Number of header reads */
293 uint f2rxdata; /* Number of frame data reads */
294 uint f2txdata; /* Number of f2 frame writes */
295 uint f1regdata; /* Number of f1 register accesses */
296
3fd79f7c 297 u8 *ctrl_frame_buf;
66cbd3ab 298 u32 ctrl_frame_len;
cf2b4488
HP		 299 bool ctrl_frame_stat;
300} dhd_bus_t;
301
302/* clkstate */
303#define CLK_NONE 0
304#define CLK_SDONLY 1
305#define CLK_PENDING 2 /* Not used yet */
306#define CLK_AVAIL 3
307
308#define DHD_NOPMU(dhd) (FALSE)
309
310#ifdef DHD_DEBUG
311static int qcount[NUMPRIO];
312static int tx_packets[NUMPRIO];
313#endif /* DHD_DEBUG */
314
315/* Deferred transmit */
316const uint dhd_deferred_tx = 1;
317
318extern uint dhd_watchdog_ms;
319extern void dhd_os_wd_timer(void *bus, uint wdtick);
320
321/* Tx/Rx bounds */
322uint dhd_txbound;
323uint dhd_rxbound;
324uint dhd_txminmax;
325
326/* override the RAM size if possible */
327#define DONGLE_MIN_MEMSIZE (128 * 1024)
328int dhd_dongle_memsize;
329
330static bool dhd_doflow;
331static bool dhd_alignctl;
332
333static bool sd1idle;
334
335static bool retrydata;
336#define RETRYCHAN(chan) (((chan) == SDPCM_EVENT_CHANNEL) || retrydata)
337
338static const uint watermark = 8;
339static const uint firstread = DHD_FIRSTREAD;
340
341#define HDATLEN (firstread - (SDPCM_HDRLEN))
342
343/* Retry count for register access failures */
344static const uint retry_limit = 2;
345
346/* Force even SD lengths (some host controllers mess up on odd bytes) */
347static bool forcealign;
348
349#define ALIGNMENT 4
350
351#if defined(OOB_INTR_ONLY) && defined(HW_OOB)
352extern void bcmsdh_enable_hw_oob_intr(void *sdh, bool enable);
353#endif
354
355#if defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD)
356#error OOB_INTR_ONLY is NOT working with SDIO_ISR_THREAD
357#endif /* defined(OOB_INTR_ONLY) && defined(SDIO_ISR_THREAD) */
358#define PKTALIGN(osh, p, len, align) \
359 do { \
360 uint datalign; \
361 datalign = (uintptr)PKTDATA((p)); \
362 datalign = ROUNDUP(datalign, (align)) - datalign; \
363 ASSERT(datalign < (align)); \
364 ASSERT(PKTLEN((p)) >= ((len) + datalign)); \
365 if (datalign) \
366 PKTPULL((p), datalign); \
367 PKTSETLEN((p), (len)); \
368 } while (0)
369
370/* Limit on rounding up frames */
371static const uint max_roundup = 512;
372
373/* Try doing readahead */
374static bool dhd_readahead;
375
376/* To check if there's window offered */
377#define DATAOK(bus) \
3fd79f7c
GKH		 378 (((u8)(bus->tx_max - bus->tx_seq) != 0) && \
379 (((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0))
cf2b4488
HP		 380
381/* Macros to get register read/write status */
382/* NOTE: these assume a local dhdsdio_bus_t *bus! */
383#define R_SDREG(regvar, regaddr, retryvar) \
384do { \
385 retryvar = 0; \
386 do { \
387 regvar = R_REG(bus->dhd->osh, regaddr); \
388 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
389 if (retryvar) { \
390 bus->regfails += (retryvar-1); \
391 if (retryvar > retry_limit) { \
392 DHD_ERROR(("%s: FAILED" #regvar "READ, LINE %d\n", \
393 __func__, __LINE__)); \
394 regvar = 0; \
395 } \
396 } \
397} while (0)
398
399#define W_SDREG(regval, regaddr, retryvar) \
400do { \
401 retryvar = 0; \
402 do { \
403 W_REG(bus->dhd->osh, regaddr, regval); \
404 } while (bcmsdh_regfail(bus->sdh) && (++retryvar <= retry_limit)); \
405 if (retryvar) { \
406 bus->regfails += (retryvar-1); \
407 if (retryvar > retry_limit) \
408 DHD_ERROR(("%s: FAILED REGISTER WRITE, LINE %d\n", \
409 __func__, __LINE__)); \
410 } \
411} while (0)
412
413#define DHD_BUS SDIO_BUS
414
415#define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
416
417#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
418
419#define GSPI_PR55150_BAILOUT
420
421#ifdef SDTEST
422static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
423static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
424#endif
425
426#ifdef DHD_DEBUG
3fd79f7c 427static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size);
cf2b4488
HP		 428static int dhdsdio_mem_dump(dhd_bus_t *bus);
429#endif /* DHD_DEBUG */
430static int dhdsdio_download_state(dhd_bus_t *bus, bool enter);
431
432static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh);
433static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh);
434static void dhdsdio_disconnect(void *ptr);
7d4df48e 435static bool dhdsdio_chipmatch(u16 chipid);
cf2b4488 436static bool dhdsdio_probe_attach(dhd_bus_t *bus, osl_t *osh, void *sdh,
7d4df48e 437 void *regsva, u16 devid);
cf2b4488
HP		 438static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh);
439static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh);
440static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t * osh);
441
442static uint process_nvram_vars(char *varbuf, uint len);
443
444static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
66cbd3ab 445static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
3fd79f7c 446 uint flags, u8 *buf, uint nbytes, void *pkt,
cf2b4488 447 bcmsdh_cmplt_fn_t complete, void *handle);
66cbd3ab 448static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
3fd79f7c 449 uint flags, u8 *buf, uint nbytes, void *pkt,
cf2b4488
HP		 450 bcmsdh_cmplt_fn_t complete, void *handle);
451
452static bool dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh,
453 void *sdh);
454static int _dhdsdio_download_firmware(struct dhd_bus *bus);
455
456static int dhdsdio_download_code_file(struct dhd_bus *bus, char *image_path);
457static int dhdsdio_download_nvram(struct dhd_bus *bus);
458#ifdef BCMEMBEDIMAGE
459static int dhdsdio_download_code_array(struct dhd_bus *bus);
460#endif
461
462static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
463{
3e26416e 464 s32 min_size = DONGLE_MIN_MEMSIZE;
cf2b4488
HP		 465 /* Restrict the memsize to user specified limit */
466 DHD_ERROR(("user: Restrict the dongle ram size to %d, min %d\n",
467 dhd_dongle_memsize, min_size));
468 if ((dhd_dongle_memsize > min_size) &&
3e26416e 469 (dhd_dongle_memsize < (s32) bus->orig_ramsize))
cf2b4488
HP		 470 bus->ramsize = dhd_dongle_memsize;
471}
472
66cbd3ab 473static int dhdsdio_set_siaddr_window(dhd_bus_t *bus, u32 address)
cf2b4488
HP		 474{
475 int err = 0;
476 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRLOW,
477 (address >> 8) & SBSDIO_SBADDRLOW_MASK, &err);
478 if (!err)
479 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRMID,
480 (address >> 16) & SBSDIO_SBADDRMID_MASK, &err);
481 if (!err)
482 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SBADDRHIGH,
483 (address >> 24) & SBSDIO_SBADDRHIGH_MASK,
484 &err);
485 return err;
486}
487
488/* Turn backplane clock on or off */
489static int dhdsdio_htclk(dhd_bus_t *bus, bool on, bool pendok)
490{
491 int err;
3fd79f7c 492 u8 clkctl, clkreq, devctl;
cf2b4488
HP		 493 bcmsdh_info_t *sdh;
494
495 DHD_TRACE(("%s: Enter\n", __func__));
496
497#if defined(OOB_INTR_ONLY)
498 pendok = FALSE;
499#endif
500 clkctl = 0;
501 sdh = bus->sdh;
502
503 if (on) {
504 /* Request HT Avail */
505 clkreq =
506 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
507
508 if ((bus->sih->chip == BCM4329_CHIP_ID)
509 && (bus->sih->chiprev == 0))
510 clkreq |= SBSDIO_FORCE_ALP;
511
512 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
513 clkreq, &err);
514 if (err) {
515 DHD_ERROR(("%s: HT Avail request error: %d\n",
516 __func__, err));
517 return BCME_ERROR;
518 }
519
520 if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
521 && (bus->sih->buscorerev == 9))) {
66cbd3ab 522 u32 dummy, retries;
cf2b4488
HP		 523 R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
524 }
525
526 /* Check current status */
527 clkctl =
528 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
529 &err);
530 if (err) {
531 DHD_ERROR(("%s: HT Avail read error: %d\n",
532 __func__, err));
533 return BCME_ERROR;
534 }
535
536 /* Go to pending and await interrupt if appropriate */
537 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
538 /* Allow only clock-available interrupt */
539 devctl =
540 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
541 &err);
542 if (err) {
543 DHD_ERROR(("%s: Devctl error setting CA: %d\n",
544 __func__, err));
545 return BCME_ERROR;
546 }
547
548 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
549 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
550 devctl, &err);
551 DHD_INFO(("CLKCTL: set PENDING\n"));
552 bus->clkstate = CLK_PENDING;
553
554 return BCME_OK;
555 } else if (bus->clkstate == CLK_PENDING) {
556 /* Cancel CA-only interrupt filter */
557 devctl =
558 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
559 &err);
560 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
561 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
562 devctl, &err);
563 }
564
565 /* Otherwise, wait here (polling) for HT Avail */
566 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
567 SPINWAIT_SLEEP(sdioh_spinwait_sleep,
568 ((clkctl =
569 bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
570 SBSDIO_FUNC1_CHIPCLKCSR,
571 &err)),
572 !SBSDIO_CLKAV(clkctl, bus->alp_only)),
573 PMU_MAX_TRANSITION_DLY);
574 }
575 if (err) {
576 DHD_ERROR(("%s: HT Avail request error: %d\n",
577 __func__, err));
578 return BCME_ERROR;
579 }
580 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
581 DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
582 __func__, PMU_MAX_TRANSITION_DLY, clkctl));
583 return BCME_ERROR;
584 }
585
586 /* Mark clock available */
587 bus->clkstate = CLK_AVAIL;
588 DHD_INFO(("CLKCTL: turned ON\n"));
589
590#if defined(DHD_DEBUG)
591 if (bus->alp_only == TRUE) {
592#if !defined(BCMLXSDMMC)
593 if (!SBSDIO_ALPONLY(clkctl)) {
594 DHD_ERROR(("%s: HT Clock, when ALP Only\n",
595 __func__));
596 }
597#endif /* !defined(BCMLXSDMMC) */
598 } else {
599 if (SBSDIO_ALPONLY(clkctl)) {
600 DHD_ERROR(("%s: HT Clock should be on.\n",
601 __func__));
602 }
603 }
604#endif /* defined (DHD_DEBUG) */
605
606 bus->activity = TRUE;
607 } else {
608 clkreq = 0;
609
610 if (bus->clkstate == CLK_PENDING) {
611 /* Cancel CA-only interrupt filter */
612 devctl =
613 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
614 &err);
615 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
616 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
617 devctl, &err);
618 }
619
620 bus->clkstate = CLK_SDONLY;
621 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
622 clkreq, &err);
623 DHD_INFO(("CLKCTL: turned OFF\n"));
624 if (err) {
625 DHD_ERROR(("%s: Failed access turning clock off: %d\n",
626 __func__, err));
627 return BCME_ERROR;
628 }
629 }
630 return BCME_OK;
631}
632
633/* Change idle/active SD state */
634static int dhdsdio_sdclk(dhd_bus_t *bus, bool on)
635{
636 int err;
3e26416e 637 s32 iovalue;
cf2b4488
HP		 638
639 DHD_TRACE(("%s: Enter\n", __func__));
640
641 if (on) {
642 if (bus->idleclock == DHD_IDLE_STOP) {
643 /* Turn on clock and restore mode */
644 iovalue = 1;
645 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
646 &iovalue, sizeof(iovalue), TRUE);
647 if (err) {
648 DHD_ERROR(("%s: error enabling sd_clock: %d\n",
649 __func__, err));
650 return BCME_ERROR;
651 }
652
653 iovalue = bus->sd_mode;
654 err = bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
655 &iovalue, sizeof(iovalue), TRUE);
656 if (err) {
657 DHD_ERROR(("%s: error changing sd_mode: %d\n",
658 __func__, err));
659 return BCME_ERROR;
660 }
661 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
662 /* Restore clock speed */
663 iovalue = bus->sd_divisor;
664 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
665 &iovalue, sizeof(iovalue), TRUE);
666 if (err) {
667 DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
668 __func__, err));
669 return BCME_ERROR;
670 }
671 }
672 bus->clkstate = CLK_SDONLY;
673 } else {
674 /* Stop or slow the SD clock itself */
675 if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
676 DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
677 __func__, bus->sd_divisor, bus->sd_mode));
678 return BCME_ERROR;
679 }
680 if (bus->idleclock == DHD_IDLE_STOP) {
681 if (sd1idle) {
682 /* Change to SD1 mode and turn off clock */
683 iovalue = 1;
684 err =
685 bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL,
686 0, &iovalue,
687 sizeof(iovalue), TRUE);
688 if (err) {
689 DHD_ERROR(("%s: error changing sd_clock: %d\n",
690 __func__, err));
691 return BCME_ERROR;
692 }
693 }
694
695 iovalue = 0;
696 err = bcmsdh_iovar_op(bus->sdh, "sd_clock", NULL, 0,
697 &iovalue, sizeof(iovalue), TRUE);
698 if (err) {
699 DHD_ERROR(("%s: error disabling sd_clock: %d\n",
700 __func__, err));
701 return BCME_ERROR;
702 }
703 } else if (bus->idleclock != DHD_IDLE_ACTIVE) {
704 /* Set divisor to idle value */
705 iovalue = bus->idleclock;
706 err = bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
707 &iovalue, sizeof(iovalue), TRUE);
708 if (err) {
709 DHD_ERROR(("%s: error changing sd_divisor: %d\n",
710 __func__, err));
711 return BCME_ERROR;
712 }
713 }
714 bus->clkstate = CLK_NONE;
715 }
716
717 return BCME_OK;
718}
719
720/* Transition SD and backplane clock readiness */
721static int dhdsdio_clkctl(dhd_bus_t *bus, uint target, bool pendok)
722{
723#ifdef DHD_DEBUG
724 uint oldstate = bus->clkstate;
725#endif /* DHD_DEBUG */
726
727 DHD_TRACE(("%s: Enter\n", __func__));
728
729 /* Early exit if we're already there */
730 if (bus->clkstate == target) {
731 if (target == CLK_AVAIL) {
732 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
733 bus->activity = TRUE;
734 }
735 return BCME_OK;
736 }
737
738 switch (target) {
739 case CLK_AVAIL:
740 /* Make sure SD clock is available */
741 if (bus->clkstate == CLK_NONE)
742 dhdsdio_sdclk(bus, TRUE);
743 /* Now request HT Avail on the backplane */
744 dhdsdio_htclk(bus, TRUE, pendok);
745 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
746 bus->activity = TRUE;
747 break;
748
749 case CLK_SDONLY:
750 /* Remove HT request, or bring up SD clock */
751 if (bus->clkstate == CLK_NONE)
752 dhdsdio_sdclk(bus, TRUE);
753 else if (bus->clkstate == CLK_AVAIL)
754 dhdsdio_htclk(bus, FALSE, FALSE);
755 else
756 DHD_ERROR(("dhdsdio_clkctl: request for %d -> %d\n",
757 bus->clkstate, target));
758 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
759 break;
760
761 case CLK_NONE:
762 /* Make sure to remove HT request */
763 if (bus->clkstate == CLK_AVAIL)
764 dhdsdio_htclk(bus, FALSE, FALSE);
765 /* Now remove the SD clock */
766 dhdsdio_sdclk(bus, FALSE);
767 dhd_os_wd_timer(bus->dhd, 0);
768 break;
769 }
770#ifdef DHD_DEBUG
771 DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
772#endif /* DHD_DEBUG */
773
774 return BCME_OK;
775}
776
777int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
778{
779 bcmsdh_info_t *sdh = bus->sdh;
780 sdpcmd_regs_t *regs = bus->regs;
781 uint retries = 0;
782
783 DHD_INFO(("dhdsdio_bussleep: request %s (currently %s)\n",
784 (sleep ? "SLEEP" : "WAKE"),
785 (bus->sleeping ? "SLEEP" : "WAKE")));
786
787 /* Done if we're already in the requested state */
788 if (sleep == bus->sleeping)
789 return BCME_OK;
790
791 /* Going to sleep: set the alarm and turn off the lights... */
792 if (sleep) {
793 /* Don't sleep if something is pending */
794 if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
795 return BCME_BUSY;
796
797 /* Disable SDIO interrupts (no longer interested) */
798 bcmsdh_intr_disable(bus->sdh);
799
800 /* Make sure the controller has the bus up */
801 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
802
803 /* Tell device to start using OOB wakeup */
804 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
805 if (retries > retry_limit)
806 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
807
808 /* Turn off our contribution to the HT clock request */
809 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
810
811 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
812 SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
813
814 /* Isolate the bus */
815 if (bus->sih->chip != BCM4329_CHIP_ID
816 && bus->sih->chip != BCM4319_CHIP_ID) {
817 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
818 SBSDIO_DEVCTL_PADS_ISO, NULL);
819 }
820
821 /* Change state */
822 bus->sleeping = TRUE;
823
824 } else {
825 /* Waking up: bus power up is ok, set local state */
826
827 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
828 0, NULL);
829
830 /* Force pad isolation off if possible
831 (in case power never toggled) */
832 if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
833 && (bus->sih->buscorerev >= 10))
834 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
835 NULL);
836
837 /* Make sure the controller has the bus up */
838 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
839
840 /* Send misc interrupt to indicate OOB not needed */
841 W_SDREG(0, &regs->tosbmailboxdata, retries);
842 if (retries <= retry_limit)
843 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
844
845 if (retries > retry_limit)
846 DHD_ERROR(("CANNOT SIGNAL CHIP TO CLEAR OOB!!\n"));
847
848 /* Make sure we have SD bus access */
849 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
850
851 /* Change state */
852 bus->sleeping = FALSE;
853
854 /* Enable interrupts again */
855 if (bus->intr && (bus->dhd->busstate == DHD_BUS_DATA)) {
856 bus->intdis = FALSE;
857 bcmsdh_intr_enable(bus->sdh);
858 }
859 }
860
861 return BCME_OK;
862}
863
864#if defined(OOB_INTR_ONLY)
865void dhd_enable_oob_intr(struct dhd_bus *bus, bool enable)
866{
867#if defined(HW_OOB)
868 bcmsdh_enable_hw_oob_intr(bus->sdh, enable);
869#else
870 sdpcmd_regs_t *regs = bus->regs;
871 uint retries = 0;
872
873 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
874 if (enable == TRUE) {
875
876 /* Tell device to start using OOB wakeup */
877 W_SDREG(SMB_USE_OOB, &regs->tosbmailbox, retries);
878 if (retries > retry_limit)
879 DHD_ERROR(("CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n"));
880
881 } else {
882 /* Send misc interrupt to indicate OOB not needed */
883 W_SDREG(0, &regs->tosbmailboxdata, retries);
884 if (retries <= retry_limit)
885 W_SDREG(SMB_DEV_INT, &regs->tosbmailbox, retries);
886 }
887
888 /* Turn off our contribution to the HT clock request */
889 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
890#endif /* !defined(HW_OOB) */
891}
892#endif /* defined(OOB_INTR_ONLY) */
893
894#define BUS_WAKE(bus) \
895 do { \
896 if ((bus)->sleeping) \
897 dhdsdio_bussleep((bus), FALSE); \
898 } while (0);
899
900/* Writes a HW/SW header into the packet and sends it. */
901/* Assumes: (a) header space already there, (b) caller holds lock */
902static int dhdsdio_txpkt(dhd_bus_t *bus, void *pkt, uint chan, bool free_pkt)
903{
904 int ret;
905 osl_t *osh;
3fd79f7c 906 u8 *frame;
7d4df48e 907 u16 len, pad = 0;
66cbd3ab 908 u32 swheader;
cf2b4488
HP		 909 uint retries = 0;
910 bcmsdh_info_t *sdh;
911 void *new;
912 int i;
913
914 DHD_TRACE(("%s: Enter\n", __func__));
915
916 sdh = bus->sdh;
917 osh = bus->dhd->osh;
918
919 if (bus->dhd->dongle_reset) {
920 ret = BCME_NOTREADY;
921 goto done;
922 }
923
3fd79f7c 924 frame = (u8 *) PKTDATA(pkt);
cf2b4488
HP		 925
926 /* Add alignment padding, allocate new packet if needed */
927 pad = ((uintptr) frame % DHD_SDALIGN);
928 if (pad) {
929 if (PKTHEADROOM(pkt) < pad) {
930 DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
931 __func__, (int)PKTHEADROOM(pkt), pad));
932 bus->dhd->tx_realloc++;
933 new = PKTGET(osh, (PKTLEN(pkt) + DHD_SDALIGN), TRUE);
934 if (!new) {
935 DHD_ERROR(("%s: couldn't allocate new %d-byte "
936 "packet\n",
937 __func__, PKTLEN(pkt) + DHD_SDALIGN));
938 ret = BCME_NOMEM;
939 goto done;
940 }
941
942 PKTALIGN(osh, new, PKTLEN(pkt), DHD_SDALIGN);
943 bcopy(PKTDATA(pkt), PKTDATA(new), PKTLEN(pkt));
944 if (free_pkt)
945 PKTFREE(osh, pkt, TRUE);
946 /* free the pkt if canned one is not used */
947 free_pkt = TRUE;
948 pkt = new;
3fd79f7c 949 frame = (u8 *) PKTDATA(pkt);
cf2b4488
HP		 950 ASSERT(((uintptr) frame % DHD_SDALIGN) == 0);
951 pad = 0;
952 } else {
953 PKTPUSH(pkt, pad);
3fd79f7c 954 frame = (u8 *) PKTDATA(pkt);
cf2b4488
HP		 955
956 ASSERT((pad + SDPCM_HDRLEN) <= (int)PKTLEN(pkt));
957 bzero(frame, pad + SDPCM_HDRLEN);
958 }
959 }
960 ASSERT(pad < DHD_SDALIGN);
961
962 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
7d4df48e
GKH		 963 len = (u16) PKTLEN(pkt);
964 *(u16 *) frame = htol16(len);
965 *(((u16 *) frame) + 1) = htol16(~len);
cf2b4488
HP		 966
967 /* Software tag: channel, sequence number, data offset */
968 swheader =
969 ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
970 (((pad +
971 SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
972 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
973 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
974
975#ifdef DHD_DEBUG
976 tx_packets[PKTPRIO(pkt)]++;
977 if (DHD_BYTES_ON() &&
978 (((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
979 (DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
980 prhex("Tx Frame", frame, len);
981 } else if (DHD_HDRS_ON()) {
982 prhex("TxHdr", frame, MIN(len, 16));
983 }
984#endif
985
986 /* Raise len to next SDIO block to eliminate tail command */
987 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
7d4df48e 988 u16 pad = bus->blocksize - (len % bus->blocksize);
cf2b4488
HP		 989 if ((pad <= bus->roundup) && (pad < bus->blocksize))
990#ifdef NOTUSED
991 if (pad <= PKTTAILROOM(pkt))
992#endif /* NOTUSED */
993 len += pad;
994 } else if (len % DHD_SDALIGN) {
995 len += DHD_SDALIGN - (len % DHD_SDALIGN);
996 }
997
998 /* Some controllers have trouble with odd bytes -- round to even */
999 if (forcealign && (len & (ALIGNMENT - 1))) {
1000#ifdef NOTUSED
1001 if (PKTTAILROOM(pkt))
1002#endif
1003 len = ROUNDUP(len, ALIGNMENT);
1004#ifdef NOTUSED
1005 else
1006 DHD_ERROR(("%s: sending unrounded %d-byte packet\n",
1007 __func__, len));
1008#endif
1009 }
1010
1011 do {
1012 ret =
1013 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
1014 F2SYNC, frame, len, pkt, NULL, NULL);
1015 bus->f2txdata++;
1016 ASSERT(ret != BCME_PENDING);
1017
1018 if (ret < 0) {
1019 /* On failure, abort the command
1020 and terminate the frame */
1021 DHD_INFO(("%s: sdio error %d, abort command and "
1022 "terminate frame.\n", __func__, ret));
1023 bus->tx_sderrs++;
1024
1025 bcmsdh_abort(sdh, SDIO_FUNC_2);
1026 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1027 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
1028 NULL);
1029 bus->f1regdata++;
1030
1031 for (i = 0; i < 3; i++) {
3fd79f7c 1032 u8 hi, lo;
cf2b4488
HP		 1033 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1034 SBSDIO_FUNC1_WFRAMEBCHI,
1035 NULL);
1036 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1037 SBSDIO_FUNC1_WFRAMEBCLO,
1038 NULL);
1039 bus->f1regdata += 2;
1040 if ((hi == 0) && (lo == 0))
1041 break;
1042 }
1043
1044 }
1045 if (ret == 0)
1046 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1047
1048 } while ((ret < 0) && retrydata && retries++ < TXRETRIES);
1049
1050done:
1051 /* restore pkt buffer pointer before calling tx complete routine */
1052 PKTPULL(pkt, SDPCM_HDRLEN + pad);
1053 dhd_os_sdunlock(bus->dhd);
1054 dhd_txcomplete(bus->dhd, pkt, ret != 0);
1055 dhd_os_sdlock(bus->dhd);
1056
1057 if (free_pkt)
1058 PKTFREE(osh, pkt, TRUE);
1059
1060 return ret;
1061}
1062
1063int dhd_bus_txdata(struct dhd_bus *bus, void *pkt)
1064{
1065 int ret = BCME_ERROR;
1066 osl_t *osh;
1067 uint datalen, prec;
1068
1069 DHD_TRACE(("%s: Enter\n", __func__));
1070
1071 osh = bus->dhd->osh;
1072 datalen = PKTLEN(pkt);
1073
1074#ifdef SDTEST
1075 /* Push the test header if doing loopback */
1076 if (bus->ext_loop) {
3fd79f7c 1077 u8 *data;
cf2b4488
HP		 1078 PKTPUSH(pkt, SDPCM_TEST_HDRLEN);
1079 data = PKTDATA(pkt);
1080 *data++ = SDPCM_TEST_ECHOREQ;
3fd79f7c 1081 *data++ = (u8) bus->loopid++;
cf2b4488
HP		 1082 *data++ = (datalen >> 0);
1083 *data++ = (datalen >> 8);
1084 datalen += SDPCM_TEST_HDRLEN;
1085 }
1086#endif /* SDTEST */
1087
1088 /* Add space for the header */
1089 PKTPUSH(pkt, SDPCM_HDRLEN);
1090 ASSERT(ISALIGNED((uintptr) PKTDATA(pkt), 2));
1091
1092 prec = PRIO2PREC((PKTPRIO(pkt) & PRIOMASK));
1093
1094 /* Check for existing queue, current flow-control,
1095 pending event, or pending clock */
1096 if (dhd_deferred_tx || bus->fcstate || pktq_len(&bus->txq)
1097 || bus->dpc_sched || (!DATAOK(bus))
1098 || (bus->flowcontrol & NBITVAL(prec))
1099 || (bus->clkstate != CLK_AVAIL)) {
1100 DHD_TRACE(("%s: deferring pktq len %d\n", __func__,
1101 pktq_len(&bus->txq)));
1102 bus->fcqueued++;
1103
1104 /* Priority based enq */
1105 dhd_os_sdlock_txq(bus->dhd);
1106 if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == FALSE) {
1107 PKTPULL(pkt, SDPCM_HDRLEN);
1108 dhd_txcomplete(bus->dhd, pkt, FALSE);
1109 PKTFREE(osh, pkt, TRUE);
1110 DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
1111 ret = BCME_NORESOURCE;
1112 } else {
1113 ret = BCME_OK;
1114 }
1115 dhd_os_sdunlock_txq(bus->dhd);
1116
1117 if ((pktq_len(&bus->txq) >= FCHI) && dhd_doflow)
1118 dhd_txflowcontrol(bus->dhd, 0, ON);
1119
1120#ifdef DHD_DEBUG
1121 if (pktq_plen(&bus->txq, prec) > qcount[prec])
1122 qcount[prec] = pktq_plen(&bus->txq, prec);
1123#endif
1124 /* Schedule DPC if needed to send queued packet(s) */
1125 if (dhd_deferred_tx && !bus->dpc_sched) {
1126 bus->dpc_sched = TRUE;
1127 dhd_sched_dpc(bus->dhd);
1128 }
1129 } else {
1130 /* Lock: we're about to use shared data/code (and SDIO) */
1131 dhd_os_sdlock(bus->dhd);
1132
1133 /* Otherwise, send it now */
1134 BUS_WAKE(bus);
1135 /* Make sure back plane ht clk is on, no pending allowed */
1136 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
1137
1138#ifndef SDTEST
1139 DHD_TRACE(("%s: calling txpkt\n", __func__));
1140 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, TRUE);
1141#else
1142 ret = dhdsdio_txpkt(bus, pkt,
1143 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1144 SDPCM_DATA_CHANNEL), TRUE);
1145#endif
1146 if (ret)
1147 bus->dhd->tx_errors++;
1148 else
1149 bus->dhd->dstats.tx_bytes += datalen;
1150
1151 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1152 bus->activity = FALSE;
1153 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
1154 }
1155
1156 dhd_os_sdunlock(bus->dhd);
1157 }
1158
1159 return ret;
1160}
1161
1162static uint dhdsdio_sendfromq(dhd_bus_t *bus, uint maxframes)
1163{
1164 void *pkt;
66cbd3ab 1165 u32 intstatus = 0;
cf2b4488
HP		 1166 uint retries = 0;
1167 int ret = 0, prec_out;
1168 uint cnt = 0;
1169 uint datalen;
3fd79f7c 1170 u8 tx_prec_map;
cf2b4488
HP		 1171
1172 dhd_pub_t *dhd = bus->dhd;
1173 sdpcmd_regs_t *regs = bus->regs;
1174
1175 DHD_TRACE(("%s: Enter\n", __func__));
1176
1177 tx_prec_map = ~bus->flowcontrol;
1178
1179 /* Send frames until the limit or some other event */
1180 for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
1181 dhd_os_sdlock_txq(bus->dhd);
1182 pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
1183 if (pkt == NULL) {
1184 dhd_os_sdunlock_txq(bus->dhd);
1185 break;
1186 }
1187 dhd_os_sdunlock_txq(bus->dhd);
1188 datalen = PKTLEN(pkt) - SDPCM_HDRLEN;
1189
1190#ifndef SDTEST
1191 ret = dhdsdio_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, TRUE);
1192#else
1193 ret = dhdsdio_txpkt(bus, pkt,
1194 (bus->ext_loop ? SDPCM_TEST_CHANNEL :
1195 SDPCM_DATA_CHANNEL), TRUE);
1196#endif
1197 if (ret)
1198 bus->dhd->tx_errors++;
1199 else
1200 bus->dhd->dstats.tx_bytes += datalen;
1201
1202 /* In poll mode, need to check for other events */
1203 if (!bus->intr && cnt) {
1204 /* Check device status, signal pending interrupt */
1205 R_SDREG(intstatus, &regs->intstatus, retries);
1206 bus->f2txdata++;
1207 if (bcmsdh_regfail(bus->sdh))
1208 break;
1209 if (intstatus & bus->hostintmask)
1210 bus->ipend = TRUE;
1211 }
1212 }
1213
1214 /* Deflow-control stack if needed */
1215 if (dhd_doflow && dhd->up && (dhd->busstate == DHD_BUS_DATA) &&
1216 dhd->txoff && (pktq_len(&bus->txq) < FCLOW))
1217 dhd_txflowcontrol(dhd, 0, OFF);
1218
1219 return cnt;
1220}
1221
580a0bd9 1222int dhd_bus_txctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
cf2b4488 1223{
3fd79f7c 1224 u8 *frame;
7d4df48e 1225 u16 len;
66cbd3ab 1226 u32 swheader;
cf2b4488
HP		 1227 uint retries = 0;
1228 bcmsdh_info_t *sdh = bus->sdh;
3fd79f7c 1229 u8 doff = 0;
cf2b4488
HP		 1230 int ret = -1;
1231 int i;
1232
1233 DHD_TRACE(("%s: Enter\n", __func__));
1234
1235 if (bus->dhd->dongle_reset)
1236 return -EIO;
1237
1238 /* Back the pointer to make a room for bus header */
1239 frame = msg - SDPCM_HDRLEN;
1240 len = (msglen += SDPCM_HDRLEN);
1241
1242 /* Add alignment padding (optional for ctl frames) */
1243 if (dhd_alignctl) {
9b890325
JC		 1244 doff = ((uintptr) frame % DHD_SDALIGN);
1245 if (doff) {
cf2b4488
HP		 1246 frame -= doff;
1247 len += doff;
1248 msglen += doff;
1249 bzero(frame, doff + SDPCM_HDRLEN);
1250 }
1251 ASSERT(doff < DHD_SDALIGN);
1252 }
1253 doff += SDPCM_HDRLEN;
1254
1255 /* Round send length to next SDIO block */
1256 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
7d4df48e 1257 u16 pad = bus->blocksize - (len % bus->blocksize);
cf2b4488
HP		 1258 if ((pad <= bus->roundup) && (pad < bus->blocksize))
1259 len += pad;
1260 } else if (len % DHD_SDALIGN) {
1261 len += DHD_SDALIGN - (len % DHD_SDALIGN);
1262 }
1263
1264 /* Satisfy length-alignment requirements */
1265 if (forcealign && (len & (ALIGNMENT - 1)))
1266 len = ROUNDUP(len, ALIGNMENT);
1267
1268 ASSERT(ISALIGNED((uintptr) frame, 2));
1269
1270 /* Need to lock here to protect txseq and SDIO tx calls */
1271 dhd_os_sdlock(bus->dhd);
1272
1273 BUS_WAKE(bus);
1274
1275 /* Make sure backplane clock is on */
1276 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
1277
1278 /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
7d4df48e
GKH		 1279 *(u16 *) frame = htol16((u16) msglen);
1280 *(((u16 *) frame) + 1) = htol16(~msglen);
cf2b4488
HP		 1281
1282 /* Software tag: channel, sequence number, data offset */
1283 swheader =
1284 ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
1285 SDPCM_CHANNEL_MASK)
1286 | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
1287 SDPCM_DOFFSET_MASK);
1288 htol32_ua_store(swheader, frame + SDPCM_FRAMETAG_LEN);
1289 htol32_ua_store(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
1290
1291 if (!DATAOK(bus)) {
1292 DHD_INFO(("%s: No bus credit bus->tx_max %d, bus->tx_seq %d\n",
1293 __func__, bus->tx_max, bus->tx_seq));
1294 bus->ctrl_frame_stat = TRUE;
1295 /* Send from dpc */
1296 bus->ctrl_frame_buf = frame;
1297 bus->ctrl_frame_len = len;
1298
1299 dhd_wait_for_event(bus->dhd, &bus->ctrl_frame_stat);
1300
1301 if (bus->ctrl_frame_stat == FALSE) {
1302 DHD_INFO(("%s: ctrl_frame_stat == FALSE\n", __func__));
1303 ret = 0;
1304 } else {
1305 DHD_INFO(("%s: ctrl_frame_stat == TRUE\n", __func__));
1306 ret = -1;
1307 }
1308 }
1309
1310 if (ret == -1) {
1311#ifdef DHD_DEBUG
1312 if (DHD_BYTES_ON() && DHD_CTL_ON())
1313 prhex("Tx Frame", frame, len);
1314 else if (DHD_HDRS_ON())
1315 prhex("TxHdr", frame, MIN(len, 16));
1316#endif
1317
1318 do {
1319 bus->ctrl_frame_stat = FALSE;
1320 ret =
1321 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh),
1322 SDIO_FUNC_2, F2SYNC, frame, len,
1323 NULL, NULL, NULL);
1324
1325 ASSERT(ret != BCME_PENDING);
1326
1327 if (ret < 0) {
1328 /* On failure, abort the command and
1329 terminate the frame */
1330 DHD_INFO(("%s: sdio error %d, abort command and terminate frame.\n",
1331 __func__, ret));
1332 bus->tx_sderrs++;
1333
1334 bcmsdh_abort(sdh, SDIO_FUNC_2);
1335
1336 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
1337 SBSDIO_FUNC1_FRAMECTRL,
1338 SFC_WF_TERM, NULL);
1339 bus->f1regdata++;
1340
1341 for (i = 0; i < 3; i++) {
3fd79f7c 1342 u8 hi, lo;
cf2b4488
HP		 1343 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1344 SBSDIO_FUNC1_WFRAMEBCHI,
1345 NULL);
1346 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
1347 SBSDIO_FUNC1_WFRAMEBCLO,
1348 NULL);
1349 bus->f1regdata += 2;
1350 if ((hi == 0) && (lo == 0))
1351 break;
1352 }
1353
1354 }
1355 if (ret == 0) {
1356 bus->tx_seq =
1357 (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
1358 }
1359 } while ((ret < 0) && retries++ < TXRETRIES);
1360 }
1361
1362 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
1363 bus->activity = FALSE;
1364 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
1365 }
1366
1367 dhd_os_sdunlock(bus->dhd);
1368
1369 if (ret)
1370 bus->dhd->tx_ctlerrs++;
1371 else
1372 bus->dhd->tx_ctlpkts++;
1373
1374 return ret ? -EIO : 0;
1375}
1376
580a0bd9 1377int dhd_bus_rxctl(struct dhd_bus *bus, unsigned char *msg, uint msglen)
cf2b4488
HP		 1378{
1379 int timeleft;
1380 uint rxlen = 0;
1381 bool pending;
1382
1383 DHD_TRACE(("%s: Enter\n", __func__));
1384
1385 if (bus->dhd->dongle_reset)
1386 return -EIO;
1387
1388 /* Wait until control frame is available */
1389 timeleft = dhd_os_ioctl_resp_wait(bus->dhd, &bus->rxlen, &pending);
1390
1391 dhd_os_sdlock(bus->dhd);
1392 rxlen = bus->rxlen;
1393 bcopy(bus->rxctl, msg, MIN(msglen, rxlen));
1394 bus->rxlen = 0;
1395 dhd_os_sdunlock(bus->dhd);
1396
1397 if (rxlen) {
1398 DHD_CTL(("%s: resumed on rxctl frame, got %d expected %d\n",
1399 __func__, rxlen, msglen));
1400 } else if (timeleft == 0) {
1401 DHD_ERROR(("%s: resumed on timeout\n", __func__));
1402#ifdef DHD_DEBUG
1403 dhd_os_sdlock(bus->dhd);
1404 dhdsdio_checkdied(bus, NULL, 0);
1405 dhd_os_sdunlock(bus->dhd);
1406#endif /* DHD_DEBUG */
1407 } else if (pending == TRUE) {
1408 DHD_CTL(("%s: cancelled\n", __func__));
1409 return -ERESTARTSYS;
1410 } else {
1411 DHD_CTL(("%s: resumed for unknown reason?\n", __func__));
1412#ifdef DHD_DEBUG
1413 dhd_os_sdlock(bus->dhd);
1414 dhdsdio_checkdied(bus, NULL, 0);
1415 dhd_os_sdunlock(bus->dhd);
1416#endif /* DHD_DEBUG */
1417 }
1418
1419 if (rxlen)
1420 bus->dhd->rx_ctlpkts++;
1421 else
1422 bus->dhd->rx_ctlerrs++;
1423
e9887c9d 1424 return rxlen ? (int)rxlen : -ETIMEDOUT;
cf2b4488
HP		 1425}
1426
1427/* IOVar table */
1428enum {
1429 IOV_INTR = 1,
1430 IOV_POLLRATE,
1431 IOV_SDREG,
1432 IOV_SBREG,
1433 IOV_SDCIS,
1434 IOV_MEMBYTES,
1435 IOV_MEMSIZE,
1436#ifdef DHD_DEBUG
1437 IOV_CHECKDIED,
1438#endif
1439 IOV_DOWNLOAD,
1440 IOV_FORCEEVEN,
1441 IOV_SDIOD_DRIVE,
1442 IOV_READAHEAD,
1443 IOV_SDRXCHAIN,
1444 IOV_ALIGNCTL,
1445 IOV_SDALIGN,
1446 IOV_DEVRESET,
1447 IOV_CPU,
1448#ifdef SDTEST
1449 IOV_PKTGEN,
1450 IOV_EXTLOOP,
1451#endif /* SDTEST */
1452 IOV_SPROM,
1453 IOV_TXBOUND,
1454 IOV_RXBOUND,
1455 IOV_TXMINMAX,
1456 IOV_IDLETIME,
1457 IOV_IDLECLOCK,
1458 IOV_SD1IDLE,
1459 IOV_SLEEP,
1460 IOV_VARS
1461};
1462
1463const bcm_iovar_t dhdsdio_iovars[] = {
1464 {"intr", IOV_INTR, 0, IOVT_BOOL, 0},
1465 {"sleep", IOV_SLEEP, 0, IOVT_BOOL, 0},
1466 {"pollrate", IOV_POLLRATE, 0, IOVT_UINT32, 0},
1467 {"idletime", IOV_IDLETIME, 0, IOVT_INT32, 0},
1468 {"idleclock", IOV_IDLECLOCK, 0, IOVT_INT32, 0},
1469 {"sd1idle", IOV_SD1IDLE, 0, IOVT_BOOL, 0},
1470 {"membytes", IOV_MEMBYTES, 0, IOVT_BUFFER, 2 * sizeof(int)},
1471 {"memsize", IOV_MEMSIZE, 0, IOVT_UINT32, 0},
1472 {"download", IOV_DOWNLOAD, 0, IOVT_BOOL, 0},
1473 {"vars", IOV_VARS, 0, IOVT_BUFFER, 0},
1474 {"sdiod_drive", IOV_SDIOD_DRIVE, 0, IOVT_UINT32, 0},
1475 {"readahead", IOV_READAHEAD, 0, IOVT_BOOL, 0},
1476 {"sdrxchain", IOV_SDRXCHAIN, 0, IOVT_BOOL, 0},
1477 {"alignctl", IOV_ALIGNCTL, 0, IOVT_BOOL, 0},
1478 {"sdalign", IOV_SDALIGN, 0, IOVT_BOOL, 0},
1479 {"devreset", IOV_DEVRESET, 0, IOVT_BOOL, 0},
1480#ifdef DHD_DEBUG
1481 {"sdreg", IOV_SDREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1482 ,
1483 {"sbreg", IOV_SBREG, 0, IOVT_BUFFER, sizeof(sdreg_t)}
1484 ,
1485 {"sd_cis", IOV_SDCIS, 0, IOVT_BUFFER, DHD_IOCTL_MAXLEN}
1486 ,
1487 {"forcealign", IOV_FORCEEVEN, 0, IOVT_BOOL, 0}
1488 ,
1489 {"txbound", IOV_TXBOUND, 0, IOVT_UINT32, 0}
1490 ,
1491 {"rxbound", IOV_RXBOUND, 0, IOVT_UINT32, 0}
1492 ,
1493 {"txminmax", IOV_TXMINMAX, 0, IOVT_UINT32, 0}
1494 ,
1495 {"cpu", IOV_CPU, 0, IOVT_BOOL, 0}
1496 ,
1497#ifdef DHD_DEBUG
1498 {"checkdied", IOV_CHECKDIED, 0, IOVT_BUFFER, 0}
1499 ,
1500#endif /* DHD_DEBUG */
1501#endif /* DHD_DEBUG */
1502#ifdef SDTEST
1503 {"extloop", IOV_EXTLOOP, 0, IOVT_BOOL, 0}
1504 ,
1505 {"pktgen", IOV_PKTGEN, 0, IOVT_BUFFER, sizeof(dhd_pktgen_t)}
1506 ,
1507#endif /* SDTEST */
1508
1509 {NULL, 0, 0, 0, 0}
1510};
1511
1512static void
1513dhd_dump_pct(struct bcmstrbuf *strbuf, char *desc, uint num, uint div)
1514{
1515 uint q1, q2;
1516
1517 if (!div) {
1518 bcm_bprintf(strbuf, "%s N/A", desc);
1519 } else {
1520 q1 = num / div;
1521 q2 = (100 * (num - (q1 * div))) / div;
1522 bcm_bprintf(strbuf, "%s %d.%02d", desc, q1, q2);
1523 }
1524}
1525
1526void dhd_bus_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
1527{
1528 dhd_bus_t *bus = dhdp->bus;
1529
1530 bcm_bprintf(strbuf, "Bus SDIO structure:\n");
1531 bcm_bprintf(strbuf,
1532 "hostintmask 0x%08x intstatus 0x%08x sdpcm_ver %d\n",
1533 bus->hostintmask, bus->intstatus, bus->sdpcm_ver);
1534 bcm_bprintf(strbuf,
1535 "fcstate %d qlen %d tx_seq %d, max %d, rxskip %d rxlen %d rx_seq %d\n",
1536 bus->fcstate, pktq_len(&bus->txq), bus->tx_seq, bus->tx_max,
1537 bus->rxskip, bus->rxlen, bus->rx_seq);
1538 bcm_bprintf(strbuf, "intr %d intrcount %d lastintrs %d spurious %d\n",
1539 bus->intr, bus->intrcount, bus->lastintrs, bus->spurious);
1540 bcm_bprintf(strbuf, "pollrate %d pollcnt %d regfails %d\n",
1541 bus->pollrate, bus->pollcnt, bus->regfails);
1542
1543 bcm_bprintf(strbuf, "\nAdditional counters:\n");
1544 bcm_bprintf(strbuf,
1545 "tx_sderrs %d fcqueued %d rxrtx %d rx_toolong %d rxc_errors %d\n",
1546 bus->tx_sderrs, bus->fcqueued, bus->rxrtx, bus->rx_toolong,
1547 bus->rxc_errors);
1548 bcm_bprintf(strbuf, "rx_hdrfail %d badhdr %d badseq %d\n",
1549 bus->rx_hdrfail, bus->rx_badhdr, bus->rx_badseq);
1550 bcm_bprintf(strbuf, "fc_rcvd %d, fc_xoff %d, fc_xon %d\n", bus->fc_rcvd,
1551 bus->fc_xoff, bus->fc_xon);
1552 bcm_bprintf(strbuf, "rxglomfail %d, rxglomframes %d, rxglompkts %d\n",
1553 bus->rxglomfail, bus->rxglomframes, bus->rxglompkts);
1554 bcm_bprintf(strbuf, "f2rx (hdrs/data) %d (%d/%d), f2tx %d f1regs %d\n",
1555 (bus->f2rxhdrs + bus->f2rxdata), bus->f2rxhdrs,
1556 bus->f2rxdata, bus->f2txdata, bus->f1regdata);
1557 {
1558 dhd_dump_pct(strbuf, "\nRx: pkts/f2rd", bus->dhd->rx_packets,
1559 (bus->f2rxhdrs + bus->f2rxdata));
1560 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->rx_packets,
1561 bus->f1regdata);
1562 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->rx_packets,
1563 (bus->f2rxhdrs + bus->f2rxdata + bus->f1regdata));
1564 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->rx_packets,
1565 bus->intrcount);
1566 bcm_bprintf(strbuf, "\n");
1567
1568 dhd_dump_pct(strbuf, "Rx: glom pct", (100 * bus->rxglompkts),
1569 bus->dhd->rx_packets);
1570 dhd_dump_pct(strbuf, ", pkts/glom", bus->rxglompkts,
1571 bus->rxglomframes);
1572 bcm_bprintf(strbuf, "\n");
1573
1574 dhd_dump_pct(strbuf, "Tx: pkts/f2wr", bus->dhd->tx_packets,
1575 bus->f2txdata);
1576 dhd_dump_pct(strbuf, ", pkts/f1sd", bus->dhd->tx_packets,
1577 bus->f1regdata);
1578 dhd_dump_pct(strbuf, ", pkts/sd", bus->dhd->tx_packets,
1579 (bus->f2txdata + bus->f1regdata));
1580 dhd_dump_pct(strbuf, ", pkts/int", bus->dhd->tx_packets,
1581 bus->intrcount);
1582 bcm_bprintf(strbuf, "\n");
1583
1584 dhd_dump_pct(strbuf, "Total: pkts/f2rw",
1585 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1586 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata));
1587 dhd_dump_pct(strbuf, ", pkts/f1sd",
1588 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1589 bus->f1regdata);
1590 dhd_dump_pct(strbuf, ", pkts/sd",
1591 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1592 (bus->f2txdata + bus->f2rxhdrs + bus->f2rxdata +
1593 bus->f1regdata));
1594 dhd_dump_pct(strbuf, ", pkts/int",
1595 (bus->dhd->tx_packets + bus->dhd->rx_packets),
1596 bus->intrcount);
1597 bcm_bprintf(strbuf, "\n\n");
1598 }
1599
1600#ifdef SDTEST
1601 if (bus->pktgen_count) {
1602 bcm_bprintf(strbuf, "pktgen config and count:\n");
1603 bcm_bprintf(strbuf,
1604 "freq %d count %d print %d total %d min %d len %d\n",
1605 bus->pktgen_freq, bus->pktgen_count,
1606 bus->pktgen_print, bus->pktgen_total,
1607 bus->pktgen_minlen, bus->pktgen_maxlen);
1608 bcm_bprintf(strbuf, "send attempts %d rcvd %d fail %d\n",
1609 bus->pktgen_sent, bus->pktgen_rcvd,
1610 bus->pktgen_fail);
1611 }
1612#endif /* SDTEST */
1613#ifdef DHD_DEBUG
1614 bcm_bprintf(strbuf, "dpc_sched %d host interrupt%spending\n",
1615 bus->dpc_sched,
1616 (bcmsdh_intr_pending(bus->sdh) ? " " : " not "));
1617 bcm_bprintf(strbuf, "blocksize %d roundup %d\n", bus->blocksize,
1618 bus->roundup);
1619#endif /* DHD_DEBUG */
1620 bcm_bprintf(strbuf,
1621 "clkstate %d activity %d idletime %d idlecount %d sleeping %d\n",
1622 bus->clkstate, bus->activity, bus->idletime, bus->idlecount,
1623 bus->sleeping);
1624}
1625
1626void dhd_bus_clearcounts(dhd_pub_t *dhdp)
1627{
1628 dhd_bus_t *bus = (dhd_bus_t *) dhdp->bus;
1629
1630 bus->intrcount = bus->lastintrs = bus->spurious = bus->regfails = 0;
1631 bus->rxrtx = bus->rx_toolong = bus->rxc_errors = 0;
1632 bus->rx_hdrfail = bus->rx_badhdr = bus->rx_badseq = 0;
1633 bus->tx_sderrs = bus->fc_rcvd = bus->fc_xoff = bus->fc_xon = 0;
1634 bus->rxglomfail = bus->rxglomframes = bus->rxglompkts = 0;
1635 bus->f2rxhdrs = bus->f2rxdata = bus->f2txdata = bus->f1regdata = 0;
1636}
1637
1638#ifdef SDTEST
3fd79f7c 1639static int dhdsdio_pktgen_get(dhd_bus_t *bus, u8 *arg)
cf2b4488
HP		 1640{
1641 dhd_pktgen_t pktgen;
1642
1643 pktgen.version = DHD_PKTGEN_VERSION;
1644 pktgen.freq = bus->pktgen_freq;
1645 pktgen.count = bus->pktgen_count;
1646 pktgen.print = bus->pktgen_print;
1647 pktgen.total = bus->pktgen_total;
1648 pktgen.minlen = bus->pktgen_minlen;
1649 pktgen.maxlen = bus->pktgen_maxlen;
1650 pktgen.numsent = bus->pktgen_sent;
1651 pktgen.numrcvd = bus->pktgen_rcvd;
1652 pktgen.numfail = bus->pktgen_fail;
1653 pktgen.mode = bus->pktgen_mode;
1654 pktgen.stop = bus->pktgen_stop;
1655
1656 bcopy(&pktgen, arg, sizeof(pktgen));
1657
1658 return 0;
1659}
1660
3fd79f7c 1661static int dhdsdio_pktgen_set(dhd_bus_t *bus, u8 *arg)
cf2b4488
HP		 1662{
1663 dhd_pktgen_t pktgen;
1664 uint oldcnt, oldmode;
1665
1666 bcopy(arg, &pktgen, sizeof(pktgen));
1667 if (pktgen.version != DHD_PKTGEN_VERSION)
1668 return BCME_BADARG;
1669
1670 oldcnt = bus->pktgen_count;
1671 oldmode = bus->pktgen_mode;
1672
1673 bus->pktgen_freq = pktgen.freq;
1674 bus->pktgen_count = pktgen.count;
1675 bus->pktgen_print = pktgen.print;
1676 bus->pktgen_total = pktgen.total;
1677 bus->pktgen_minlen = pktgen.minlen;
1678 bus->pktgen_maxlen = pktgen.maxlen;
1679 bus->pktgen_mode = pktgen.mode;
1680 bus->pktgen_stop = pktgen.stop;
1681
1682 bus->pktgen_tick = bus->pktgen_ptick = 0;
1683 bus->pktgen_len = MAX(bus->pktgen_len, bus->pktgen_minlen);
1684 bus->pktgen_len = MIN(bus->pktgen_len, bus->pktgen_maxlen);
1685
1686 /* Clear counts for a new pktgen (mode change, or was stopped) */
1687 if (bus->pktgen_count && (!oldcnt || oldmode != bus->pktgen_mode))
1688 bus->pktgen_sent = bus->pktgen_rcvd = bus->pktgen_fail = 0;
1689
1690 return 0;
1691}
1692#endif /* SDTEST */
1693
1694static int
66cbd3ab 1695dhdsdio_membytes(dhd_bus_t *bus, bool write, u32 address, u8 *data,
cf2b4488
HP		 1696 uint size)
1697{
1698 int bcmerror = 0;
66cbd3ab 1699 u32 sdaddr;
cf2b4488
HP		 1700 uint dsize;
1701
1702 /* Determine initial transfer parameters */
1703 sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
1704 if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
1705 dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
1706 else
1707 dsize = size;
1708
1709 /* Set the backplane window to include the start address */
1710 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1711 if (bcmerror) {
1712 DHD_ERROR(("%s: window change failed\n", __func__));
1713 goto xfer_done;
1714 }
1715
1716 /* Do the transfer(s) */
1717 while (size) {
1718 DHD_INFO(("%s: %s %d bytes at offset 0x%08x in window 0x%08x\n",
1719 __func__, (write ? "write" : "read"), dsize,
1720 sdaddr, (address & SBSDIO_SBWINDOW_MASK)));
1721 bcmerror =
1722 bcmsdh_rwdata(bus->sdh, write, sdaddr, data, dsize);
1723 if (bcmerror) {
1724 DHD_ERROR(("%s: membytes transfer failed\n", __func__));
1725 break;
1726 }
1727
1728 /* Adjust for next transfer (if any) */
1729 size -= dsize;
1730 if (size) {
1731 data += dsize;
1732 address += dsize;
1733 bcmerror = dhdsdio_set_siaddr_window(bus, address);
1734 if (bcmerror) {
1735 DHD_ERROR(("%s: window change failed\n",
1736 __func__));
1737 break;
1738 }
1739 sdaddr = 0;
1740 dsize = MIN(SBSDIO_SB_OFT_ADDR_LIMIT, size);
1741 }
1742 }
1743
1744xfer_done:
1745 /* Return the window to backplane enumeration space for core access */
1746 if (dhdsdio_set_siaddr_window(bus, bcmsdh_cur_sbwad(bus->sdh))) {
1747 DHD_ERROR(("%s: FAILED to set window back to 0x%x\n",
1748 __func__, bcmsdh_cur_sbwad(bus->sdh)));
1749 }
1750
1751 return bcmerror;
1752}
1753
1754#ifdef DHD_DEBUG
1755static int dhdsdio_readshared(dhd_bus_t *bus, sdpcm_shared_t *sh)
1756{
66cbd3ab 1757 u32 addr;
cf2b4488
HP		 1758 int rv;
1759
1760 /* Read last word in memory to determine address of
1761 sdpcm_shared structure */
3fd79f7c 1762 rv = dhdsdio_membytes(bus, FALSE, bus->ramsize - 4, (u8 *)&addr, 4);
9b890325 1763 if (rv < 0)
cf2b4488
HP		 1764 return rv;
1765
1766 addr = ltoh32(addr);
1767
1768 DHD_INFO(("sdpcm_shared address 0x%08X\n", addr));
1769
1770 /*
1771 * Check if addr is valid.
1772 * NVRAM length at the end of memory should have been overwritten.
1773 */
1774 if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
1775 DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
1776 __func__, addr));
1777 return BCME_ERROR;
1778 }
1779
1780 /* Read hndrte_shared structure */
3fd79f7c 1781 rv = dhdsdio_membytes(bus, FALSE, addr, (u8 *) sh,
cf2b4488
HP		 1782 sizeof(sdpcm_shared_t));
1783 if (rv < 0)
1784 return rv;
1785
1786 /* Endianness */
1787 sh->flags = ltoh32(sh->flags);
1788 sh->trap_addr = ltoh32(sh->trap_addr);
1789 sh->assert_exp_addr = ltoh32(sh->assert_exp_addr);
1790 sh->assert_file_addr = ltoh32(sh->assert_file_addr);
1791 sh->assert_line = ltoh32(sh->assert_line);
1792 sh->console_addr = ltoh32(sh->console_addr);
1793 sh->msgtrace_addr = ltoh32(sh->msgtrace_addr);
1794
1795 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) != SDPCM_SHARED_VERSION) {
1796 DHD_ERROR(("%s: sdpcm_shared version %d in dhd "
1797 "is different than sdpcm_shared version %d in dongle\n",
1798 __func__, SDPCM_SHARED_VERSION,
1799 sh->flags & SDPCM_SHARED_VERSION_MASK));
1800 return BCME_ERROR;
1801 }
1802
1803 return BCME_OK;
1804}
1805
3fd79f7c 1806static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
cf2b4488
HP		 1807{
1808 int bcmerror = 0;
1809 uint msize = 512;
1810 char *mbuffer = NULL;
1811 uint maxstrlen = 256;
1812 char *str = NULL;
1813 trap_t tr;
1814 sdpcm_shared_t sdpcm_shared;
1815 struct bcmstrbuf strbuf;
1816
1817 DHD_TRACE(("%s: Enter\n", __func__));
1818
1819 if (data == NULL) {
1820 /*
1821 * Called after a rx ctrl timeout. "data" is NULL.
1822 * allocate memory to trace the trap or assert.
1823 */
1824 size = msize;
1825 mbuffer = data = MALLOC(bus->dhd->osh, msize);
1826 if (mbuffer == NULL) {
1827 DHD_ERROR(("%s: MALLOC(%d) failed\n", __func__,
1828 msize));
1829 bcmerror = BCME_NOMEM;
1830 goto done;
1831 }
1832 }
1833
9b890325
JC		 1834 str = MALLOC(bus->dhd->osh, maxstrlen);
1835 if (str == NULL) {
cf2b4488
HP		 1836 DHD_ERROR(("%s: MALLOC(%d) failed\n", __func__, maxstrlen));
1837 bcmerror = BCME_NOMEM;
1838 goto done;
1839 }
1840
9b890325
JC		 1841 bcmerror = dhdsdio_readshared(bus, &sdpcm_shared);
1842 if (bcmerror < 0)
cf2b4488
HP		 1843 goto done;
1844
1845 bcm_binit(&strbuf, data, size);
1846
1847 bcm_bprintf(&strbuf,
1848 "msgtrace address : 0x%08X\nconsole address : 0x%08X\n",
1849 sdpcm_shared.msgtrace_addr, sdpcm_shared.console_addr);
1850
1851 if ((sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
1852 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1853 * (Avoids conflict with real asserts for programmatic
1854 * parsing of output.)
1855 */
1856 bcm_bprintf(&strbuf, "Assrt not built in dongle\n");
1857 }
1858
1859 if ((sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP)) ==
1860 0) {
1861 /* NOTE: Misspelled assert is intentional - DO NOT FIX.
1862 * (Avoids conflict with real asserts for programmatic
1863 * parsing of output.)
1864 */
1865 bcm_bprintf(&strbuf, "No trap%s in dongle",
1866 (sdpcm_shared.flags & SDPCM_SHARED_ASSERT_BUILT)
1867 ? "/assrt" : "");
1868 } else {
1869 if (sdpcm_shared.flags & SDPCM_SHARED_ASSERT) {
1870 /* Download assert */
1871 bcm_bprintf(&strbuf, "Dongle assert");
1872 if (sdpcm_shared.assert_exp_addr != 0) {
1873 str[0] = '\0';
9b890325
JC		 1874 bcmerror = dhdsdio_membytes(bus, FALSE,
1875 sdpcm_shared.assert_exp_addr,
3fd79f7c 1876 (u8 *) str, maxstrlen);
9b890325 1877 if (bcmerror < 0)
cf2b4488
HP		 1878 goto done;
1879
1880 str[maxstrlen - 1] = '\0';
1881 bcm_bprintf(&strbuf, " expr \"%s\"", str);
1882 }
1883
1884 if (sdpcm_shared.assert_file_addr != 0) {
1885 str[0] = '\0';
9b890325
JC		 1886 bcmerror = dhdsdio_membytes(bus, FALSE,
1887 sdpcm_shared.assert_file_addr,
3fd79f7c 1888 (u8 *) str, maxstrlen);
9b890325 1889 if (bcmerror < 0)
cf2b4488
HP		 1890 goto done;
1891
1892 str[maxstrlen - 1] = '\0';
1893 bcm_bprintf(&strbuf, " file \"%s\"", str);
1894 }
1895
1896 bcm_bprintf(&strbuf, " line %d ",
1897 sdpcm_shared.assert_line);
1898 }
1899
1900 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
9b890325 1901 bcmerror = dhdsdio_membytes(bus, FALSE,
3fd79f7c 1902 sdpcm_shared.trap_addr, (u8 *)&tr,
9b890325
JC		 1903 sizeof(trap_t));
1904 if (bcmerror < 0)
cf2b4488
HP		 1905 goto done;
1906
1907 bcm_bprintf(&strbuf,
1908 "Dongle trap type 0x%x @ epc 0x%x, cpsr 0x%x, spsr 0x%x, sp 0x%x,"
1909 "lp 0x%x, rpc 0x%x Trap offset 0x%x, "
1910 "r0 0x%x, r1 0x%x, r2 0x%x, r3 0x%x, r4 0x%x, r5 0x%x, r6 0x%x, r7 0x%x\n",
1911 tr.type, tr.epc, tr.cpsr, tr.spsr, tr.r13,
1912 tr.r14, tr.pc, sdpcm_shared.trap_addr,
1913 tr.r0, tr.r1, tr.r2, tr.r3, tr.r4, tr.r5,
1914 tr.r6, tr.r7);
1915 }
1916 }
1917
1918 if (sdpcm_shared.flags & (SDPCM_SHARED_ASSERT | SDPCM_SHARED_TRAP))
1919 DHD_ERROR(("%s: %s\n", __func__, strbuf.origbuf));
1920
1921#ifdef DHD_DEBUG
1922 if (sdpcm_shared.flags & SDPCM_SHARED_TRAP) {
1923 /* Mem dump to a file on device */
1924 dhdsdio_mem_dump(bus);
1925 }
1926#endif /* DHD_DEBUG */
1927
1928done:
1929 if (mbuffer)
1930 MFREE(bus->dhd->osh, mbuffer, msize);
1931 if (str)
1932 MFREE(bus->dhd->osh, str, maxstrlen);
1933
1934 return bcmerror;
1935}
1936
1937static int dhdsdio_mem_dump(dhd_bus_t *bus)
1938{
1939 int ret = 0;
1940 int size; /* Full mem size */
1941 int start = 0; /* Start address */
1942 int read_size = 0; /* Read size of each iteration */
3fd79f7c 1943 u8 *buf = NULL, *databuf = NULL;
cf2b4488
HP		 1944
1945 /* Get full mem size */
1946 size = bus->ramsize;
1947 buf = MALLOC(bus->dhd->osh, size);
1948 if (!buf) {
1949 printf("%s: Out of memory (%d bytes)\n", __func__, size);
1950 return -1;
1951 }
1952
1953 /* Read mem content */
1954 printf("Dump dongle memory");
1955 databuf = buf;
1956 while (size) {
1957 read_size = MIN(MEMBLOCK, size);
1958 ret = dhdsdio_membytes(bus, FALSE, start, databuf, read_size);
1959 if (ret) {
1960 printf("%s: Error membytes %d\n", __func__, ret);
1961 if (buf)
1962 MFREE(bus->dhd->osh, buf, size);
1963 return -1;
1964 }
1965 printf(".");
1966
1967 /* Decrement size and increment start address */
1968 size -= read_size;
1969 start += read_size;
1970 databuf += read_size;
1971 }
1972 printf("Done\n");
1973
1974 /* free buf before return !!! */
1975 if (write_to_file(bus->dhd, buf, bus->ramsize)) {
1976 printf("%s: Error writing to files\n", __func__);
1977 return -1;
1978 }
1979
1980 /* buf free handled in write_to_file, not here */
1981 return 0;
1982}
1983
1984#define CONSOLE_LINE_MAX 192
1985
1986static int dhdsdio_readconsole(dhd_bus_t *bus)
1987{
1988 dhd_console_t *c = &bus->console;
3fd79f7c 1989 u8 line[CONSOLE_LINE_MAX], ch;
66cbd3ab 1990 u32 n, idx, addr;
cf2b4488
HP		 1991 int rv;
1992
1993 /* Don't do anything until FWREADY updates console address */
1994 if (bus->console_addr == 0)
1995 return 0;
1996
1997 /* Read console log struct */
1998 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, log);
3fd79f7c 1999 rv = dhdsdio_membytes(bus, FALSE, addr, (u8 *)&c->log,
9b890325
JC		 2000 sizeof(c->log));
2001 if (rv < 0)
cf2b4488
HP		 2002 return rv;
2003
2004 /* Allocate console buffer (one time only) */
2005 if (c->buf == NULL) {
2006 c->bufsize = ltoh32(c->log.buf_size);
9b890325
JC		 2007 c->buf = MALLOC(bus->dhd->osh, c->bufsize);
2008 if (c->buf == NULL)
cf2b4488
HP		 2009 return BCME_NOMEM;
2010 }
2011
2012 idx = ltoh32(c->log.idx);
2013
2014 /* Protect against corrupt value */
2015 if (idx > c->bufsize)
2016 return BCME_ERROR;
2017
2018 /* Skip reading the console buffer if the index pointer
2019 has not moved */
2020 if (idx == c->last)
2021 return BCME_OK;
2022
2023 /* Read the console buffer */
2024 addr = ltoh32(c->log.buf);
2025 rv = dhdsdio_membytes(bus, FALSE, addr, c->buf, c->bufsize);
2026 if (rv < 0)
2027 return rv;
2028
2029 while (c->last != idx) {
2030 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2031 if (c->last == idx) {
2032 /* This would output a partial line.
2033 * Instead, back up
2034 * the buffer pointer and output this
2035 * line next time around.
2036 */
2037 if (c->last >= n)
2038 c->last -= n;
2039 else
2040 c->last = c->bufsize - n;
2041 goto break2;
2042 }
2043 ch = c->buf[c->last];
2044 c->last = (c->last + 1) % c->bufsize;
2045 if (ch == '\n')
2046 break;
2047 line[n] = ch;
2048 }
2049
2050 if (n > 0) {
2051 if (line[n - 1] == '\r')
2052 n--;
2053 line[n] = 0;
2054 printf("CONSOLE: %s\n", line);
2055 }
2056 }
2057break2:
2058
2059 return BCME_OK;
2060}
2061#endif /* DHD_DEBUG */
2062
2063int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
2064{
2065 int bcmerror = BCME_OK;
2066
2067 DHD_TRACE(("%s: Enter\n", __func__));
2068
2069 /* Basic sanity checks */
2070 if (bus->dhd->up) {
2071 bcmerror = BCME_NOTDOWN;
2072 goto err;
2073 }
2074 if (!len) {
2075 bcmerror = BCME_BUFTOOSHORT;
2076 goto err;
2077 }
2078
2079 /* Free the old ones and replace with passed variables */
2080 if (bus->vars)
2081 MFREE(bus->dhd->osh, bus->vars, bus->varsz);
2082
2083 bus->vars = MALLOC(bus->dhd->osh, len);
2084 bus->varsz = bus->vars ? len : 0;
2085 if (bus->vars == NULL) {
2086 bcmerror = BCME_NOMEM;
2087 goto err;
2088 }
2089
2090 /* Copy the passed variables, which should include the
2091 terminating double-null */
2092 bcopy(arg, bus->vars, bus->varsz);
2093err:
2094 return bcmerror;
2095}
2096
2097static int
66cbd3ab 2098dhdsdio_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, u32 actionid,
cf2b4488
HP		 2099 const char *name, void *params, int plen, void *arg, int len,
2100 int val_size)
2101{
2102 int bcmerror = 0;
3e26416e 2103 s32 int_val = 0;
cf2b4488
HP		 2104 bool bool_val = 0;
2105
2106 DHD_TRACE(("%s: Enter, action %d name %s params %p plen %d arg %p "
2107 "len %d val_size %d\n",
2108 __func__, actionid, name, params, plen, arg, len, val_size));
2109
2110 bcmerror = bcm_iovar_lencheck(vi, arg, len, IOV_ISSET(actionid));
2111 if (bcmerror != 0)
2112 goto exit;
2113
2114 if (plen >= (int)sizeof(int_val))
2115 bcopy(params, &int_val, sizeof(int_val));
2116
2117 bool_val = (int_val != 0) ? TRUE : FALSE;
2118
2119 /* Some ioctls use the bus */
2120 dhd_os_sdlock(bus->dhd);
2121
2122 /* Check if dongle is in reset. If so, only allow DEVRESET iovars */
2123 if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
2124 actionid == IOV_GVAL(IOV_DEVRESET))) {
2125 bcmerror = BCME_NOTREADY;
2126 goto exit;
2127 }
2128
2129 /* Handle sleep stuff before any clock mucking */
2130 if (vi->varid == IOV_SLEEP) {
2131 if (IOV_ISSET(actionid)) {
2132 bcmerror = dhdsdio_bussleep(bus, bool_val);
2133 } else {
3e26416e 2134 int_val = (s32) bus->sleeping;
cf2b4488
HP		 2135 bcopy(&int_val, arg, val_size);
2136 }
2137 goto exit;
2138 }
2139
2140 /* Request clock to allow SDIO accesses */
2141 if (!bus->dhd->dongle_reset) {
2142 BUS_WAKE(bus);
2143 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2144 }
2145
2146 switch (actionid) {
2147 case IOV_GVAL(IOV_INTR):
3e26416e 2148 int_val = (s32) bus->intr;
cf2b4488
HP		 2149 bcopy(&int_val, arg, val_size);
2150 break;
2151
2152 case IOV_SVAL(IOV_INTR):
2153 bus->intr = bool_val;
2154 bus->intdis = FALSE;
2155 if (bus->dhd->up) {
2156 if (bus->intr) {
2157 DHD_INTR(("%s: enable SDIO device interrupts\n",
2158 __func__));
2159 bcmsdh_intr_enable(bus->sdh);
2160 } else {
2161 DHD_INTR(("%s: disable SDIO interrupts\n",
2162 __func__));
2163 bcmsdh_intr_disable(bus->sdh);
2164 }
2165 }
2166 break;
2167
2168 case IOV_GVAL(IOV_POLLRATE):
3e26416e 2169 int_val = (s32) bus->pollrate;
cf2b4488
HP		 2170 bcopy(&int_val, arg, val_size);
2171 break;
2172
2173 case IOV_SVAL(IOV_POLLRATE):
2174 bus->pollrate = (uint) int_val;
2175 bus->poll = (bus->pollrate != 0);
2176 break;
2177
2178 case IOV_GVAL(IOV_IDLETIME):
2179 int_val = bus->idletime;
2180 bcopy(&int_val, arg, val_size);
2181 break;
2182
2183 case IOV_SVAL(IOV_IDLETIME):
2184 if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
2185 bcmerror = BCME_BADARG;
2186 else
2187 bus->idletime = int_val;
2188 break;
2189
2190 case IOV_GVAL(IOV_IDLECLOCK):
3e26416e 2191 int_val = (s32) bus->idleclock;
cf2b4488
HP		 2192 bcopy(&int_val, arg, val_size);
2193 break;
2194
2195 case IOV_SVAL(IOV_IDLECLOCK):
2196 bus->idleclock = int_val;
2197 break;
2198
2199 case IOV_GVAL(IOV_SD1IDLE):
3e26416e 2200 int_val = (s32) sd1idle;
cf2b4488
HP		 2201 bcopy(&int_val, arg, val_size);
2202 break;
2203
2204 case IOV_SVAL(IOV_SD1IDLE):
2205 sd1idle = bool_val;
2206 break;
2207
2208 case IOV_SVAL(IOV_MEMBYTES):
2209 case IOV_GVAL(IOV_MEMBYTES):
2210 {
66cbd3ab 2211 u32 address;
cf2b4488 2212 uint size, dsize;
3fd79f7c 2213 u8 *data;
cf2b4488
HP		 2214
2215 bool set = (actionid == IOV_SVAL(IOV_MEMBYTES));
2216
2217 ASSERT(plen >= 2 * sizeof(int));
2218
66cbd3ab 2219 address = (u32) int_val;
cf2b4488
HP		 2220 bcopy((char *)params + sizeof(int_val), &int_val,
2221 sizeof(int_val));
2222 size = (uint) int_val;
2223
2224 /* Do some validation */
2225 dsize = set ? plen - (2 * sizeof(int)) : len;
2226 if (dsize < size) {
2227 DHD_ERROR(("%s: error on %s membytes, addr "
2228 "0x%08x size %d dsize %d\n",
2229 __func__, (set ? "set" : "get"),
2230 address, size, dsize));
2231 bcmerror = BCME_BADARG;
2232 break;
2233 }
2234
2235 DHD_INFO(("%s: Request to %s %d bytes at address "
2236 "0x%08x\n",
2237 __func__, (set ? "write" : "read"), size, address));
2238
2239 /* If we know about SOCRAM, check for a fit */
2240 if ((bus->orig_ramsize) &&
2241 ((address > bus->orig_ramsize)
2242 || (address + size > bus->orig_ramsize))) {
2243 DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
2244 "bytes at 0x%08x\n",
2245 __func__, bus->orig_ramsize, size, address));
2246 bcmerror = BCME_BADARG;
2247 break;
2248 }
2249
2250 /* Generate the actual data pointer */
2251 data =
3fd79f7c
GKH		 2252 set ? (u8 *) params +
2253 2 * sizeof(int) : (u8 *) arg;
cf2b4488
HP		 2254
2255 /* Call to do the transfer */
2256 bcmerror =
2257 dhdsdio_membytes(bus, set, address, data, size);
2258
2259 break;
2260 }
2261
2262 case IOV_GVAL(IOV_MEMSIZE):
3e26416e 2263 int_val = (s32) bus->ramsize;
cf2b4488
HP		 2264 bcopy(&int_val, arg, val_size);
2265 break;
2266
2267 case IOV_GVAL(IOV_SDIOD_DRIVE):
3e26416e 2268 int_val = (s32) dhd_sdiod_drive_strength;
cf2b4488
HP		 2269 bcopy(&int_val, arg, val_size);
2270 break;
2271
2272 case IOV_SVAL(IOV_SDIOD_DRIVE):
2273 dhd_sdiod_drive_strength = int_val;
2274 si_sdiod_drive_strength_init(bus->sih, bus->dhd->osh,
2275 dhd_sdiod_drive_strength);
2276 break;
2277
2278 case IOV_SVAL(IOV_DOWNLOAD):
2279 bcmerror = dhdsdio_download_state(bus, bool_val);
2280 break;
2281
2282 case IOV_SVAL(IOV_VARS):
2283 bcmerror = dhdsdio_downloadvars(bus, arg, len);
2284 break;
2285
2286 case IOV_GVAL(IOV_READAHEAD):
3e26416e 2287 int_val = (s32) dhd_readahead;
cf2b4488
HP		 2288 bcopy(&int_val, arg, val_size);
2289 break;
2290
2291 case IOV_SVAL(IOV_READAHEAD):
2292 if (bool_val && !dhd_readahead)
2293 bus->nextlen = 0;
2294 dhd_readahead = bool_val;
2295 break;
2296
2297 case IOV_GVAL(IOV_SDRXCHAIN):
3e26416e 2298 int_val = (s32) bus->use_rxchain;
cf2b4488
HP		 2299 bcopy(&int_val, arg, val_size);
2300 break;
2301
2302 case IOV_SVAL(IOV_SDRXCHAIN):
2303 if (bool_val && !bus->sd_rxchain)
2304 bcmerror = BCME_UNSUPPORTED;
2305 else
2306 bus->use_rxchain = bool_val;
2307 break;
2308 case IOV_GVAL(IOV_ALIGNCTL):
3e26416e 2309 int_val = (s32) dhd_alignctl;
cf2b4488
HP		 2310 bcopy(&int_val, arg, val_size);
2311 break;
2312
2313 case IOV_SVAL(IOV_ALIGNCTL):
2314 dhd_alignctl = bool_val;
2315 break;
2316
2317 case IOV_GVAL(IOV_SDALIGN):
2318 int_val = DHD_SDALIGN;
2319 bcopy(&int_val, arg, val_size);
2320 break;
2321
2322#ifdef DHD_DEBUG
2323 case IOV_GVAL(IOV_VARS):
2324 if (bus->varsz < (uint) len)
2325 bcopy(bus->vars, arg, bus->varsz);
2326 else
2327 bcmerror = BCME_BUFTOOSHORT;
2328 break;
2329#endif /* DHD_DEBUG */
2330
2331#ifdef DHD_DEBUG
2332 case IOV_GVAL(IOV_SDREG):
2333 {
2334 sdreg_t *sd_ptr;
66cbd3ab 2335 u32 addr, size;
cf2b4488
HP		 2336
2337 sd_ptr = (sdreg_t *) params;
2338
2339 addr = (uintptr) bus->regs + sd_ptr->offset;
2340 size = sd_ptr->func;
3e26416e 2341 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
cf2b4488
HP		 2342 if (bcmsdh_regfail(bus->sdh))
2343 bcmerror = BCME_SDIO_ERROR;
3e26416e 2344 bcopy(&int_val, arg, sizeof(s32));
cf2b4488
HP		 2345 break;
2346 }
2347
2348 case IOV_SVAL(IOV_SDREG):
2349 {
2350 sdreg_t *sd_ptr;
66cbd3ab 2351 u32 addr, size;
cf2b4488
HP		 2352
2353 sd_ptr = (sdreg_t *) params;
2354
2355 addr = (uintptr) bus->regs + sd_ptr->offset;
2356 size = sd_ptr->func;
2357 bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
2358 if (bcmsdh_regfail(bus->sdh))
2359 bcmerror = BCME_SDIO_ERROR;
2360 break;
2361 }
2362
2363 /* Same as above, but offset is not backplane
2364 (not SDIO core) */
2365 case IOV_GVAL(IOV_SBREG):
2366 {
2367 sdreg_t sdreg;
66cbd3ab 2368 u32 addr, size;
cf2b4488
HP		 2369
2370 bcopy(params, &sdreg, sizeof(sdreg));
2371
2372 addr = SI_ENUM_BASE + sdreg.offset;
2373 size = sdreg.func;
3e26416e 2374 int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
cf2b4488
HP		 2375 if (bcmsdh_regfail(bus->sdh))
2376 bcmerror = BCME_SDIO_ERROR;
3e26416e 2377 bcopy(&int_val, arg, sizeof(s32));
cf2b4488
HP		 2378 break;
2379 }
2380
2381 case IOV_SVAL(IOV_SBREG):
2382 {
2383 sdreg_t sdreg;
66cbd3ab 2384 u32 addr, size;
cf2b4488
HP		 2385
2386 bcopy(params, &sdreg, sizeof(sdreg));
2387
2388 addr = SI_ENUM_BASE + sdreg.offset;
2389 size = sdreg.func;
2390 bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
2391 if (bcmsdh_regfail(bus->sdh))
2392 bcmerror = BCME_SDIO_ERROR;
2393 break;
2394 }
2395
2396 case IOV_GVAL(IOV_SDCIS):
2397 {
2398 *(char *)arg = 0;
2399
2400 bcmstrcat(arg, "\nFunc 0\n");
2401 bcmsdh_cis_read(bus->sdh, 0x10,
3fd79f7c 2402 (u8 *) arg + strlen(arg),
cf2b4488
HP		 2403 SBSDIO_CIS_SIZE_LIMIT);
2404 bcmstrcat(arg, "\nFunc 1\n");
2405 bcmsdh_cis_read(bus->sdh, 0x11,
3fd79f7c 2406 (u8 *) arg + strlen(arg),
cf2b4488
HP		 2407 SBSDIO_CIS_SIZE_LIMIT);
2408 bcmstrcat(arg, "\nFunc 2\n");
2409 bcmsdh_cis_read(bus->sdh, 0x12,
3fd79f7c 2410 (u8 *) arg + strlen(arg),
cf2b4488
HP		 2411 SBSDIO_CIS_SIZE_LIMIT);
2412 break;
2413 }
2414
2415 case IOV_GVAL(IOV_FORCEEVEN):
3e26416e 2416 int_val = (s32) forcealign;
cf2b4488
HP		 2417 bcopy(&int_val, arg, val_size);
2418 break;
2419
2420 case IOV_SVAL(IOV_FORCEEVEN):
2421 forcealign = bool_val;
2422 break;
2423
2424 case IOV_GVAL(IOV_TXBOUND):
3e26416e 2425 int_val = (s32) dhd_txbound;
cf2b4488
HP		 2426 bcopy(&int_val, arg, val_size);
2427 break;
2428
2429 case IOV_SVAL(IOV_TXBOUND):
2430 dhd_txbound = (uint) int_val;
2431 break;
2432
2433 case IOV_GVAL(IOV_RXBOUND):
3e26416e 2434 int_val = (s32) dhd_rxbound;
cf2b4488
HP		 2435 bcopy(&int_val, arg, val_size);
2436 break;
2437
2438 case IOV_SVAL(IOV_RXBOUND):
2439 dhd_rxbound = (uint) int_val;
2440 break;
2441
2442 case IOV_GVAL(IOV_TXMINMAX):
3e26416e 2443 int_val = (s32) dhd_txminmax;
cf2b4488
HP		 2444 bcopy(&int_val, arg, val_size);
2445 break;
2446
2447 case IOV_SVAL(IOV_TXMINMAX):
2448 dhd_txminmax = (uint) int_val;
2449 break;
2450#endif /* DHD_DEBUG */
2451
2452#ifdef SDTEST
2453 case IOV_GVAL(IOV_EXTLOOP):
3e26416e 2454 int_val = (s32) bus->ext_loop;
cf2b4488
HP		 2455 bcopy(&int_val, arg, val_size);
2456 break;
2457
2458 case IOV_SVAL(IOV_EXTLOOP):
2459 bus->ext_loop = bool_val;
2460 break;
2461
2462 case IOV_GVAL(IOV_PKTGEN):
2463 bcmerror = dhdsdio_pktgen_get(bus, arg);
2464 break;
2465
2466 case IOV_SVAL(IOV_PKTGEN):
2467 bcmerror = dhdsdio_pktgen_set(bus, arg);
2468 break;
2469#endif /* SDTEST */
2470
2471 case IOV_SVAL(IOV_DEVRESET):
2472 DHD_TRACE(("%s: Called set IOV_DEVRESET=%d dongle_reset=%d "
2473 "busstate=%d\n",
2474 __func__, bool_val, bus->dhd->dongle_reset,
2475 bus->dhd->busstate));
2476
2477 ASSERT(bus->dhd->osh);
2478 /* ASSERT(bus->cl_devid); */
2479
3fd79f7c 2480 dhd_bus_devreset(bus->dhd, (u8) bool_val);
cf2b4488
HP		 2481
2482 break;
2483
2484 case IOV_GVAL(IOV_DEVRESET):
2485 DHD_TRACE(("%s: Called get IOV_DEVRESET\n", __func__));
2486
2487 /* Get its status */
2488 int_val = (bool) bus->dhd->dongle_reset;
2489 bcopy(&int_val, arg, val_size);
2490
2491 break;
2492
2493 default:
2494 bcmerror = BCME_UNSUPPORTED;
2495 break;
2496 }
2497
2498exit:
2499 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2500 bus->activity = FALSE;
2501 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
2502 }
2503
2504 dhd_os_sdunlock(bus->dhd);
2505
2506 if (actionid == IOV_SVAL(IOV_DEVRESET) && bool_val == FALSE)
2507 dhd_preinit_ioctls((dhd_pub_t *) bus->dhd);
2508
2509 return bcmerror;
2510}
2511
2512static int dhdsdio_write_vars(dhd_bus_t *bus)
2513{
2514 int bcmerror = 0;
66cbd3ab
GKH		 2515 u32 varsize;
2516 u32 varaddr;
3fd79f7c 2517 u8 *vbuffer;
66cbd3ab 2518 u32 varsizew;
cf2b4488
HP		 2519#ifdef DHD_DEBUG
2520 char *nvram_ularray;
2521#endif /* DHD_DEBUG */
2522
2523 /* Even if there are no vars are to be written, we still
2524 need to set the ramsize. */
2525 varsize = bus->varsz ? ROUNDUP(bus->varsz, 4) : 0;
2526 varaddr = (bus->ramsize - 4) - varsize;
2527
2528 if (bus->vars) {
3fd79f7c 2529 vbuffer = (u8 *) MALLOC(bus->dhd->osh, varsize);
cf2b4488
HP		 2530 if (!vbuffer)
2531 return BCME_NOMEM;
2532
2533 bzero(vbuffer, varsize);
2534 bcopy(bus->vars, vbuffer, bus->varsz);
2535
2536 /* Write the vars list */
2537 bcmerror =
2538 dhdsdio_membytes(bus, TRUE, varaddr, vbuffer, varsize);
2539#ifdef DHD_DEBUG
2540 /* Verify NVRAM bytes */
2541 DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
2542 nvram_ularray = (char *)MALLOC(bus->dhd->osh, varsize);
2543 if (!nvram_ularray)
2544 return BCME_NOMEM;
2545
2546 /* Upload image to verify downloaded contents. */
2547 memset(nvram_ularray, 0xaa, varsize);
2548
2549 /* Read the vars list to temp buffer for comparison */
2550 bcmerror =
2551 dhdsdio_membytes(bus, FALSE, varaddr, nvram_ularray,
2552 varsize);
2553 if (bcmerror) {
2554 DHD_ERROR(("%s: error %d on reading %d nvram bytes at "
2555 "0x%08x\n", __func__, bcmerror, varsize, varaddr));
2556 }
2557 /* Compare the org NVRAM with the one read from RAM */
2558 if (memcmp(vbuffer, nvram_ularray, varsize)) {
2559 DHD_ERROR(("%s: Downloaded NVRAM image is corrupted.\n",
2560 __func__));
2561 } else
2562 DHD_ERROR(("%s: Download/Upload/Compare of NVRAM ok.\n",
2563 __func__));
2564
2565 MFREE(bus->dhd->osh, nvram_ularray, varsize);
2566#endif /* DHD_DEBUG */
2567
2568 MFREE(bus->dhd->osh, vbuffer, varsize);
2569 }
2570
2571 /* adjust to the user specified RAM */
2572 DHD_INFO(("Physical memory size: %d, usable memory size: %d\n",
2573 bus->orig_ramsize, bus->ramsize));
2574 DHD_INFO(("Vars are at %d, orig varsize is %d\n", varaddr, varsize));
2575 varsize = ((bus->orig_ramsize - 4) - varaddr);
2576
2577 /*
2578 * Determine the length token:
2579 * Varsize, converted to words, in lower 16-bits, checksum
2580 * in upper 16-bits.
2581 */
2582 if (bcmerror) {
2583 varsizew = 0;
2584 } else {
2585 varsizew = varsize / 4;
2586 varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
2587 varsizew = htol32(varsizew);
2588 }
2589
2590 DHD_INFO(("New varsize is %d, length token=0x%08x\n", varsize,
2591 varsizew));
2592
2593 /* Write the length token to the last word */
2594 bcmerror = dhdsdio_membytes(bus, TRUE, (bus->orig_ramsize - 4),
3fd79f7c 2595 (u8 *)&varsizew, 4);
cf2b4488
HP		 2596
2597 return bcmerror;
2598}
2599
2600static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
2601{
2602 uint retries;
2603 int bcmerror = 0;
2604
2605 /* To enter download state, disable ARM and reset SOCRAM.
2606 * To exit download state, simply reset ARM (default is RAM boot).
2607 */
2608 if (enter) {
2609
2610 bus->alp_only = TRUE;
2611
2612 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2613 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2614 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2615 bcmerror = BCME_ERROR;
2616 goto fail;
2617 }
2618
2619 si_core_disable(bus->sih, 0);
2620 if (bcmsdh_regfail(bus->sdh)) {
2621 bcmerror = BCME_SDIO_ERROR;
2622 goto fail;
2623 }
2624
2625 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2626 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2627 __func__));
2628 bcmerror = BCME_ERROR;
2629 goto fail;
2630 }
2631
2632 si_core_reset(bus->sih, 0, 0);
2633 if (bcmsdh_regfail(bus->sdh)) {
2634 DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
2635 __func__));
2636 bcmerror = BCME_SDIO_ERROR;
2637 goto fail;
2638 }
2639
2640 /* Clear the top bit of memory */
2641 if (bus->ramsize) {
66cbd3ab 2642 u32 zeros = 0;
cf2b4488 2643 dhdsdio_membytes(bus, TRUE, bus->ramsize - 4,
3fd79f7c 2644 (u8 *)&zeros, 4);
cf2b4488
HP		 2645 }
2646 } else {
2647 if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
2648 DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
2649 __func__));
2650 bcmerror = BCME_ERROR;
2651 goto fail;
2652 }
2653
2654 if (!si_iscoreup(bus->sih)) {
2655 DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
2656 __func__));
2657 bcmerror = BCME_ERROR;
2658 goto fail;
2659 }
2660
2661 bcmerror = dhdsdio_write_vars(bus);
2662 if (bcmerror) {
2663 DHD_ERROR(("%s: no vars written to RAM\n", __func__));
2664 bcmerror = 0;
2665 }
2666
2667 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
2668 !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
2669 DHD_ERROR(("%s: Can't change back to SDIO core?\n",
2670 __func__));
2671 bcmerror = BCME_ERROR;
2672 goto fail;
2673 }
2674 W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
2675
2676 if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
2677 !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
2678 DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
2679 bcmerror = BCME_ERROR;
2680 goto fail;
2681 }
2682
2683 si_core_reset(bus->sih, 0, 0);
2684 if (bcmsdh_regfail(bus->sdh)) {
2685 DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
2686 __func__));
2687 bcmerror = BCME_SDIO_ERROR;
2688 goto fail;
2689 }
2690
2691 /* Allow HT Clock now that the ARM is running. */
2692 bus->alp_only = FALSE;
2693
2694 bus->dhd->busstate = DHD_BUS_LOAD;
2695 }
2696
2697fail:
2698 /* Always return to SDIOD core */
2699 if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
2700 si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2701
2702 return bcmerror;
2703}
2704
2705int
2706dhd_bus_iovar_op(dhd_pub_t *dhdp, const char *name,
2707 void *params, int plen, void *arg, int len, bool set)
2708{
2709 dhd_bus_t *bus = dhdp->bus;
2710 const bcm_iovar_t *vi = NULL;
2711 int bcmerror = 0;
2712 int val_size;
66cbd3ab 2713 u32 actionid;
cf2b4488
HP		 2714
2715 DHD_TRACE(("%s: Enter\n", __func__));
2716
2717 ASSERT(name);
2718 ASSERT(len >= 0);
2719
2720 /* Get MUST have return space */
2721 ASSERT(set || (arg && len));
2722
2723 /* Set does NOT take qualifiers */
2724 ASSERT(!set || (!params && !plen));
2725
2726 /* Look up var locally; if not found pass to host driver */
2727 vi = bcm_iovar_lookup(dhdsdio_iovars, name);
2728 if (vi == NULL) {
2729 dhd_os_sdlock(bus->dhd);
2730
2731 BUS_WAKE(bus);
2732
2733 /* Turn on clock in case SD command needs backplane */
2734 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2735
2736 bcmerror =
2737 bcmsdh_iovar_op(bus->sdh, name, params, plen, arg, len,
2738 set);
2739
2740 /* Check for bus configuration changes of interest */
2741
2742 /* If it was divisor change, read the new one */
2743 if (set && strcmp(name, "sd_divisor") == 0) {
2744 if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
3e26416e 2745 &bus->sd_divisor, sizeof(s32),
cf2b4488
HP		 2746 FALSE) != BCME_OK) {
2747 bus->sd_divisor = -1;
2748 DHD_ERROR(("%s: fail on %s get\n", __func__,
2749 name));
2750 } else {
2751 DHD_INFO(("%s: noted %s update, value now %d\n",
2752 __func__, name, bus->sd_divisor));
2753 }
2754 }
2755 /* If it was a mode change, read the new one */
2756 if (set && strcmp(name, "sd_mode") == 0) {
2757 if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
3e26416e 2758 &bus->sd_mode, sizeof(s32),
cf2b4488
HP		 2759 FALSE) != BCME_OK) {
2760 bus->sd_mode = -1;
2761 DHD_ERROR(("%s: fail on %s get\n", __func__,
2762 name));
2763 } else {
2764 DHD_INFO(("%s: noted %s update, value now %d\n",
2765 __func__, name, bus->sd_mode));
2766 }
2767 }
2768 /* Similar check for blocksize change */
2769 if (set && strcmp(name, "sd_blocksize") == 0) {
3e26416e 2770 s32 fnum = 2;
cf2b4488 2771 if (bcmsdh_iovar_op
3e26416e
GKH		 2772 (bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
2773 &bus->blocksize, sizeof(s32),
cf2b4488
HP		 2774 FALSE) != BCME_OK) {
2775 bus->blocksize = 0;
2776 DHD_ERROR(("%s: fail on %s get\n", __func__,
2777 "sd_blocksize"));
2778 } else {
2779 DHD_INFO(("%s: noted %s update, value now %d\n",
2780 __func__, "sd_blocksize",
2781 bus->blocksize));
2782 }
2783 }
2784 bus->roundup = MIN(max_roundup, bus->blocksize);
2785
2786 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
2787 bus->activity = FALSE;
2788 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
2789 }
2790
2791 dhd_os_sdunlock(bus->dhd);
2792 goto exit;
2793 }
2794
2795 DHD_CTL(("%s: %s %s, len %d plen %d\n", __func__,
2796 name, (set ? "set" : "get"), len, plen));
2797
2798 /* set up 'params' pointer in case this is a set command so that
2799 * the convenience int and bool code can be common to set and get
2800 */
2801 if (params == NULL) {
2802 params = arg;
2803 plen = len;
2804 }
2805
2806 if (vi->type == IOVT_VOID)
2807 val_size = 0;
2808 else if (vi->type == IOVT_BUFFER)
2809 val_size = len;
2810 else
2811 /* all other types are integer sized */
2812 val_size = sizeof(int);
2813
2814 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid);
2815 bcmerror =
2816 dhdsdio_doiovar(bus, vi, actionid, name, params, plen, arg, len,
2817 val_size);
2818
2819exit:
2820 return bcmerror;
2821}
2822
2823void dhd_bus_stop(struct dhd_bus *bus, bool enforce_mutex)
2824{
2825 osl_t *osh = bus->dhd->osh;
66cbd3ab 2826 u32 local_hostintmask;
3fd79f7c 2827 u8 saveclk;
cf2b4488
HP		 2828 uint retries;
2829 int err;
2830
2831 DHD_TRACE(("%s: Enter\n", __func__));
2832
2833 if (enforce_mutex)
2834 dhd_os_sdlock(bus->dhd);
2835
2836 BUS_WAKE(bus);
2837
2838 /* Enable clock for device interrupts */
2839 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2840
2841 /* Disable and clear interrupts at the chip level also */
2842 W_SDREG(0, &bus->regs->hostintmask, retries);
2843 local_hostintmask = bus->hostintmask;
2844 bus->hostintmask = 0;
2845
2846 /* Change our idea of bus state */
2847 bus->dhd->busstate = DHD_BUS_DOWN;
2848
2849 /* Force clocks on backplane to be sure F2 interrupt propagates */
2850 saveclk =
2851 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2852 &err);
2853 if (!err) {
2854 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2855 (saveclk | SBSDIO_FORCE_HT), &err);
2856 }
2857 if (err) {
2858 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2859 __func__, err));
2860 }
2861
2862 /* Turn off the bus (F2), free any pending packets */
2863 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2864 bcmsdh_intr_disable(bus->sdh);
2865 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
2866 SDIO_FUNC_ENABLE_1, NULL);
2867
2868 /* Clear any pending interrupts now that F2 is disabled */
2869 W_SDREG(local_hostintmask, &bus->regs->intstatus, retries);
2870
2871 /* Turn off the backplane clock (only) */
2872 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
2873
2874 /* Clear the data packet queues */
2875 pktq_flush(osh, &bus->txq, TRUE);
2876
2877 /* Clear any held glomming stuff */
2878 if (bus->glomd)
2879 PKTFREE(osh, bus->glomd, FALSE);
2880
2881 if (bus->glom)
2882 PKTFREE(osh, bus->glom, FALSE);
2883
2884 bus->glom = bus->glomd = NULL;
2885
2886 /* Clear rx control and wake any waiters */
2887 bus->rxlen = 0;
2888 dhd_os_ioctl_resp_wake(bus->dhd);
2889
2890 /* Reset some F2 state stuff */
2891 bus->rxskip = FALSE;
2892 bus->tx_seq = bus->rx_seq = 0;
2893
2894 if (enforce_mutex)
2895 dhd_os_sdunlock(bus->dhd);
2896}
2897
2898int dhd_bus_init(dhd_pub_t *dhdp, bool enforce_mutex)
2899{
2900 dhd_bus_t *bus = dhdp->bus;
2901 dhd_timeout_t tmo;
2902 uint retries = 0;
3fd79f7c 2903 u8 ready, enable;
cf2b4488 2904 int err, ret = 0;
3fd79f7c 2905 u8 saveclk;
cf2b4488
HP		 2906
2907 DHD_TRACE(("%s: Enter\n", __func__));
2908
2909 ASSERT(bus->dhd);
2910 if (!bus->dhd)
2911 return 0;
2912
2913 if (enforce_mutex)
2914 dhd_os_sdlock(bus->dhd);
2915
2916 /* Make sure backplane clock is on, needed to generate F2 interrupt */
2917 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
2918 if (bus->clkstate != CLK_AVAIL)
2919 goto exit;
2920
2921 /* Force clocks on backplane to be sure F2 interrupt propagates */
2922 saveclk =
2923 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2924 &err);
2925 if (!err) {
2926 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2927 (saveclk | SBSDIO_FORCE_HT), &err);
2928 }
2929 if (err) {
2930 DHD_ERROR(("%s: Failed to force clock for F2: err %d\n",
2931 __func__, err));
2932 goto exit;
2933 }
2934
2935 /* Enable function 2 (frame transfers) */
2936 W_SDREG((SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT),
2937 &bus->regs->tosbmailboxdata, retries);
2938 enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
2939
2940 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable, NULL);
2941
2942 /* Give the dongle some time to do its thing and set IOR2 */
2943 dhd_timeout_start(&tmo, DHD_WAIT_F2RDY * 1000);
2944
2945 ready = 0;
2946 while (ready != enable && !dhd_timeout_expired(&tmo))
2947 ready =
2948 bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IORDY,
2949 NULL);
2950
2951 DHD_INFO(("%s: enable 0x%02x, ready 0x%02x (waited %uus)\n",
2952 __func__, enable, ready, tmo.elapsed));
2953
2954 /* If F2 successfully enabled, set core and enable interrupts */
2955 if (ready == enable) {
2956 /* Make sure we're talking to the core. */
2957 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
2958 if (!(bus->regs))
2959 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
2960
2961 /* Set up the interrupt mask and enable interrupts */
2962 bus->hostintmask = HOSTINTMASK;
2963 W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
2964
2965 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
3fd79f7c 2966 (u8) watermark, &err);
cf2b4488
HP		 2967
2968 /* Set bus state according to enable result */
2969 dhdp->busstate = DHD_BUS_DATA;
2970
2971 /* bcmsdh_intr_unmask(bus->sdh); */
2972
2973 bus->intdis = FALSE;
2974 if (bus->intr) {
2975 DHD_INTR(("%s: enable SDIO device interrupts\n",
2976 __func__));
2977 bcmsdh_intr_enable(bus->sdh);
2978 } else {
2979 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
2980 bcmsdh_intr_disable(bus->sdh);
2981 }
2982
2983 }
2984
2985 else {
2986 /* Disable F2 again */
2987 enable = SDIO_FUNC_ENABLE_1;
2988 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, enable,
2989 NULL);
2990 }
2991
2992 /* Restore previous clock setting */
2993 bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
2994 saveclk, &err);
2995
2996 /* If we didn't come up, turn off backplane clock */
2997 if (dhdp->busstate != DHD_BUS_DATA)
2998 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
2999
3000exit:
3001 if (enforce_mutex)
3002 dhd_os_sdunlock(bus->dhd);
3003
3004 return ret;
3005}
3006
3007static void dhdsdio_rxfail(dhd_bus_t *bus, bool abort, bool rtx)
3008{
3009 bcmsdh_info_t *sdh = bus->sdh;
3010 sdpcmd_regs_t *regs = bus->regs;
3011 uint retries = 0;
7d4df48e 3012 u16 lastrbc;
3fd79f7c 3013 u8 hi, lo;
cf2b4488
HP		 3014 int err;
3015
3016 DHD_ERROR(("%s: %sterminate frame%s\n", __func__,
3017 (abort ? "abort command, " : ""),
3018 (rtx ? ", send NAK" : "")));
3019
3020 if (abort)
3021 bcmsdh_abort(sdh, SDIO_FUNC_2);
3022
3023 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM,
3024 &err);
3025 bus->f1regdata++;
3026
3027 /* Wait until the packet has been flushed (device/FIFO stable) */
3028 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
3029 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCHI,
3030 NULL);
3031 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_RFRAMEBCLO,
3032 NULL);
3033 bus->f1regdata += 2;
3034
3035 if ((hi == 0) && (lo == 0))
3036 break;
3037
3038 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
3039 DHD_ERROR(("%s: count growing: last 0x%04x now "
3040 "0x%04x\n",
3041 __func__, lastrbc, ((hi << 8) + lo)));
3042 }
3043 lastrbc = (hi << 8) + lo;
3044 }
3045
3046 if (!retries) {
3047 DHD_ERROR(("%s: count never zeroed: last 0x%04x\n",
3048 __func__, lastrbc));
3049 } else {
3050 DHD_INFO(("%s: flush took %d iterations\n", __func__,
3051 (0xffff - retries)));
3052 }
3053
3054 if (rtx) {
3055 bus->rxrtx++;
3056 W_SDREG(SMB_NAK, &regs->tosbmailbox, retries);
3057 bus->f1regdata++;
3058 if (retries <= retry_limit)
3059 bus->rxskip = TRUE;
3060 }
3061
3062 /* Clear partial in any case */
3063 bus->nextlen = 0;
3064
3065 /* If we can't reach the device, signal failure */
3066 if (err || bcmsdh_regfail(sdh))
3067 bus->dhd->busstate = DHD_BUS_DOWN;
3068}
3069
3070static void
3fd79f7c 3071dhdsdio_read_control(dhd_bus_t *bus, u8 *hdr, uint len, uint doff)
cf2b4488
HP		 3072{
3073 bcmsdh_info_t *sdh = bus->sdh;
3074 uint rdlen, pad;
3075
3076 int sdret;
3077
3078 DHD_TRACE(("%s: Enter\n", __func__));
3079
3080 /* Control data already received in aligned rxctl */
3081 if ((bus->bus == SPI_BUS) && (!bus->usebufpool))
3082 goto gotpkt;
3083
3084 ASSERT(bus->rxbuf);
3085 /* Set rxctl for frame (w/optional alignment) */
3086 bus->rxctl = bus->rxbuf;
3087 if (dhd_alignctl) {
3088 bus->rxctl += firstread;
3089 pad = ((uintptr) bus->rxctl % DHD_SDALIGN);
3090 if (pad)
3091 bus->rxctl += (DHD_SDALIGN - pad);
3092 bus->rxctl -= firstread;
3093 }
3094 ASSERT(bus->rxctl >= bus->rxbuf);
3095
3096 /* Copy the already-read portion over */
3097 bcopy(hdr, bus->rxctl, firstread);
3098 if (len <= firstread)
3099 goto gotpkt;
3100
3101 /* Copy the full data pkt in gSPI case and process ioctl. */
3102 if (bus->bus == SPI_BUS) {
3103 bcopy(hdr, bus->rxctl, len);
3104 goto gotpkt;
3105 }
3106
3107 /* Raise rdlen to next SDIO block to avoid tail command */
3108 rdlen = len - firstread;
3109 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
3110 pad = bus->blocksize - (rdlen % bus->blocksize);
3111 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
3112 ((len + pad) < bus->dhd->maxctl))
3113 rdlen += pad;
3114 } else if (rdlen % DHD_SDALIGN) {
3115 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3116 }
3117
3118 /* Satisfy length-alignment requirements */
3119 if (forcealign && (rdlen & (ALIGNMENT - 1)))
3120 rdlen = ROUNDUP(rdlen, ALIGNMENT);
3121
3122 /* Drop if the read is too big or it exceeds our maximum */
3123 if ((rdlen + firstread) > bus->dhd->maxctl) {
3124 DHD_ERROR(("%s: %d-byte control read exceeds %d-byte buffer\n",
3125 __func__, rdlen, bus->dhd->maxctl));
3126 bus->dhd->rx_errors++;
3127 dhdsdio_rxfail(bus, FALSE, FALSE);
3128 goto done;
3129 }
3130
3131 if ((len - doff) > bus->dhd->maxctl) {
3132 DHD_ERROR(("%s: %d-byte ctl frame (%d-byte ctl data) exceeds "
3133 "%d-byte limit\n",
3134 __func__, len, (len - doff), bus->dhd->maxctl));
3135 bus->dhd->rx_errors++;
3136 bus->rx_toolong++;
3137 dhdsdio_rxfail(bus, FALSE, FALSE);
3138 goto done;
3139 }
3140
3141 /* Read remainder of frame body into the rxctl buffer */
3142 sdret =
3143 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
3144 (bus->rxctl + firstread), rdlen, NULL, NULL,
3145 NULL);
3146 bus->f2rxdata++;
3147 ASSERT(sdret != BCME_PENDING);
3148
3149 /* Control frame failures need retransmission */
3150 if (sdret < 0) {
3151 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3152 __func__, rdlen, sdret));
3153 bus->rxc_errors++; /* dhd.rx_ctlerrs is higher level */
3154 dhdsdio_rxfail(bus, TRUE, TRUE);
3155 goto done;
3156 }
3157
3158gotpkt:
3159
3160#ifdef DHD_DEBUG
3161 if (DHD_BYTES_ON() && DHD_CTL_ON())
3162 prhex("RxCtrl", bus->rxctl, len);
3163#endif
3164
3165 /* Point to valid data and indicate its length */
3166 bus->rxctl += doff;
3167 bus->rxlen = len - doff;
3168
3169done:
3170 /* Awake any waiters */
3171 dhd_os_ioctl_resp_wake(bus->dhd);
3172}
3173
3fd79f7c 3174static u8 dhdsdio_rxglom(dhd_bus_t *bus, u8 rxseq)
cf2b4488 3175{
7d4df48e 3176 u16 dlen, totlen;
3fd79f7c 3177 u8 *dptr, num = 0;
cf2b4488 3178
7d4df48e 3179 u16 sublen, check;
cf2b4488
HP		 3180 void *pfirst, *plast, *pnext, *save_pfirst;
3181 osl_t *osh = bus->dhd->osh;
3182
3183 int errcode;
3fd79f7c
GKH		 3184 u8 chan, seq, doff, sfdoff;
3185 u8 txmax;
cf2b4488
HP		 3186
3187 int ifidx = 0;
3188 bool usechain = bus->use_rxchain;
3189
3190 /* If packets, issue read(s) and send up packet chain */
3191 /* Return sequence numbers consumed? */
3192
3193 DHD_TRACE(("dhdsdio_rxglom: start: glomd %p glom %p\n", bus->glomd,
3194 bus->glom));
3195
3196 /* If there's a descriptor, generate the packet chain */
3197 if (bus->glomd) {
3198 dhd_os_sdlock_rxq(bus->dhd);
3199
3200 pfirst = plast = pnext = NULL;
7d4df48e 3201 dlen = (u16) PKTLEN(bus->glomd);
cf2b4488
HP		 3202 dptr = PKTDATA(bus->glomd);
3203 if (!dlen || (dlen & 1)) {
3204 DHD_ERROR(("%s: bad glomd len(%d), ignore descriptor\n",
3205 __func__, dlen));
3206 dlen = 0;
3207 }
3208
3209 for (totlen = num = 0; dlen; num++) {
3210 /* Get (and move past) next length */
3211 sublen = ltoh16_ua(dptr);
7d4df48e
GKH		 3212 dlen -= sizeof(u16);
3213 dptr += sizeof(u16);
cf2b4488
HP		 3214 if ((sublen < SDPCM_HDRLEN) ||
3215 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
3216 DHD_ERROR(("%s: descriptor len %d bad: %d\n",
3217 __func__, num, sublen));
3218 pnext = NULL;
3219 break;
3220 }
3221 if (sublen % DHD_SDALIGN) {
3222 DHD_ERROR(("%s: sublen %d not multiple of %d\n",
3223 __func__, sublen, DHD_SDALIGN));
3224 usechain = FALSE;
3225 }
3226 totlen += sublen;
3227
3228 /* For last frame, adjust read len so total
3229 is a block multiple */
3230 if (!dlen) {
3231 sublen +=
3232 (ROUNDUP(totlen, bus->blocksize) - totlen);
3233 totlen = ROUNDUP(totlen, bus->blocksize);
3234 }
3235
3236 /* Allocate/chain packet for next subframe */
3237 pnext = PKTGET(osh, sublen + DHD_SDALIGN, FALSE);
3238 if (pnext == NULL) {
3239 DHD_ERROR(("%s: PKTGET failed, num %d len %d\n",
3240 __func__, num, sublen));
3241 break;
3242 }
3243 ASSERT(!PKTLINK(pnext));
3244 if (!pfirst) {
3245 ASSERT(!plast);
3246 pfirst = plast = pnext;
3247 } else {
3248 ASSERT(plast);
3249 PKTSETNEXT(plast, pnext);
3250 plast = pnext;
3251 }
3252
3253 /* Adhere to start alignment requirements */
3254 PKTALIGN(osh, pnext, sublen, DHD_SDALIGN);
3255 }
3256
3257 /* If all allocations succeeded, save packet chain
3258 in bus structure */
3259 if (pnext) {
3260 DHD_GLOM(("%s: allocated %d-byte packet chain for %d "
3261 "subframes\n", __func__, totlen, num));
3262 if (DHD_GLOM_ON() && bus->nextlen) {
3263 if (totlen != bus->nextlen) {
3264 DHD_GLOM(("%s: glomdesc mismatch: nextlen %d glomdesc %d " "rxseq %d\n",
3265 __func__, bus->nextlen,
3266 totlen, rxseq));
3267 }
3268 }
3269 bus->glom = pfirst;
3270 pfirst = pnext = NULL;
3271 } else {
3272 if (pfirst)
3273 PKTFREE(osh, pfirst, FALSE);
3274 bus->glom = NULL;
3275 num = 0;
3276 }
3277
3278 /* Done with descriptor packet */
3279 PKTFREE(osh, bus->glomd, FALSE);
3280 bus->glomd = NULL;
3281 bus->nextlen = 0;
3282
3283 dhd_os_sdunlock_rxq(bus->dhd);
3284 }
3285
3286 /* Ok -- either we just generated a packet chain,
3287 or had one from before */
3288 if (bus->glom) {
3289 if (DHD_GLOM_ON()) {
3290 DHD_GLOM(("%s: try superframe read, packet chain:\n",
3291 __func__));
3292 for (pnext = bus->glom; pnext; pnext = PKTNEXT(pnext)) {
3293 DHD_GLOM((" %p: %p len 0x%04x (%d)\n",
3fd79f7c 3294 pnext, (u8 *) PKTDATA(pnext),
cf2b4488
HP		 3295 PKTLEN(pnext), PKTLEN(pnext)));
3296 }
3297 }
3298
3299 pfirst = bus->glom;
7d4df48e 3300 dlen = (u16) pkttotlen(osh, pfirst);
cf2b4488
HP		 3301
3302 /* Do an SDIO read for the superframe. Configurable iovar to
3303 * read directly into the chained packet, or allocate a large
3304 * packet and and copy into the chain.
3305 */
3306 if (usechain) {
3307 errcode = dhd_bcmsdh_recv_buf(bus,
3308 bcmsdh_cur_sbwad
3309 (bus->sdh), SDIO_FUNC_2,
3310 F2SYNC,
3fd79f7c 3311 (u8 *) PKTDATA(pfirst),
cf2b4488
HP		 3312 dlen, pfirst, NULL, NULL);
3313 } else if (bus->dataptr) {
3314 errcode = dhd_bcmsdh_recv_buf(bus,
3315 bcmsdh_cur_sbwad
3316 (bus->sdh), SDIO_FUNC_2,
3317 F2SYNC, bus->dataptr,
3318 dlen, NULL, NULL, NULL);
3319 sublen =
7d4df48e 3320 (u16) pktfrombuf(osh, pfirst, 0, dlen,
cf2b4488
HP		 3321 bus->dataptr);
3322 if (sublen != dlen) {
3323 DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
3324 __func__, dlen, sublen));
3325 errcode = -1;
3326 }
3327 pnext = NULL;
3328 } else {
3329 DHD_ERROR(("COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
3330 dlen));
3331 errcode = -1;
3332 }
3333 bus->f2rxdata++;
3334 ASSERT(errcode != BCME_PENDING);
3335
3336 /* On failure, kill the superframe, allow a couple retries */
3337 if (errcode < 0) {
3338 DHD_ERROR(("%s: glom read of %d bytes failed: %d\n",
3339 __func__, dlen, errcode));
3340 bus->dhd->rx_errors++;
3341
3342 if (bus->glomerr++ < 3) {
3343 dhdsdio_rxfail(bus, TRUE, TRUE);
3344 } else {
3345 bus->glomerr = 0;
3346 dhdsdio_rxfail(bus, TRUE, FALSE);
3347 dhd_os_sdlock_rxq(bus->dhd);
3348 PKTFREE(osh, bus->glom, FALSE);
3349 dhd_os_sdunlock_rxq(bus->dhd);
3350 bus->rxglomfail++;
3351 bus->glom = NULL;
3352 }
3353 return 0;
3354 }
3355#ifdef DHD_DEBUG
3356 if (DHD_GLOM_ON()) {
3357 prhex("SUPERFRAME", PKTDATA(pfirst),
3358 MIN(PKTLEN(pfirst), 48));
3359 }
3360#endif
3361
3362 /* Validate the superframe header */
3fd79f7c 3363 dptr = (u8 *) PKTDATA(pfirst);
cf2b4488 3364 sublen = ltoh16_ua(dptr);
7d4df48e 3365 check = ltoh16_ua(dptr + sizeof(u16));
cf2b4488
HP		 3366
3367 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3368 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3369 bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
3370 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3371 DHD_INFO(("%s: nextlen too large (%d) seq %d\n",
3372 __func__, bus->nextlen, seq));
3373 bus->nextlen = 0;
3374 }
3375 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3376 txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3377
3378 errcode = 0;
7d4df48e 3379 if ((u16)~(sublen ^ check)) {
cf2b4488
HP		 3380 DHD_ERROR(("%s (superframe): HW hdr error: len/check "
3381 "0x%04x/0x%04x\n", __func__, sublen, check));
3382 errcode = -1;
3383 } else if (ROUNDUP(sublen, bus->blocksize) != dlen) {
3384 DHD_ERROR(("%s (superframe): len 0x%04x, rounded "
3385 "0x%04x, expect 0x%04x\n",
3386 __func__, sublen,
3387 ROUNDUP(sublen, bus->blocksize), dlen));
3388 errcode = -1;
3389 } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
3390 SDPCM_GLOM_CHANNEL) {
3391 DHD_ERROR(("%s (superframe): bad channel %d\n",
3392 __func__,
3393 SDPCM_PACKET_CHANNEL(&dptr
3394 [SDPCM_FRAMETAG_LEN])));
3395 errcode = -1;
3396 } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
3397 DHD_ERROR(("%s (superframe): got second descriptor?\n",
3398 __func__));
3399 errcode = -1;
3400 } else if ((doff < SDPCM_HDRLEN) ||
3401 (doff > (PKTLEN(pfirst) - SDPCM_HDRLEN))) {
3402 DHD_ERROR(("%s (superframe): Bad data offset %d: HW %d "
3403 "pkt %d min %d\n",
3404 __func__, doff, sublen,
3405 PKTLEN(pfirst), SDPCM_HDRLEN));
3406 errcode = -1;
3407 }
3408
3409 /* Check sequence number of superframe SW header */
3410 if (rxseq != seq) {
3411 DHD_INFO(("%s: (superframe) rx_seq %d, expected %d\n",
3412 __func__, seq, rxseq));
3413 bus->rx_badseq++;
3414 rxseq = seq;
3415 }
3416
3417 /* Check window for sanity */
3fd79f7c 3418 if ((u8) (txmax - bus->tx_seq) > 0x40) {
cf2b4488
HP		 3419 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
3420 __func__, txmax, bus->tx_seq));
3421 txmax = bus->tx_seq + 2;
3422 }
3423 bus->tx_max = txmax;
3424
3425 /* Remove superframe header, remember offset */
3426 PKTPULL(pfirst, doff);
3427 sfdoff = doff;
3428
3429 /* Validate all the subframe headers */
3430 for (num = 0, pnext = pfirst; pnext && !errcode;
3431 num++, pnext = PKTNEXT(pnext)) {
3fd79f7c 3432 dptr = (u8 *) PKTDATA(pnext);
7d4df48e 3433 dlen = (u16) PKTLEN(pnext);
cf2b4488 3434 sublen = ltoh16_ua(dptr);
7d4df48e 3435 check = ltoh16_ua(dptr + sizeof(u16));
cf2b4488
HP		 3436 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3437 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3438#ifdef DHD_DEBUG
3439 if (DHD_GLOM_ON())
3440 prhex("subframe", dptr, 32);
3441#endif
3442
7d4df48e 3443 if ((u16)~(sublen ^ check)) {
cf2b4488
HP		 3444 DHD_ERROR(("%s (subframe %d): HW hdr error: "
3445 "len/check 0x%04x/0x%04x\n",
3446 __func__, num, sublen, check));
3447 errcode = -1;
3448 } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
3449 DHD_ERROR(("%s (subframe %d): length mismatch: "
3450 "len 0x%04x, expect 0x%04x\n",
3451 __func__, num, sublen, dlen));
3452 errcode = -1;
3453 } else if ((chan != SDPCM_DATA_CHANNEL) &&
3454 (chan != SDPCM_EVENT_CHANNEL)) {
3455 DHD_ERROR(("%s (subframe %d): bad channel %d\n",
3456 __func__, num, chan));
3457 errcode = -1;
3458 } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
3459 DHD_ERROR(("%s (subframe %d): Bad data offset %d: HW %d min %d\n",
3460 __func__, num, doff, sublen,
3461 SDPCM_HDRLEN));
3462 errcode = -1;
3463 }
3464 }
3465
3466 if (errcode) {
3467 /* Terminate frame on error, request
3468 a couple retries */
3469 if (bus->glomerr++ < 3) {
3470 /* Restore superframe header space */
3471 PKTPUSH(pfirst, sfdoff);
3472 dhdsdio_rxfail(bus, TRUE, TRUE);
3473 } else {
3474 bus->glomerr = 0;
3475 dhdsdio_rxfail(bus, TRUE, FALSE);
3476 dhd_os_sdlock_rxq(bus->dhd);
3477 PKTFREE(osh, bus->glom, FALSE);
3478 dhd_os_sdunlock_rxq(bus->dhd);
3479 bus->rxglomfail++;
3480 bus->glom = NULL;
3481 }
3482 bus->nextlen = 0;
3483 return 0;
3484 }
3485
3486 /* Basic SD framing looks ok - process each packet (header) */
3487 save_pfirst = pfirst;
3488 bus->glom = NULL;
3489 plast = NULL;
3490
3491 dhd_os_sdlock_rxq(bus->dhd);
3492 for (num = 0; pfirst; rxseq++, pfirst = pnext) {
3493 pnext = PKTNEXT(pfirst);
3494 PKTSETNEXT(pfirst, NULL);
3495
3fd79f7c 3496 dptr = (u8 *) PKTDATA(pfirst);
cf2b4488
HP		 3497 sublen = ltoh16_ua(dptr);
3498 chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
3499 seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
3500 doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
3501
3502 DHD_GLOM(("%s: Get subframe %d, %p(%p/%d), sublen %d "
3503 "chan %d seq %d\n",
3504 __func__, num, pfirst, PKTDATA(pfirst),
3505 PKTLEN(pfirst), sublen, chan, seq));
3506
3507 ASSERT((chan == SDPCM_DATA_CHANNEL)
3508 || (chan == SDPCM_EVENT_CHANNEL));
3509
3510 if (rxseq != seq) {
3511 DHD_GLOM(("%s: rx_seq %d, expected %d\n",
3512 __func__, seq, rxseq));
3513 bus->rx_badseq++;
3514 rxseq = seq;
3515 }
3516#ifdef DHD_DEBUG
3517 if (DHD_BYTES_ON() && DHD_DATA_ON())
3518 prhex("Rx Subframe Data", dptr, dlen);
3519#endif
3520
3521 PKTSETLEN(pfirst, sublen);
3522 PKTPULL(pfirst, doff);
3523
3524 if (PKTLEN(pfirst) == 0) {
3525 PKTFREE(bus->dhd->osh, pfirst, FALSE);
3526 if (plast) {
3527 PKTSETNEXT(plast, pnext);
3528 } else {
3529 ASSERT(save_pfirst == pfirst);
3530 save_pfirst = pnext;
3531 }
3532 continue;
3533 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pfirst) !=
3534 0) {
3535 DHD_ERROR(("%s: rx protocol error\n",
3536 __func__));
3537 bus->dhd->rx_errors++;
3538 PKTFREE(osh, pfirst, FALSE);
3539 if (plast) {
3540 PKTSETNEXT(plast, pnext);
3541 } else {
3542 ASSERT(save_pfirst == pfirst);
3543 save_pfirst = pnext;
3544 }
3545 continue;
3546 }
3547
3548 /* this packet will go up, link back into
3549 chain and count it */
3550 PKTSETNEXT(pfirst, pnext);
3551 plast = pfirst;
3552 num++;
3553
3554#ifdef DHD_DEBUG
3555 if (DHD_GLOM_ON()) {
3556 DHD_GLOM(("%s subframe %d to stack, %p(%p/%d) "
3557 "nxt/lnk %p/%p\n",
3558 __func__, num, pfirst, PKTDATA(pfirst),
3559 PKTLEN(pfirst), PKTNEXT(pfirst),
3560 PKTLINK(pfirst)));
3fd79f7c 3561 prhex("", (u8 *) PKTDATA(pfirst),
cf2b4488
HP		 3562 MIN(PKTLEN(pfirst), 32));
3563 }
3564#endif /* DHD_DEBUG */
3565 }
3566 dhd_os_sdunlock_rxq(bus->dhd);
3567 if (num) {
3568 dhd_os_sdunlock(bus->dhd);
3569 dhd_rx_frame(bus->dhd, ifidx, save_pfirst, num);
3570 dhd_os_sdlock(bus->dhd);
3571 }
3572
3573 bus->rxglomframes++;
3574 bus->rxglompkts += num;
3575 }
3576 return num;
3577}
3578
3579/* Return TRUE if there may be more frames to read */
3580static uint dhdsdio_readframes(dhd_bus_t *bus, uint maxframes, bool *finished)
3581{
3582 osl_t *osh = bus->dhd->osh;
3583 bcmsdh_info_t *sdh = bus->sdh;
3584
7d4df48e 3585 u16 len, check; /* Extracted hardware header fields */
3fd79f7c
GKH		 3586 u8 chan, seq, doff; /* Extracted software header fields */
3587 u8 fcbits; /* Extracted fcbits from software header */
3588 u8 delta;
cf2b4488
HP		 3589
3590 void *pkt; /* Packet for event or data frames */
7d4df48e
GKH		 3591 u16 pad; /* Number of pad bytes to read */
3592 u16 rdlen; /* Total number of bytes to read */
3fd79f7c 3593 u8 rxseq; /* Next sequence number to expect */
cf2b4488
HP		 3594 uint rxleft = 0; /* Remaining number of frames allowed */
3595 int sdret; /* Return code from bcmsdh calls */
3fd79f7c 3596 u8 txmax; /* Maximum tx sequence offered */
cf2b4488
HP		 3597 bool len_consistent; /* Result of comparing readahead len and
3598 len from hw-hdr */
3fd79f7c 3599 u8 *rxbuf;
cf2b4488
HP		 3600 int ifidx = 0;
3601 uint rxcount = 0; /* Total frames read */
3602
3603#if defined(DHD_DEBUG) || defined(SDTEST)
3604 bool sdtest = FALSE; /* To limit message spew from test mode */
3605#endif
3606
3607 DHD_TRACE(("%s: Enter\n", __func__));
3608
3609 ASSERT(maxframes);
3610
3611#ifdef SDTEST
3612 /* Allow pktgen to override maxframes */
3613 if (bus->pktgen_count && (bus->pktgen_mode == DHD_PKTGEN_RECV)) {
3614 maxframes = bus->pktgen_count;
3615 sdtest = TRUE;
3616 }
3617#endif
3618
3619 /* Not finished unless we encounter no more frames indication */
3620 *finished = FALSE;
3621
3622 for (rxseq = bus->rx_seq, rxleft = maxframes;
3623 !bus->rxskip && rxleft && bus->dhd->busstate != DHD_BUS_DOWN;
3624 rxseq++, rxleft--) {
3625
3626 /* Handle glomming separately */
3627 if (bus->glom || bus->glomd) {
3fd79f7c 3628 u8 cnt;
cf2b4488
HP		 3629 DHD_GLOM(("%s: calling rxglom: glomd %p, glom %p\n",
3630 __func__, bus->glomd, bus->glom));
3631 cnt = dhdsdio_rxglom(bus, rxseq);
3632 DHD_GLOM(("%s: rxglom returned %d\n", __func__, cnt));
3633 rxseq += cnt - 1;
3634 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
3635 continue;
3636 }
3637
3638 /* Try doing single read if we can */
3639 if (dhd_readahead && bus->nextlen) {
7d4df48e 3640 u16 nextlen = bus->nextlen;
cf2b4488
HP		 3641 bus->nextlen = 0;
3642
3643 if (bus->bus == SPI_BUS) {
3644 rdlen = len = nextlen;
3645 } else {
3646 rdlen = len = nextlen << 4;
3647
3648 /* Pad read to blocksize for efficiency */
3649 if (bus->roundup && bus->blocksize
3650 && (rdlen > bus->blocksize)) {
3651 pad =
3652 bus->blocksize -
3653 (rdlen % bus->blocksize);
3654 if ((pad <= bus->roundup)
3655 && (pad < bus->blocksize)
3656 && ((rdlen + pad + firstread) <
3657 MAX_RX_DATASZ))
3658 rdlen += pad;
3659 } else if (rdlen % DHD_SDALIGN) {
3660 rdlen +=
3661 DHD_SDALIGN - (rdlen % DHD_SDALIGN);
3662 }
3663 }
3664
3665 /* We use bus->rxctl buffer in WinXP for initial
3666 * control pkt receives.
3667 * Later we use buffer-poll for data as well
3668 * as control packets.
3669 * This is required becuase dhd receives full
3670 * frame in gSPI unlike SDIO.
3671 * After the frame is received we have to
3672 * distinguish whether it is data
3673 * or non-data frame.
3674 */
3675 /* Allocate a packet buffer */
3676 dhd_os_sdlock_rxq(bus->dhd);
3677 pkt = PKTGET(osh, rdlen + DHD_SDALIGN, FALSE);
3678 if (!pkt) {
3679 if (bus->bus == SPI_BUS) {
3680 bus->usebufpool = FALSE;
3681 bus->rxctl = bus->rxbuf;
3682 if (dhd_alignctl) {
3683 bus->rxctl += firstread;
3684 pad = ((uintptr) bus->rxctl %
3685 DHD_SDALIGN);
3686 if (pad)
3687 bus->rxctl +=
3688 (DHD_SDALIGN - pad);
3689 bus->rxctl -= firstread;
3690 }
3691 ASSERT(bus->rxctl >= bus->rxbuf);
3692 rxbuf = bus->rxctl;
3693 /* Read the entire frame */
3694 sdret = dhd_bcmsdh_recv_buf(bus,
3695 bcmsdh_cur_sbwad
3696 (sdh),
3697 SDIO_FUNC_2,
3698 F2SYNC,
3699 rxbuf,
3700 rdlen, NULL,
3701 NULL, NULL);
3702 bus->f2rxdata++;
3703 ASSERT(sdret != BCME_PENDING);
3704
3705 /* Control frame failures need
3706 retransmission */
3707 if (sdret < 0) {
3708 DHD_ERROR(("%s: read %d control bytes failed: %d\n",
3709 __func__,
3710 rdlen, sdret));
3711 /* dhd.rx_ctlerrs is higher */
3712 bus->rxc_errors++;
3713 dhd_os_sdunlock_rxq(bus->dhd);
3714 dhdsdio_rxfail(bus, TRUE,
3715 (bus->bus ==
3716 SPI_BUS) ? FALSE
3717 : TRUE);
3718 continue;
3719 }
3720 } else {
3721 /* Give up on data,
3722 request rtx of events */
3723 DHD_ERROR(("%s (nextlen): PKTGET failed: len %d rdlen %d " "expected rxseq %d\n",
3724 __func__, len, rdlen, rxseq));
3725 /* Just go try again w/normal
3726 header read */
3727 dhd_os_sdunlock_rxq(bus->dhd);
3728 continue;
3729 }
3730 } else {
3731 if (bus->bus == SPI_BUS)
3732 bus->usebufpool = TRUE;
3733
3734 ASSERT(!PKTLINK(pkt));
3735 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
3fd79f7c 3736 rxbuf = (u8 *) PKTDATA(pkt);
cf2b4488
HP		 3737 /* Read the entire frame */
3738 sdret =
3739 dhd_bcmsdh_recv_buf(bus,
3740 bcmsdh_cur_sbwad(sdh),
3741 SDIO_FUNC_2, F2SYNC,
3742 rxbuf, rdlen, pkt, NULL,
3743 NULL);
3744 bus->f2rxdata++;
3745 ASSERT(sdret != BCME_PENDING);
3746
3747 if (sdret < 0) {
3748 DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
3749 __func__, rdlen, sdret));
3750 PKTFREE(bus->dhd->osh, pkt, FALSE);
3751 bus->dhd->rx_errors++;
3752 dhd_os_sdunlock_rxq(bus->dhd);
3753 /* Force retry w/normal header read.
3754 * Don't attemp NAK for
3755 * gSPI
3756 */
3757 dhdsdio_rxfail(bus, TRUE,
3758 (bus->bus ==
3759 SPI_BUS) ? FALSE :
3760 TRUE);
3761 continue;
3762 }
3763 }
3764 dhd_os_sdunlock_rxq(bus->dhd);
3765
3766 /* Now check the header */
3767 bcopy(rxbuf, bus->rxhdr, SDPCM_HDRLEN);
3768
3769 /* Extract hardware header fields */
3770 len = ltoh16_ua(bus->rxhdr);
7d4df48e 3771 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
cf2b4488
HP		 3772
3773 /* All zeros means readahead info was bad */
3774 if (!(len | check)) {
3775 DHD_INFO(("%s (nextlen): read zeros in HW "
3776 "header???\n", __func__));
3777 dhd_os_sdlock_rxq(bus->dhd);
3778 PKTFREE2();
3779 dhd_os_sdunlock_rxq(bus->dhd);
3780 GSPI_PR55150_BAILOUT;
3781 continue;
3782 }
3783
3784 /* Validate check bytes */
7d4df48e 3785 if ((u16)~(len ^ check)) {
cf2b4488
HP		 3786 DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
3787 __func__, nextlen, len, check));
3788 dhd_os_sdlock_rxq(bus->dhd);
3789 PKTFREE2();
3790 dhd_os_sdunlock_rxq(bus->dhd);
3791 bus->rx_badhdr++;
3792 dhdsdio_rxfail(bus, FALSE, FALSE);
3793 GSPI_PR55150_BAILOUT;
3794 continue;
3795 }
3796
3797 /* Validate frame length */
3798 if (len < SDPCM_HDRLEN) {
3799 DHD_ERROR(("%s (nextlen): HW hdr length "
3800 "invalid: %d\n", __func__, len));
3801 dhd_os_sdlock_rxq(bus->dhd);
3802 PKTFREE2();
3803 dhd_os_sdunlock_rxq(bus->dhd);
3804 GSPI_PR55150_BAILOUT;
3805 continue;
3806 }
3807
3808 /* Check for consistency withreadahead info */
3809 len_consistent = (nextlen != (ROUNDUP(len, 16) >> 4));
3810 if (len_consistent) {
3811 /* Mismatch, force retry w/normal
3812 header (may be >4K) */
3813 DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
3814 __func__, nextlen,
3815 len, ROUNDUP(len, 16), rxseq));
3816 dhd_os_sdlock_rxq(bus->dhd);
3817 PKTFREE2();
3818 dhd_os_sdunlock_rxq(bus->dhd);
3819 dhdsdio_rxfail(bus, TRUE,
3820 (bus->bus ==
3821 SPI_BUS) ? FALSE : TRUE);
3822 GSPI_PR55150_BAILOUT;
3823 continue;
3824 }
3825
3826 /* Extract software header fields */
3827 chan =
3828 SDPCM_PACKET_CHANNEL(&bus->rxhdr
3829 [SDPCM_FRAMETAG_LEN]);
3830 seq =
3831 SDPCM_PACKET_SEQUENCE(&bus->rxhdr
3832 [SDPCM_FRAMETAG_LEN]);
3833 doff =
3834 SDPCM_DOFFSET_VALUE(&bus->rxhdr
3835 [SDPCM_FRAMETAG_LEN]);
3836 txmax =
3837 SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3838
3839 bus->nextlen =
3840 bus->rxhdr[SDPCM_FRAMETAG_LEN +
3841 SDPCM_NEXTLEN_OFFSET];
3842 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
3843 DHD_INFO(("%s (nextlen): got frame w/nextlen too large" " (%d), seq %d\n",
3844 __func__, bus->nextlen, seq));
3845 bus->nextlen = 0;
3846 }
3847
3848 bus->dhd->rx_readahead_cnt++;
3849 /* Handle Flow Control */
3850 fcbits =
3851 SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3852
3853 delta = 0;
3854 if (~bus->flowcontrol & fcbits) {
3855 bus->fc_xoff++;
3856 delta = 1;
3857 }
3858 if (bus->flowcontrol & ~fcbits) {
3859 bus->fc_xon++;
3860 delta = 1;
3861 }
3862
3863 if (delta) {
3864 bus->fc_rcvd++;
3865 bus->flowcontrol = fcbits;
3866 }
3867
3868 /* Check and update sequence number */
3869 if (rxseq != seq) {
3870 DHD_INFO(("%s (nextlen): rx_seq %d, expected "
3871 "%d\n", __func__, seq, rxseq));
3872 bus->rx_badseq++;
3873 rxseq = seq;
3874 }
3875
3876 /* Check window for sanity */
3fd79f7c 3877 if ((u8) (txmax - bus->tx_seq) > 0x40) {
cf2b4488
HP		 3878 DHD_ERROR(("%s: got unlikely tx max %d with "
3879 "tx_seq %d\n",
3880 __func__, txmax, bus->tx_seq));
3881 txmax = bus->tx_seq + 2;
3882 }
3883 bus->tx_max = txmax;
3884
3885#ifdef DHD_DEBUG
3886 if (DHD_BYTES_ON() && DHD_DATA_ON())
3887 prhex("Rx Data", rxbuf, len);
3888 else if (DHD_HDRS_ON())
3889 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3890#endif
3891
3892 if (chan == SDPCM_CONTROL_CHANNEL) {
3893 if (bus->bus == SPI_BUS) {
3894 dhdsdio_read_control(bus, rxbuf, len,
3895 doff);
3896 if (bus->usebufpool) {
3897 dhd_os_sdlock_rxq(bus->dhd);
3898 PKTFREE(bus->dhd->osh, pkt,
3899 FALSE);
3900 dhd_os_sdunlock_rxq(bus->dhd);
3901 }
3902 continue;
3903 } else {
3904 DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
3905 __func__, seq));
3906 /* Force retry w/normal header read */
3907 bus->nextlen = 0;
3908 dhdsdio_rxfail(bus, FALSE, TRUE);
3909 dhd_os_sdlock_rxq(bus->dhd);
3910 PKTFREE2();
3911 dhd_os_sdunlock_rxq(bus->dhd);
3912 continue;
3913 }
3914 }
3915
3916 if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
3917 DHD_ERROR(("Received %d bytes on %d channel. Running out of " "rx pktbuf's or not yet malloced.\n",
3918 len, chan));
3919 continue;
3920 }
3921
3922 /* Validate data offset */
3923 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3924 DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
3925 __func__, doff, len, SDPCM_HDRLEN));
3926 dhd_os_sdlock_rxq(bus->dhd);
3927 PKTFREE2();
3928 dhd_os_sdunlock_rxq(bus->dhd);
3929 ASSERT(0);
3930 dhdsdio_rxfail(bus, FALSE, FALSE);
3931 continue;
3932 }
3933
3934 /* All done with this one -- now deliver the packet */
3935 goto deliver;
3936 }
3937 /* gSPI frames should not be handled in fractions */
3938 if (bus->bus == SPI_BUS)
3939 break;
3940
3941 /* Read frame header (hardware and software) */
3942 sdret =
3943 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3944 F2SYNC, bus->rxhdr, firstread, NULL,
3945 NULL, NULL);
3946 bus->f2rxhdrs++;
3947 ASSERT(sdret != BCME_PENDING);
3948
3949 if (sdret < 0) {
3950 DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
3951 sdret));
3952 bus->rx_hdrfail++;
3953 dhdsdio_rxfail(bus, TRUE, TRUE);
3954 continue;
3955 }
3956#ifdef DHD_DEBUG
3957 if (DHD_BYTES_ON() || DHD_HDRS_ON())
3958 prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
3959#endif
3960
3961 /* Extract hardware header fields */
3962 len = ltoh16_ua(bus->rxhdr);
7d4df48e 3963 check = ltoh16_ua(bus->rxhdr + sizeof(u16));
cf2b4488
HP		 3964
3965 /* All zeros means no more frames */
3966 if (!(len | check)) {
3967 *finished = TRUE;
3968 break;
3969 }
3970
3971 /* Validate check bytes */
7d4df48e 3972 if ((u16) ~(len ^ check)) {
cf2b4488
HP		 3973 DHD_ERROR(("%s: HW hdr err: len/check 0x%04x/0x%04x\n",
3974 __func__, len, check));
3975 bus->rx_badhdr++;
3976 dhdsdio_rxfail(bus, FALSE, FALSE);
3977 continue;
3978 }
3979
3980 /* Validate frame length */
3981 if (len < SDPCM_HDRLEN) {
3982 DHD_ERROR(("%s: HW hdr length invalid: %d\n",
3983 __func__, len));
3984 continue;
3985 }
3986
3987 /* Extract software header fields */
3988 chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3989 seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3990 doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3991 txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
3992
3993 /* Validate data offset */
3994 if ((doff < SDPCM_HDRLEN) || (doff > len)) {
3995 DHD_ERROR(("%s: Bad data offset %d: HW len %d, min %d "
3996 "seq %d\n",
3997 __func__, doff, len, SDPCM_HDRLEN, seq));
3998 bus->rx_badhdr++;
3999 ASSERT(0);
4000 dhdsdio_rxfail(bus, FALSE, FALSE);
4001 continue;
4002 }
4003
4004 /* Save the readahead length if there is one */
4005 bus->nextlen =
4006 bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
4007 if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
4008 DHD_INFO(("%s (nextlen): got frame w/nextlen too large "
4009 "(%d), seq %d\n",
4010 __func__, bus->nextlen, seq));
4011 bus->nextlen = 0;
4012 }
4013
4014 /* Handle Flow Control */
4015 fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
4016
4017 delta = 0;
4018 if (~bus->flowcontrol & fcbits) {
4019 bus->fc_xoff++;
4020 delta = 1;
4021 }
4022 if (bus->flowcontrol & ~fcbits) {
4023 bus->fc_xon++;
4024 delta = 1;
4025 }
4026
4027 if (delta) {
4028 bus->fc_rcvd++;
4029 bus->flowcontrol = fcbits;
4030 }
4031
4032 /* Check and update sequence number */
4033 if (rxseq != seq) {
4034 DHD_INFO(("%s: rx_seq %d, expected %d\n", __func__,
4035 seq, rxseq));
4036 bus->rx_badseq++;
4037 rxseq = seq;
4038 }
4039
4040 /* Check window for sanity */
3fd79f7c 4041 if ((u8) (txmax - bus->tx_seq) > 0x40) {
cf2b4488
HP		 4042 DHD_ERROR(("%s: unlikely tx max %d with tx_seq %d\n",
4043 __func__, txmax, bus->tx_seq));
4044 txmax = bus->tx_seq + 2;
4045 }
4046 bus->tx_max = txmax;
4047
4048 /* Call a separate function for control frames */
4049 if (chan == SDPCM_CONTROL_CHANNEL) {
4050 dhdsdio_read_control(bus, bus->rxhdr, len, doff);
4051 continue;
4052 }
4053
4054 ASSERT((chan == SDPCM_DATA_CHANNEL)
4055 || (chan == SDPCM_EVENT_CHANNEL)
4056 || (chan == SDPCM_TEST_CHANNEL)
4057 || (chan == SDPCM_GLOM_CHANNEL));
4058
4059 /* Length to read */
4060 rdlen = (len > firstread) ? (len - firstread) : 0;
4061
4062 /* May pad read to blocksize for efficiency */
4063 if (bus->roundup && bus->blocksize &&
4064 (rdlen > bus->blocksize)) {
4065 pad = bus->blocksize - (rdlen % bus->blocksize);
4066 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
4067 ((rdlen + pad + firstread) < MAX_RX_DATASZ))
4068 rdlen += pad;
4069 } else if (rdlen % DHD_SDALIGN) {
4070 rdlen += DHD_SDALIGN - (rdlen % DHD_SDALIGN);
4071 }
4072
4073 /* Satisfy length-alignment requirements */
4074 if (forcealign && (rdlen & (ALIGNMENT - 1)))
4075 rdlen = ROUNDUP(rdlen, ALIGNMENT);
4076
4077 if ((rdlen + firstread) > MAX_RX_DATASZ) {
4078 /* Too long -- skip this frame */
4079 DHD_ERROR(("%s: too long: len %d rdlen %d\n",
4080 __func__, len, rdlen));
4081 bus->dhd->rx_errors++;
4082 bus->rx_toolong++;
4083 dhdsdio_rxfail(bus, FALSE, FALSE);
4084 continue;
4085 }
4086
4087 dhd_os_sdlock_rxq(bus->dhd);
4088 pkt = PKTGET(osh, (rdlen + firstread + DHD_SDALIGN), FALSE);
4089 if (!pkt) {
4090 /* Give up on data, request rtx of events */
4091 DHD_ERROR(("%s: PKTGET failed: rdlen %d chan %d\n",
4092 __func__, rdlen, chan));
4093 bus->dhd->rx_dropped++;
4094 dhd_os_sdunlock_rxq(bus->dhd);
4095 dhdsdio_rxfail(bus, FALSE, RETRYCHAN(chan));
4096 continue;
4097 }
4098 dhd_os_sdunlock_rxq(bus->dhd);
4099
4100 ASSERT(!PKTLINK(pkt));
4101
4102 /* Leave room for what we already read, and align remainder */
4103 ASSERT(firstread < (PKTLEN(pkt)));
4104 PKTPULL(pkt, firstread);
4105 PKTALIGN(osh, pkt, rdlen, DHD_SDALIGN);
4106
4107 /* Read the remaining frame data */
4108 sdret =
4109 dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3fd79f7c 4110 F2SYNC, ((u8 *) PKTDATA(pkt)), rdlen,
cf2b4488
HP		 4111 pkt, NULL, NULL);
4112 bus->f2rxdata++;
4113 ASSERT(sdret != BCME_PENDING);
4114
4115 if (sdret < 0) {
4116 DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
4117 __func__, rdlen,
4118 ((chan ==
4119 SDPCM_EVENT_CHANNEL) ? "event" : ((chan ==
4120 SDPCM_DATA_CHANNEL)
4121 ? "data" : "test")),
4122 sdret));
4123 dhd_os_sdlock_rxq(bus->dhd);
4124 PKTFREE(bus->dhd->osh, pkt, FALSE);
4125 dhd_os_sdunlock_rxq(bus->dhd);
4126 bus->dhd->rx_errors++;
4127 dhdsdio_rxfail(bus, TRUE, RETRYCHAN(chan));
4128 continue;
4129 }
4130
4131 /* Copy the already-read portion */
4132 PKTPUSH(pkt, firstread);
4133 bcopy(bus->rxhdr, PKTDATA(pkt), firstread);
4134
4135#ifdef DHD_DEBUG
4136 if (DHD_BYTES_ON() && DHD_DATA_ON())
4137 prhex("Rx Data", PKTDATA(pkt), len);
4138#endif
4139
4140deliver:
4141 /* Save superframe descriptor and allocate packet frame */
4142 if (chan == SDPCM_GLOM_CHANNEL) {
4143 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
4144 DHD_GLOM(("%s: glom descriptor, %d bytes:\n",
4145 __func__, len));
4146#ifdef DHD_DEBUG
4147 if (DHD_GLOM_ON()) {
4148 prhex("Glom Data", PKTDATA(pkt), len);
4149 }
4150#endif
4151 PKTSETLEN(pkt, len);
4152 ASSERT(doff == SDPCM_HDRLEN);
4153 PKTPULL(pkt, SDPCM_HDRLEN);
4154 bus->glomd = pkt;
4155 } else {
4156 DHD_ERROR(("%s: glom superframe w/o "
4157 "descriptor!\n", __func__));
4158 dhdsdio_rxfail(bus, FALSE, FALSE);
4159 }
4160 continue;
4161 }
4162
4163 /* Fill in packet len and prio, deliver upward */
4164 PKTSETLEN(pkt, len);
4165 PKTPULL(pkt, doff);
4166
4167#ifdef SDTEST
4168 /* Test channel packets are processed separately */
4169 if (chan == SDPCM_TEST_CHANNEL) {
4170 dhdsdio_testrcv(bus, pkt, seq);
4171 continue;
4172 }
4173#endif /* SDTEST */
4174
4175 if (PKTLEN(pkt) == 0) {
4176 dhd_os_sdlock_rxq(bus->dhd);
4177 PKTFREE(bus->dhd->osh, pkt, FALSE);
4178 dhd_os_sdunlock_rxq(bus->dhd);
4179 continue;
4180 } else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
4181 DHD_ERROR(("%s: rx protocol error\n", __func__));
4182 dhd_os_sdlock_rxq(bus->dhd);
4183 PKTFREE(bus->dhd->osh, pkt, FALSE);
4184 dhd_os_sdunlock_rxq(bus->dhd);
4185 bus->dhd->rx_errors++;
4186 continue;
4187 }
4188
4189 /* Unlock during rx call */
4190 dhd_os_sdunlock(bus->dhd);
4191 dhd_rx_frame(bus->dhd, ifidx, pkt, 1);
4192 dhd_os_sdlock(bus->dhd);
4193 }
4194 rxcount = maxframes - rxleft;
4195#ifdef DHD_DEBUG
4196 /* Message if we hit the limit */
4197 if (!rxleft && !sdtest)
4198 DHD_DATA(("%s: hit rx limit of %d frames\n", __func__,
4199 maxframes));
4200 else
4201#endif /* DHD_DEBUG */
4202 DHD_DATA(("%s: processed %d frames\n", __func__, rxcount));
4203 /* Back off rxseq if awaiting rtx, update rx_seq */
4204 if (bus->rxskip)
4205 rxseq--;
4206 bus->rx_seq = rxseq;
4207
4208 return rxcount;
4209}
4210
66cbd3ab 4211static u32 dhdsdio_hostmail(dhd_bus_t *bus)
cf2b4488
HP		 4212{
4213 sdpcmd_regs_t *regs = bus->regs;
66cbd3ab
GKH		 4214 u32 intstatus = 0;
4215 u32 hmb_data;
3fd79f7c 4216 u8 fcbits;
cf2b4488
HP		 4217 uint retries = 0;
4218
4219 DHD_TRACE(("%s: Enter\n", __func__));
4220
4221 /* Read mailbox data and ack that we did so */
4222 R_SDREG(hmb_data, &regs->tohostmailboxdata, retries);
4223 if (retries <= retry_limit)
4224 W_SDREG(SMB_INT_ACK, &regs->tosbmailbox, retries);
4225 bus->f1regdata += 2;
4226
4227 /* Dongle recomposed rx frames, accept them again */
4228 if (hmb_data & HMB_DATA_NAKHANDLED) {
4229 DHD_INFO(("Dongle reports NAK handled, expect rtx of %d\n",
4230 bus->rx_seq));
4231 if (!bus->rxskip)
4232 DHD_ERROR(("%s: unexpected NAKHANDLED!\n", __func__));
4233
4234 bus->rxskip = FALSE;
4235 intstatus |= I_HMB_FRAME_IND;
4236 }
4237
4238 /*
4239 * DEVREADY does not occur with gSPI.
4240 */
4241 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
4242 bus->sdpcm_ver =
4243 (hmb_data & HMB_DATA_VERSION_MASK) >>
4244 HMB_DATA_VERSION_SHIFT;
4245 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
4246 DHD_ERROR(("Version mismatch, dongle reports %d, "
4247 "expecting %d\n",
4248 bus->sdpcm_ver, SDPCM_PROT_VERSION));
4249 else
4250 DHD_INFO(("Dongle ready, protocol version %d\n",
4251 bus->sdpcm_ver));
4252 }
4253
4254 /*
4255 * Flow Control has been moved into the RX headers and this out of band
4256 * method isn't used any more. Leae this here for possibly
4257 * remaining backward
4258 * compatible with older dongles
4259 */
4260 if (hmb_data & HMB_DATA_FC) {
4261 fcbits =
4262 (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
4263
4264 if (fcbits & ~bus->flowcontrol)
4265 bus->fc_xoff++;
4266 if (bus->flowcontrol & ~fcbits)
4267 bus->fc_xon++;
4268
4269 bus->fc_rcvd++;
4270 bus->flowcontrol = fcbits;
4271 }
4272
4273 /* Shouldn't be any others */
4274 if (hmb_data & ~(HMB_DATA_DEVREADY |
4275 HMB_DATA_NAKHANDLED |
4276 HMB_DATA_FC |
4277 HMB_DATA_FWREADY |
4278 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) {
4279 DHD_ERROR(("Unknown mailbox data content: 0x%02x\n", hmb_data));
4280 }
4281
4282 return intstatus;
4283}
4284
4285bool dhdsdio_dpc(dhd_bus_t *bus)
4286{
4287 bcmsdh_info_t *sdh = bus->sdh;
4288 sdpcmd_regs_t *regs = bus->regs;
66cbd3ab 4289 u32 intstatus, newstatus = 0;
cf2b4488
HP		 4290 uint retries = 0;
4291 uint rxlimit = dhd_rxbound; /* Rx frames to read before resched */
4292 uint txlimit = dhd_txbound; /* Tx frames to send before resched */
4293 uint framecnt = 0; /* Temporary counter of tx/rx frames */
4294 bool rxdone = TRUE; /* Flag for no more read data */
4295 bool resched = FALSE; /* Flag indicating resched wanted */
4296
4297 DHD_TRACE(("%s: Enter\n", __func__));
4298
4299 /* Start with leftover status bits */
4300 intstatus = bus->intstatus;
4301
4302 dhd_os_sdlock(bus->dhd);
4303
4304 /* If waiting for HTAVAIL, check status */
4305 if (bus->clkstate == CLK_PENDING) {
4306 int err;
3fd79f7c 4307 u8 clkctl, devctl = 0;
cf2b4488
HP		 4308
4309#ifdef DHD_DEBUG
4310 /* Check for inconsistent device control */
4311 devctl =
4312 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, &err);
4313 if (err) {
4314 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4315 __func__, err));
4316 bus->dhd->busstate = DHD_BUS_DOWN;
4317 } else {
4318 ASSERT(devctl & SBSDIO_DEVCTL_CA_INT_ONLY);
4319 }
4320#endif /* DHD_DEBUG */
4321
4322 /* Read CSR, if clock on switch to AVAIL, else ignore */
4323 clkctl =
4324 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
4325 &err);
4326 if (err) {
4327 DHD_ERROR(("%s: error reading CSR: %d\n", __func__,
4328 err));
4329 bus->dhd->busstate = DHD_BUS_DOWN;
4330 }
4331
4332 DHD_INFO(("DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", devctl,
4333 clkctl));
4334
4335 if (SBSDIO_HTAV(clkctl)) {
4336 devctl =
4337 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4338 &err);
4339 if (err) {
4340 DHD_ERROR(("%s: error reading DEVCTL: %d\n",
4341 __func__, err));
4342 bus->dhd->busstate = DHD_BUS_DOWN;
4343 }
4344 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
4345 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
4346 devctl, &err);
4347 if (err) {
4348 DHD_ERROR(("%s: error writing DEVCTL: %d\n",
4349 __func__, err));
4350 bus->dhd->busstate = DHD_BUS_DOWN;
4351 }
4352 bus->clkstate = CLK_AVAIL;
4353 } else {
4354 goto clkwait;
4355 }
4356 }
4357
4358 BUS_WAKE(bus);
4359
4360 /* Make sure backplane clock is on */
4361 dhdsdio_clkctl(bus, CLK_AVAIL, TRUE);
4362 if (bus->clkstate == CLK_PENDING)
4363 goto clkwait;
4364
4365 /* Pending interrupt indicates new device status */
4366 if (bus->ipend) {
4367 bus->ipend = FALSE;
4368 R_SDREG(newstatus, &regs->intstatus, retries);
4369 bus->f1regdata++;
4370 if (bcmsdh_regfail(bus->sdh))
4371 newstatus = 0;
4372 newstatus &= bus->hostintmask;
4373 bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
4374 if (newstatus) {
4375 W_SDREG(newstatus, &regs->intstatus, retries);
4376 bus->f1regdata++;
4377 }
4378 }
4379
4380 /* Merge new bits with previous */
4381 intstatus |= newstatus;
4382 bus->intstatus = 0;
4383
4384 /* Handle flow-control change: read new state in case our ack
4385 * crossed another change interrupt. If change still set, assume
4386 * FC ON for safety, let next loop through do the debounce.
4387 */
4388 if (intstatus & I_HMB_FC_CHANGE) {
4389 intstatus &= ~I_HMB_FC_CHANGE;
4390 W_SDREG(I_HMB_FC_CHANGE, &regs->intstatus, retries);
4391 R_SDREG(newstatus, &regs->intstatus, retries);
4392 bus->f1regdata += 2;
4393 bus->fcstate =
4394 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
4395 intstatus |= (newstatus & bus->hostintmask);
4396 }
4397
4398 /* Handle host mailbox indication */
4399 if (intstatus & I_HMB_HOST_INT) {
4400 intstatus &= ~I_HMB_HOST_INT;
4401 intstatus |= dhdsdio_hostmail(bus);
4402 }
4403
4404 /* Generally don't ask for these, can get CRC errors... */
4405 if (intstatus & I_WR_OOSYNC) {
4406 DHD_ERROR(("Dongle reports WR_OOSYNC\n"));
4407 intstatus &= ~I_WR_OOSYNC;
4408 }
4409
4410 if (intstatus & I_RD_OOSYNC) {
4411 DHD_ERROR(("Dongle reports RD_OOSYNC\n"));
4412 intstatus &= ~I_RD_OOSYNC;
4413 }
4414
4415 if (intstatus & I_SBINT) {
4416 DHD_ERROR(("Dongle reports SBINT\n"));
4417 intstatus &= ~I_SBINT;
4418 }
4419
4420 /* Would be active due to wake-wlan in gSPI */
4421 if (intstatus & I_CHIPACTIVE) {
4422 DHD_INFO(("Dongle reports CHIPACTIVE\n"));
4423 intstatus &= ~I_CHIPACTIVE;
4424 }
4425
4426 /* Ignore frame indications if rxskip is set */
4427 if (bus->rxskip)
4428 intstatus &= ~I_HMB_FRAME_IND;
4429
4430 /* On frame indication, read available frames */
4431 if (PKT_AVAILABLE()) {
4432 framecnt = dhdsdio_readframes(bus, rxlimit, &rxdone);
4433 if (rxdone || bus->rxskip)
4434 intstatus &= ~I_HMB_FRAME_IND;
4435 rxlimit -= MIN(framecnt, rxlimit);
4436 }
4437
4438 /* Keep still-pending events for next scheduling */
4439 bus->intstatus = intstatus;
4440
4441clkwait:
4442#if defined(OOB_INTR_ONLY)
4443 bcmsdh_oob_intr_set(1);
4444#endif /* (OOB_INTR_ONLY) */
4445 /* Re-enable interrupts to detect new device events (mailbox, rx frame)
4446 * or clock availability. (Allows tx loop to check ipend if desired.)
4447 * (Unless register access seems hosed, as we may not be able to ACK...)
4448 */
4449 if (bus->intr && bus->intdis && !bcmsdh_regfail(sdh)) {
4450 DHD_INTR(("%s: enable SDIO interrupts, rxdone %d framecnt %d\n",
4451 __func__, rxdone, framecnt));
4452 bus->intdis = FALSE;
4453 bcmsdh_intr_enable(sdh);
4454 }
4455
4456 if (DATAOK(bus) && bus->ctrl_frame_stat &&
4457 (bus->clkstate == CLK_AVAIL)) {
4458 int ret, i;
4459
4460 ret =
4461 dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
3fd79f7c 4462 F2SYNC, (u8 *) bus->ctrl_frame_buf,
66cbd3ab 4463 (u32) bus->ctrl_frame_len, NULL,
cf2b4488
HP		 4464 NULL, NULL);
4465 ASSERT(ret != BCME_PENDING);
4466
4467 if (ret < 0) {
4468 /* On failure, abort the command and
4469 terminate the frame */
4470 DHD_INFO(("%s: sdio error %d, abort command and "
4471 "terminate frame.\n", __func__, ret));
4472 bus->tx_sderrs++;
4473
4474 bcmsdh_abort(sdh, SDIO_FUNC_2);
4475
4476 bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
4477 SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
4478 NULL);
4479 bus->f1regdata++;
4480
4481 for (i = 0; i < 3; i++) {
3fd79f7c 4482 u8 hi, lo;
cf2b4488
HP		 4483 hi = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4484 SBSDIO_FUNC1_WFRAMEBCHI,
4485 NULL);
4486 lo = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
4487 SBSDIO_FUNC1_WFRAMEBCLO,
4488 NULL);
4489 bus->f1regdata += 2;
4490 if ((hi == 0) && (lo == 0))
4491 break;
4492 }
4493
4494 }
4495 if (ret == 0)
4496 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
4497
4498 printf("Return_dpc value is : %d\n", ret);
4499 bus->ctrl_frame_stat = FALSE;
4500 dhd_wait_event_wakeup(bus->dhd);
4501 }
4502 /* Send queued frames (limit 1 if rx may still be pending) */
4503 else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
4504 pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
4505 && DATAOK(bus)) {
4506 framecnt = rxdone ? txlimit : MIN(txlimit, dhd_txminmax);
4507 framecnt = dhdsdio_sendfromq(bus, framecnt);
4508 txlimit -= framecnt;
4509 }
4510
4511 /* Resched if events or tx frames are pending,
4512 else await next interrupt */
4513 /* On failed register access, all bets are off:
4514 no resched or interrupts */
4515 if ((bus->dhd->busstate == DHD_BUS_DOWN) || bcmsdh_regfail(sdh)) {
4516 DHD_ERROR(("%s: failed backplane access over SDIO, halting "
4517 "operation %d\n", __func__, bcmsdh_regfail(sdh)));
4518 bus->dhd->busstate = DHD_BUS_DOWN;
4519 bus->intstatus = 0;
4520 } else if (bus->clkstate == CLK_PENDING) {
4521 DHD_INFO(("%s: rescheduled due to CLK_PENDING awaiting "
4522 "I_CHIPACTIVE interrupt\n", __func__));
4523 resched = TRUE;
4524 } else if (bus->intstatus || bus->ipend ||
4525 (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
4526 DATAOK(bus)) || PKT_AVAILABLE()) {
4527 resched = TRUE;
4528 }
4529
4530 bus->dpc_sched = resched;
4531
4532 /* If we're done for now, turn off clock request. */
4533 if ((bus->clkstate != CLK_PENDING)
4534 && bus->idletime == DHD_IDLE_IMMEDIATE) {
4535 bus->activity = FALSE;
4536 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4537 }
4538
4539 dhd_os_sdunlock(bus->dhd);
4540
4541 return resched;
4542}
4543
4544bool dhd_bus_dpc(struct dhd_bus *bus)
4545{
4546 bool resched;
4547
4548 /* Call the DPC directly. */
4549 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4550 resched = dhdsdio_dpc(bus);
4551
4552 return resched;
4553}
4554
4555void dhdsdio_isr(void *arg)
4556{
4557 dhd_bus_t *bus = (dhd_bus_t *) arg;
4558 bcmsdh_info_t *sdh;
4559
4560 DHD_TRACE(("%s: Enter\n", __func__));
4561
4562 if (!bus) {
4563 DHD_ERROR(("%s : bus is null pointer , exit\n", __func__));
4564 return;
4565 }
4566 sdh = bus->sdh;
4567
4568 if (bus->dhd->busstate == DHD_BUS_DOWN) {
4569 DHD_ERROR(("%s : bus is down. we have nothing to do\n",
4570 __func__));
4571 return;
4572 }
4573 /* Count the interrupt call */
4574 bus->intrcount++;
4575 bus->ipend = TRUE;
4576
4577 /* Shouldn't get this interrupt if we're sleeping? */
4578 if (bus->sleeping) {
4579 DHD_ERROR(("INTERRUPT WHILE SLEEPING??\n"));
4580 return;
4581 }
4582
4583 /* Disable additional interrupts (is this needed now)? */
4584 if (bus->intr)
4585 DHD_INTR(("%s: disable SDIO interrupts\n", __func__));
4586 else
4587 DHD_ERROR(("dhdsdio_isr() w/o interrupt configured!\n"));
4588
4589 bcmsdh_intr_disable(sdh);
4590 bus->intdis = TRUE;
4591
4592#if defined(SDIO_ISR_THREAD)
4593 DHD_TRACE(("Calling dhdsdio_dpc() from %s\n", __func__));
4594 while (dhdsdio_dpc(bus))
4595 ;
4596#else
4597 bus->dpc_sched = TRUE;
4598 dhd_sched_dpc(bus->dhd);
4599#endif
4600
4601}
4602
4603#ifdef SDTEST
4604static void dhdsdio_pktgen_init(dhd_bus_t *bus)
4605{
4606 /* Default to specified length, or full range */
4607 if (dhd_pktgen_len) {
4608 bus->pktgen_maxlen = MIN(dhd_pktgen_len, MAX_PKTGEN_LEN);
4609 bus->pktgen_minlen = bus->pktgen_maxlen;
4610 } else {
4611 bus->pktgen_maxlen = MAX_PKTGEN_LEN;
4612 bus->pktgen_minlen = 0;
4613 }
7d4df48e 4614 bus->pktgen_len = (u16) bus->pktgen_minlen;
cf2b4488
HP		 4615
4616 /* Default to per-watchdog burst with 10s print time */
4617 bus->pktgen_freq = 1;
4618 bus->pktgen_print = 10000 / dhd_watchdog_ms;
4619 bus->pktgen_count = (dhd_pktgen * dhd_watchdog_ms + 999) / 1000;
4620
4621 /* Default to echo mode */
4622 bus->pktgen_mode = DHD_PKTGEN_ECHO;
4623 bus->pktgen_stop = 1;
4624}
4625
4626static void dhdsdio_pktgen(dhd_bus_t *bus)
4627{
4628 void *pkt;
3fd79f7c 4629 u8 *data;
cf2b4488
HP		 4630 uint pktcount;
4631 uint fillbyte;
4632 osl_t *osh = bus->dhd->osh;
7d4df48e 4633 u16 len;
cf2b4488
HP		 4634
4635 /* Display current count if appropriate */
4636 if (bus->pktgen_print && (++bus->pktgen_ptick >= bus->pktgen_print)) {
4637 bus->pktgen_ptick = 0;
4638 printf("%s: send attempts %d rcvd %d\n",
4639 __func__, bus->pktgen_sent, bus->pktgen_rcvd);
4640 }
4641
4642 /* For recv mode, just make sure dongle has started sending */
4643 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4644 if (!bus->pktgen_rcvd)
4645 dhdsdio_sdtest_set(bus, TRUE);
4646 return;
4647 }
4648
4649 /* Otherwise, generate or request the specified number of packets */
4650 for (pktcount = 0; pktcount < bus->pktgen_count; pktcount++) {
4651 /* Stop if total has been reached */
4652 if (bus->pktgen_total
4653 && (bus->pktgen_sent >= bus->pktgen_total)) {
4654 bus->pktgen_count = 0;
4655 break;
4656 }
4657
4658 /* Allocate an appropriate-sized packet */
4659 len = bus->pktgen_len;
9b890325
JC		 4660 pkt = PKTGET(osh,
4661 (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
4662 TRUE);
4663 if (!pkt) {
cf2b4488
HP		 4664 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4665 break;
4666 }
4667 PKTALIGN(osh, pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
4668 DHD_SDALIGN);
3fd79f7c 4669 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
cf2b4488
HP		 4670
4671 /* Write test header cmd and extra based on mode */
4672 switch (bus->pktgen_mode) {
4673 case DHD_PKTGEN_ECHO:
4674 *data++ = SDPCM_TEST_ECHOREQ;
3fd79f7c 4675 *data++ = (u8) bus->pktgen_sent;
cf2b4488
HP		 4676 break;
4677
4678 case DHD_PKTGEN_SEND:
4679 *data++ = SDPCM_TEST_DISCARD;
3fd79f7c 4680 *data++ = (u8) bus->pktgen_sent;
cf2b4488
HP		 4681 break;
4682
4683 case DHD_PKTGEN_RXBURST:
4684 *data++ = SDPCM_TEST_BURST;
3fd79f7c 4685 *data++ = (u8) bus->pktgen_count;
cf2b4488
HP		 4686 break;
4687
4688 default:
4689 DHD_ERROR(("Unrecognized pktgen mode %d\n",
4690 bus->pktgen_mode));
4691 PKTFREE(osh, pkt, TRUE);
4692 bus->pktgen_count = 0;
4693 return;
4694 }
4695
4696 /* Write test header length field */
4697 *data++ = (len >> 0);
4698 *data++ = (len >> 8);
4699
4700 /* Then fill in the remainder -- N/A for burst,
4701 but who cares... */
4702 for (fillbyte = 0; fillbyte < len; fillbyte++)
4703 *data++ =
3fd79f7c 4704 SDPCM_TEST_FILL(fillbyte, (u8) bus->pktgen_sent);
cf2b4488
HP		 4705
4706#ifdef DHD_DEBUG
4707 if (DHD_BYTES_ON() && DHD_DATA_ON()) {
3fd79f7c 4708 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
cf2b4488
HP		 4709 prhex("dhdsdio_pktgen: Tx Data", data,
4710 PKTLEN(pkt) - SDPCM_HDRLEN);
4711 }
4712#endif
4713
4714 /* Send it */
4715 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE)) {
4716 bus->pktgen_fail++;
4717 if (bus->pktgen_stop
4718 && bus->pktgen_stop == bus->pktgen_fail)
4719 bus->pktgen_count = 0;
4720 }
4721 bus->pktgen_sent++;
4722
4723 /* Bump length if not fixed, wrap at max */
4724 if (++bus->pktgen_len > bus->pktgen_maxlen)
7d4df48e 4725 bus->pktgen_len = (u16) bus->pktgen_minlen;
cf2b4488
HP		 4726
4727 /* Special case for burst mode: just send one request! */
4728 if (bus->pktgen_mode == DHD_PKTGEN_RXBURST)
4729 break;
4730 }
4731}
4732
4733static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start)
4734{
4735 void *pkt;
3fd79f7c 4736 u8 *data;
cf2b4488
HP		 4737 osl_t *osh = bus->dhd->osh;
4738
4739 /* Allocate the packet */
9b890325
JC		 4740 pkt = PKTGET(osh, SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
4741 TRUE);
4742 if (!pkt) {
cf2b4488
HP		 4743 DHD_ERROR(("%s: PKTGET failed!\n", __func__));
4744 return;
4745 }
4746 PKTALIGN(osh, pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
3fd79f7c 4747 data = (u8 *) PKTDATA(pkt) + SDPCM_HDRLEN;
cf2b4488
HP		 4748
4749 /* Fill in the test header */
4750 *data++ = SDPCM_TEST_SEND;
4751 *data++ = start;
4752 *data++ = (bus->pktgen_maxlen >> 0);
4753 *data++ = (bus->pktgen_maxlen >> 8);
4754
4755 /* Send it */
4756 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE))
4757 bus->pktgen_fail++;
4758}
4759
4760static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq)
4761{
4762 osl_t *osh = bus->dhd->osh;
3fd79f7c 4763 u8 *data;
cf2b4488
HP		 4764 uint pktlen;
4765
3fd79f7c
GKH		 4766 u8 cmd;
4767 u8 extra;
7d4df48e
GKH		 4768 u16 len;
4769 u16 offset;
cf2b4488
HP		 4770
4771 /* Check for min length */
4772 pktlen = PKTLEN(pkt);
4773 if (pktlen < SDPCM_TEST_HDRLEN) {
4774 DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
4775 pktlen));
4776 PKTFREE(osh, pkt, FALSE);
4777 return;
4778 }
4779
4780 /* Extract header fields */
4781 data = PKTDATA(pkt);
4782 cmd = *data++;
4783 extra = *data++;
4784 len = *data++;
4785 len += *data++ << 8;
4786
4787 /* Check length for relevant commands */
4788 if (cmd == SDPCM_TEST_DISCARD || cmd == SDPCM_TEST_ECHOREQ
4789 || cmd == SDPCM_TEST_ECHORSP) {
4790 if (pktlen != len + SDPCM_TEST_HDRLEN) {
4791 DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
4792 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4793 pktlen, seq, cmd, extra, len));
4794 PKTFREE(osh, pkt, FALSE);
4795 return;
4796 }
4797 }
4798
4799 /* Process as per command */
4800 switch (cmd) {
4801 case SDPCM_TEST_ECHOREQ:
4802 /* Rx->Tx turnaround ok (even on NDIS w/current
4803 implementation) */
3fd79f7c 4804 *(u8 *) (PKTDATA(pkt)) = SDPCM_TEST_ECHORSP;
cf2b4488
HP		 4805 if (dhdsdio_txpkt(bus, pkt, SDPCM_TEST_CHANNEL, TRUE) == 0) {
4806 bus->pktgen_sent++;
4807 } else {
4808 bus->pktgen_fail++;
4809 PKTFREE(osh, pkt, FALSE);
4810 }
4811 bus->pktgen_rcvd++;
4812 break;
4813
4814 case SDPCM_TEST_ECHORSP:
4815 if (bus->ext_loop) {
4816 PKTFREE(osh, pkt, FALSE);
4817 bus->pktgen_rcvd++;
4818 break;
4819 }
4820
4821 for (offset = 0; offset < len; offset++, data++) {
4822 if (*data != SDPCM_TEST_FILL(offset, extra)) {
4823 DHD_ERROR(("dhdsdio_testrcv: echo data mismatch: " "offset %d (len %d) expect 0x%02x rcvd 0x%02x\n",
4824 offset, len,
4825 SDPCM_TEST_FILL(offset, extra), *data));
4826 break;
4827 }
4828 }
4829 PKTFREE(osh, pkt, FALSE);
4830 bus->pktgen_rcvd++;
4831 break;
4832
4833 case SDPCM_TEST_DISCARD:
4834 PKTFREE(osh, pkt, FALSE);
4835 bus->pktgen_rcvd++;
4836 break;
4837
4838 case SDPCM_TEST_BURST:
4839 case SDPCM_TEST_SEND:
4840 default:
4841 DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
4842 "pktlen %d seq %d" " cmd %d extra %d len %d\n",
4843 pktlen, seq, cmd, extra, len));
4844 PKTFREE(osh, pkt, FALSE);
4845 break;
4846 }
4847
4848 /* For recv mode, stop at limie (and tell dongle to stop sending) */
4849 if (bus->pktgen_mode == DHD_PKTGEN_RECV) {
4850 if (bus->pktgen_total
4851 && (bus->pktgen_rcvd >= bus->pktgen_total)) {
4852 bus->pktgen_count = 0;
4853 dhdsdio_sdtest_set(bus, FALSE);
4854 }
4855 }
4856}
4857#endif /* SDTEST */
4858
4859extern bool dhd_bus_watchdog(dhd_pub_t *dhdp)
4860{
4861 dhd_bus_t *bus;
4862
4863 DHD_TIMER(("%s: Enter\n", __func__));
4864
4865 bus = dhdp->bus;
4866
4867 if (bus->dhd->dongle_reset)
4868 return FALSE;
4869
4870 /* Ignore the timer if simulating bus down */
4871 if (bus->sleeping)
4872 return FALSE;
4873
4874 dhd_os_sdlock(bus->dhd);
4875
4876 /* Poll period: check device if appropriate. */
4877 if (bus->poll && (++bus->polltick >= bus->pollrate)) {
66cbd3ab 4878 u32 intstatus = 0;
cf2b4488
HP		 4879
4880 /* Reset poll tick */
4881 bus->polltick = 0;
4882
4883 /* Check device if no interrupts */
4884 if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
4885
4886 if (!bus->dpc_sched) {
3fd79f7c 4887 u8 devpend;
cf2b4488
HP		 4888 devpend = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_0,
4889 SDIOD_CCCR_INTPEND,
4890 NULL);
4891 intstatus =
4892 devpend & (INTR_STATUS_FUNC1 |
4893 INTR_STATUS_FUNC2);
4894 }
4895
4896 /* If there is something, make like the ISR and
4897 schedule the DPC */
4898 if (intstatus) {
4899 bus->pollcnt++;
4900 bus->ipend = TRUE;
4901 if (bus->intr)
4902 bcmsdh_intr_disable(bus->sdh);
4903
4904 bus->dpc_sched = TRUE;
4905 dhd_sched_dpc(bus->dhd);
4906
4907 }
4908 }
4909
4910 /* Update interrupt tracking */
4911 bus->lastintrs = bus->intrcount;
4912 }
4913#ifdef DHD_DEBUG
4914 /* Poll for console output periodically */
4915 if (dhdp->busstate == DHD_BUS_DATA && dhd_console_ms != 0) {
4916 bus->console.count += dhd_watchdog_ms;
4917 if (bus->console.count >= dhd_console_ms) {
4918 bus->console.count -= dhd_console_ms;
4919 /* Make sure backplane clock is on */
4920 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4921 if (dhdsdio_readconsole(bus) < 0)
4922 dhd_console_ms = 0; /* On error,
4923 stop trying */
4924 }
4925 }
4926#endif /* DHD_DEBUG */
4927
4928#ifdef SDTEST
4929 /* Generate packets if configured */
4930 if (bus->pktgen_count && (++bus->pktgen_tick >= bus->pktgen_freq)) {
4931 /* Make sure backplane clock is on */
4932 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4933 bus->pktgen_tick = 0;
4934 dhdsdio_pktgen(bus);
4935 }
4936#endif
4937
4938 /* On idle timeout clear activity flag and/or turn off clock */
4939 if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
4940 if (++bus->idlecount >= bus->idletime) {
4941 bus->idlecount = 0;
4942 if (bus->activity) {
4943 bus->activity = FALSE;
4944 dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
4945 } else {
4946 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
4947 }
4948 }
4949 }
4950
4951 dhd_os_sdunlock(bus->dhd);
4952
4953 return bus->ipend;
4954}
4955
4956#ifdef DHD_DEBUG
580a0bd9 4957extern int dhd_bus_console_in(dhd_pub_t *dhdp, unsigned char *msg, uint msglen)
cf2b4488
HP		 4958{
4959 dhd_bus_t *bus = dhdp->bus;
66cbd3ab 4960 u32 addr, val;
cf2b4488
HP		 4961 int rv;
4962 void *pkt;
4963
4964 /* Address could be zero if CONSOLE := 0 in dongle Makefile */
4965 if (bus->console_addr == 0)
4966 return BCME_UNSUPPORTED;
4967
4968 /* Exclusive bus access */
4969 dhd_os_sdlock(bus->dhd);
4970
4971 /* Don't allow input if dongle is in reset */
4972 if (bus->dhd->dongle_reset) {
4973 dhd_os_sdunlock(bus->dhd);
4974 return BCME_NOTREADY;
4975 }
4976
4977 /* Request clock to allow SDIO accesses */
4978 BUS_WAKE(bus);
4979 /* No pend allowed since txpkt is called later, ht clk has to be on */
4980 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
4981
4982 /* Zero cbuf_index */
4983 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, cbuf_idx);
4984 val = htol32(0);
3fd79f7c 4985 rv = dhdsdio_membytes(bus, TRUE, addr, (u8 *)&val, sizeof(val));
9b890325 4986 if (rv < 0)
cf2b4488
HP		 4987 goto done;
4988
4989 /* Write message into cbuf */
4990 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, cbuf);
3fd79f7c 4991 rv = dhdsdio_membytes(bus, TRUE, addr, (u8 *)msg, msglen);
9b890325 4992 if (rv < 0)
cf2b4488
HP		 4993 goto done;
4994
4995 /* Write length into vcons_in */
4996 addr = bus->console_addr + OFFSETOF(hndrte_cons_t, vcons_in);
4997 val = htol32(msglen);
3fd79f7c 4998 rv = dhdsdio_membytes(bus, TRUE, addr, (u8 *)&val, sizeof(val));
9b890325 4999 if (rv < 0)
cf2b4488
HP		 5000 goto done;
5001
5002 /* Bump dongle by sending an empty event pkt.
5003 * sdpcm_sendup (RX) checks for virtual console input.
5004 */
9b890325
JC		 5005 pkt = PKTGET(bus->dhd->osh, 4 + SDPCM_RESERVE, TRUE);
5006 if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
cf2b4488
HP		 5007 dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, TRUE);
5008
5009done:
5010 if ((bus->idletime == DHD_IDLE_IMMEDIATE) && !bus->dpc_sched) {
5011 bus->activity = FALSE;
5012 dhdsdio_clkctl(bus, CLK_NONE, TRUE);
5013 }
5014
5015 dhd_os_sdunlock(bus->dhd);
5016
5017 return rv;
5018}
5019#endif /* DHD_DEBUG */
5020
5021#ifdef DHD_DEBUG
3fd79f7c 5022static void dhd_dump_cis(uint fn, u8 *cis)
cf2b4488
HP		 5023{
5024 uint byte, tag, tdata;
5025 DHD_INFO(("Function %d CIS:\n", fn));
5026
5027 for (tdata = byte = 0; byte < SBSDIO_CIS_SIZE_LIMIT; byte++) {
5028 if ((byte % 16) == 0)
5029 DHD_INFO((" "));
5030 DHD_INFO(("%02x ", cis[byte]));
5031 if ((byte % 16) == 15)
5032 DHD_INFO(("\n"));
5033 if (!tdata--) {
5034 tag = cis[byte];
5035 if (tag == 0xff)
5036 break;
5037 else if (!tag)
5038 tdata = 0;
5039 else if ((byte + 1) < SBSDIO_CIS_SIZE_LIMIT)
5040 tdata = cis[byte + 1] + 1;
5041 else
5042 DHD_INFO(("]"));
5043 }
5044 }
5045 if ((byte % 16) != 15)
5046 DHD_INFO(("\n"));
5047}
5048#endif /* DHD_DEBUG */
5049
7d4df48e 5050static bool dhdsdio_chipmatch(u16 chipid)
cf2b4488
HP		 5051{
5052 if (chipid == BCM4325_CHIP_ID)
5053 return TRUE;
5054 if (chipid == BCM4329_CHIP_ID)
5055 return TRUE;
5056 if (chipid == BCM4319_CHIP_ID)
5057 return TRUE;
5058 return FALSE;
5059}
5060
7d4df48e
GKH		 5061static void *dhdsdio_probe(u16 venid, u16 devid, u16 bus_no,
5062 u16 slot, u16 func, uint bustype, void *regsva,
cf2b4488
HP		 5063 osl_t *osh, void *sdh)
5064{
5065 int ret;
5066 dhd_bus_t *bus;
5067
5068 /* Init global variables at run-time, not as part of the declaration.
5069 * This is required to support init/de-init of the driver.
5070 * Initialization
5071 * of globals as part of the declaration results in non-deterministic
5072 * behavior since the value of the globals may be different on the
5073 * first time that the driver is initialized vs subsequent
5074 * initializations.
5075 */
5076 dhd_txbound = DHD_TXBOUND;
5077 dhd_rxbound = DHD_RXBOUND;
5078 dhd_alignctl = TRUE;
5079 sd1idle = TRUE;
5080 dhd_readahead = TRUE;
5081 retrydata = FALSE;
5082 dhd_doflow = FALSE;
5083 dhd_dongle_memsize = 0;
5084 dhd_txminmax = DHD_TXMINMAX;
5085
5086 forcealign = TRUE;
5087
5088 dhd_common_init();
5089
5090 DHD_TRACE(("%s: Enter\n", __func__));
5091 DHD_INFO(("%s: venid 0x%04x devid 0x%04x\n", __func__, venid, devid));
5092
5093 /* We make assumptions about address window mappings */
5094 ASSERT((uintptr) regsva == SI_ENUM_BASE);
5095
5096 /* BCMSDH passes venid and devid based on CIS parsing -- but
5097 * low-power start
5098 * means early parse could fail, so here we should get either an ID
5099 * we recognize OR (-1) indicating we must request power first.
5100 */
5101 /* Check the Vendor ID */
5102 switch (venid) {
5103 case 0x0000:
5104 case VENDOR_BROADCOM:
5105 break;
5106 default:
5107 DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
5108 return NULL;
5109 }
5110
5111 /* Check the Device ID and make sure it's one that we support */
5112 switch (devid) {
5113 case BCM4325_D11DUAL_ID: /* 4325 802.11a/g id */
5114 case BCM4325_D11G_ID: /* 4325 802.11g 2.4Ghz band id */
5115 case BCM4325_D11A_ID: /* 4325 802.11a 5Ghz band id */
5116 DHD_INFO(("%s: found 4325 Dongle\n", __func__));
5117 break;
5118 case BCM4329_D11NDUAL_ID: /* 4329 802.11n dualband device */
5119 case BCM4329_D11N2G_ID: /* 4329 802.11n 2.4G device */
5120 case BCM4329_D11N5G_ID: /* 4329 802.11n 5G device */
5121 case 0x4329:
5122 DHD_INFO(("%s: found 4329 Dongle\n", __func__));
5123 break;
5124 case BCM4319_D11N_ID: /* 4319 802.11n id */
5125 case BCM4319_D11N2G_ID: /* 4319 802.11n2g id */
5126 case BCM4319_D11N5G_ID: /* 4319 802.11n5g id */
5127 DHD_INFO(("%s: found 4319 Dongle\n", __func__));
5128 break;
5129 case 0:
5130 DHD_INFO(("%s: allow device id 0, will check chip internals\n",
5131 __func__));
5132 break;
5133
5134 default:
5135 DHD_ERROR(("%s: skipping 0x%04x/0x%04x, not a dongle\n",
5136 __func__, venid, devid));
5137 return NULL;
5138 }
5139
5140 if (osh == NULL) {
5141 /* Ask the OS interface part for an OSL handle */
5142 osh = dhd_osl_attach(sdh, DHD_BUS);
5143 if (!osh) {
5144 DHD_ERROR(("%s: osl_attach failed!\n", __func__));
5145 return NULL;
5146 }
5147 }
5148
5149 /* Allocate private bus interface state */
5150 bus = MALLOC(osh, sizeof(dhd_bus_t));
5151 if (!bus) {
5152 DHD_ERROR(("%s: MALLOC of dhd_bus_t failed\n", __func__));
5153 goto fail;
5154 }
5155 bzero(bus, sizeof(dhd_bus_t));
5156 bus->sdh = sdh;
7d4df48e 5157 bus->cl_devid = (u16) devid;
cf2b4488
HP		 5158 bus->bus = DHD_BUS;
5159 bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
5160 bus->usebufpool = FALSE; /* Use bufpool if allocated,
5161 else use locally malloced rxbuf */
5162
5163 /* attempt to attach to the dongle */
5164 if (!(dhdsdio_probe_attach(bus, osh, sdh, regsva, devid))) {
5165 DHD_ERROR(("%s: dhdsdio_probe_attach failed\n", __func__));
5166 goto fail;
5167 }
5168
5169 /* Attach to the dhd/OS/network interface */
5170 bus->dhd = dhd_attach(osh, bus, SDPCM_RESERVE);
5171 if (!bus->dhd) {
5172 DHD_ERROR(("%s: dhd_attach failed\n", __func__));
5173 goto fail;
5174 }
5175
5176 /* Allocate buffers */
5177 if (!(dhdsdio_probe_malloc(bus, osh, sdh))) {
5178 DHD_ERROR(("%s: dhdsdio_probe_malloc failed\n", __func__));
5179 goto fail;
5180 }
5181
5182 if (!(dhdsdio_probe_init(bus, osh, sdh))) {
5183 DHD_ERROR(("%s: dhdsdio_probe_init failed\n", __func__));
5184 goto fail;
5185 }
5186
5187 /* Register interrupt callback, but mask it (not operational yet). */
5188 DHD_INTR(("%s: disable SDIO interrupts (not interested yet)\n",
5189 __func__));
5190 bcmsdh_intr_disable(sdh);
5191 ret = bcmsdh_intr_reg(sdh, dhdsdio_isr, bus);
5192 if (ret != 0) {
5193 DHD_ERROR(("%s: FAILED: bcmsdh_intr_reg returned %d\n",
5194 __func__, ret));
5195 goto fail;
5196 }
5197 DHD_INTR(("%s: registered SDIO interrupt function ok\n", __func__));
5198
5199 DHD_INFO(("%s: completed!!\n", __func__));
5200
5201 /* if firmware path present try to download and bring up bus */
9b890325
JC		 5202 ret = dhd_bus_start(bus->dhd);
5203 if (ret != 0) {
cf2b4488
HP		 5204 if (ret == BCME_NOTUP) {
5205 DHD_ERROR(("%s: dongle is not responding\n", __func__));
5206 goto fail;
5207 }
5208 }
5209 /* Ok, have the per-port tell the stack we're open for business */
5210 if (dhd_net_attach(bus->dhd, 0) != 0) {
5211 DHD_ERROR(("%s: Net attach failed!!\n", __func__));
5212 goto fail;
5213 }
5214
5215 return bus;
5216
5217fail:
5218 dhdsdio_release(bus, osh);
5219 return NULL;
5220}
5221
5222static bool
5223dhdsdio_probe_attach(struct dhd_bus *bus, osl_t *osh, void *sdh, void *regsva,
7d4df48e 5224 u16 devid)
cf2b4488 5225{
3fd79f7c 5226 u8 clkctl = 0;
cf2b4488
HP		 5227 int err = 0;
5228
5229 bus->alp_only = TRUE;
5230
5231 /* Return the window to backplane enumeration space for core access */
5232 if (dhdsdio_set_siaddr_window(bus, SI_ENUM_BASE))
5233 DHD_ERROR(("%s: FAILED to return to SI_ENUM_BASE\n", __func__));
5234
5235#ifdef DHD_DEBUG
5236 printf("F1 signature read @0x18000000=0x%4x\n",
5237 bcmsdh_reg_read(bus->sdh, SI_ENUM_BASE, 4));
5238
5239#endif /* DHD_DEBUG */
5240
5241 /* Force PLL off until si_attach() programs PLL control regs */
5242
5243 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5244 DHD_INIT_CLKCTL1, &err);
5245 if (!err)
5246 clkctl =
5247 bcmsdh_cfg_read(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5248 &err);
5249
5250 if (err || ((clkctl & ~SBSDIO_AVBITS) != DHD_INIT_CLKCTL1)) {
5251 DHD_ERROR(("dhdsdio_probe: ChipClkCSR access: err %d wrote "
5252 "0x%02x read 0x%02x\n",
5253 err, DHD_INIT_CLKCTL1, clkctl));
5254 goto fail;
5255 }
5256#ifdef DHD_DEBUG
5257 if (DHD_INFO_ON()) {
5258 uint fn, numfn;
3fd79f7c 5259 u8 *cis[SDIOD_MAX_IOFUNCS];
cf2b4488
HP		 5260 int err = 0;
5261
5262 numfn = bcmsdh_query_iofnum(sdh);
5263 ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
5264
5265 /* Make sure ALP is available before trying to read CIS */
5266 SPINWAIT(((clkctl = bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
5267 SBSDIO_FUNC1_CHIPCLKCSR,
5268 NULL)),
5269 !SBSDIO_ALPAV(clkctl)), PMU_MAX_TRANSITION_DLY);
5270
5271 /* Now request ALP be put on the bus */
5272 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
5273 DHD_INIT_CLKCTL2, &err);
5274 OSL_DELAY(65);
5275
5276 for (fn = 0; fn <= numfn; fn++) {
9b890325
JC		 5277 cis[fn] = MALLOC(osh, SBSDIO_CIS_SIZE_LIMIT);
5278 if (!cis[fn]) {
cf2b4488
HP		 5279 DHD_INFO(("dhdsdio_probe: fn %d cis malloc "
5280 "failed\n", fn));
5281 break;
5282 }
5283 bzero(cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5284
9b890325
JC		 5285 err = bcmsdh_cis_read(sdh, fn, cis[fn],
5286 SBSDIO_CIS_SIZE_LIMIT);
5287 if (err) {
cf2b4488
HP		 5288 DHD_INFO(("dhdsdio_probe: fn %d cis read "
5289 "err %d\n", fn, err));
5290 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5291 break;
5292 }
5293 dhd_dump_cis(fn, cis[fn]);
5294 }
5295
5296 while (fn-- > 0) {
5297 ASSERT(cis[fn]);
5298 MFREE(osh, cis[fn], SBSDIO_CIS_SIZE_LIMIT);
5299 }
5300
5301 if (err) {
5302 DHD_ERROR(("dhdsdio_probe: error read/parsing CIS\n"));
5303 goto fail;
5304 }
5305 }
5306#endif /* DHD_DEBUG */
5307
5308 /* si_attach() will provide an SI handle and scan the backplane */
5309 bus->sih = si_attach((uint) devid, osh, regsva, DHD_BUS, sdh,
5310 &bus->vars, &bus->varsz);
5311 if (!(bus->sih)) {
5312 DHD_ERROR(("%s: si_attach failed!\n", __func__));
5313 goto fail;
5314 }
5315
5316 bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
5317
7d4df48e 5318 if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
cf2b4488
HP		 5319 DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
5320 __func__, bus->sih->chip));
5321 goto fail;
5322 }
5323
5324 si_sdiod_drive_strength_init(bus->sih, osh, dhd_sdiod_drive_strength);
5325
5326 /* Get info on the ARM and SOCRAM cores... */
5327 if (!DHD_NOPMU(bus)) {
5328 if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
5329 (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
5330 bus->armrev = si_corerev(bus->sih);
5331 } else {
5332 DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
5333 goto fail;
5334 }
5335 bus->orig_ramsize = si_socram_size(bus->sih);
5336 if (!(bus->orig_ramsize)) {
5337 DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
5338 __func__));
5339 goto fail;
5340 }
5341 bus->ramsize = bus->orig_ramsize;
5342 if (dhd_dongle_memsize)
5343 dhd_dongle_setmemsize(bus, dhd_dongle_memsize);
5344
5345 DHD_ERROR(("DHD: dongle ram size is set to %d(orig %d)\n",
5346 bus->ramsize, bus->orig_ramsize));
5347 }
5348
5349 /* ...but normally deal with the SDPCMDEV core */
9b890325
JC		 5350 bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
5351 if (!bus->regs) {
5352 bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
5353 if (!bus->regs) {
5354 DHD_ERROR(("%s: failed to find SDIODEV core!\n",
5355 __func__));
5356 goto fail;
5357 }
cf2b4488
HP		 5358 }
5359 bus->sdpcmrev = si_corerev(bus->sih);
5360
5361 /* Set core control so an SDIO reset does a backplane reset */
5362 OR_REG(osh, &bus->regs->corecontrol, CC_BPRESEN);
5363
5364 pktq_init(&bus->txq, (PRIOMASK + 1), QLEN);
5365
5366 /* Locate an appropriately-aligned portion of hdrbuf */
3fd79f7c 5367 bus->rxhdr = (u8 *) ROUNDUP((uintptr)&bus->hdrbuf[0], DHD_SDALIGN);
cf2b4488
HP		 5368
5369 /* Set the poll and/or interrupt flags */
5370 bus->intr = (bool) dhd_intr;
9b890325
JC		 5371 bus->poll = (bool) dhd_poll;
5372 if (bus->poll)
cf2b4488
HP		 5373 bus->pollrate = 1;
5374
5375 return TRUE;
5376
5377fail:
5378 return FALSE;
5379}
5380
5381static bool dhdsdio_probe_malloc(dhd_bus_t *bus, osl_t *osh, void *sdh)
5382{
5383 DHD_TRACE(("%s: Enter\n", __func__));
5384
5385#ifndef DHD_USE_STATIC_BUF
5386 if (bus->dhd->maxctl) {
5387 bus->rxblen =
5388 ROUNDUP((bus->dhd->maxctl + SDPCM_HDRLEN),
5389 ALIGNMENT) + DHD_SDALIGN;
5390 bus->rxbuf = MALLOC(osh, bus->rxblen);
5391 if (!(bus->rxbuf)) {
5392 DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
5393 __func__, bus->rxblen));
5394 goto fail;
5395 }
5396 }
5397
5398 /* Allocate buffer to receive glomed packet */
5399 bus->databuf = MALLOC(osh, MAX_DATA_BUF);
5400 if (!(bus->databuf)) {
5401 DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
5402 __func__, MAX_DATA_BUF));
5403 /* release rxbuf which was already located as above */
5404 if (!bus->rxblen)
5405 MFREE(osh, bus->rxbuf, bus->rxblen);
5406 goto fail;
5407 }
5408#else
5409 if (bus->dhd->maxctl) {
5410 bus->rxblen =
5411 ROUNDUP((bus->dhd->maxctl + SDPCM_HDRLEN),
5412 ALIGNMENT) + DHD_SDALIGN;
5413 bus->rxbuf = dhd_os_prealloc(DHD_PREALLOC_RXBUF, bus->rxblen);
5414 if (!(bus->rxbuf)) {
5415 DHD_ERROR(("%s: MALLOC of %d-byte rxbuf failed\n",
5416 __func__, bus->rxblen));
5417 goto fail;
5418 }
5419 }
5420 /* Allocate buffer to receive glomed packet */
5421 bus->databuf = dhd_os_prealloc(DHD_PREALLOC_DATABUF, MAX_DATA_BUF);
5422 if (!(bus->databuf)) {
5423 DHD_ERROR(("%s: MALLOC of %d-byte databuf failed\n",
5424 __func__, MAX_DATA_BUF));
5425 goto fail;
5426 }
5427#endif /* DHD_USE_STATIC_BUF */
5428
5429 /* Align the buffer */
5430 if ((uintptr) bus->databuf % DHD_SDALIGN)
5431 bus->dataptr =
5432 bus->databuf + (DHD_SDALIGN -
5433 ((uintptr) bus->databuf % DHD_SDALIGN));
5434 else
5435 bus->dataptr = bus->databuf;
5436
5437 return TRUE;
5438
5439fail:
5440 return FALSE;
5441}
5442
5443static bool dhdsdio_probe_init(dhd_bus_t *bus, osl_t *osh, void *sdh)
5444{
3e26416e 5445 s32 fnum;
cf2b4488
HP		 5446
5447 DHD_TRACE(("%s: Enter\n", __func__));
5448
5449#ifdef SDTEST
5450 dhdsdio_pktgen_init(bus);
5451#endif /* SDTEST */
5452
5453 /* Disable F2 to clear any intermediate frame state on the dongle */
5454 bcmsdh_cfg_write(sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN, SDIO_FUNC_ENABLE_1,
5455 NULL);
5456
5457 bus->dhd->busstate = DHD_BUS_DOWN;
5458 bus->sleeping = FALSE;
5459 bus->rxflow = FALSE;
5460 bus->prev_rxlim_hit = 0;
5461
5462 /* Done with backplane-dependent accesses, can drop clock... */
5463 bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
5464
5465 /* ...and initialize clock/power states */
5466 bus->clkstate = CLK_SDONLY;
3e26416e 5467 bus->idletime = (s32) dhd_idletime;
cf2b4488
HP		 5468 bus->idleclock = DHD_IDLE_ACTIVE;
5469
5470 /* Query the SD clock speed */
5471 if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
3e26416e 5472 &bus->sd_divisor, sizeof(s32),
cf2b4488
HP		 5473 FALSE) != BCME_OK) {
5474 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
5475 bus->sd_divisor = -1;
5476 } else {
5477 DHD_INFO(("%s: Initial value for %s is %d\n",
5478 __func__, "sd_divisor", bus->sd_divisor));
5479 }
5480
5481 /* Query the SD bus mode */
5482 if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
3e26416e 5483 &bus->sd_mode, sizeof(s32), FALSE) != BCME_OK) {
cf2b4488
HP		 5484 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
5485 bus->sd_mode = -1;
5486 } else {
5487 DHD_INFO(("%s: Initial value for %s is %d\n",
5488 __func__, "sd_mode", bus->sd_mode));
5489 }
5490
5491 /* Query the F2 block size, set roundup accordingly */
5492 fnum = 2;
3e26416e
GKH		 5493 if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
5494 &bus->blocksize, sizeof(s32), FALSE) != BCME_OK) {
cf2b4488
HP		 5495 bus->blocksize = 0;
5496 DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
5497 } else {
5498 DHD_INFO(("%s: Initial value for %s is %d\n",
5499 __func__, "sd_blocksize", bus->blocksize));
5500 }
5501 bus->roundup = MIN(max_roundup, bus->blocksize);
5502
5503 /* Query if bus module supports packet chaining,
5504 default to use if supported */
5505 if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
3e26416e 5506 &bus->sd_rxchain, sizeof(s32),
cf2b4488
HP		 5507 FALSE) != BCME_OK) {
5508 bus->sd_rxchain = FALSE;
5509 } else {
5510 DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
5511 __func__,
5512 (bus->sd_rxchain ? "supports" : "does not support")));
5513 }
5514 bus->use_rxchain = (bool) bus->sd_rxchain;
5515
5516 return TRUE;
5517}
5518
5519bool
5520dhd_bus_download_firmware(struct dhd_bus *bus, osl_t *osh,
5521 char *fw_path, char *nv_path)
5522{
5523 bool ret;
5524 bus->fw_path = fw_path;
5525 bus->nv_path = nv_path;
5526
5527 ret = dhdsdio_download_firmware(bus, osh, bus->sdh);
5528
5529 return ret;
5530}
5531
5532static bool
5533dhdsdio_download_firmware(struct dhd_bus *bus, osl_t *osh, void *sdh)
5534{
5535 bool ret;
5536
5537 /* Download the firmware */
5538 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5539
5540 ret = _dhdsdio_download_firmware(bus) == 0;
5541
5542 dhdsdio_clkctl(bus, CLK_SDONLY, FALSE);
5543
5544 return ret;
5545}
5546
5547/* Detach and free everything */
5548static void dhdsdio_release(dhd_bus_t *bus, osl_t *osh)
5549{
5550 DHD_TRACE(("%s: Enter\n", __func__));
5551
5552 if (bus) {
5553 ASSERT(osh);
5554
5555 /* De-register interrupt handler */
5556 bcmsdh_intr_disable(bus->sdh);
5557 bcmsdh_intr_dereg(bus->sdh);
5558
5559 if (bus->dhd) {
5560
5561 dhdsdio_release_dongle(bus, osh);
5562
5563 dhd_detach(bus->dhd);
5564 bus->dhd = NULL;
5565 }
5566
5567 dhdsdio_release_malloc(bus, osh);
5568
5569 MFREE(osh, bus, sizeof(dhd_bus_t));
5570 }
5571
5572 if (osh)
5573 dhd_osl_detach(osh);
5574
5575 DHD_TRACE(("%s: Disconnected\n", __func__));
5576}
5577
5578static void dhdsdio_release_malloc(dhd_bus_t *bus, osl_t *osh)
5579{
5580 DHD_TRACE(("%s: Enter\n", __func__));
5581
5582 if (bus->dhd && bus->dhd->dongle_reset)
5583 return;
5584
5585 if (bus->rxbuf) {
5586#ifndef DHD_USE_STATIC_BUF
5587 MFREE(osh, bus->rxbuf, bus->rxblen);
5588#endif
5589 bus->rxctl = bus->rxbuf = NULL;
5590 bus->rxlen = 0;
5591 }
5592
5593 if (bus->databuf) {
5594#ifndef DHD_USE_STATIC_BUF
5595 MFREE(osh, bus->databuf, MAX_DATA_BUF);
5596#endif
5597 bus->databuf = NULL;
5598 }
5599}
5600
5601static void dhdsdio_release_dongle(dhd_bus_t *bus, osl_t *osh)
5602{
5603 DHD_TRACE(("%s: Enter\n", __func__));
5604
5605 if (bus->dhd && bus->dhd->dongle_reset)
5606 return;
5607
5608 if (bus->sih) {
5609 dhdsdio_clkctl(bus, CLK_AVAIL, FALSE);
5610#if !defined(BCMLXSDMMC)
5611 si_watchdog(bus->sih, 4);
5612#endif /* !defined(BCMLXSDMMC) */
5613 dhdsdio_clkctl(bus, CLK_NONE, FALSE);
5614 si_detach(bus->sih);
5615 if (bus->vars && bus->varsz)
5616 MFREE(osh, bus->vars, bus->varsz);
5617 bus->vars = NULL;
5618 }
5619
5620 DHD_TRACE(("%s: Disconnected\n", __func__));
5621}
5622
5623static void dhdsdio_disconnect(void *ptr)
5624{
5625 dhd_bus_t *bus = (dhd_bus_t *)ptr;
5626
5627 DHD_TRACE(("%s: Enter\n", __func__));
5628
5629 if (bus) {
5630 ASSERT(bus->dhd);
5631 dhdsdio_release(bus, bus->dhd->osh);
5632 }
5633
5634 DHD_TRACE(("%s: Disconnected\n", __func__));
5635}
5636
5637/* Register/Unregister functions are called by the main DHD entry
5638 * point (e.g. module insertion) to link with the bus driver, in
5639 * order to look for or await the device.
5640 */
5641
5642static bcmsdh_driver_t dhd_sdio = {
5643 dhdsdio_probe,
5644 dhdsdio_disconnect
5645};
5646
5647int dhd_bus_register(void)
5648{
5649 DHD_TRACE(("%s: Enter\n", __func__));
5650
5651 return bcmsdh_register(&dhd_sdio);
5652}
5653
5654void dhd_bus_unregister(void)
5655{
5656 DHD_TRACE(("%s: Enter\n", __func__));
5657
5658 bcmsdh_unregister();
5659}
5660
5661#ifdef BCMEMBEDIMAGE
5662static int dhdsdio_download_code_array(struct dhd_bus *bus)
5663{
5664 int bcmerror = -1;
5665 int offset = 0;
5666
5667 DHD_INFO(("%s: download embedded firmware...\n", __func__));
5668
5669 /* Download image */
5670 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5671 bcmerror =
5672 dhdsdio_membytes(bus, TRUE, offset, dlarray + offset,
5673 MEMBLOCK);
5674 if (bcmerror) {
5675 DHD_ERROR(("%s: error %d on writing %d membytes at "
5676 "0x%08x\n",
5677 __func__, bcmerror, MEMBLOCK, offset));
5678 goto err;
5679 }
5680
5681 offset += MEMBLOCK;
5682 }
5683
5684 if (offset < sizeof(dlarray)) {
5685 bcmerror = dhdsdio_membytes(bus, TRUE, offset,
5686 dlarray + offset,
5687 sizeof(dlarray) - offset);
5688 if (bcmerror) {
5689 DHD_ERROR(("%s: error %d on writing %d membytes at "
5690 "0x%08x\n", __func__, bcmerror,
5691 sizeof(dlarray) - offset, offset));
5692 goto err;
5693 }
5694 }
5695#ifdef DHD_DEBUG
5696 /* Upload and compare the downloaded code */
5697 {
5698 unsigned char *ularray;
5699
5700 ularray = MALLOC(bus->dhd->osh, bus->ramsize);
5701 /* Upload image to verify downloaded contents. */
5702 offset = 0;
5703 memset(ularray, 0xaa, bus->ramsize);
5704 while ((offset + MEMBLOCK) < sizeof(dlarray)) {
5705 bcmerror =
5706 dhdsdio_membytes(bus, FALSE, offset,
5707 ularray + offset, MEMBLOCK);
5708 if (bcmerror) {
5709 DHD_ERROR(("%s: error %d on reading %d membytes"
5710 " at 0x%08x\n",
5711 __func__, bcmerror, MEMBLOCK, offset));
5712 goto err;
5713 }
5714
5715 offset += MEMBLOCK;
5716 }
5717
5718 if (offset < sizeof(dlarray)) {
5719 bcmerror = dhdsdio_membytes(bus, FALSE, offset,
5720 ularray + offset,
5721 sizeof(dlarray) - offset);
5722 if (bcmerror) {
5723 DHD_ERROR(("%s: error %d on reading %d membytes at 0x%08x\n",
5724 __func__, bcmerror,
5725 sizeof(dlarray) - offset, offset));
5726 goto err;
5727 }
5728 }
5729
5730 if (memcmp(dlarray, ularray, sizeof(dlarray))) {
5731 DHD_ERROR(("%s: Downloaded image is corrupted.\n",
5732 __func__));
5733 ASSERT(0);
5734 goto err;
5735 } else
5736 DHD_ERROR(("%s: Download/Upload/Compare succeeded.\n",
5737 __func__));
5738
5739 MFREE(bus->dhd->osh, ularray, bus->ramsize);
5740 }
5741#endif /* DHD_DEBUG */
5742
5743err:
5744 return bcmerror;
5745}
5746#endif /* BCMEMBEDIMAGE */
5747
5748static int dhdsdio_download_code_file(struct dhd_bus *bus, char *fw_path)
5749{
5750 int bcmerror = -1;
5751 int offset = 0;
5752 uint len;
5753 void *image = NULL;
3fd79f7c 5754 u8 *memblock = NULL, *memptr;
cf2b4488
HP		 5755
5756 DHD_INFO(("%s: download firmware %s\n", __func__, fw_path));
5757
5758 image = dhd_os_open_image(fw_path);
5759 if (image == NULL)
5760 goto err;
5761
5762 memptr = memblock = MALLOC(bus->dhd->osh, MEMBLOCK + DHD_SDALIGN);
5763 if (memblock == NULL) {
5764 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5765 __func__, MEMBLOCK));
5766 goto err;
5767 }
66cbd3ab 5768 if ((u32) (uintptr) memblock % DHD_SDALIGN)
cf2b4488 5769 memptr +=
66cbd3ab 5770 (DHD_SDALIGN - ((u32) (uintptr) memblock % DHD_SDALIGN));
cf2b4488
HP		 5771
5772 /* Download image */
5773 while ((len =
5774 dhd_os_get_image_block((char *)memptr, MEMBLOCK, image))) {
5775 bcmerror = dhdsdio_membytes(bus, TRUE, offset, memptr, len);
5776 if (bcmerror) {
5777 DHD_ERROR(("%s: error %d on writing %d membytes at "
5778 "0x%08x\n", __func__, bcmerror, MEMBLOCK, offset));
5779 goto err;
5780 }
5781
5782 offset += MEMBLOCK;
5783 }
5784
5785err:
5786 if (memblock)
5787 MFREE(bus->dhd->osh, memblock, MEMBLOCK + DHD_SDALIGN);
5788
5789 if (image)
5790 dhd_os_close_image(image);
5791
5792 return bcmerror;
5793}
5794
5795/*
5796 * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
5797 * and ending in a NUL.
5798 * Removes carriage returns, empty lines, comment lines, and converts
5799 * newlines to NULs.
5800 * Shortens buffer as needed and pads with NULs. End of buffer is marked
5801 * by two NULs.
5802*/
5803
5804static uint process_nvram_vars(char *varbuf, uint len)
5805{
5806 char *dp;
5807 bool findNewline;
5808 int column;
5809 uint buf_len, n;
5810
5811 dp = varbuf;
5812
5813 findNewline = FALSE;
5814 column = 0;
5815
5816 for (n = 0; n < len; n++) {
5817 if (varbuf[n] == 0)
5818 break;
5819 if (varbuf[n] == '\r')
5820 continue;
5821 if (findNewline && varbuf[n] != '\n')
5822 continue;
5823 findNewline = FALSE;
5824 if (varbuf[n] == '#') {
5825 findNewline = TRUE;
5826 continue;
5827 }
5828 if (varbuf[n] == '\n') {
5829 if (column == 0)
5830 continue;
5831 *dp++ = 0;
5832 column = 0;
5833 continue;
5834 }
5835 *dp++ = varbuf[n];
5836 column++;
5837 }
5838 buf_len = dp - varbuf;
5839
5840 while (dp < varbuf + n)
5841 *dp++ = 0;
5842
5843 return buf_len;
5844}
5845
5846/*
5847 EXAMPLE: nvram_array
5848 nvram_arry format:
5849 name=value
5850 Use carriage return at the end of each assignment,
5851 and an empty string with
5852 carriage return at the end of array.
5853
5854 For example:
5855 unsigned char nvram_array[] = {"name1=value1\n",
5856 "name2=value2\n", "\n"};
5857 Hex values start with 0x, and mac addr format: xx:xx:xx:xx:xx:xx.
5858
5859 Search "EXAMPLE: nvram_array" to see how the array is activated.
5860*/
5861
5862void dhd_bus_set_nvram_params(struct dhd_bus *bus, const char *nvram_params)
5863{
5864 bus->nvram_params = nvram_params;
5865}
5866
5867static int dhdsdio_download_nvram(struct dhd_bus *bus)
5868{
5869 int bcmerror = -1;
5870 uint len;
5871 void *image = NULL;
5872 char *memblock = NULL;
5873 char *bufp;
5874 char *nv_path;
5875 bool nvram_file_exists;
5876
5877 nv_path = bus->nv_path;
5878
5879 nvram_file_exists = ((nv_path != NULL) && (nv_path[0] != '\0'));
5880 if (!nvram_file_exists && (bus->nvram_params == NULL))
5881 return 0;
5882
5883 if (nvram_file_exists) {
5884 image = dhd_os_open_image(nv_path);
5885 if (image == NULL)
5886 goto err;
5887 }
5888
5889 memblock = MALLOC(bus->dhd->osh, MEMBLOCK);
5890 if (memblock == NULL) {
5891 DHD_ERROR(("%s: Failed to allocate memory %d bytes\n",
5892 __func__, MEMBLOCK));
5893 goto err;
5894 }
5895
5896 /* Download variables */
5897 if (nvram_file_exists) {
5898 len = dhd_os_get_image_block(memblock, MEMBLOCK, image);
5899 } else {
5900 len = strlen(bus->nvram_params);
5901 ASSERT(len <= MEMBLOCK);
5902 if (len > MEMBLOCK)
5903 len = MEMBLOCK;
5904 memcpy(memblock, bus->nvram_params, len);
5905 }
5906
5907 if (len > 0 && len < MEMBLOCK) {
5908 bufp = (char *)memblock;
5909 bufp[len] = 0;
5910 len = process_nvram_vars(bufp, len);
5911 bufp += len;
5912 *bufp++ = 0;
5913 if (len)
5914 bcmerror = dhdsdio_downloadvars(bus, memblock, len + 1);
5915 if (bcmerror) {
5916 DHD_ERROR(("%s: error downloading vars: %d\n",
5917 __func__, bcmerror));
5918 }
5919 } else {
5920 DHD_ERROR(("%s: error reading nvram file: %d\n",
5921 __func__, len));
5922 bcmerror = BCME_SDIO_ERROR;
5923 }
5924
5925err:
5926 if (memblock)
5927 MFREE(bus->dhd->osh, memblock, MEMBLOCK);
5928
5929 if (image)
5930 dhd_os_close_image(image);
5931
5932 return bcmerror;
5933}
5934
5935static int _dhdsdio_download_firmware(struct dhd_bus *bus)
5936{
5937 int bcmerror = -1;
5938
5939 bool embed = FALSE; /* download embedded firmware */
5940 bool dlok = FALSE; /* download firmware succeeded */
5941
5942 /* Out immediately if no image to download */
5943 if ((bus->fw_path == NULL) || (bus->fw_path[0] == '\0')) {
5944#ifdef BCMEMBEDIMAGE
5945 embed = TRUE;
5946#else
5947 return bcmerror;
5948#endif
5949 }
5950
5951 /* Keep arm in reset */
5952 if (dhdsdio_download_state(bus, TRUE)) {
5953 DHD_ERROR(("%s: error placing ARM core in reset\n", __func__));
5954 goto err;
5955 }
5956
5957 /* External image takes precedence if specified */
5958 if ((bus->fw_path != NULL) && (bus->fw_path[0] != '\0')) {
5959 if (dhdsdio_download_code_file(bus, bus->fw_path)) {
5960 DHD_ERROR(("%s: dongle image file download failed\n",
5961 __func__));
5962#ifdef BCMEMBEDIMAGE
5963 embed = TRUE;
5964#else
5965 goto err;
5966#endif
5967 } else {
5968 embed = FALSE;
5969 dlok = TRUE;
5970 }
5971 }
5972#ifdef BCMEMBEDIMAGE
5973 if (embed) {
5974 if (dhdsdio_download_code_array(bus)) {
5975 DHD_ERROR(("%s: dongle image array download failed\n",
5976 __func__));
5977 goto err;
5978 } else {
5979 dlok = TRUE;
5980 }
5981 }
5982#endif
5983 if (!dlok) {
5984 DHD_ERROR(("%s: dongle image download failed\n", __func__));
5985 goto err;
5986 }
5987
5988 /* EXAMPLE: nvram_array */
5989 /* If a valid nvram_arry is specified as above, it can be passed
5990 down to dongle */
5991 /* dhd_bus_set_nvram_params(bus, (char *)&nvram_array); */
5992
5993 /* External nvram takes precedence if specified */
5994 if (dhdsdio_download_nvram(bus)) {
5995 DHD_ERROR(("%s: dongle nvram file download failed\n",
5996 __func__));
5997 }
5998
5999 /* Take arm out of reset */
6000 if (dhdsdio_download_state(bus, FALSE)) {
6001 DHD_ERROR(("%s: error getting out of ARM core reset\n",
6002 __func__));
6003 goto err;
6004 }
6005
6006 bcmerror = 0;
6007
6008err:
6009 return bcmerror;
6010}
6011
6012static int
66cbd3ab 6013dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
3fd79f7c 6014 u8 *buf, uint nbytes, void *pkt,
cf2b4488
HP		 6015 bcmsdh_cmplt_fn_t complete, void *handle)
6016{
6017 int status;
6018
6019 /* 4329: GSPI check */
6020 status =
6021 bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
6022 complete, handle);
6023 return status;
6024}
6025
6026static int
66cbd3ab 6027dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
3fd79f7c 6028 u8 *buf, uint nbytes, void *pkt,
cf2b4488
HP		 6029 bcmsdh_cmplt_fn_t complete, void *handle)
6030{
6031 return bcmsdh_send_buf
6032 (bus->sdh, addr, fn, flags, buf, nbytes, pkt, complete,
6033 handle);
6034}
6035
6036uint dhd_bus_chip(struct dhd_bus *bus)
6037{
6038 ASSERT(bus->sih != NULL);
6039 return bus->sih->chip;
6040}
6041
6042void *dhd_bus_pub(struct dhd_bus *bus)
6043{
6044 return bus->dhd;
6045}
6046
6047void *dhd_bus_txq(struct dhd_bus *bus)
6048{
6049 return &bus->txq;
6050}
6051
6052uint dhd_bus_hdrlen(struct dhd_bus *bus)
6053{
6054 return SDPCM_HDRLEN;
6055}
6056
3fd79f7c 6057int dhd_bus_devreset(dhd_pub_t *dhdp, u8 flag)
cf2b4488
HP		 6058{
6059 int bcmerror = 0;
6060 dhd_bus_t *bus;
6061
6062 bus = dhdp->bus;
6063
6064 if (flag == TRUE) {
6065 if (!bus->dhd->dongle_reset) {
6066 /* Expect app to have torn down any
6067 connection before calling */
6068 /* Stop the bus, disable F2 */
6069 dhd_bus_stop(bus, FALSE);
6070
6071 /* Clean tx/rx buffer pointers,
6072 detach from the dongle */
6073 dhdsdio_release_dongle(bus, bus->dhd->osh);
6074
6075 bus->dhd->dongle_reset = TRUE;
6076 bus->dhd->up = FALSE;
6077
6078 DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
6079 /* App can now remove power from device */
6080 } else
6081 bcmerror = BCME_SDIO_ERROR;
6082 } else {
6083 /* App must have restored power to device before calling */
6084
6085 DHD_TRACE(("\n\n%s: == WLAN ON ==\n", __func__));
6086
6087 if (bus->dhd->dongle_reset) {
6088 /* Turn on WLAN */
6089 /* Reset SD client */
6090 bcmsdh_reset(bus->sdh);
6091
6092 /* Attempt to re-attach & download */
6093 if (dhdsdio_probe_attach(bus, bus->dhd->osh, bus->sdh,
66cbd3ab 6094 (u32 *) SI_ENUM_BASE,
cf2b4488
HP		 6095 bus->cl_devid)) {
6096 /* Attempt to download binary to the dongle */
6097 if (dhdsdio_probe_init
6098 (bus, bus->dhd->osh, bus->sdh)
6099 && dhdsdio_download_firmware(bus,
6100 bus->dhd->osh,
6101 bus->sdh)) {
6102
6103 /* Re-init bus, enable F2 transfer */
6104 dhd_bus_init((dhd_pub_t *) bus->dhd,
6105 FALSE);
6106
6107#if defined(OOB_INTR_ONLY)
6108 dhd_enable_oob_intr(bus, TRUE);
6109#endif /* defined(OOB_INTR_ONLY) */
6110
6111 bus->dhd->dongle_reset = FALSE;
6112 bus->dhd->up = TRUE;
6113
6114 DHD_TRACE(("%s: WLAN ON DONE\n",
6115 __func__));
6116 } else
6117 bcmerror = BCME_SDIO_ERROR;
6118 } else
6119 bcmerror = BCME_SDIO_ERROR;
6120 } else {
6121 bcmerror = BCME_NOTDOWN;
6122 DHD_ERROR(("%s: Set DEVRESET=FALSE invoked when device "
6123 "is on\n", __func__));
6124 bcmerror = BCME_SDIO_ERROR;
6125 }
6126 }
6127 return bcmerror;
6128}
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