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1/*
2 * Sonics Silicon Backplane
3 * Subsystem core
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include "ssb_private.h"
12
13#include <linux/delay.h>
6faf035c 14#include <linux/io.h>
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15#include <linux/ssb/ssb.h>
16#include <linux/ssb/ssb_regs.h>
aab547ce 17#include <linux/ssb/ssb_driver_gige.h>
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18#include <linux/dma-mapping.h>
19#include <linux/pci.h>
24ea602e 20#include <linux/mmc/sdio_func.h>
5a0e3ad6 21#include <linux/slab.h>
61e115a5 22
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23#include <pcmcia/cistpl.h>
24#include <pcmcia/ds.h>
25
26
27MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
28MODULE_LICENSE("GPL");
29
30
31/* Temporary list of yet-to-be-attached buses */
32static LIST_HEAD(attach_queue);
33/* List if running buses */
34static LIST_HEAD(buses);
35/* Software ID counter */
36static unsigned int next_busnumber;
37/* buses_mutes locks the two buslists and the next_busnumber.
38 * Don't lock this directly, but use ssb_buses_[un]lock() below. */
39static DEFINE_MUTEX(buses_mutex);
40
41/* There are differences in the codeflow, if the bus is
42 * initialized from early boot, as various needed services
43 * are not available early. This is a mechanism to delay
44 * these initializations to after early boot has finished.
45 * It's also used to avoid mutex locking, as that's not
46 * available and needed early. */
47static bool ssb_is_early_boot = 1;
48
49static void ssb_buses_lock(void);
50static void ssb_buses_unlock(void);
51
52
53#ifdef CONFIG_SSB_PCIHOST
54struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
55{
56 struct ssb_bus *bus;
57
58 ssb_buses_lock();
59 list_for_each_entry(bus, &buses, list) {
60 if (bus->bustype == SSB_BUSTYPE_PCI &&
61 bus->host_pci == pdev)
62 goto found;
63 }
64 bus = NULL;
65found:
66 ssb_buses_unlock();
67
68 return bus;
69}
70#endif /* CONFIG_SSB_PCIHOST */
71
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72#ifdef CONFIG_SSB_PCMCIAHOST
73struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
74{
75 struct ssb_bus *bus;
76
77 ssb_buses_lock();
78 list_for_each_entry(bus, &buses, list) {
79 if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
80 bus->host_pcmcia == pdev)
81 goto found;
82 }
83 bus = NULL;
84found:
85 ssb_buses_unlock();
86
87 return bus;
88}
89#endif /* CONFIG_SSB_PCMCIAHOST */
90
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91#ifdef CONFIG_SSB_SDIOHOST
92struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
93{
94 struct ssb_bus *bus;
95
96 ssb_buses_lock();
97 list_for_each_entry(bus, &buses, list) {
98 if (bus->bustype == SSB_BUSTYPE_SDIO &&
99 bus->host_sdio == func)
100 goto found;
101 }
102 bus = NULL;
103found:
104 ssb_buses_unlock();
105
106 return bus;
107}
108#endif /* CONFIG_SSB_SDIOHOST */
109
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110int ssb_for_each_bus_call(unsigned long data,
111 int (*func)(struct ssb_bus *bus, unsigned long data))
112{
113 struct ssb_bus *bus;
114 int res;
115
116 ssb_buses_lock();
117 list_for_each_entry(bus, &buses, list) {
118 res = func(bus, data);
119 if (res >= 0) {
120 ssb_buses_unlock();
121 return res;
122 }
123 }
124 ssb_buses_unlock();
125
126 return -ENODEV;
127}
128
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129static struct ssb_device *ssb_device_get(struct ssb_device *dev)
130{
131 if (dev)
132 get_device(dev->dev);
133 return dev;
134}
135
136static void ssb_device_put(struct ssb_device *dev)
137{
138 if (dev)
139 put_device(dev->dev);
140}
141
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142static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
143{
144 if (drv)
145 get_driver(&drv->drv);
146 return drv;
147}
148
149static inline void ssb_driver_put(struct ssb_driver *drv)
150{
151 if (drv)
152 put_driver(&drv->drv);
153}
154
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155static int ssb_device_resume(struct device *dev)
156{
157 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
158 struct ssb_driver *ssb_drv;
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159 int err = 0;
160
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161 if (dev->driver) {
162 ssb_drv = drv_to_ssb_drv(dev->driver);
163 if (ssb_drv && ssb_drv->resume)
164 err = ssb_drv->resume(ssb_dev);
165 if (err)
166 goto out;
167 }
168out:
169 return err;
170}
171
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172static int ssb_device_suspend(struct device *dev, pm_message_t state)
173{
174 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
175 struct ssb_driver *ssb_drv;
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176 int err = 0;
177
178 if (dev->driver) {
179 ssb_drv = drv_to_ssb_drv(dev->driver);
180 if (ssb_drv && ssb_drv->suspend)
181 err = ssb_drv->suspend(ssb_dev, state);
182 if (err)
183 goto out;
184 }
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185out:
186 return err;
187}
61e115a5 188
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189int ssb_bus_resume(struct ssb_bus *bus)
190{
191 int err;
192
193 /* Reset HW state information in memory, so that HW is
194 * completely reinitialized. */
195 bus->mapped_device = NULL;
196#ifdef CONFIG_SSB_DRIVER_PCICORE
197 bus->pcicore.setup_done = 0;
198#endif
199
200 err = ssb_bus_powerup(bus, 0);
201 if (err)
202 return err;
203 err = ssb_pcmcia_hardware_setup(bus);
204 if (err) {
205 ssb_bus_may_powerdown(bus);
206 return err;
61e115a5 207 }
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208 ssb_chipco_resume(&bus->chipco);
209 ssb_bus_may_powerdown(bus);
61e115a5 210
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211 return 0;
212}
213EXPORT_SYMBOL(ssb_bus_resume);
214
215int ssb_bus_suspend(struct ssb_bus *bus)
216{
217 ssb_chipco_suspend(&bus->chipco);
218 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
219
220 return 0;
61e115a5 221}
8fe2b65a 222EXPORT_SYMBOL(ssb_bus_suspend);
61e115a5 223
d72bb40f 224#ifdef CONFIG_SSB_SPROM
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225/** ssb_devices_freeze - Freeze all devices on the bus.
226 *
227 * After freezing no device driver will be handling a device
228 * on this bus anymore. ssb_devices_thaw() must be called after
229 * a successful freeze to reactivate the devices.
230 *
231 * @bus: The bus.
232 * @ctx: Context structure. Pass this to ssb_devices_thaw().
233 */
234int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
61e115a5 235{
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236 struct ssb_device *sdev;
237 struct ssb_driver *sdrv;
238 unsigned int i;
239
240 memset(ctx, 0, sizeof(*ctx));
241 ctx->bus = bus;
242 SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
61e115a5 243
61e115a5 244 for (i = 0; i < bus->nr_devices; i++) {
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245 sdev = ssb_device_get(&bus->devices[i]);
246
247 if (!sdev->dev || !sdev->dev->driver ||
248 !device_is_registered(sdev->dev)) {
249 ssb_device_put(sdev);
61e115a5 250 continue;
61e115a5 251 }
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252 sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
253 if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
254 ssb_device_put(sdev);
61e115a5 255 continue;
61e115a5 256 }
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257 sdrv->remove(sdev);
258 ctx->device_frozen[i] = 1;
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259 }
260
261 return 0;
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262}
263
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264/** ssb_devices_thaw - Unfreeze all devices on the bus.
265 *
266 * This will re-attach the device drivers and re-init the devices.
267 *
268 * @ctx: The context structure from ssb_devices_freeze()
269 */
270int ssb_devices_thaw(struct ssb_freeze_context *ctx)
61e115a5 271{
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272 struct ssb_bus *bus = ctx->bus;
273 struct ssb_device *sdev;
274 struct ssb_driver *sdrv;
275 unsigned int i;
276 int err, result = 0;
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277
278 for (i = 0; i < bus->nr_devices; i++) {
3ba6018a 279 if (!ctx->device_frozen[i])
61e115a5 280 continue;
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281 sdev = &bus->devices[i];
282
283 if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
61e115a5 284 continue;
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285 sdrv = drv_to_ssb_drv(sdev->dev->driver);
286 if (SSB_WARN_ON(!sdrv || !sdrv->probe))
61e115a5 287 continue;
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288
289 err = sdrv->probe(sdev, &sdev->id);
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290 if (err) {
291 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
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292 dev_name(sdev->dev));
293 result = err;
61e115a5 294 }
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295 ssb_driver_put(sdrv);
296 ssb_device_put(sdev);
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297 }
298
3ba6018a 299 return result;
61e115a5 300}
d72bb40f 301#endif /* CONFIG_SSB_SPROM */
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302
303static void ssb_device_shutdown(struct device *dev)
304{
305 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
306 struct ssb_driver *ssb_drv;
307
308 if (!dev->driver)
309 return;
310 ssb_drv = drv_to_ssb_drv(dev->driver);
311 if (ssb_drv && ssb_drv->shutdown)
312 ssb_drv->shutdown(ssb_dev);
313}
314
315static int ssb_device_remove(struct device *dev)
316{
317 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
318 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
319
320 if (ssb_drv && ssb_drv->remove)
321 ssb_drv->remove(ssb_dev);
322 ssb_device_put(ssb_dev);
323
324 return 0;
325}
326
327static int ssb_device_probe(struct device *dev)
328{
329 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
330 struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
331 int err = 0;
332
333 ssb_device_get(ssb_dev);
334 if (ssb_drv && ssb_drv->probe)
335 err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
336 if (err)
337 ssb_device_put(ssb_dev);
338
339 return err;
340}
341
342static int ssb_match_devid(const struct ssb_device_id *tabid,
343 const struct ssb_device_id *devid)
344{
345 if ((tabid->vendor != devid->vendor) &&
346 tabid->vendor != SSB_ANY_VENDOR)
347 return 0;
348 if ((tabid->coreid != devid->coreid) &&
349 tabid->coreid != SSB_ANY_ID)
350 return 0;
351 if ((tabid->revision != devid->revision) &&
352 tabid->revision != SSB_ANY_REV)
353 return 0;
354 return 1;
355}
356
357static int ssb_bus_match(struct device *dev, struct device_driver *drv)
358{
359 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
360 struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
361 const struct ssb_device_id *id;
362
363 for (id = ssb_drv->id_table;
364 id->vendor || id->coreid || id->revision;
365 id++) {
366 if (ssb_match_devid(id, &ssb_dev->id))
367 return 1; /* found */
368 }
369
370 return 0;
371}
372
7ac0326c 373static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
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374{
375 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
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376
377 if (!dev)
378 return -ENODEV;
379
7ac0326c 380 return add_uevent_var(env,
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381 "MODALIAS=ssb:v%04Xid%04Xrev%02X",
382 ssb_dev->id.vendor, ssb_dev->id.coreid,
383 ssb_dev->id.revision);
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384}
385
386static struct bus_type ssb_bustype = {
387 .name = "ssb",
388 .match = ssb_bus_match,
389 .probe = ssb_device_probe,
390 .remove = ssb_device_remove,
391 .shutdown = ssb_device_shutdown,
392 .suspend = ssb_device_suspend,
393 .resume = ssb_device_resume,
394 .uevent = ssb_device_uevent,
395};
396
397static void ssb_buses_lock(void)
398{
399 /* See the comment at the ssb_is_early_boot definition */
400 if (!ssb_is_early_boot)
401 mutex_lock(&buses_mutex);
402}
403
404static void ssb_buses_unlock(void)
405{
406 /* See the comment at the ssb_is_early_boot definition */
407 if (!ssb_is_early_boot)
408 mutex_unlock(&buses_mutex);
409}
410
411static void ssb_devices_unregister(struct ssb_bus *bus)
412{
413 struct ssb_device *sdev;
414 int i;
415
416 for (i = bus->nr_devices - 1; i >= 0; i--) {
417 sdev = &(bus->devices[i]);
418 if (sdev->dev)
419 device_unregister(sdev->dev);
420 }
421}
422
423void ssb_bus_unregister(struct ssb_bus *bus)
424{
425 ssb_buses_lock();
426 ssb_devices_unregister(bus);
427 list_del(&bus->list);
428 ssb_buses_unlock();
429
e7ec2e32 430 ssb_pcmcia_exit(bus);
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431 ssb_pci_exit(bus);
432 ssb_iounmap(bus);
433}
434EXPORT_SYMBOL(ssb_bus_unregister);
435
436static void ssb_release_dev(struct device *dev)
437{
438 struct __ssb_dev_wrapper *devwrap;
439
440 devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
441 kfree(devwrap);
442}
443
444static int ssb_devices_register(struct ssb_bus *bus)
445{
446 struct ssb_device *sdev;
447 struct device *dev;
448 struct __ssb_dev_wrapper *devwrap;
449 int i, err = 0;
450 int dev_idx = 0;
451
452 for (i = 0; i < bus->nr_devices; i++) {
453 sdev = &(bus->devices[i]);
454
455 /* We don't register SSB-system devices to the kernel,
456 * as the drivers for them are built into SSB. */
457 switch (sdev->id.coreid) {
458 case SSB_DEV_CHIPCOMMON:
459 case SSB_DEV_PCI:
460 case SSB_DEV_PCIE:
461 case SSB_DEV_PCMCIA:
462 case SSB_DEV_MIPS:
463 case SSB_DEV_MIPS_3302:
464 case SSB_DEV_EXTIF:
465 continue;
466 }
467
468 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
469 if (!devwrap) {
470 ssb_printk(KERN_ERR PFX
471 "Could not allocate device\n");
472 err = -ENOMEM;
473 goto error;
474 }
475 dev = &devwrap->dev;
476 devwrap->sdev = sdev;
477
478 dev->release = ssb_release_dev;
479 dev->bus = &ssb_bustype;
b7b05fe7 480 dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
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481
482 switch (bus->bustype) {
483 case SSB_BUSTYPE_PCI:
484#ifdef CONFIG_SSB_PCIHOST
485 sdev->irq = bus->host_pci->irq;
486 dev->parent = &bus->host_pci->dev;
14f92952 487 sdev->dma_dev = dev->parent;
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488#endif
489 break;
490 case SSB_BUSTYPE_PCMCIA:
491#ifdef CONFIG_SSB_PCMCIAHOST
eb14120f 492 sdev->irq = bus->host_pcmcia->irq;
61e115a5 493 dev->parent = &bus->host_pcmcia->dev;
24ea602e
AH
494#endif
495 break;
496 case SSB_BUSTYPE_SDIO:
391ae22a 497#ifdef CONFIG_SSB_SDIOHOST
24ea602e 498 dev->parent = &bus->host_sdio->dev;
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499#endif
500 break;
501 case SSB_BUSTYPE_SSB:
ac82da33 502 dev->dma_mask = &dev->coherent_dma_mask;
14f92952 503 sdev->dma_dev = dev;
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504 break;
505 }
506
507 sdev->dev = dev;
508 err = device_register(dev);
509 if (err) {
510 ssb_printk(KERN_ERR PFX
511 "Could not register %s\n",
b7b05fe7 512 dev_name(dev));
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513 /* Set dev to NULL to not unregister
514 * dev on error unwinding. */
515 sdev->dev = NULL;
516 kfree(devwrap);
517 goto error;
518 }
519 dev_idx++;
520 }
521
522 return 0;
523error:
524 /* Unwind the already registered devices. */
525 ssb_devices_unregister(bus);
526 return err;
527}
528
529/* Needs ssb_buses_lock() */
530static int ssb_attach_queued_buses(void)
531{
532 struct ssb_bus *bus, *n;
533 int err = 0;
534 int drop_them_all = 0;
535
536 list_for_each_entry_safe(bus, n, &attach_queue, list) {
537 if (drop_them_all) {
538 list_del(&bus->list);
539 continue;
540 }
541 /* Can't init the PCIcore in ssb_bus_register(), as that
542 * is too early in boot for embedded systems
543 * (no udelay() available). So do it here in attach stage.
544 */
545 err = ssb_bus_powerup(bus, 0);
546 if (err)
547 goto error;
548 ssb_pcicore_init(&bus->pcicore);
549 ssb_bus_may_powerdown(bus);
550
551 err = ssb_devices_register(bus);
552error:
553 if (err) {
554 drop_them_all = 1;
555 list_del(&bus->list);
556 continue;
557 }
558 list_move_tail(&bus->list, &buses);
559 }
560
561 return err;
562}
563
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564static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
565{
566 struct ssb_bus *bus = dev->bus;
567
568 offset += dev->core_index * SSB_CORE_SIZE;
569 return readb(bus->mmio + offset);
570}
571
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572static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
573{
574 struct ssb_bus *bus = dev->bus;
575
576 offset += dev->core_index * SSB_CORE_SIZE;
577 return readw(bus->mmio + offset);
578}
579
580static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
581{
582 struct ssb_bus *bus = dev->bus;
583
584 offset += dev->core_index * SSB_CORE_SIZE;
585 return readl(bus->mmio + offset);
586}
587
d625a29b
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588#ifdef CONFIG_SSB_BLOCKIO
589static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
590 size_t count, u16 offset, u8 reg_width)
591{
592 struct ssb_bus *bus = dev->bus;
593 void __iomem *addr;
594
595 offset += dev->core_index * SSB_CORE_SIZE;
596 addr = bus->mmio + offset;
597
598 switch (reg_width) {
599 case sizeof(u8): {
600 u8 *buf = buffer;
601
602 while (count) {
603 *buf = __raw_readb(addr);
604 buf++;
605 count--;
606 }
607 break;
608 }
609 case sizeof(u16): {
610 __le16 *buf = buffer;
611
612 SSB_WARN_ON(count & 1);
613 while (count) {
614 *buf = (__force __le16)__raw_readw(addr);
615 buf++;
616 count -= 2;
617 }
618 break;
619 }
620 case sizeof(u32): {
621 __le32 *buf = buffer;
622
623 SSB_WARN_ON(count & 3);
624 while (count) {
625 *buf = (__force __le32)__raw_readl(addr);
626 buf++;
627 count -= 4;
628 }
629 break;
630 }
631 default:
632 SSB_WARN_ON(1);
633 }
634}
635#endif /* CONFIG_SSB_BLOCKIO */
636
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637static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
638{
639 struct ssb_bus *bus = dev->bus;
640
641 offset += dev->core_index * SSB_CORE_SIZE;
642 writeb(value, bus->mmio + offset);
643}
644
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645static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
646{
647 struct ssb_bus *bus = dev->bus;
648
649 offset += dev->core_index * SSB_CORE_SIZE;
650 writew(value, bus->mmio + offset);
651}
652
653static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
654{
655 struct ssb_bus *bus = dev->bus;
656
657 offset += dev->core_index * SSB_CORE_SIZE;
658 writel(value, bus->mmio + offset);
659}
660
d625a29b
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661#ifdef CONFIG_SSB_BLOCKIO
662static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
663 size_t count, u16 offset, u8 reg_width)
664{
665 struct ssb_bus *bus = dev->bus;
666 void __iomem *addr;
667
668 offset += dev->core_index * SSB_CORE_SIZE;
669 addr = bus->mmio + offset;
670
671 switch (reg_width) {
672 case sizeof(u8): {
673 const u8 *buf = buffer;
674
675 while (count) {
676 __raw_writeb(*buf, addr);
677 buf++;
678 count--;
679 }
680 break;
681 }
682 case sizeof(u16): {
683 const __le16 *buf = buffer;
684
685 SSB_WARN_ON(count & 1);
686 while (count) {
687 __raw_writew((__force u16)(*buf), addr);
688 buf++;
689 count -= 2;
690 }
691 break;
692 }
693 case sizeof(u32): {
694 const __le32 *buf = buffer;
695
696 SSB_WARN_ON(count & 3);
697 while (count) {
698 __raw_writel((__force u32)(*buf), addr);
699 buf++;
700 count -= 4;
701 }
702 break;
703 }
704 default:
705 SSB_WARN_ON(1);
706 }
707}
708#endif /* CONFIG_SSB_BLOCKIO */
709
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710/* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
711static const struct ssb_bus_ops ssb_ssb_ops = {
ffc7689d 712 .read8 = ssb_ssb_read8,
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MB
713 .read16 = ssb_ssb_read16,
714 .read32 = ssb_ssb_read32,
ffc7689d 715 .write8 = ssb_ssb_write8,
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MB
716 .write16 = ssb_ssb_write16,
717 .write32 = ssb_ssb_write32,
d625a29b
MB
718#ifdef CONFIG_SSB_BLOCKIO
719 .block_read = ssb_ssb_block_read,
720 .block_write = ssb_ssb_block_write,
721#endif
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MB
722};
723
724static int ssb_fetch_invariants(struct ssb_bus *bus,
725 ssb_invariants_func_t get_invariants)
726{
727 struct ssb_init_invariants iv;
728 int err;
729
730 memset(&iv, 0, sizeof(iv));
731 err = get_invariants(bus, &iv);
732 if (err)
733 goto out;
734 memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
735 memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
7cb44615 736 bus->has_cardbus_slot = iv.has_cardbus_slot;
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MB
737out:
738 return err;
739}
740
741static int ssb_bus_register(struct ssb_bus *bus,
742 ssb_invariants_func_t get_invariants,
743 unsigned long baseaddr)
744{
745 int err;
746
747 spin_lock_init(&bus->bar_lock);
748 INIT_LIST_HEAD(&bus->list);
53521d8c
MB
749#ifdef CONFIG_SSB_EMBEDDED
750 spin_lock_init(&bus->gpio_lock);
751#endif
61e115a5
MB
752
753 /* Powerup the bus */
754 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
755 if (err)
756 goto out;
24ea602e
AH
757
758 /* Init SDIO-host device (if any), before the scan */
759 err = ssb_sdio_init(bus);
760 if (err)
761 goto err_disable_xtal;
762
61e115a5
MB
763 ssb_buses_lock();
764 bus->busnumber = next_busnumber;
765 /* Scan for devices (cores) */
766 err = ssb_bus_scan(bus, baseaddr);
767 if (err)
24ea602e 768 goto err_sdio_exit;
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MB
769
770 /* Init PCI-host device (if any) */
771 err = ssb_pci_init(bus);
772 if (err)
773 goto err_unmap;
774 /* Init PCMCIA-host device (if any) */
775 err = ssb_pcmcia_init(bus);
776 if (err)
777 goto err_pci_exit;
778
779 /* Initialize basic system devices (if available) */
780 err = ssb_bus_powerup(bus, 0);
781 if (err)
782 goto err_pcmcia_exit;
783 ssb_chipcommon_init(&bus->chipco);
784 ssb_mipscore_init(&bus->mipscore);
785 err = ssb_fetch_invariants(bus, get_invariants);
786 if (err) {
787 ssb_bus_may_powerdown(bus);
788 goto err_pcmcia_exit;
789 }
790 ssb_bus_may_powerdown(bus);
791
792 /* Queue it for attach.
793 * See the comment at the ssb_is_early_boot definition. */
794 list_add_tail(&bus->list, &attach_queue);
795 if (!ssb_is_early_boot) {
796 /* This is not early boot, so we must attach the bus now */
797 err = ssb_attach_queued_buses();
798 if (err)
799 goto err_dequeue;
800 }
801 next_busnumber++;
802 ssb_buses_unlock();
803
804out:
805 return err;
806
807err_dequeue:
808 list_del(&bus->list);
809err_pcmcia_exit:
e7ec2e32 810 ssb_pcmcia_exit(bus);
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MB
811err_pci_exit:
812 ssb_pci_exit(bus);
813err_unmap:
814 ssb_iounmap(bus);
24ea602e
AH
815err_sdio_exit:
816 ssb_sdio_exit(bus);
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MB
817err_disable_xtal:
818 ssb_buses_unlock();
819 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
820 return err;
821}
822
823#ifdef CONFIG_SSB_PCIHOST
824int ssb_bus_pcibus_register(struct ssb_bus *bus,
825 struct pci_dev *host_pci)
826{
827 int err;
828
829 bus->bustype = SSB_BUSTYPE_PCI;
830 bus->host_pci = host_pci;
831 bus->ops = &ssb_pci_ops;
832
833 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
834 if (!err) {
835 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
b7b05fe7 836 "PCI device %s\n", dev_name(&host_pci->dev));
ce9626ea
LF
837 } else {
838 ssb_printk(KERN_ERR PFX "Failed to register PCI version"
839 " of SSB with error %d\n", err);
61e115a5
MB
840 }
841
842 return err;
843}
844EXPORT_SYMBOL(ssb_bus_pcibus_register);
845#endif /* CONFIG_SSB_PCIHOST */
846
847#ifdef CONFIG_SSB_PCMCIAHOST
848int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
849 struct pcmcia_device *pcmcia_dev,
850 unsigned long baseaddr)
851{
852 int err;
853
854 bus->bustype = SSB_BUSTYPE_PCMCIA;
855 bus->host_pcmcia = pcmcia_dev;
856 bus->ops = &ssb_pcmcia_ops;
857
858 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
859 if (!err) {
860 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
861 "PCMCIA device %s\n", pcmcia_dev->devname);
862 }
863
864 return err;
865}
866EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
867#endif /* CONFIG_SSB_PCMCIAHOST */
868
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AH
869#ifdef CONFIG_SSB_SDIOHOST
870int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
871 unsigned int quirks)
872{
873 int err;
874
875 bus->bustype = SSB_BUSTYPE_SDIO;
876 bus->host_sdio = func;
877 bus->ops = &ssb_sdio_ops;
878 bus->quirks = quirks;
879
880 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
881 if (!err) {
882 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
883 "SDIO device %s\n", sdio_func_id(func));
884 }
885
886 return err;
887}
888EXPORT_SYMBOL(ssb_bus_sdiobus_register);
889#endif /* CONFIG_SSB_PCMCIAHOST */
890
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891int ssb_bus_ssbbus_register(struct ssb_bus *bus,
892 unsigned long baseaddr,
893 ssb_invariants_func_t get_invariants)
894{
895 int err;
896
897 bus->bustype = SSB_BUSTYPE_SSB;
898 bus->ops = &ssb_ssb_ops;
899
900 err = ssb_bus_register(bus, get_invariants, baseaddr);
901 if (!err) {
902 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
903 "address 0x%08lX\n", baseaddr);
904 }
905
906 return err;
907}
908
909int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
910{
911 drv->drv.name = drv->name;
912 drv->drv.bus = &ssb_bustype;
913 drv->drv.owner = owner;
914
915 return driver_register(&drv->drv);
916}
917EXPORT_SYMBOL(__ssb_driver_register);
918
919void ssb_driver_unregister(struct ssb_driver *drv)
920{
921 driver_unregister(&drv->drv);
922}
923EXPORT_SYMBOL(ssb_driver_unregister);
924
925void ssb_set_devtypedata(struct ssb_device *dev, void *data)
926{
927 struct ssb_bus *bus = dev->bus;
928 struct ssb_device *ent;
929 int i;
930
931 for (i = 0; i < bus->nr_devices; i++) {
932 ent = &(bus->devices[i]);
933 if (ent->id.vendor != dev->id.vendor)
934 continue;
935 if (ent->id.coreid != dev->id.coreid)
936 continue;
937
938 ent->devtypedata = data;
939 }
940}
941EXPORT_SYMBOL(ssb_set_devtypedata);
942
943static u32 clkfactor_f6_resolve(u32 v)
944{
945 /* map the magic values */
946 switch (v) {
947 case SSB_CHIPCO_CLK_F6_2:
948 return 2;
949 case SSB_CHIPCO_CLK_F6_3:
950 return 3;
951 case SSB_CHIPCO_CLK_F6_4:
952 return 4;
953 case SSB_CHIPCO_CLK_F6_5:
954 return 5;
955 case SSB_CHIPCO_CLK_F6_6:
956 return 6;
957 case SSB_CHIPCO_CLK_F6_7:
958 return 7;
959 }
960 return 0;
961}
962
963/* Calculate the speed the backplane would run at a given set of clockcontrol values */
964u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
965{
966 u32 n1, n2, clock, m1, m2, m3, mc;
967
968 n1 = (n & SSB_CHIPCO_CLK_N1);
969 n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
970
971 switch (plltype) {
972 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
973 if (m & SSB_CHIPCO_CLK_T6_MMASK)
974 return SSB_CHIPCO_CLK_T6_M0;
975 return SSB_CHIPCO_CLK_T6_M1;
976 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
977 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
978 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
979 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
980 n1 = clkfactor_f6_resolve(n1);
981 n2 += SSB_CHIPCO_CLK_F5_BIAS;
982 break;
983 case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
984 n1 += SSB_CHIPCO_CLK_T2_BIAS;
985 n2 += SSB_CHIPCO_CLK_T2_BIAS;
986 SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
987 SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
988 break;
989 case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
990 return 100000000;
991 default:
992 SSB_WARN_ON(1);
993 }
994
995 switch (plltype) {
996 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
997 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
998 clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
999 break;
1000 default:
1001 clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1002 }
1003 if (!clock)
1004 return 0;
1005
1006 m1 = (m & SSB_CHIPCO_CLK_M1);
1007 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1008 m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1009 mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1010
1011 switch (plltype) {
1012 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1013 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1014 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1015 case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1016 m1 = clkfactor_f6_resolve(m1);
1017 if ((plltype == SSB_PLLTYPE_1) ||
1018 (plltype == SSB_PLLTYPE_3))
1019 m2 += SSB_CHIPCO_CLK_F5_BIAS;
1020 else
1021 m2 = clkfactor_f6_resolve(m2);
1022 m3 = clkfactor_f6_resolve(m3);
1023
1024 switch (mc) {
1025 case SSB_CHIPCO_CLK_MC_BYPASS:
1026 return clock;
1027 case SSB_CHIPCO_CLK_MC_M1:
1028 return (clock / m1);
1029 case SSB_CHIPCO_CLK_MC_M1M2:
1030 return (clock / (m1 * m2));
1031 case SSB_CHIPCO_CLK_MC_M1M2M3:
1032 return (clock / (m1 * m2 * m3));
1033 case SSB_CHIPCO_CLK_MC_M1M3:
1034 return (clock / (m1 * m3));
1035 }
1036 return 0;
1037 case SSB_PLLTYPE_2:
1038 m1 += SSB_CHIPCO_CLK_T2_BIAS;
1039 m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1040 m3 += SSB_CHIPCO_CLK_T2_BIAS;
1041 SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1042 SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1043 SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1044
1045 if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1046 clock /= m1;
1047 if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1048 clock /= m2;
1049 if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1050 clock /= m3;
1051 return clock;
1052 default:
1053 SSB_WARN_ON(1);
1054 }
1055 return 0;
1056}
1057
1058/* Get the current speed the backplane is running at */
1059u32 ssb_clockspeed(struct ssb_bus *bus)
1060{
1061 u32 rate;
1062 u32 plltype;
1063 u32 clkctl_n, clkctl_m;
1064
1065 if (ssb_extif_available(&bus->extif))
1066 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1067 &clkctl_n, &clkctl_m);
1068 else if (bus->chipco.dev)
1069 ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1070 &clkctl_n, &clkctl_m);
1071 else
1072 return 0;
1073
1074 if (bus->chip_id == 0x5365) {
1075 rate = 100000000;
1076 } else {
1077 rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1078 if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1079 rate /= 2;
1080 }
1081
1082 return rate;
1083}
1084EXPORT_SYMBOL(ssb_clockspeed);
1085
1086static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1087{
c272ef44
LF
1088 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1089
61e115a5
MB
1090 /* The REJECT bit changed position in TMSLOW between
1091 * Backplane revisions. */
c272ef44 1092 switch (rev) {
61e115a5
MB
1093 case SSB_IDLOW_SSBREV_22:
1094 return SSB_TMSLOW_REJECT_22;
1095 case SSB_IDLOW_SSBREV_23:
1096 return SSB_TMSLOW_REJECT_23;
c272ef44
LF
1097 case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1098 case SSB_IDLOW_SSBREV_25: /* same here */
1099 case SSB_IDLOW_SSBREV_26: /* same here */
1100 case SSB_IDLOW_SSBREV_27: /* same here */
1101 return SSB_TMSLOW_REJECT_23; /* this is a guess */
61e115a5 1102 default:
c272ef44 1103 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
61e115a5
MB
1104 WARN_ON(1);
1105 }
1106 return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1107}
1108
1109int ssb_device_is_enabled(struct ssb_device *dev)
1110{
1111 u32 val;
1112 u32 reject;
1113
1114 reject = ssb_tmslow_reject_bitmask(dev);
1115 val = ssb_read32(dev, SSB_TMSLOW);
1116 val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1117
1118 return (val == SSB_TMSLOW_CLOCK);
1119}
1120EXPORT_SYMBOL(ssb_device_is_enabled);
1121
1122static void ssb_flush_tmslow(struct ssb_device *dev)
1123{
1124 /* Make _really_ sure the device has finished the TMSLOW
1125 * register write transaction, as we risk running into
1126 * a machine check exception otherwise.
1127 * Do this by reading the register back to commit the
1128 * PCI write and delay an additional usec for the device
1129 * to react to the change. */
1130 ssb_read32(dev, SSB_TMSLOW);
1131 udelay(1);
1132}
1133
1134void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1135{
1136 u32 val;
1137
1138 ssb_device_disable(dev, core_specific_flags);
1139 ssb_write32(dev, SSB_TMSLOW,
1140 SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1141 SSB_TMSLOW_FGC | core_specific_flags);
1142 ssb_flush_tmslow(dev);
1143
1144 /* Clear SERR if set. This is a hw bug workaround. */
1145 if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1146 ssb_write32(dev, SSB_TMSHIGH, 0);
1147
1148 val = ssb_read32(dev, SSB_IMSTATE);
1149 if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1150 val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1151 ssb_write32(dev, SSB_IMSTATE, val);
1152 }
1153
1154 ssb_write32(dev, SSB_TMSLOW,
1155 SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1156 core_specific_flags);
1157 ssb_flush_tmslow(dev);
1158
1159 ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1160 core_specific_flags);
1161 ssb_flush_tmslow(dev);
1162}
1163EXPORT_SYMBOL(ssb_device_enable);
1164
1165/* Wait for a bit in a register to get set or unset.
1166 * timeout is in units of ten-microseconds */
1167static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1168 int timeout, int set)
1169{
1170 int i;
1171 u32 val;
1172
1173 for (i = 0; i < timeout; i++) {
1174 val = ssb_read32(dev, reg);
1175 if (set) {
1176 if (val & bitmask)
1177 return 0;
1178 } else {
1179 if (!(val & bitmask))
1180 return 0;
1181 }
1182 udelay(10);
1183 }
1184 printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1185 "register %04X to %s.\n",
1186 bitmask, reg, (set ? "set" : "clear"));
1187
1188 return -ETIMEDOUT;
1189}
1190
1191void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1192{
1193 u32 reject;
1194
1195 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1196 return;
1197
1198 reject = ssb_tmslow_reject_bitmask(dev);
1199 ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1200 ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1201 ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1202 ssb_write32(dev, SSB_TMSLOW,
1203 SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1204 reject | SSB_TMSLOW_RESET |
1205 core_specific_flags);
1206 ssb_flush_tmslow(dev);
1207
1208 ssb_write32(dev, SSB_TMSLOW,
1209 reject | SSB_TMSLOW_RESET |
1210 core_specific_flags);
1211 ssb_flush_tmslow(dev);
1212}
1213EXPORT_SYMBOL(ssb_device_disable);
1214
1215u32 ssb_dma_translation(struct ssb_device *dev)
1216{
1217 switch (dev->bus->bustype) {
1218 case SSB_BUSTYPE_SSB:
1219 return 0;
1220 case SSB_BUSTYPE_PCI:
61e115a5 1221 return SSB_PCI_DMA;
f225763a
MB
1222 default:
1223 __ssb_dma_not_implemented(dev);
61e115a5
MB
1224 }
1225 return 0;
1226}
1227EXPORT_SYMBOL(ssb_dma_translation);
1228
61e115a5
MB
1229int ssb_bus_may_powerdown(struct ssb_bus *bus)
1230{
1231 struct ssb_chipcommon *cc;
1232 int err = 0;
1233
1234 /* On buses where more than one core may be working
1235 * at a time, we must not powerdown stuff if there are
1236 * still cores that may want to run. */
1237 if (bus->bustype == SSB_BUSTYPE_SSB)
1238 goto out;
1239
1240 cc = &bus->chipco;
881400a2
SB
1241
1242 if (!cc->dev)
1243 goto out;
1244 if (cc->dev->id.revision < 5)
1245 goto out;
1246
61e115a5
MB
1247 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1248 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1249 if (err)
1250 goto error;
1251out:
1252#ifdef CONFIG_SSB_DEBUG
1253 bus->powered_up = 0;
1254#endif
1255 return err;
1256error:
1257 ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1258 goto out;
1259}
1260EXPORT_SYMBOL(ssb_bus_may_powerdown);
1261
1262int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1263{
1264 struct ssb_chipcommon *cc;
1265 int err;
1266 enum ssb_clkmode mode;
1267
1268 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1269 if (err)
1270 goto error;
1271 cc = &bus->chipco;
1272 mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1273 ssb_chipco_set_clockmode(cc, mode);
1274
1275#ifdef CONFIG_SSB_DEBUG
1276 bus->powered_up = 1;
1277#endif
1278 return 0;
1279error:
1280 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1281 return err;
1282}
1283EXPORT_SYMBOL(ssb_bus_powerup);
1284
1285u32 ssb_admatch_base(u32 adm)
1286{
1287 u32 base = 0;
1288
1289 switch (adm & SSB_ADM_TYPE) {
1290 case SSB_ADM_TYPE0:
1291 base = (adm & SSB_ADM_BASE0);
1292 break;
1293 case SSB_ADM_TYPE1:
1294 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1295 base = (adm & SSB_ADM_BASE1);
1296 break;
1297 case SSB_ADM_TYPE2:
1298 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1299 base = (adm & SSB_ADM_BASE2);
1300 break;
1301 default:
1302 SSB_WARN_ON(1);
1303 }
1304
1305 return base;
1306}
1307EXPORT_SYMBOL(ssb_admatch_base);
1308
1309u32 ssb_admatch_size(u32 adm)
1310{
1311 u32 size = 0;
1312
1313 switch (adm & SSB_ADM_TYPE) {
1314 case SSB_ADM_TYPE0:
1315 size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1316 break;
1317 case SSB_ADM_TYPE1:
1318 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1319 size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1320 break;
1321 case SSB_ADM_TYPE2:
1322 SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1323 size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1324 break;
1325 default:
1326 SSB_WARN_ON(1);
1327 }
1328 size = (1 << (size + 1));
1329
1330 return size;
1331}
1332EXPORT_SYMBOL(ssb_admatch_size);
1333
1334static int __init ssb_modinit(void)
1335{
1336 int err;
1337
1338 /* See the comment at the ssb_is_early_boot definition */
1339 ssb_is_early_boot = 0;
1340 err = bus_register(&ssb_bustype);
1341 if (err)
1342 return err;
1343
1344 /* Maybe we already registered some buses at early boot.
1345 * Check for this and attach them
1346 */
1347 ssb_buses_lock();
1348 err = ssb_attach_queued_buses();
1349 ssb_buses_unlock();
e6c463e3 1350 if (err) {
61e115a5 1351 bus_unregister(&ssb_bustype);
e6c463e3
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1352 goto out;
1353 }
61e115a5
MB
1354
1355 err = b43_pci_ssb_bridge_init();
1356 if (err) {
1357 ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
aab547ce
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1358 "initialization failed\n");
1359 /* don't fail SSB init because of this */
1360 err = 0;
1361 }
1362 err = ssb_gige_init();
1363 if (err) {
1364 ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1365 "driver initialization failed\n");
61e115a5
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1366 /* don't fail SSB init because of this */
1367 err = 0;
1368 }
e6c463e3 1369out:
61e115a5
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1370 return err;
1371}
8d8c90e3
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1372/* ssb must be initialized after PCI but before the ssb drivers.
1373 * That means we must use some initcall between subsys_initcall
1374 * and device_initcall. */
1375fs_initcall(ssb_modinit);
61e115a5
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1376
1377static void __exit ssb_modexit(void)
1378{
aab547ce 1379 ssb_gige_exit();
61e115a5
MB
1380 b43_pci_ssb_bridge_exit();
1381 bus_unregister(&ssb_bustype);
1382}
1383module_exit(ssb_modexit)