[net-next-2.6.git] / drivers / spi / spi_mpc83xx.c

/*
 * MPC83xx SPI controller driver.
 *
 * Maintainer: Kumar Gala
 *
 * Copyright (C) 2006 Polycom, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/irq.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/platform_device.h>
#include <linux/fsl_devices.h>

#include <asm/irq.h>
#include <asm/io.h>

/* SPI Controller registers */
struct mpc83xx_spi_reg {
	u8 res1[0x20];
	__be32 mode;
	__be32 event;
	__be32 mask;
	__be32 command;
	__be32 transmit;
	__be32 receive;
};

/* SPI Controller mode register definitions */
#define	SPMODE_LOOP		(1 << 30)
#define	SPMODE_CI_INACTIVEHIGH	(1 << 29)
#define	SPMODE_CP_BEGIN_EDGECLK	(1 << 28)
#define	SPMODE_DIV16		(1 << 27)
#define	SPMODE_REV		(1 << 26)
#define	SPMODE_MS		(1 << 25)
#define	SPMODE_ENABLE		(1 << 24)
#define	SPMODE_LEN(x)		((x) << 20)
#define	SPMODE_PM(x)		((x) << 16)
#define	SPMODE_OP		(1 << 14)
#define	SPMODE_CG(x)		((x) << 7)

/*
 * Default for SPI Mode:
 * 	SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
 */
#define	SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
			 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))

/* SPIE register values */
#define	SPIE_NE		0x00000200	/* Not empty */
#define	SPIE_NF		0x00000100	/* Not full */

/* SPIM register values */
#define	SPIM_NE		0x00000200	/* Not empty */
#define	SPIM_NF		0x00000100	/* Not full */

/* SPI Controller driver's private data. */
struct mpc83xx_spi {
	struct mpc83xx_spi_reg __iomem *base;

	/* rx & tx bufs from the spi_transfer */
	const void *tx;
	void *rx;

	/* functions to deal with different sized buffers */
	void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
	u32(*get_tx) (struct mpc83xx_spi *);

	unsigned int count;
	int irq;

	unsigned nsecs;		/* (clock cycle time)/2 */

	u32 spibrg;		/* SPIBRG input clock */
	u32 rx_shift;		/* RX data reg shift when in qe mode */
	u32 tx_shift;		/* TX data reg shift when in qe mode */

	bool qe_mode;

	void (*activate_cs) (u8 cs, u8 polarity);
	void (*deactivate_cs) (u8 cs, u8 polarity);

	u8 busy;

	struct workqueue_struct *workqueue;
	struct work_struct work;

	struct list_head queue;
	spinlock_t lock;

	struct completion done;
};

struct spi_mpc83xx_cs {
	/* functions to deal with different sized buffers */
	void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
	u32 (*get_tx) (struct mpc83xx_spi *);
	u32 rx_shift;		/* RX data reg shift when in qe mode */
	u32 tx_shift;		/* TX data reg shift when in qe mode */
	u32 hw_mode;		/* Holds HW mode register settings */
};

static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
{
	out_be32(reg, val);
}

static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
{
	return in_be32(reg);
}

#define MPC83XX_SPI_RX_BUF(type) 					  \
void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
{									  \
	type * rx = mpc83xx_spi->rx;					  \
	*rx++ = (type)(data >> mpc83xx_spi->rx_shift);			  \
	mpc83xx_spi->rx = rx;						  \
}

#define MPC83XX_SPI_TX_BUF(type)				\
u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi)	\
{								\
	u32 data;						\
	const type * tx = mpc83xx_spi->tx;			\
	if (!tx)						\
		return 0;					\
	data = *tx++ << mpc83xx_spi->tx_shift;			\
	mpc83xx_spi->tx = tx;					\
	return data;						\
}

MPC83XX_SPI_RX_BUF(u8)
MPC83XX_SPI_RX_BUF(u16)
MPC83XX_SPI_RX_BUF(u32)
MPC83XX_SPI_TX_BUF(u8)
MPC83XX_SPI_TX_BUF(u16)
MPC83XX_SPI_TX_BUF(u32)

static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
	struct spi_mpc83xx_cs	*cs = spi->controller_state;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (value == BITBANG_CS_INACTIVE) {
		if (mpc83xx_spi->deactivate_cs)
			mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
	}

	if (value == BITBANG_CS_ACTIVE) {
		u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);

		mpc83xx_spi->rx_shift = cs->rx_shift;
		mpc83xx_spi->tx_shift = cs->tx_shift;
		mpc83xx_spi->get_rx = cs->get_rx;
		mpc83xx_spi->get_tx = cs->get_tx;

		if (cs->hw_mode != regval) {
			unsigned long flags;
			void *tmp_ptr = &mpc83xx_spi->base->mode;

			regval = cs->hw_mode;
			/* Turn off IRQs locally to minimize time that
			 * SPI is disabled
			 */
			local_irq_save(flags);
			/* Turn off SPI unit prior changing mode */
			mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
			mpc83xx_spi_write_reg(tmp_ptr, regval);
			local_irq_restore(flags);
		}
		if (mpc83xx_spi->activate_cs)
			mpc83xx_spi->activate_cs(spi->chip_select, pol);
	}
}

static
int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u32 regval;
	u8 bits_per_word, pm;
	u32 hz;
	struct spi_mpc83xx_cs	*cs = spi->controller_state;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;

	/* Make sure its a bit width we support [4..16, 32] */
	if ((bits_per_word < 4)
	    || ((bits_per_word > 16) && (bits_per_word != 32)))
		return -EINVAL;

	if (!hz)
		hz = spi->max_speed_hz;

	cs->rx_shift = 0;
	cs->tx_shift = 0;
	if (bits_per_word <= 8) {
		cs->get_rx = mpc83xx_spi_rx_buf_u8;
		cs->get_tx = mpc83xx_spi_tx_buf_u8;
		if (mpc83xx_spi->qe_mode) {
			cs->rx_shift = 16;
			cs->tx_shift = 24;
		}
	} else if (bits_per_word <= 16) {
		cs->get_rx = mpc83xx_spi_rx_buf_u16;
		cs->get_tx = mpc83xx_spi_tx_buf_u16;
		if (mpc83xx_spi->qe_mode) {
			cs->rx_shift = 16;
			cs->tx_shift = 16;
		}
	} else if (bits_per_word <= 32) {
		cs->get_rx = mpc83xx_spi_rx_buf_u32;
		cs->get_tx = mpc83xx_spi_tx_buf_u32;
	} else
		return -EINVAL;

	if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
		cs->tx_shift = 0;
		if (bits_per_word <= 8)
			cs->rx_shift = 8;
		else
			cs->rx_shift = 0;
	}

	mpc83xx_spi->rx_shift = cs->rx_shift;
	mpc83xx_spi->tx_shift = cs->tx_shift;
	mpc83xx_spi->get_rx = cs->get_rx;
	mpc83xx_spi->get_tx = cs->get_tx;

	if (bits_per_word == 32)
		bits_per_word = 0;
	else
		bits_per_word = bits_per_word - 1;

	/* mask out bits we are going to set */
	cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16
				  | SPMODE_PM(0xF));

	cs->hw_mode |= SPMODE_LEN(bits_per_word);

	if ((mpc83xx_spi->spibrg / hz) > 64) {
		pm = mpc83xx_spi->spibrg / (hz * 64);
		if (pm > 16) {
			cs->hw_mode |= SPMODE_DIV16;
			pm /= 16;
			if (pm > 16) {
				dev_err(&spi->dev, "Requested speed is too "
					"low: %d Hz. Will use %d Hz instead.\n",
					hz, mpc83xx_spi->spibrg / 1024);
				pm = 16;
			}
		}
	} else
		pm = mpc83xx_spi->spibrg / (hz * 4);
	if (pm)
		pm--;

	cs->hw_mode |= SPMODE_PM(pm);
	regval =  mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	if (cs->hw_mode != regval) {
		unsigned long flags;
		void *tmp_ptr = &mpc83xx_spi->base->mode;

		regval = cs->hw_mode;
		/* Turn off IRQs locally to minimize time
		 * that SPI is disabled
		 */
		local_irq_save(flags);
		/* Turn off SPI unit prior changing mode */
		mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
		mpc83xx_spi_write_reg(tmp_ptr, regval);
		local_irq_restore(flags);
	}
	return 0;
}

static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct mpc83xx_spi *mpc83xx_spi;
	u32 word, len, bits_per_word;

	mpc83xx_spi = spi_master_get_devdata(spi->master);

	mpc83xx_spi->tx = t->tx_buf;
	mpc83xx_spi->rx = t->rx_buf;
	bits_per_word = spi->bits_per_word;
	if (t->bits_per_word)
		bits_per_word = t->bits_per_word;
	len = t->len;
	if (bits_per_word > 8)
		len /= 2;
	if (bits_per_word > 16)
		len /= 2;
	mpc83xx_spi->count = len;
	INIT_COMPLETION(mpc83xx_spi->done);

	/* enable rx ints */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);

	/* transmit word */
	word = mpc83xx_spi->get_tx(mpc83xx_spi);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);

	wait_for_completion(&mpc83xx_spi->done);

	/* disable rx ints */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);

	return mpc83xx_spi->count;
}

static void mpc83xx_spi_work(struct work_struct *work)
{
	struct mpc83xx_spi *mpc83xx_spi =
		container_of(work, struct mpc83xx_spi, work);

	spin_lock_irq(&mpc83xx_spi->lock);
	mpc83xx_spi->busy = 1;
	while (!list_empty(&mpc83xx_spi->queue)) {
		struct spi_message *m;
		struct spi_device *spi;
		struct spi_transfer *t = NULL;
		unsigned cs_change;
		int status, nsecs = 50;

		m = container_of(mpc83xx_spi->queue.next,
				struct spi_message, queue);
		list_del_init(&m->queue);
		spin_unlock_irq(&mpc83xx_spi->lock);

		spi = m->spi;
		cs_change = 1;
		status = 0;
		list_for_each_entry(t, &m->transfers, transfer_list) {
			if (t->bits_per_word || t->speed_hz) {
				/* Don't allow changes if CS is active */
				status = -EINVAL;

				if (cs_change)
					status = mpc83xx_spi_setup_transfer(spi, t);
				if (status < 0)
					break;
			}

			if (cs_change)
				mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
			cs_change = t->cs_change;
			if (t->len)
				status = mpc83xx_spi_bufs(spi, t);
			if (status) {
				status = -EMSGSIZE;
				break;
			}
			m->actual_length += t->len;

			if (t->delay_usecs)
				udelay(t->delay_usecs);

			if (cs_change) {
				ndelay(nsecs);
				mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
				ndelay(nsecs);
			}
		}

		m->status = status;
		m->complete(m->context);

		if (status || !cs_change) {
			ndelay(nsecs);
			mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
		}

		mpc83xx_spi_setup_transfer(spi, NULL);

		spin_lock_irq(&mpc83xx_spi->lock);
	}
	mpc83xx_spi->busy = 0;
	spin_unlock_irq(&mpc83xx_spi->lock);
}

/* the spi->mode bits understood by this driver: */
#define MODEBITS	(SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
			| SPI_LSB_FIRST | SPI_LOOP)

static int mpc83xx_spi_setup(struct spi_device *spi)
{
	struct mpc83xx_spi *mpc83xx_spi;
	int retval;
	u32 hw_mode;
	struct spi_mpc83xx_cs	*cs = spi->controller_state;

	if (spi->mode & ~MODEBITS) {
		dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
			spi->mode & ~MODEBITS);
		return -EINVAL;
	}

	if (!spi->max_speed_hz)
		return -EINVAL;

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}
	mpc83xx_spi = spi_master_get_devdata(spi->master);

	if (!spi->bits_per_word)
		spi->bits_per_word = 8;

	hw_mode = cs->hw_mode; /* Save orginal settings */
	cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	/* mask out bits we are going to set */
	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
			 | SPMODE_REV | SPMODE_LOOP);

	if (spi->mode & SPI_CPHA)
		cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK;
	if (spi->mode & SPI_CPOL)
		cs->hw_mode |= SPMODE_CI_INACTIVEHIGH;
	if (!(spi->mode & SPI_LSB_FIRST))
		cs->hw_mode |= SPMODE_REV;
	if (spi->mode & SPI_LOOP)
		cs->hw_mode |= SPMODE_LOOP;

	retval = mpc83xx_spi_setup_transfer(spi, NULL);
	if (retval < 0) {
		cs->hw_mode = hw_mode; /* Restore settings */
		return retval;
	}

	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
		__func__, spi->mode & (SPI_CPOL | SPI_CPHA),
		spi->bits_per_word, spi->max_speed_hz);
#if 0 /* Don't think this is needed */
	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	spin_lock(&mpc83xx_spi->lock);
	if (!mpc83xx_spi->busy)
		mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
	spin_unlock(&mpc83xx_spi->lock);
#endif
	return 0;
}

irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
{
	struct mpc83xx_spi *mpc83xx_spi = context_data;
	u32 event;
	irqreturn_t ret = IRQ_NONE;

	/* Get interrupt events(tx/rx) */
	event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);

	/* We need handle RX first */
	if (event & SPIE_NE) {
		u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);

		if (mpc83xx_spi->rx)
			mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);

		ret = IRQ_HANDLED;
	}

	if ((event & SPIE_NF) == 0)
		/* spin until TX is done */
		while (((event =
			 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
						SPIE_NF) == 0)
			 cpu_relax();

	mpc83xx_spi->count -= 1;
	if (mpc83xx_spi->count) {
		u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
		mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
	} else {
		complete(&mpc83xx_spi->done);
	}

	/* Clear the events */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);

	return ret;
}
static int mpc83xx_spi_transfer(struct spi_device *spi,
				struct spi_message *m)
{
	struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
	unsigned long flags;

	m->actual_length = 0;
	m->status = -EINPROGRESS;

	spin_lock_irqsave(&mpc83xx_spi->lock, flags);
	list_add_tail(&m->queue, &mpc83xx_spi->queue);
	queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
	spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);

	return 0;
}


static void mpc83xx_spi_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}

static int __init mpc83xx_spi_probe(struct platform_device *dev)
{
	struct spi_master *master;
	struct mpc83xx_spi *mpc83xx_spi;
	struct fsl_spi_platform_data *pdata;
	struct resource *r;
	u32 regval;
	int ret = 0;

	/* Get resources(memory, IRQ) associated with the device */
	master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));

	if (master == NULL) {
		ret = -ENOMEM;
		goto err;
	}

	platform_set_drvdata(dev, master);
	pdata = dev->dev.platform_data;

	if (pdata == NULL) {
		ret = -ENODEV;
		goto free_master;
	}

	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENODEV;
		goto free_master;
	}
	master->setup = mpc83xx_spi_setup;
	master->transfer = mpc83xx_spi_transfer;
	master->cleanup = mpc83xx_spi_cleanup;

	mpc83xx_spi = spi_master_get_devdata(master);
	mpc83xx_spi->activate_cs = pdata->activate_cs;
	mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
	mpc83xx_spi->qe_mode = pdata->qe_mode;
	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
	mpc83xx_spi->spibrg = pdata->sysclk;

	mpc83xx_spi->rx_shift = 0;
	mpc83xx_spi->tx_shift = 0;
	if (mpc83xx_spi->qe_mode) {
		mpc83xx_spi->rx_shift = 16;
		mpc83xx_spi->tx_shift = 24;
	}

	init_completion(&mpc83xx_spi->done);

	mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
	if (mpc83xx_spi->base == NULL) {
		ret = -ENOMEM;
		goto put_master;
	}

	mpc83xx_spi->irq = platform_get_irq(dev, 0);

	if (mpc83xx_spi->irq < 0) {
		ret = -ENXIO;
		goto unmap_io;
	}

	/* Register for SPI Interrupt */
	ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
			  0, "mpc83xx_spi", mpc83xx_spi);

	if (ret != 0)
		goto unmap_io;

	master->bus_num = pdata->bus_num;
	master->num_chipselect = pdata->max_chipselect;

	/* SPI controller initializations */
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);

	/* Enable SPI interface */
	regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
	if (pdata->qe_mode)
		regval |= SPMODE_OP;

	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
	spin_lock_init(&mpc83xx_spi->lock);
	init_completion(&mpc83xx_spi->done);
	INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
	INIT_LIST_HEAD(&mpc83xx_spi->queue);

	mpc83xx_spi->workqueue = create_singlethread_workqueue(
		master->dev.parent->bus_id);
	if (mpc83xx_spi->workqueue == NULL) {
		ret = -EBUSY;
		goto free_irq;
	}

	ret = spi_register_master(master);
	if (ret < 0)
		goto unreg_master;

	printk(KERN_INFO
	       "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
	       dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);

	return ret;

unreg_master:
	destroy_workqueue(mpc83xx_spi->workqueue);
free_irq:
	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
unmap_io:
	iounmap(mpc83xx_spi->base);
put_master:
	spi_master_put(master);
free_master:
	kfree(master);
err:
	return ret;
}

static int __exit mpc83xx_spi_remove(struct platform_device *dev)
{
	struct mpc83xx_spi *mpc83xx_spi;
	struct spi_master *master;

	master = platform_get_drvdata(dev);
	mpc83xx_spi = spi_master_get_devdata(master);

	flush_workqueue(mpc83xx_spi->workqueue);
	destroy_workqueue(mpc83xx_spi->workqueue);
	spi_unregister_master(master);

	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	iounmap(mpc83xx_spi->base);

	return 0;
}

MODULE_ALIAS("platform:mpc83xx_spi");
static struct platform_driver mpc83xx_spi_driver = {
	.remove = __exit_p(mpc83xx_spi_remove),
	.driver = {
		.name = "mpc83xx_spi",
		.owner = THIS_MODULE,
	},
};

static int __init mpc83xx_spi_init(void)
{
	return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
}

static void __exit mpc83xx_spi_exit(void)
{
	platform_driver_unregister(&mpc83xx_spi_driver);
}

module_init(mpc83xx_spi_init);
module_exit(mpc83xx_spi_exit);

MODULE_AUTHOR("Kumar Gala");
MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ccf06998 KG	1	/*
	2	* MPC83xx SPI controller driver.
	3	*
	4	* Maintainer: Kumar Gala
	5	*
	6	* Copyright (C) 2006 Polycom, Inc.
	7	*
	8	* This program is free software; you can redistribute it and/or modify it
	9	* under the terms of the GNU General Public License as published by the
	10	* Free Software Foundation; either version 2 of the License, or (at your
	11	* option) any later version.
	12	*/
	13	#include <linux/module.h>
	14	#include <linux/init.h>
	15	#include <linux/types.h>
	16	#include <linux/kernel.h>
	17	#include <linux/completion.h>
	18	#include <linux/interrupt.h>
	19	#include <linux/delay.h>
	20	#include <linux/irq.h>
	21	#include <linux/device.h>
	22	#include <linux/spi/spi.h>
	23	#include <linux/spi/spi_bitbang.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/fsl_devices.h>
	26
	27	#include <asm/irq.h>
	28	#include <asm/io.h>
	29
	30	/* SPI Controller registers */
	31	struct mpc83xx_spi_reg {
	32	u8 res1[0x20];
	33	__be32 mode;
	34	__be32 event;
	35	__be32 mask;
	36	__be32 command;
	37	__be32 transmit;
	38	__be32 receive;
	39	};
	40
	41	/* SPI Controller mode register definitions */
2a485d7a	42	#define SPMODE_LOOP (1 << 30)
ccf06998 KG	43	#define SPMODE_CI_INACTIVEHIGH (1 << 29)
	44	#define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
	45	#define SPMODE_DIV16 (1 << 27)
	46	#define SPMODE_REV (1 << 26)
	47	#define SPMODE_MS (1 << 25)
	48	#define SPMODE_ENABLE (1 << 24)
	49	#define SPMODE_LEN(x) ((x) << 20)
	50	#define SPMODE_PM(x) ((x) << 16)
f29ba280	51	#define SPMODE_OP (1 << 14)
c9bfcb31	52	#define SPMODE_CG(x) ((x) << 7)
ccf06998 KG	53
	54	/*
	55	* Default for SPI Mode:
	56	* SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
	57	*/
	58	#define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH \| SPMODE_DIV16 \| SPMODE_REV \| \
	59	SPMODE_MS \| SPMODE_LEN(7) \| SPMODE_PM(0xf))
	60
	61	/* SPIE register values */
	62	#define SPIE_NE 0x00000200 /* Not empty */
	63	#define SPIE_NF 0x00000100 /* Not full */
	64
	65	/* SPIM register values */
	66	#define SPIM_NE 0x00000200 /* Not empty */
	67	#define SPIM_NF 0x00000100 /* Not full */
	68
	69	/* SPI Controller driver's private data. */
	70	struct mpc83xx_spi {
ccf06998 KG	71	struct mpc83xx_spi_reg __iomem *base;
	72
	73	/* rx & tx bufs from the spi_transfer */
	74	const void *tx;
	75	void *rx;
	76
	77	/* functions to deal with different sized buffers */
	78	void (get_rx) (u32 rx_data, struct mpc83xx_spi );
	79	u32(get_tx) (struct mpc83xx_spi );
	80
	81	unsigned int count;
c9bfcb31	82	int irq;
ccf06998 KG	83
	84	unsigned nsecs; /* (clock cycle time)/2 */
	85
e24a4d1e	86	u32 spibrg; /* SPIBRG input clock */
f29ba280 JT	87	u32 rx_shift; /* RX data reg shift when in qe mode */
	88	u32 tx_shift; /* TX data reg shift when in qe mode */
	89
	90	bool qe_mode;
	91
ccf06998 KG	92	void (*activate_cs) (u8 cs, u8 polarity);
ccf06998 KG	93	void (*deactivate_cs) (u8 cs, u8 polarity);
c9bfcb31 JT	94
	95	u8 busy;
	96
	97	struct workqueue_struct *workqueue;
	98	struct work_struct work;
	99
	100	struct list_head queue;
	101	spinlock_t lock;
	102
	103	struct completion done;
	104	};
	105
	106	struct spi_mpc83xx_cs {
	107	/* functions to deal with different sized buffers */
	108	void (get_rx) (u32 rx_data, struct mpc83xx_spi );
	109	u32 (get_tx) (struct mpc83xx_spi );
	110	u32 rx_shift; /* RX data reg shift when in qe mode */
	111	u32 tx_shift; /* TX data reg shift when in qe mode */
	112	u32 hw_mode; /* Holds HW mode register settings */
ccf06998 KG	113	};
	114
	115	static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
	116	{
	117	out_be32(reg, val);
	118	}
	119
	120	static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
	121	{
	122	return in_be32(reg);
	123	}
	124
	125	#define MPC83XX_SPI_RX_BUF(type) \
	126	void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
	127	{ \
	128	type * rx = mpc83xx_spi->rx; \
f29ba280	129	*rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
ccf06998 KG	130	mpc83xx_spi->rx = rx; \
	131	}
	132
	133	#define MPC83XX_SPI_TX_BUF(type) \
	134	u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
	135	{ \
	136	u32 data; \
	137	const type * tx = mpc83xx_spi->tx; \
4b1badf5 DB	138	if (!tx) \
4b1badf5 DB	139	return 0; \
f29ba280	140	data = *tx++ << mpc83xx_spi->tx_shift; \
ccf06998 KG	141	mpc83xx_spi->tx = tx; \
	142	return data; \
	143	}
	144
	145	MPC83XX_SPI_RX_BUF(u8)
	146	MPC83XX_SPI_RX_BUF(u16)
	147	MPC83XX_SPI_RX_BUF(u32)
	148	MPC83XX_SPI_TX_BUF(u8)
	149	MPC83XX_SPI_TX_BUF(u16)
	150	MPC83XX_SPI_TX_BUF(u32)
	151
	152	static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
	153	{
	154	struct mpc83xx_spi *mpc83xx_spi;
	155	u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
c9bfcb31	156	struct spi_mpc83xx_cs *cs = spi->controller_state;
ccf06998 KG	157
	158	mpc83xx_spi = spi_master_get_devdata(spi->master);
	159
	160	if (value == BITBANG_CS_INACTIVE) {
	161	if (mpc83xx_spi->deactivate_cs)
	162	mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
	163	}
	164
	165	if (value == BITBANG_CS_ACTIVE) {
	166	u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
a44648b0	167
c9bfcb31 JT	168	mpc83xx_spi->rx_shift = cs->rx_shift;
	169	mpc83xx_spi->tx_shift = cs->tx_shift;
	170	mpc83xx_spi->get_rx = cs->get_rx;
	171	mpc83xx_spi->get_tx = cs->get_tx;
	172
	173	if (cs->hw_mode != regval) {
	174	unsigned long flags;
	175	void *tmp_ptr = &mpc83xx_spi->base->mode;
	176
	177	regval = cs->hw_mode;
	178	/* Turn off IRQs locally to minimize time that
	179	* SPI is disabled
	180	*/
	181	local_irq_save(flags);
	182	/* Turn off SPI unit prior changing mode */
	183	mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
	184	mpc83xx_spi_write_reg(tmp_ptr, regval);
	185	local_irq_restore(flags);
ccf06998	186	}
ccf06998 KG	187	if (mpc83xx_spi->activate_cs)
	188	mpc83xx_spi->activate_cs(spi->chip_select, pol);
	189	}
	190	}
	191
	192	static
	193	int mpc83xx_spi_setup_transfer(struct spi_device spi, struct spi_transfer t)
	194	{
	195	struct mpc83xx_spi *mpc83xx_spi;
	196	u32 regval;
c9bfcb31	197	u8 bits_per_word, pm;
ccf06998	198	u32 hz;
c9bfcb31	199	struct spi_mpc83xx_cs *cs = spi->controller_state;
ccf06998 KG	200
	201	mpc83xx_spi = spi_master_get_devdata(spi->master);
	202
	203	if (t) {
	204	bits_per_word = t->bits_per_word;
	205	hz = t->speed_hz;
	206	} else {
	207	bits_per_word = 0;
	208	hz = 0;
	209	}
	210
	211	/* spi_transfer level calls that work per-word */
	212	if (!bits_per_word)
	213	bits_per_word = spi->bits_per_word;
	214
	215	/* Make sure its a bit width we support [4..16, 32] */
	216	if ((bits_per_word < 4)
	217	\|\| ((bits_per_word > 16) && (bits_per_word != 32)))
	218	return -EINVAL;
	219
c9bfcb31 JT	220	if (!hz)
	221	hz = spi->max_speed_hz;
	222
	223	cs->rx_shift = 0;
	224	cs->tx_shift = 0;
ccf06998	225	if (bits_per_word <= 8) {
c9bfcb31 JT	226	cs->get_rx = mpc83xx_spi_rx_buf_u8;
c9bfcb31 JT	227	cs->get_tx = mpc83xx_spi_tx_buf_u8;
f29ba280	228	if (mpc83xx_spi->qe_mode) {
c9bfcb31 JT	229	cs->rx_shift = 16;
c9bfcb31 JT	230	cs->tx_shift = 24;
f29ba280	231	}
ccf06998	232	} else if (bits_per_word <= 16) {
c9bfcb31 JT	233	cs->get_rx = mpc83xx_spi_rx_buf_u16;
c9bfcb31 JT	234	cs->get_tx = mpc83xx_spi_tx_buf_u16;
f29ba280	235	if (mpc83xx_spi->qe_mode) {
c9bfcb31 JT	236	cs->rx_shift = 16;
c9bfcb31 JT	237	cs->tx_shift = 16;
f29ba280	238	}
ccf06998	239	} else if (bits_per_word <= 32) {
c9bfcb31 JT	240	cs->get_rx = mpc83xx_spi_rx_buf_u32;
c9bfcb31 JT	241	cs->get_tx = mpc83xx_spi_tx_buf_u32;
ccf06998 KG	242	} else
	243	return -EINVAL;
	244
35cc0b97	245	if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
c9bfcb31	246	cs->tx_shift = 0;
35cc0b97	247	if (bits_per_word <= 8)
c9bfcb31	248	cs->rx_shift = 8;
35cc0b97	249	else
c9bfcb31	250	cs->rx_shift = 0;
35cc0b97 AV	251	}
35cc0b97 AV	252
c9bfcb31 JT	253	mpc83xx_spi->rx_shift = cs->rx_shift;
	254	mpc83xx_spi->tx_shift = cs->tx_shift;
	255	mpc83xx_spi->get_rx = cs->get_rx;
	256	mpc83xx_spi->get_tx = cs->get_tx;
ccf06998 KG	257
	258	if (bits_per_word == 32)
	259	bits_per_word = 0;
	260	else
	261	bits_per_word = bits_per_word - 1;
	262
32421daa	263	/* mask out bits we are going to set */
c9bfcb31 JT	264	cs->hw_mode &= ~(SPMODE_LEN(0xF) \| SPMODE_DIV16
	265	\| SPMODE_PM(0xF));
	266
	267	cs->hw_mode \|= SPMODE_LEN(bits_per_word);
	268
a61f5345 CG	269	if ((mpc83xx_spi->spibrg / hz) > 64) {
	270	pm = mpc83xx_spi->spibrg / (hz * 64);
	271	if (pm > 16) {
	272	cs->hw_mode \|= SPMODE_DIV16;
	273	pm /= 16;
	274	if (pm > 16) {
	275	dev_err(&spi->dev, "Requested speed is too "
	276	"low: %d Hz. Will use %d Hz instead.\n",
	277	hz, mpc83xx_spi->spibrg / 1024);
	278	pm = 16;
	279	}
c9bfcb31	280	}
a61f5345	281	} else
c9bfcb31	282	pm = mpc83xx_spi->spibrg / (hz * 4);
a61f5345 CG	283	if (pm)
	284	pm--;
	285
	286	cs->hw_mode \|= SPMODE_PM(pm);
c9bfcb31 JT	287	regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	288	if (cs->hw_mode != regval) {
	289	unsigned long flags;
	290	void *tmp_ptr = &mpc83xx_spi->base->mode;
	291
	292	regval = cs->hw_mode;
	293	/* Turn off IRQs locally to minimize time
	294	* that SPI is disabled
	295	*/
	296	local_irq_save(flags);
	297	/* Turn off SPI unit prior changing mode */
	298	mpc83xx_spi_write_reg(tmp_ptr, regval & ~SPMODE_ENABLE);
	299	mpc83xx_spi_write_reg(tmp_ptr, regval);
	300	local_irq_restore(flags);
	301	}
	302	return 0;
	303	}
ccf06998	304
c9bfcb31 JT	305	static int mpc83xx_spi_bufs(struct spi_device spi, struct spi_transfer t)
	306	{
	307	struct mpc83xx_spi *mpc83xx_spi;
	308	u32 word, len, bits_per_word;
ccf06998	309
c9bfcb31 JT	310	mpc83xx_spi = spi_master_get_devdata(spi->master);
	311
	312	mpc83xx_spi->tx = t->tx_buf;
	313	mpc83xx_spi->rx = t->rx_buf;
	314	bits_per_word = spi->bits_per_word;
	315	if (t->bits_per_word)
	316	bits_per_word = t->bits_per_word;
	317	len = t->len;
	318	if (bits_per_word > 8)
	319	len /= 2;
	320	if (bits_per_word > 16)
	321	len /= 2;
	322	mpc83xx_spi->count = len;
	323	INIT_COMPLETION(mpc83xx_spi->done);
	324
	325	/* enable rx ints */
	326	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
	327
	328	/* transmit word */
	329	word = mpc83xx_spi->get_tx(mpc83xx_spi);
	330	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
	331
	332	wait_for_completion(&mpc83xx_spi->done);
	333
	334	/* disable rx ints */
	335	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	336
	337	return mpc83xx_spi->count;
	338	}
	339
	340	static void mpc83xx_spi_work(struct work_struct *work)
	341	{
	342	struct mpc83xx_spi *mpc83xx_spi =
	343	container_of(work, struct mpc83xx_spi, work);
	344
	345	spin_lock_irq(&mpc83xx_spi->lock);
	346	mpc83xx_spi->busy = 1;
	347	while (!list_empty(&mpc83xx_spi->queue)) {
	348	struct spi_message *m;
	349	struct spi_device *spi;
	350	struct spi_transfer *t = NULL;
	351	unsigned cs_change;
	352	int status, nsecs = 50;
	353
	354	m = container_of(mpc83xx_spi->queue.next,
	355	struct spi_message, queue);
	356	list_del_init(&m->queue);
	357	spin_unlock_irq(&mpc83xx_spi->lock);
	358
	359	spi = m->spi;
	360	cs_change = 1;
	361	status = 0;
	362	list_for_each_entry(t, &m->transfers, transfer_list) {
	363	if (t->bits_per_word \|\| t->speed_hz) {
	364	/* Don't allow changes if CS is active */
	365	status = -EINVAL;
	366
	367	if (cs_change)
	368	status = mpc83xx_spi_setup_transfer(spi, t);
	369	if (status < 0)
	370	break;
	371	}
	372
	373	if (cs_change)
374	mpc83xx_spi_chipselect(spi, BITBANG_CS_ACTIVE);
375	cs_change = t->cs_change;
376	if (t->len)
377	status = mpc83xx_spi_bufs(spi, t);
378	if (status) {
379	status = -EMSGSIZE;
380	break;
381	}
382	m->actual_length += t->len;
383
384	if (t->delay_usecs)
385	udelay(t->delay_usecs);
386
387	if (cs_change) {
388	ndelay(nsecs);
389	mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
390	ndelay(nsecs);
391	}
392	}
393
394	m->status = status;
395	m->complete(m->context);
396
397	if (status \|\| !cs_change) {
398	ndelay(nsecs);
399	mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
400	}
401
402	mpc83xx_spi_setup_transfer(spi, NULL);
403
404	spin_lock_irq(&mpc83xx_spi->lock);
405	}
406	mpc83xx_spi->busy = 0;
407	spin_unlock_irq(&mpc83xx_spi->lock);
ccf06998 KG	408	}
ccf06998 KG	409
dccd573b	410	/* the spi->mode bits understood by this driver: */
2a485d7a AV	411	#define MODEBITS (SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH \
2a485d7a AV	412	\| SPI_LSB_FIRST \| SPI_LOOP)
dccd573b	413
ccf06998 KG	414	static int mpc83xx_spi_setup(struct spi_device *spi)
ccf06998 KG	415	{
ccf06998 KG	416	struct mpc83xx_spi *mpc83xx_spi;
ccf06998 KG	417	int retval;
c9bfcb31 JT	418	u32 hw_mode;
c9bfcb31 JT	419	struct spi_mpc83xx_cs *cs = spi->controller_state;
ccf06998	420
dccd573b DB	421	if (spi->mode & ~MODEBITS) {
	422	dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
	423	spi->mode & ~MODEBITS);
	424	return -EINVAL;
	425	}
	426
ccf06998 KG	427	if (!spi->max_speed_hz)
	428	return -EINVAL;
	429
c9bfcb31 JT	430	if (!cs) {
	431	cs = kzalloc(sizeof *cs, GFP_KERNEL);
	432	if (!cs)
	433	return -ENOMEM;
	434	spi->controller_state = cs;
	435	}
ccf06998 KG	436	mpc83xx_spi = spi_master_get_devdata(spi->master);
	437
	438	if (!spi->bits_per_word)
	439	spi->bits_per_word = 8;
	440
c9bfcb31 JT	441	hw_mode = cs->hw_mode; /* Save orginal settings */
	442	cs->hw_mode = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
	443	/* mask out bits we are going to set */
	444	cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK \| SPMODE_CI_INACTIVEHIGH
	445	\| SPMODE_REV \| SPMODE_LOOP);
	446
	447	if (spi->mode & SPI_CPHA)
	448	cs->hw_mode \|= SPMODE_CP_BEGIN_EDGECLK;
	449	if (spi->mode & SPI_CPOL)
	450	cs->hw_mode \|= SPMODE_CI_INACTIVEHIGH;
	451	if (!(spi->mode & SPI_LSB_FIRST))
	452	cs->hw_mode \|= SPMODE_REV;
	453	if (spi->mode & SPI_LOOP)
	454	cs->hw_mode \|= SPMODE_LOOP;
	455
ccf06998	456	retval = mpc83xx_spi_setup_transfer(spi, NULL);
c9bfcb31 JT	457	if (retval < 0) {
c9bfcb31 JT	458	cs->hw_mode = hw_mode; /* Restore settings */
ccf06998	459	return retval;
c9bfcb31	460	}
ccf06998	461
c9bfcb31	462	dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u Hz\n",
b687d2a8	463	__func__, spi->mode & (SPI_CPOL \| SPI_CPHA),
c9bfcb31 JT	464	spi->bits_per_word, spi->max_speed_hz);
c9bfcb31 JT	465	#if 0 /* Don't think this is needed */
ccf06998 KG	466	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	467	* setup, unless the hardware defaults cooperate to avoid confusion
	468	* between normal (active low) and inverted chipselects.
	469	*/
	470
	471	/* deselect chip (low or high) */
c9bfcb31 JT	472	spin_lock(&mpc83xx_spi->lock);
	473	if (!mpc83xx_spi->busy)
	474	mpc83xx_spi_chipselect(spi, BITBANG_CS_INACTIVE);
	475	spin_unlock(&mpc83xx_spi->lock);
	476	#endif
ccf06998 KG	477	return 0;
	478	}
	479
7d12e780	480	irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
ccf06998 KG	481	{
	482	struct mpc83xx_spi *mpc83xx_spi = context_data;
	483	u32 event;
	484	irqreturn_t ret = IRQ_NONE;
	485
	486	/* Get interrupt events(tx/rx) */
	487	event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
	488
	489	/* We need handle RX first */
	490	if (event & SPIE_NE) {
	491	u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
	492
	493	if (mpc83xx_spi->rx)
	494	mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
	495
	496	ret = IRQ_HANDLED;
	497	}
	498
	499	if ((event & SPIE_NF) == 0)
	500	/* spin until TX is done */
	501	while (((event =
	502	mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
	503	SPIE_NF) == 0)
	504	cpu_relax();
	505
	506	mpc83xx_spi->count -= 1;
	507	if (mpc83xx_spi->count) {
65e213cd JA	508	u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
65e213cd JA	509	mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
ccf06998 KG	510	} else {
	511	complete(&mpc83xx_spi->done);
	512	}
	513
	514	/* Clear the events */
	515	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
	516
	517	return ret;
	518	}
c9bfcb31 JT	519	static int mpc83xx_spi_transfer(struct spi_device *spi,
	520	struct spi_message *m)
	521	{
	522	struct mpc83xx_spi *mpc83xx_spi = spi_master_get_devdata(spi->master);
	523	unsigned long flags;
	524
	525	m->actual_length = 0;
	526	m->status = -EINPROGRESS;
	527
	528	spin_lock_irqsave(&mpc83xx_spi->lock, flags);
	529	list_add_tail(&m->queue, &mpc83xx_spi->queue);
	530	queue_work(mpc83xx_spi->workqueue, &mpc83xx_spi->work);
	531	spin_unlock_irqrestore(&mpc83xx_spi->lock, flags);
	532
	533	return 0;
	534	}
	535
	536
	537	static void mpc83xx_spi_cleanup(struct spi_device *spi)
	538	{
	539	kfree(spi->controller_state);
	540	}
ccf06998 KG	541
	542	static int __init mpc83xx_spi_probe(struct platform_device *dev)
	543	{
	544	struct spi_master *master;
	545	struct mpc83xx_spi *mpc83xx_spi;
	546	struct fsl_spi_platform_data *pdata;
	547	struct resource *r;
	548	u32 regval;
	549	int ret = 0;
	550
	551	/* Get resources(memory, IRQ) associated with the device */
	552	master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
	553
	554	if (master == NULL) {
	555	ret = -ENOMEM;
	556	goto err;
	557	}
	558
	559	platform_set_drvdata(dev, master);
	560	pdata = dev->dev.platform_data;
	561
	562	if (pdata == NULL) {
	563	ret = -ENODEV;
	564	goto free_master;
	565	}
	566
	567	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	568	if (r == NULL) {
	569	ret = -ENODEV;
	570	goto free_master;
	571	}
c9bfcb31 JT	572	master->setup = mpc83xx_spi_setup;
	573	master->transfer = mpc83xx_spi_transfer;
	574	master->cleanup = mpc83xx_spi_cleanup;
	575
ccf06998	576	mpc83xx_spi = spi_master_get_devdata(master);
ccf06998 KG	577	mpc83xx_spi->activate_cs = pdata->activate_cs;
ccf06998 KG	578	mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
f29ba280	579	mpc83xx_spi->qe_mode = pdata->qe_mode;
ccf06998 KG	580	mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
ccf06998 KG	581	mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
59a0ea50	582	mpc83xx_spi->spibrg = pdata->sysclk;
e24a4d1e	583
f29ba280 JT	584	mpc83xx_spi->rx_shift = 0;
	585	mpc83xx_spi->tx_shift = 0;
	586	if (mpc83xx_spi->qe_mode) {
	587	mpc83xx_spi->rx_shift = 16;
	588	mpc83xx_spi->tx_shift = 24;
	589	}
	590
ccf06998 KG	591	init_completion(&mpc83xx_spi->done);
	592
	593	mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
	594	if (mpc83xx_spi->base == NULL) {
	595	ret = -ENOMEM;
	596	goto put_master;
	597	}
	598
	599	mpc83xx_spi->irq = platform_get_irq(dev, 0);
	600
	601	if (mpc83xx_spi->irq < 0) {
	602	ret = -ENXIO;
	603	goto unmap_io;
	604	}
	605
	606	/* Register for SPI Interrupt */
	607	ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
	608	0, "mpc83xx_spi", mpc83xx_spi);
	609
	610	if (ret != 0)
	611	goto unmap_io;
	612
	613	master->bus_num = pdata->bus_num;
	614	master->num_chipselect = pdata->max_chipselect;
	615
	616	/* SPI controller initializations */
	617	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
	618	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
	619	mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
	620	mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
	621
	622	/* Enable SPI interface */
	623	regval = pdata->initial_spmode \| SPMODE_INIT_VAL \| SPMODE_ENABLE;
f29ba280 JT	624	if (pdata->qe_mode)
	625	regval \|= SPMODE_OP;
	626
ccf06998	627	mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
c9bfcb31 JT	628	spin_lock_init(&mpc83xx_spi->lock);
	629	init_completion(&mpc83xx_spi->done);
	630	INIT_WORK(&mpc83xx_spi->work, mpc83xx_spi_work);
	631	INIT_LIST_HEAD(&mpc83xx_spi->queue);
ccf06998	632
c9bfcb31 JT	633	mpc83xx_spi->workqueue = create_singlethread_workqueue(
	634	master->dev.parent->bus_id);
	635	if (mpc83xx_spi->workqueue == NULL) {
	636	ret = -EBUSY;
ccf06998	637	goto free_irq;
c9bfcb31 JT	638	}
	639
	640	ret = spi_register_master(master);
	641	if (ret < 0)
	642	goto unreg_master;
ccf06998 KG	643
	644	printk(KERN_INFO
	645	"%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
	646	dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
	647
	648	return ret;
	649
c9bfcb31 JT	650	unreg_master:
c9bfcb31 JT	651	destroy_workqueue(mpc83xx_spi->workqueue);
ccf06998 KG	652	free_irq:
	653	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
	654	unmap_io:
	655	iounmap(mpc83xx_spi->base);
	656	put_master:
	657	spi_master_put(master);
	658	free_master:
	659	kfree(master);
	660	err:
	661	return ret;
	662	}
	663
d1e44d9c	664	static int __exit mpc83xx_spi_remove(struct platform_device *dev)
ccf06998 KG	665	{
	666	struct mpc83xx_spi *mpc83xx_spi;
	667	struct spi_master *master;
	668
	669	master = platform_get_drvdata(dev);
	670	mpc83xx_spi = spi_master_get_devdata(master);
	671
c9bfcb31 JT	672	flush_workqueue(mpc83xx_spi->workqueue);
	673	destroy_workqueue(mpc83xx_spi->workqueue);
	674	spi_unregister_master(master);
	675
ccf06998 KG	676	free_irq(mpc83xx_spi->irq, mpc83xx_spi);
ccf06998 KG	677	iounmap(mpc83xx_spi->base);
ccf06998 KG	678
	679	return 0;
	680	}
	681
7e38c3c4	682	MODULE_ALIAS("platform:mpc83xx_spi");
ccf06998	683	static struct platform_driver mpc83xx_spi_driver = {
d1e44d9c	684	.remove = __exit_p(mpc83xx_spi_remove),
ccf06998	685	.driver = {
7e38c3c4 KS	686	.name = "mpc83xx_spi",
7e38c3c4 KS	687	.owner = THIS_MODULE,
ccf06998 KG	688	},
	689	};
	690
	691	static int __init mpc83xx_spi_init(void)
	692	{
d1e44d9c	693	return platform_driver_probe(&mpc83xx_spi_driver, mpc83xx_spi_probe);
ccf06998 KG	694	}
	695
	696	static void __exit mpc83xx_spi_exit(void)
	697	{
	698	platform_driver_unregister(&mpc83xx_spi_driver);
	699	}
	700
	701	module_init(mpc83xx_spi_init);
	702	module_exit(mpc83xx_spi_exit);
	703
	704	MODULE_AUTHOR("Kumar Gala");
	705	MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
	706	MODULE_LICENSE("GPL");