[net-next-2.6.git] / drivers / spi / spi_bitbang.c

/*
 * spi_bitbang.c - polling/bitbanging SPI master controller driver utilities
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/init.h>
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/platform_device.h>
#include <linux/slab.h>

#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>


/*----------------------------------------------------------------------*/

/*
 * FIRST PART (OPTIONAL):  word-at-a-time spi_transfer support.
 * Use this for GPIO or shift-register level hardware APIs.
 *
 * spi_bitbang_cs is in spi_device->controller_state, which is unavailable
 * to glue code.  These bitbang setup() and cleanup() routines are always
 * used, though maybe they're called from controller-aware code.
 *
 * chipselect() and friends may use use spi_device->controller_data and
 * controller registers as appropriate.
 *
 *
 * NOTE:  SPI controller pins can often be used as GPIO pins instead,
 * which means you could use a bitbang driver either to get hardware
 * working quickly, or testing for differences that aren't speed related.
 */

struct spi_bitbang_cs {
	unsigned	nsecs;	/* (clock cycle time)/2 */
	u32		(*txrx_word)(struct spi_device *spi, unsigned nsecs,
					u32 word, u8 bits);
	unsigned	(*txrx_bufs)(struct spi_device *,
					u32 (*txrx_word)(
						struct spi_device *spi,
						unsigned nsecs,
						u32 word, u8 bits),
					unsigned, struct spi_transfer *);
};

static unsigned bitbang_txrx_8(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = spi->bits_per_word;
	unsigned		count = t->len;
	const u8		*tx = t->tx_buf;
	u8			*rx = t->rx_buf;

	while (likely(count > 0)) {
		u8		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 1;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_16(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = spi->bits_per_word;
	unsigned		count = t->len;
	const u16		*tx = t->tx_buf;
	u16			*rx = t->rx_buf;

	while (likely(count > 1)) {
		u16		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 2;
	}
	return t->len - count;
}

static unsigned bitbang_txrx_32(
	struct spi_device	*spi,
	u32			(*txrx_word)(struct spi_device *spi,
					unsigned nsecs,
					u32 word, u8 bits),
	unsigned		ns,
	struct spi_transfer	*t
) {
	unsigned		bits = spi->bits_per_word;
	unsigned		count = t->len;
	const u32		*tx = t->tx_buf;
	u32			*rx = t->rx_buf;

	while (likely(count > 3)) {
		u32		word = 0;

		if (tx)
			word = *tx++;
		word = txrx_word(spi, ns, word, bits);
		if (rx)
			*rx++ = word;
		count -= 4;
	}
	return t->len - count;
}

int spi_bitbang_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	u8			bits_per_word;
	u32			hz;

	if (t) {
		bits_per_word = t->bits_per_word;
		hz = t->speed_hz;
	} else {
		bits_per_word = 0;
		hz = 0;
	}

	/* spi_transfer level calls that work per-word */
	if (!bits_per_word)
		bits_per_word = spi->bits_per_word;
	if (bits_per_word <= 8)
		cs->txrx_bufs = bitbang_txrx_8;
	else if (bits_per_word <= 16)
		cs->txrx_bufs = bitbang_txrx_16;
	else if (bits_per_word <= 32)
		cs->txrx_bufs = bitbang_txrx_32;
	else
		return -EINVAL;

	/* nsecs = (clock period)/2 */
	if (!hz)
		hz = spi->max_speed_hz;
	if (hz) {
		cs->nsecs = (1000000000/2) / hz;
		if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
			return -EINVAL;
	}

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);

/**
 * spi_bitbang_setup - default setup for per-word I/O loops
 */
int spi_bitbang_setup(struct spi_device *spi)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	struct spi_bitbang	*bitbang;
	int			retval;
	unsigned long		flags;

	bitbang = spi_master_get_devdata(spi->master);

	if (!cs) {
		cs = kzalloc(sizeof *cs, GFP_KERNEL);
		if (!cs)
			return -ENOMEM;
		spi->controller_state = cs;
	}

	/* per-word shift register access, in hardware or bitbanging */
	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL|SPI_CPHA)];
	if (!cs->txrx_word)
		return -EINVAL;

	retval = bitbang->setup_transfer(spi, NULL);
	if (retval < 0)
		return retval;

	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);

	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	 * setup, unless the hardware defaults cooperate to avoid confusion
	 * between normal (active low) and inverted chipselects.
	 */

	/* deselect chip (low or high) */
	spin_lock_irqsave(&bitbang->lock, flags);
	if (!bitbang->busy) {
		bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
		ndelay(cs->nsecs);
	}
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_setup);

/**
 * spi_bitbang_cleanup - default cleanup for per-word I/O loops
 */
void spi_bitbang_cleanup(struct spi_device *spi)
{
	kfree(spi->controller_state);
}
EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);

static int spi_bitbang_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct spi_bitbang_cs	*cs = spi->controller_state;
	unsigned		nsecs = cs->nsecs;

	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
}

/*----------------------------------------------------------------------*/

/*
 * SECOND PART ... simple transfer queue runner.
 *
 * This costs a task context per controller, running the queue by
 * performing each transfer in sequence.  Smarter hardware can queue
 * several DMA transfers at once, and process several controller queues
 * in parallel; this driver doesn't match such hardware very well.
 *
 * Drivers can provide word-at-a-time i/o primitives, or provide
 * transfer-at-a-time ones to leverage dma or fifo hardware.
 */
static void bitbang_work(struct work_struct *work)
{
	struct spi_bitbang	*bitbang =
		container_of(work, struct spi_bitbang, work);
	unsigned long		flags;
	int			(*setup_transfer)(struct spi_device *,
					struct spi_transfer *);

	setup_transfer = bitbang->setup_transfer;

	spin_lock_irqsave(&bitbang->lock, flags);
	bitbang->busy = 1;
	while (!list_empty(&bitbang->queue)) {
		struct spi_message	*m;
		struct spi_device	*spi;
		unsigned		nsecs;
		struct spi_transfer	*t = NULL;
		unsigned		tmp;
		unsigned		cs_change;
		int			status;
		int			do_setup = -1;

		m = container_of(bitbang->queue.next, struct spi_message,
				queue);
		list_del_init(&m->queue);
		spin_unlock_irqrestore(&bitbang->lock, flags);

		/* FIXME this is made-up ... the correct value is known to
		 * word-at-a-time bitbang code, and presumably chipselect()
		 * should enforce these requirements too?
		 */
		nsecs = 100;

		spi = m->spi;
		tmp = 0;
		cs_change = 1;
		status = 0;

		list_for_each_entry (t, &m->transfers, transfer_list) {

			/* override speed or wordsize? */
			if (t->speed_hz || t->bits_per_word)
				do_setup = 1;

			/* init (-1) or override (1) transfer params */
			if (do_setup != 0) {
				if (!setup_transfer) {
					status = -ENOPROTOOPT;
					break;
				}
				status = setup_transfer(spi, t);
				if (status < 0)
					break;
				if (do_setup == -1)
					do_setup = 0;
			}

			/* set up default clock polarity, and activate chip;
			 * this implicitly updates clock and spi modes as
			 * previously recorded for this device via setup().
			 * (and also deselects any other chip that might be
			 * selected ...)
			 */
			if (cs_change) {
				bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
				ndelay(nsecs);
			}
			cs_change = t->cs_change;
			if (!t->tx_buf && !t->rx_buf && t->len) {
				status = -EINVAL;
				break;
			}

			/* transfer data.  the lower level code handles any
			 * new dma mappings it needs. our caller always gave
			 * us dma-safe buffers.
			 */
			if (t->len) {
				/* REVISIT dma API still needs a designated
				 * DMA_ADDR_INVALID; ~0 might be better.
				 */
				if (!m->is_dma_mapped)
					t->rx_dma = t->tx_dma = 0;
				status = bitbang->txrx_bufs(spi, t);
			}
			if (status > 0)
				m->actual_length += status;
			if (status != t->len) {
				/* always report some kind of error */
				if (status >= 0)
					status = -EREMOTEIO;
				break;
			}
			status = 0;

			/* protocol tweaks before next transfer */
			if (t->delay_usecs)
				udelay(t->delay_usecs);

			if (!cs_change)
				continue;
			if (t->transfer_list.next == &m->transfers)
				break;

			/* sometimes a short mid-message deselect of the chip
			 * may be needed to terminate a mode or command
			 */
			ndelay(nsecs);
			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
			ndelay(nsecs);
		}

		m->status = status;
		m->complete(m->context);

		/* normally deactivate chipselect ... unless no error and
		 * cs_change has hinted that the next message will probably
		 * be for this chip too.
		 */
		if (!(status == 0 && cs_change)) {
			ndelay(nsecs);
			bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
			ndelay(nsecs);
		}

		spin_lock_irqsave(&bitbang->lock, flags);
	}
	bitbang->busy = 0;
	spin_unlock_irqrestore(&bitbang->lock, flags);
}

/**
 * spi_bitbang_transfer - default submit to transfer queue
 */
int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct spi_bitbang	*bitbang;
	unsigned long		flags;
	int			status = 0;

	m->actual_length = 0;
	m->status = -EINPROGRESS;

	bitbang = spi_master_get_devdata(spi->master);

	spin_lock_irqsave(&bitbang->lock, flags);
	if (!spi->max_speed_hz)
		status = -ENETDOWN;
	else {
		list_add_tail(&m->queue, &bitbang->queue);
		queue_work(bitbang->workqueue, &bitbang->work);
	}
	spin_unlock_irqrestore(&bitbang->lock, flags);

	return status;
}
EXPORT_SYMBOL_GPL(spi_bitbang_transfer);

/*----------------------------------------------------------------------*/

/**
 * spi_bitbang_start - start up a polled/bitbanging SPI master driver
 * @bitbang: driver handle
 *
 * Caller should have zero-initialized all parts of the structure, and then
 * provided callbacks for chip selection and I/O loops.  If the master has
 * a transfer method, its final step should call spi_bitbang_transfer; or,
 * that's the default if the transfer routine is not initialized.  It should
 * also set up the bus number and number of chipselects.
 *
 * For i/o loops, provide callbacks either per-word (for bitbanging, or for
 * hardware that basically exposes a shift register) or per-spi_transfer
 * (which takes better advantage of hardware like fifos or DMA engines).
 *
 * Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
 * spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
 * master methods.  Those methods are the defaults if the bitbang->txrx_bufs
 * routine isn't initialized.
 *
 * This routine registers the spi_master, which will process requests in a
 * dedicated task, keeping IRQs unblocked most of the time.  To stop
 * processing those requests, call spi_bitbang_stop().
 */
int spi_bitbang_start(struct spi_bitbang *bitbang)
{
	int	status;

	if (!bitbang->master || !bitbang->chipselect)
		return -EINVAL;

	INIT_WORK(&bitbang->work, bitbang_work);
	spin_lock_init(&bitbang->lock);
	INIT_LIST_HEAD(&bitbang->queue);

	if (!bitbang->master->mode_bits)
		bitbang->master->mode_bits = SPI_CPOL | SPI_CPHA | bitbang->flags;

	if (!bitbang->master->transfer)
		bitbang->master->transfer = spi_bitbang_transfer;
	if (!bitbang->txrx_bufs) {
		bitbang->use_dma = 0;
		bitbang->txrx_bufs = spi_bitbang_bufs;
		if (!bitbang->master->setup) {
			if (!bitbang->setup_transfer)
				bitbang->setup_transfer =
					 spi_bitbang_setup_transfer;
			bitbang->master->setup = spi_bitbang_setup;
			bitbang->master->cleanup = spi_bitbang_cleanup;
		}
	} else if (!bitbang->master->setup)
		return -EINVAL;

	/* this task is the only thing to touch the SPI bits */
	bitbang->busy = 0;
	bitbang->workqueue = create_singlethread_workqueue(
			dev_name(bitbang->master->dev.parent));
	if (bitbang->workqueue == NULL) {
		status = -EBUSY;
		goto err1;
	}

	/* driver may get busy before register() returns, especially
	 * if someone registered boardinfo for devices
	 */
	status = spi_register_master(bitbang->master);
	if (status < 0)
		goto err2;

	return status;

err2:
	destroy_workqueue(bitbang->workqueue);
err1:
	return status;
}
EXPORT_SYMBOL_GPL(spi_bitbang_start);

/**
 * spi_bitbang_stop - stops the task providing spi communication
 */
int spi_bitbang_stop(struct spi_bitbang *bitbang)
{
	spi_unregister_master(bitbang->master);

	WARN_ON(!list_empty(&bitbang->queue));

	destroy_workqueue(bitbang->workqueue);

	return 0;
}
EXPORT_SYMBOL_GPL(spi_bitbang_stop);

MODULE_LICENSE("GPL");
Commit	Line	Data
9904f22a DB	1	/*
	2	* spi_bitbang.c - polling/bitbanging SPI master controller driver utilities
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
9904f22a DB	19	#include <linux/init.h>
	20	#include <linux/spinlock.h>
	21	#include <linux/workqueue.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/delay.h>
	24	#include <linux/errno.h>
	25	#include <linux/platform_device.h>
5a0e3ad6	26	#include <linux/slab.h>
9904f22a DB	27
	28	#include <linux/spi/spi.h>
	29	#include <linux/spi/spi_bitbang.h>
	30
	31
	32	/----------------------------------------------------------------------/
	33
	34	/*
	35	* FIRST PART (OPTIONAL): word-at-a-time spi_transfer support.
	36	* Use this for GPIO or shift-register level hardware APIs.
	37	*
	38	* spi_bitbang_cs is in spi_device->controller_state, which is unavailable
	39	* to glue code. These bitbang setup() and cleanup() routines are always
	40	* used, though maybe they're called from controller-aware code.
	41	*
	42	* chipselect() and friends may use use spi_device->controller_data and
	43	* controller registers as appropriate.
	44	*
	45	*
	46	* NOTE: SPI controller pins can often be used as GPIO pins instead,
	47	* which means you could use a bitbang driver either to get hardware
	48	* working quickly, or testing for differences that aren't speed related.
	49	*/
	50
	51	struct spi_bitbang_cs {
	52	unsigned nsecs; /* (clock cycle time)/2 */
	53	u32 (txrx_word)(struct spi_device spi, unsigned nsecs,
	54	u32 word, u8 bits);
	55	unsigned (txrx_bufs)(struct spi_device ,
	56	u32 (*txrx_word)(
	57	struct spi_device *spi,
	58	unsigned nsecs,
	59	u32 word, u8 bits),
	60	unsigned, struct spi_transfer *);
	61	};
	62
	63	static unsigned bitbang_txrx_8(
	64	struct spi_device *spi,
	65	u32 (txrx_word)(struct spi_device spi,
	66	unsigned nsecs,
	67	u32 word, u8 bits),
	68	unsigned ns,
	69	struct spi_transfer *t
	70	) {
	71	unsigned bits = spi->bits_per_word;
	72	unsigned count = t->len;
	73	const u8 *tx = t->tx_buf;
	74	u8 *rx = t->rx_buf;
	75
	76	while (likely(count > 0)) {
	77	u8 word = 0;
	78
	79	if (tx)
	80	word = *tx++;
	81	word = txrx_word(spi, ns, word, bits);
	82	if (rx)
	83	*rx++ = word;
	84	count -= 1;
	85	}
	86	return t->len - count;
	87	}
	88
	89	static unsigned bitbang_txrx_16(
	90	struct spi_device *spi,
91	u32 (txrx_word)(struct spi_device spi,
92	unsigned nsecs,
93	u32 word, u8 bits),
94	unsigned ns,
95	struct spi_transfer *t
96	) {
97	unsigned bits = spi->bits_per_word;
98	unsigned count = t->len;
99	const u16 *tx = t->tx_buf;
100	u16 *rx = t->rx_buf;
101
102	while (likely(count > 1)) {
103	u16 word = 0;
104
105	if (tx)
106	word = *tx++;
107	word = txrx_word(spi, ns, word, bits);
108	if (rx)
109	*rx++ = word;
110	count -= 2;
111	}
112	return t->len - count;
113	}
114
115	static unsigned bitbang_txrx_32(
116	struct spi_device *spi,
117	u32 (txrx_word)(struct spi_device spi,
118	unsigned nsecs,
119	u32 word, u8 bits),
120	unsigned ns,
121	struct spi_transfer *t
122	) {
123	unsigned bits = spi->bits_per_word;
124	unsigned count = t->len;
125	const u32 *tx = t->tx_buf;
126	u32 *rx = t->rx_buf;
127
128	while (likely(count > 3)) {
129	u32 word = 0;
130
131	if (tx)
132	word = *tx++;
133	word = txrx_word(spi, ns, word, bits);
134	if (rx)
135	*rx++ = word;
136	count -= 4;
137	}
138	return t->len - count;
139	}
140
ff9f4771	141	int spi_bitbang_setup_transfer(struct spi_device spi, struct spi_transfer t)
4cff33f9 ID	142	{
	143	struct spi_bitbang_cs *cs = spi->controller_state;
	144	u8 bits_per_word;
	145	u32 hz;
	146
	147	if (t) {
	148	bits_per_word = t->bits_per_word;
	149	hz = t->speed_hz;
	150	} else {
	151	bits_per_word = 0;
	152	hz = 0;
	153	}
	154
	155	/* spi_transfer level calls that work per-word */
	156	if (!bits_per_word)
	157	bits_per_word = spi->bits_per_word;
	158	if (bits_per_word <= 8)
	159	cs->txrx_bufs = bitbang_txrx_8;
	160	else if (bits_per_word <= 16)
	161	cs->txrx_bufs = bitbang_txrx_16;
	162	else if (bits_per_word <= 32)
	163	cs->txrx_bufs = bitbang_txrx_32;
	164	else
	165	return -EINVAL;
	166
	167	/* nsecs = (clock period)/2 */
	168	if (!hz)
	169	hz = spi->max_speed_hz;
1e316d75 DB	170	if (hz) {
	171	cs->nsecs = (1000000000/2) / hz;
	172	if (cs->nsecs > (MAX_UDELAY_MS * 1000 * 1000))
	173	return -EINVAL;
	174	}
4cff33f9 ID	175
	176	return 0;
	177	}
ff9f4771	178	EXPORT_SYMBOL_GPL(spi_bitbang_setup_transfer);
4cff33f9	179
9904f22a DB	180	/**
	181	* spi_bitbang_setup - default setup for per-word I/O loops
	182	*/
	183	int spi_bitbang_setup(struct spi_device *spi)
	184	{
	185	struct spi_bitbang_cs *cs = spi->controller_state;
	186	struct spi_bitbang *bitbang;
4cff33f9	187	int retval;
d52df2e2	188	unsigned long flags;
9904f22a	189
ccf77cc4 DB	190	bitbang = spi_master_get_devdata(spi->master);
ccf77cc4 DB	191
9904f22a	192	if (!cs) {
e94b1766	193	cs = kzalloc(sizeof *cs, GFP_KERNEL);
9904f22a DB	194	if (!cs)
	195	return -ENOMEM;
	196	spi->controller_state = cs;
	197	}
9904f22a	198
9904f22a DB	199	/* per-word shift register access, in hardware or bitbanging */
	200	cs->txrx_word = bitbang->txrx_word[spi->mode & (SPI_CPOL\|SPI_CPHA)];
	201	if (!cs->txrx_word)
	202	return -EINVAL;
	203
7f8c7619	204	retval = bitbang->setup_transfer(spi, NULL);
4cff33f9 ID	205	if (retval < 0)
4cff33f9 ID	206	return retval;
9904f22a	207
7d077197	208	dev_dbg(&spi->dev, "%s, %u nsec/bit\n", __func__, 2 * cs->nsecs);
9904f22a DB	209
	210	/* NOTE we _need_ to call chipselect() early, ideally with adapter
	211	* setup, unless the hardware defaults cooperate to avoid confusion
	212	* between normal (active low) and inverted chipselects.
	213	*/
	214
	215	/* deselect chip (low or high) */
d52df2e2	216	spin_lock_irqsave(&bitbang->lock, flags);
9904f22a	217	if (!bitbang->busy) {
8275c642	218	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
9904f22a DB	219	ndelay(cs->nsecs);
9904f22a DB	220	}
d52df2e2	221	spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a DB	222
	223	return 0;
	224	}
	225	EXPORT_SYMBOL_GPL(spi_bitbang_setup);
	226
	227	/**
	228	* spi_bitbang_cleanup - default cleanup for per-word I/O loops
	229	*/
0ffa0285	230	void spi_bitbang_cleanup(struct spi_device *spi)
9904f22a DB	231	{
	232	kfree(spi->controller_state);
	233	}
	234	EXPORT_SYMBOL_GPL(spi_bitbang_cleanup);
	235
	236	static int spi_bitbang_bufs(struct spi_device spi, struct spi_transfer t)
	237	{
	238	struct spi_bitbang_cs *cs = spi->controller_state;
	239	unsigned nsecs = cs->nsecs;
	240
	241	return cs->txrx_bufs(spi, cs->txrx_word, nsecs, t);
	242	}
	243
	244	/----------------------------------------------------------------------/
	245
	246	/*
	247	* SECOND PART ... simple transfer queue runner.
	248	*
	249	* This costs a task context per controller, running the queue by
	250	* performing each transfer in sequence. Smarter hardware can queue
	251	* several DMA transfers at once, and process several controller queues
	252	* in parallel; this driver doesn't match such hardware very well.
	253	*
	254	* Drivers can provide word-at-a-time i/o primitives, or provide
	255	* transfer-at-a-time ones to leverage dma or fifo hardware.
	256	*/
c4028958	257	static void bitbang_work(struct work_struct *work)
9904f22a	258	{
c4028958 DH	259	struct spi_bitbang *bitbang =
c4028958 DH	260	container_of(work, struct spi_bitbang, work);
9904f22a	261	unsigned long flags;
529ba0d9 DB	262	int (setup_transfer)(struct spi_device ,
	263	struct spi_transfer *);
	264
	265	setup_transfer = bitbang->setup_transfer;
9904f22a DB	266
	267	spin_lock_irqsave(&bitbang->lock, flags);
	268	bitbang->busy = 1;
	269	while (!list_empty(&bitbang->queue)) {
	270	struct spi_message *m;
	271	struct spi_device *spi;
	272	unsigned nsecs;
8275c642	273	struct spi_transfer *t = NULL;
9904f22a	274	unsigned tmp;
8275c642	275	unsigned cs_change;
9904f22a	276	int status;
b8f2e7bb	277	int do_setup = -1;
9904f22a DB	278
	279	m = container_of(bitbang->queue.next, struct spi_message,
	280	queue);
	281	list_del_init(&m->queue);
	282	spin_unlock_irqrestore(&bitbang->lock, flags);
	283
8275c642 VW	284	/* FIXME this is made-up ... the correct value is known to
	285	* word-at-a-time bitbang code, and presumably chipselect()
	286	* should enforce these requirements too?
	287	*/
	288	nsecs = 100;
9904f22a DB	289
9904f22a DB	290	spi = m->spi;
9904f22a	291	tmp = 0;
8275c642	292	cs_change = 1;
9904f22a DB	293	status = 0;
9904f22a DB	294
8275c642	295	list_for_each_entry (t, &m->transfers, transfer_list) {
9904f22a	296
529ba0d9 DB	297	/* override speed or wordsize? */
	298	if (t->speed_hz \|\| t->bits_per_word)
	299	do_setup = 1;
	300
	301	/* init (-1) or override (1) transfer params */
	302	if (do_setup != 0) {
4cff33f9 ID	303	if (!setup_transfer) {
	304	status = -ENOPROTOOPT;
	305	break;
	306	}
4cff33f9 ID	307	status = setup_transfer(spi, t);
	308	if (status < 0)
	309	break;
b8f2e7bb BN	310	if (do_setup == -1)
b8f2e7bb BN	311	do_setup = 0;
4cff33f9 ID	312	}
4cff33f9 ID	313
8275c642 VW	314	/* set up default clock polarity, and activate chip;
	315	* this implicitly updates clock and spi modes as
	316	* previously recorded for this device via setup().
	317	* (and also deselects any other chip that might be
	318	* selected ...)
	319	*/
	320	if (cs_change) {
	321	bitbang->chipselect(spi, BITBANG_CS_ACTIVE);
9904f22a DB	322	ndelay(nsecs);
9904f22a DB	323	}
8275c642	324	cs_change = t->cs_change;
9904f22a DB	325	if (!t->tx_buf && !t->rx_buf && t->len) {
	326	status = -EINVAL;
	327	break;
	328	}
	329
8275c642 VW	330	/* transfer data. the lower level code handles any
	331	* new dma mappings it needs. our caller always gave
	332	* us dma-safe buffers.
	333	*/
9904f22a	334	if (t->len) {
8275c642 VW	335	/* REVISIT dma API still needs a designated
8275c642 VW	336	* DMA_ADDR_INVALID; ~0 might be better.
9904f22a	337	*/
8275c642 VW	338	if (!m->is_dma_mapped)
8275c642 VW	339	t->rx_dma = t->tx_dma = 0;
9904f22a DB	340	status = bitbang->txrx_bufs(spi, t);
9904f22a DB	341	}
2cfb8ce8 JN	342	if (status > 0)
2cfb8ce8 JN	343	m->actual_length += status;
9904f22a	344	if (status != t->len) {
2cfb8ce8 JN	345	/* always report some kind of error */
	346	if (status >= 0)
	347	status = -EREMOTEIO;
9904f22a DB	348	break;
9904f22a DB	349	}
9904f22a DB	350	status = 0;
	351
	352	/* protocol tweaks before next transfer */
	353	if (t->delay_usecs)
	354	udelay(t->delay_usecs);
	355
8275c642	356	if (!cs_change)
9904f22a	357	continue;
8275c642 VW	358	if (t->transfer_list.next == &m->transfers)
8275c642 VW	359	break;
9904f22a	360
8275c642 VW	361	/* sometimes a short mid-message deselect of the chip
	362	* may be needed to terminate a mode or command
	363	*/
	364	ndelay(nsecs);
	365	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	366	ndelay(nsecs);
9904f22a DB	367	}
9904f22a DB	368
9904f22a DB	369	m->status = status;
	370	m->complete(m->context);
	371
8275c642 VW	372	/* normally deactivate chipselect ... unless no error and
	373	* cs_change has hinted that the next message will probably
	374	* be for this chip too.
	375	*/
	376	if (!(status == 0 && cs_change)) {
	377	ndelay(nsecs);
	378	bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
	379	ndelay(nsecs);
	380	}
9904f22a DB	381
	382	spin_lock_irqsave(&bitbang->lock, flags);
	383	}
	384	bitbang->busy = 0;
	385	spin_unlock_irqrestore(&bitbang->lock, flags);
	386	}
	387
	388	/**
	389	* spi_bitbang_transfer - default submit to transfer queue
	390	*/
	391	int spi_bitbang_transfer(struct spi_device spi, struct spi_message m)
	392	{
	393	struct spi_bitbang *bitbang;
	394	unsigned long flags;
1e316d75	395	int status = 0;
9904f22a DB	396
	397	m->actual_length = 0;
	398	m->status = -EINPROGRESS;
	399
	400	bitbang = spi_master_get_devdata(spi->master);
9904f22a DB	401
9904f22a DB	402	spin_lock_irqsave(&bitbang->lock, flags);
1e316d75 DB	403	if (!spi->max_speed_hz)
	404	status = -ENETDOWN;
	405	else {
	406	list_add_tail(&m->queue, &bitbang->queue);
	407	queue_work(bitbang->workqueue, &bitbang->work);
	408	}
9904f22a DB	409	spin_unlock_irqrestore(&bitbang->lock, flags);
9904f22a DB	410
1e316d75	411	return status;
9904f22a DB	412	}
	413	EXPORT_SYMBOL_GPL(spi_bitbang_transfer);
	414
	415	/----------------------------------------------------------------------/
	416
	417	/**
	418	* spi_bitbang_start - start up a polled/bitbanging SPI master driver
	419	* @bitbang: driver handle
	420	*
	421	* Caller should have zero-initialized all parts of the structure, and then
	422	* provided callbacks for chip selection and I/O loops. If the master has
	423	* a transfer method, its final step should call spi_bitbang_transfer; or,
	424	* that's the default if the transfer routine is not initialized. It should
	425	* also set up the bus number and number of chipselects.
	426	*
	427	* For i/o loops, provide callbacks either per-word (for bitbanging, or for
	428	* hardware that basically exposes a shift register) or per-spi_transfer
	429	* (which takes better advantage of hardware like fifos or DMA engines).
	430	*
7f8c7619 HPN	431	* Drivers using per-word I/O loops should use (or call) spi_bitbang_setup,
	432	* spi_bitbang_cleanup and spi_bitbang_setup_transfer to handle those spi
	433	* master methods. Those methods are the defaults if the bitbang->txrx_bufs
	434	* routine isn't initialized.
9904f22a DB	435	*
	436	* This routine registers the spi_master, which will process requests in a
	437	* dedicated task, keeping IRQs unblocked most of the time. To stop
	438	* processing those requests, call spi_bitbang_stop().
	439	*/
	440	int spi_bitbang_start(struct spi_bitbang *bitbang)
	441	{
	442	int status;
	443
	444	if (!bitbang->master \|\| !bitbang->chipselect)
	445	return -EINVAL;
	446
c4028958	447	INIT_WORK(&bitbang->work, bitbang_work);
9904f22a DB	448	spin_lock_init(&bitbang->lock);
	449	INIT_LIST_HEAD(&bitbang->queue);
	450
e7db06b5 DB	451	if (!bitbang->master->mode_bits)
	452	bitbang->master->mode_bits = SPI_CPOL \| SPI_CPHA \| bitbang->flags;
	453
9904f22a DB	454	if (!bitbang->master->transfer)
	455	bitbang->master->transfer = spi_bitbang_transfer;
	456	if (!bitbang->txrx_bufs) {
	457	bitbang->use_dma = 0;
	458	bitbang->txrx_bufs = spi_bitbang_bufs;
	459	if (!bitbang->master->setup) {
ff9f4771 KG	460	if (!bitbang->setup_transfer)
	461	bitbang->setup_transfer =
	462	spi_bitbang_setup_transfer;
9904f22a DB	463	bitbang->master->setup = spi_bitbang_setup;
	464	bitbang->master->cleanup = spi_bitbang_cleanup;
	465	}
	466	} else if (!bitbang->master->setup)
	467	return -EINVAL;
	468
	469	/* this task is the only thing to touch the SPI bits */
	470	bitbang->busy = 0;
	471	bitbang->workqueue = create_singlethread_workqueue(
35f74fca	472	dev_name(bitbang->master->dev.parent));
9904f22a DB	473	if (bitbang->workqueue == NULL) {
	474	status = -EBUSY;
	475	goto err1;
	476	}
	477
	478	/* driver may get busy before register() returns, especially
	479	* if someone registered boardinfo for devices
	480	*/
	481	status = spi_register_master(bitbang->master);
	482	if (status < 0)
	483	goto err2;
	484
	485	return status;
	486
	487	err2:
	488	destroy_workqueue(bitbang->workqueue);
	489	err1:
	490	return status;
	491	}
	492	EXPORT_SYMBOL_GPL(spi_bitbang_start);
	493
	494	/**
	495	* spi_bitbang_stop - stops the task providing spi communication
	496	*/
	497	int spi_bitbang_stop(struct spi_bitbang *bitbang)
	498	{
a836f585	499	spi_unregister_master(bitbang->master);
9904f22a	500
a836f585	501	WARN_ON(!list_empty(&bitbang->queue));
9904f22a DB	502
	503	destroy_workqueue(bitbang->workqueue);
	504
9904f22a DB	505	return 0;
	506	}
	507	EXPORT_SYMBOL_GPL(spi_bitbang_stop);
	508
	509	MODULE_LICENSE("GPL");
	510