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igmp: refine skb allocations
[net-next-2.6.git] / drivers / spi / davinci_spi.c
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358934a6
SP		 1/*
2 * Copyright (C) 2009 Texas Instruments.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/gpio.h>
22#include <linux/module.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25#include <linux/err.h>
26#include <linux/clk.h>
27#include <linux/dma-mapping.h>
28#include <linux/spi/spi.h>
29#include <linux/spi/spi_bitbang.h>
5a0e3ad6 30#include <linux/slab.h>
358934a6
SP		 31
32#include <mach/spi.h>
33#include <mach/edma.h>
34
35#define SPI_NO_RESOURCE ((resource_size_t)-1)
36
37#define SPI_MAX_CHIPSELECT 2
38
39#define CS_DEFAULT 0xFF
40
41#define SPI_BUFSIZ (SMP_CACHE_BYTES + 1)
42#define DAVINCI_DMA_DATA_TYPE_S8 0x01
43#define DAVINCI_DMA_DATA_TYPE_S16 0x02
44#define DAVINCI_DMA_DATA_TYPE_S32 0x04
45
46#define SPIFMT_PHASE_MASK BIT(16)
47#define SPIFMT_POLARITY_MASK BIT(17)
48#define SPIFMT_DISTIMER_MASK BIT(18)
49#define SPIFMT_SHIFTDIR_MASK BIT(20)
50#define SPIFMT_WAITENA_MASK BIT(21)
51#define SPIFMT_PARITYENA_MASK BIT(22)
52#define SPIFMT_ODD_PARITY_MASK BIT(23)
53#define SPIFMT_WDELAY_MASK 0x3f000000u
54#define SPIFMT_WDELAY_SHIFT 24
55#define SPIFMT_CHARLEN_MASK 0x0000001Fu
56
57/* SPIGCR1 */
58#define SPIGCR1_SPIENA_MASK 0x01000000u
59
60/* SPIPC0 */
61#define SPIPC0_DIFUN_MASK BIT(11) /* MISO */
62#define SPIPC0_DOFUN_MASK BIT(10) /* MOSI */
63#define SPIPC0_CLKFUN_MASK BIT(9) /* CLK */
64#define SPIPC0_SPIENA_MASK BIT(8) /* nREADY */
65#define SPIPC0_EN1FUN_MASK BIT(1)
66#define SPIPC0_EN0FUN_MASK BIT(0)
67
68#define SPIINT_MASKALL 0x0101035F
69#define SPI_INTLVL_1 0x000001FFu
70#define SPI_INTLVL_0 0x00000000u
71
72/* SPIDAT1 */
73#define SPIDAT1_CSHOLD_SHIFT 28
74#define SPIDAT1_CSNR_SHIFT 16
75#define SPIGCR1_CLKMOD_MASK BIT(1)
76#define SPIGCR1_MASTER_MASK BIT(0)
77#define SPIGCR1_LOOPBACK_MASK BIT(16)
78
79/* SPIBUF */
80#define SPIBUF_TXFULL_MASK BIT(29)
81#define SPIBUF_RXEMPTY_MASK BIT(31)
82
83/* Error Masks */
84#define SPIFLG_DLEN_ERR_MASK BIT(0)
85#define SPIFLG_TIMEOUT_MASK BIT(1)
86#define SPIFLG_PARERR_MASK BIT(2)
87#define SPIFLG_DESYNC_MASK BIT(3)
88#define SPIFLG_BITERR_MASK BIT(4)
89#define SPIFLG_OVRRUN_MASK BIT(6)
90#define SPIFLG_RX_INTR_MASK BIT(8)
91#define SPIFLG_TX_INTR_MASK BIT(9)
92#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
93#define SPIFLG_MASK (SPIFLG_DLEN_ERR_MASK \
94 | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
95 | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
96 | SPIFLG_OVRRUN_MASK | SPIFLG_RX_INTR_MASK \
97 | SPIFLG_TX_INTR_MASK \
98 | SPIFLG_BUF_INIT_ACTIVE_MASK)
99
100#define SPIINT_DLEN_ERR_INTR BIT(0)
101#define SPIINT_TIMEOUT_INTR BIT(1)
102#define SPIINT_PARERR_INTR BIT(2)
103#define SPIINT_DESYNC_INTR BIT(3)
104#define SPIINT_BITERR_INTR BIT(4)
105#define SPIINT_OVRRUN_INTR BIT(6)
106#define SPIINT_RX_INTR BIT(8)
107#define SPIINT_TX_INTR BIT(9)
108#define SPIINT_DMA_REQ_EN BIT(16)
109#define SPIINT_ENABLE_HIGHZ BIT(24)
110
111#define SPI_T2CDELAY_SHIFT 16
112#define SPI_C2TDELAY_SHIFT 24
113
114/* SPI Controller registers */
115#define SPIGCR0 0x00
116#define SPIGCR1 0x04
117#define SPIINT 0x08
118#define SPILVL 0x0c
119#define SPIFLG 0x10
120#define SPIPC0 0x14
121#define SPIPC1 0x18
122#define SPIPC2 0x1c
123#define SPIPC3 0x20
124#define SPIPC4 0x24
125#define SPIPC5 0x28
126#define SPIPC6 0x2c
127#define SPIPC7 0x30
128#define SPIPC8 0x34
129#define SPIDAT0 0x38
130#define SPIDAT1 0x3c
131#define SPIBUF 0x40
132#define SPIEMU 0x44
133#define SPIDELAY 0x48
134#define SPIDEF 0x4c
135#define SPIFMT0 0x50
136#define SPIFMT1 0x54
137#define SPIFMT2 0x58
138#define SPIFMT3 0x5c
139#define TGINTVEC0 0x60
140#define TGINTVEC1 0x64
141
142struct davinci_spi_slave {
143 u32 cmd_to_write;
144 u32 clk_ctrl_to_write;
145 u32 bytes_per_word;
146 u8 active_cs;
147};
148
149/* We have 2 DMA channels per CS, one for RX and one for TX */
150struct davinci_spi_dma {
151 int dma_tx_channel;
152 int dma_rx_channel;
153 int dma_tx_sync_dev;
154 int dma_rx_sync_dev;
155 enum dma_event_q eventq;
156
157 struct completion dma_tx_completion;
158 struct completion dma_rx_completion;
159};
160
161/* SPI Controller driver's private data. */
162struct davinci_spi {
163 struct spi_bitbang bitbang;
164 struct clk *clk;
165
166 u8 version;
167 resource_size_t pbase;
168 void __iomem *base;
169 size_t region_size;
170 u32 irq;
171 struct completion done;
172
173 const void *tx;
174 void *rx;
175 u8 *tmp_buf;
176 int count;
177 struct davinci_spi_dma *dma_channels;
178 struct davinci_spi_platform_data *pdata;
179
180 void (*get_rx)(u32 rx_data, struct davinci_spi *);
181 u32 (*get_tx)(struct davinci_spi *);
182
183 struct davinci_spi_slave slave[SPI_MAX_CHIPSELECT];
184};
185
186static unsigned use_dma;
187
188static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *davinci_spi)
189{
190 u8 *rx = davinci_spi->rx;
191
192 *rx++ = (u8)data;
193 davinci_spi->rx = rx;
194}
195
196static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *davinci_spi)
197{
198 u16 *rx = davinci_spi->rx;
199
200 *rx++ = (u16)data;
201 davinci_spi->rx = rx;
202}
203
204static u32 davinci_spi_tx_buf_u8(struct davinci_spi *davinci_spi)
205{
206 u32 data;
207 const u8 *tx = davinci_spi->tx;
208
209 data = *tx++;
210 davinci_spi->tx = tx;
211 return data;
212}
213
214static u32 davinci_spi_tx_buf_u16(struct davinci_spi *davinci_spi)
215{
216 u32 data;
217 const u16 *tx = davinci_spi->tx;
218
219 data = *tx++;
220 davinci_spi->tx = tx;
221 return data;
222}
223
224static inline void set_io_bits(void __iomem *addr, u32 bits)
225{
226 u32 v = ioread32(addr);
227
228 v |= bits;
229 iowrite32(v, addr);
230}
231
232static inline void clear_io_bits(void __iomem *addr, u32 bits)
233{
234 u32 v = ioread32(addr);
235
236 v &= ~bits;
237 iowrite32(v, addr);
238}
239
240static inline void set_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
241{
242 set_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
243}
244
245static inline void clear_fmt_bits(void __iomem *addr, u32 bits, int cs_num)
246{
247 clear_io_bits(addr + SPIFMT0 + (0x4 * cs_num), bits);
248}
249
250static void davinci_spi_set_dma_req(const struct spi_device *spi, int enable)
251{
252 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
253
254 if (enable)
255 set_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
256 else
257 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_DMA_REQ_EN);
258}
259
260/*
261 * Interface to control the chip select signal
262 */
263static void davinci_spi_chipselect(struct spi_device *spi, int value)
264{
265 struct davinci_spi *davinci_spi;
266 struct davinci_spi_platform_data *pdata;
267 u32 data1_reg_val = 0;
268
269 davinci_spi = spi_master_get_devdata(spi->master);
270 pdata = davinci_spi->pdata;
271
272 /*
273 * Board specific chip select logic decides the polarity and cs
274 * line for the controller
275 */
276 if (value == BITBANG_CS_INACTIVE) {
277 set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
278
279 data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
280 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
281
282 while ((ioread32(davinci_spi->base + SPIBUF)
283 & SPIBUF_RXEMPTY_MASK) == 0)
284 cpu_relax();
285 }
286}
287
288/**
289 * davinci_spi_setup_transfer - This functions will determine transfer method
290 * @spi: spi device on which data transfer to be done
291 * @t: spi transfer in which transfer info is filled
292 *
293 * This function determines data transfer method (8/16/32 bit transfer).
294 * It will also set the SPI Clock Control register according to
295 * SPI slave device freq.
296 */
297static int davinci_spi_setup_transfer(struct spi_device *spi,
298 struct spi_transfer *t)
299{
300
301 struct davinci_spi *davinci_spi;
302 struct davinci_spi_platform_data *pdata;
303 u8 bits_per_word = 0;
0c2a2ae3 304 u32 hz = 0, prescale = 0, clkspeed;
358934a6
SP		 305
306 davinci_spi = spi_master_get_devdata(spi->master);
307 pdata = davinci_spi->pdata;
308
309 if (t) {
310 bits_per_word = t->bits_per_word;
311 hz = t->speed_hz;
312 }
313
314 /* if bits_per_word is not set then set it default */
315 if (!bits_per_word)
316 bits_per_word = spi->bits_per_word;
317
318 /*
319 * Assign function pointer to appropriate transfer method
320 * 8bit, 16bit or 32bit transfer
321 */
322 if (bits_per_word <= 8 && bits_per_word >= 2) {
323 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
324 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
325 davinci_spi->slave[spi->chip_select].bytes_per_word = 1;
326 } else if (bits_per_word <= 16 && bits_per_word >= 2) {
327 davinci_spi->get_rx = davinci_spi_rx_buf_u16;
328 davinci_spi->get_tx = davinci_spi_tx_buf_u16;
329 davinci_spi->slave[spi->chip_select].bytes_per_word = 2;
330 } else
331 return -EINVAL;
332
333 if (!hz)
334 hz = spi->max_speed_hz;
335
336 clear_fmt_bits(davinci_spi->base, SPIFMT_CHARLEN_MASK,
337 spi->chip_select);
338 set_fmt_bits(davinci_spi->base, bits_per_word & 0x1f,
339 spi->chip_select);
340
0c2a2ae3
TK		 341 clkspeed = clk_get_rate(davinci_spi->clk);
342 if (hz > clkspeed / 2)
343 prescale = 1 << 8;
344 if (hz < clkspeed / 256)
345 prescale = 255 << 8;
346 if (!prescale)
347 prescale = ((clkspeed / hz - 1) << 8) & 0x0000ff00;
358934a6
SP		 348
349 clear_fmt_bits(davinci_spi->base, 0x0000ff00, spi->chip_select);
0c2a2ae3 350 set_fmt_bits(davinci_spi->base, prescale, spi->chip_select);
358934a6
SP		 351
352 return 0;
353}
354
355static void davinci_spi_dma_rx_callback(unsigned lch, u16 ch_status, void *data)
356{
357 struct spi_device *spi = (struct spi_device *)data;
358 struct davinci_spi *davinci_spi;
359 struct davinci_spi_dma *davinci_spi_dma;
360 struct davinci_spi_platform_data *pdata;
361
362 davinci_spi = spi_master_get_devdata(spi->master);
363 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
364 pdata = davinci_spi->pdata;
365
366 if (ch_status == DMA_COMPLETE)
367 edma_stop(davinci_spi_dma->dma_rx_channel);
368 else
369 edma_clean_channel(davinci_spi_dma->dma_rx_channel);
370
371 complete(&davinci_spi_dma->dma_rx_completion);
372 /* We must disable the DMA RX request */
373 davinci_spi_set_dma_req(spi, 0);
374}
375
376static void davinci_spi_dma_tx_callback(unsigned lch, u16 ch_status, void *data)
377{
378 struct spi_device *spi = (struct spi_device *)data;
379 struct davinci_spi *davinci_spi;
380 struct davinci_spi_dma *davinci_spi_dma;
381 struct davinci_spi_platform_data *pdata;
382
383 davinci_spi = spi_master_get_devdata(spi->master);
384 davinci_spi_dma = &(davinci_spi->dma_channels[spi->chip_select]);
385 pdata = davinci_spi->pdata;
386
387 if (ch_status == DMA_COMPLETE)
388 edma_stop(davinci_spi_dma->dma_tx_channel);
389 else
390 edma_clean_channel(davinci_spi_dma->dma_tx_channel);
391
392 complete(&davinci_spi_dma->dma_tx_completion);
393 /* We must disable the DMA TX request */
394 davinci_spi_set_dma_req(spi, 0);
395}
396
397static int davinci_spi_request_dma(struct spi_device *spi)
398{
399 struct davinci_spi *davinci_spi;
400 struct davinci_spi_dma *davinci_spi_dma;
401 struct davinci_spi_platform_data *pdata;
402 struct device *sdev;
403 int r;
404
405 davinci_spi = spi_master_get_devdata(spi->master);
406 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
407 pdata = davinci_spi->pdata;
408 sdev = davinci_spi->bitbang.master->dev.parent;
409
410 r = edma_alloc_channel(davinci_spi_dma->dma_rx_sync_dev,
411 davinci_spi_dma_rx_callback, spi,
412 davinci_spi_dma->eventq);
413 if (r < 0) {
414 dev_dbg(sdev, "Unable to request DMA channel for SPI RX\n");
415 return -EAGAIN;
416 }
417 davinci_spi_dma->dma_rx_channel = r;
418 r = edma_alloc_channel(davinci_spi_dma->dma_tx_sync_dev,
419 davinci_spi_dma_tx_callback, spi,
420 davinci_spi_dma->eventq);
421 if (r < 0) {
422 edma_free_channel(davinci_spi_dma->dma_rx_channel);
423 davinci_spi_dma->dma_rx_channel = -1;
424 dev_dbg(sdev, "Unable to request DMA channel for SPI TX\n");
425 return -EAGAIN;
426 }
427 davinci_spi_dma->dma_tx_channel = r;
428
429 return 0;
430}
431
432/**
433 * davinci_spi_setup - This functions will set default transfer method
434 * @spi: spi device on which data transfer to be done
435 *
436 * This functions sets the default transfer method.
437 */
438
439static int davinci_spi_setup(struct spi_device *spi)
440{
441 int retval;
442 struct davinci_spi *davinci_spi;
443 struct davinci_spi_dma *davinci_spi_dma;
444 struct device *sdev;
445
446 davinci_spi = spi_master_get_devdata(spi->master);
447 sdev = davinci_spi->bitbang.master->dev.parent;
448
449 /* if bits per word length is zero then set it default 8 */
450 if (!spi->bits_per_word)
451 spi->bits_per_word = 8;
452
453 davinci_spi->slave[spi->chip_select].cmd_to_write = 0;
454
455 if (use_dma && davinci_spi->dma_channels) {
456 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
457
458 if ((davinci_spi_dma->dma_rx_channel == -1)
459 || (davinci_spi_dma->dma_tx_channel == -1)) {
460 retval = davinci_spi_request_dma(spi);
461 if (retval < 0)
462 return retval;
463 }
464 }
465
466 /*
467 * SPI in DaVinci and DA8xx operate between
468 * 600 KHz and 50 MHz
469 */
470 if (spi->max_speed_hz < 600000 || spi->max_speed_hz > 50000000) {
471 dev_dbg(sdev, "Operating frequency is not in acceptable "
472 "range\n");
473 return -EINVAL;
474 }
475
476 /*
477 * Set up SPIFMTn register, unique to this chipselect.
478 *
479 * NOTE: we could do all of these with one write. Also, some
480 * of the "version 2" features are found in chips that don't
481 * support all of them...
482 */
483 if (spi->mode & SPI_LSB_FIRST)
484 set_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
485 spi->chip_select);
486 else
487 clear_fmt_bits(davinci_spi->base, SPIFMT_SHIFTDIR_MASK,
488 spi->chip_select);
489
490 if (spi->mode & SPI_CPOL)
491 set_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
492 spi->chip_select);
493 else
494 clear_fmt_bits(davinci_spi->base, SPIFMT_POLARITY_MASK,
495 spi->chip_select);
496
497 if (!(spi->mode & SPI_CPHA))
498 set_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
499 spi->chip_select);
500 else
501 clear_fmt_bits(davinci_spi->base, SPIFMT_PHASE_MASK,
502 spi->chip_select);
503
504 /*
505 * Version 1 hardware supports two basic SPI modes:
506 * - Standard SPI mode uses 4 pins, with chipselect
507 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
508 * (distinct from SPI_3WIRE, with just one data wire;
509 * or similar variants without MOSI or without MISO)
510 *
511 * Version 2 hardware supports an optional handshaking signal,
512 * so it can support two more modes:
513 * - 5 pin SPI variant is standard SPI plus SPI_READY
514 * - 4 pin with enable is (SPI_READY | SPI_NO_CS)
515 */
516
517 if (davinci_spi->version == SPI_VERSION_2) {
518 clear_fmt_bits(davinci_spi->base, SPIFMT_WDELAY_MASK,
519 spi->chip_select);
520 set_fmt_bits(davinci_spi->base,
521 (davinci_spi->pdata->wdelay
522 << SPIFMT_WDELAY_SHIFT)
523 & SPIFMT_WDELAY_MASK,
524 spi->chip_select);
525
526 if (davinci_spi->pdata->odd_parity)
527 set_fmt_bits(davinci_spi->base,
528 SPIFMT_ODD_PARITY_MASK,
529 spi->chip_select);
530 else
531 clear_fmt_bits(davinci_spi->base,
532 SPIFMT_ODD_PARITY_MASK,
533 spi->chip_select);
534
535 if (davinci_spi->pdata->parity_enable)
536 set_fmt_bits(davinci_spi->base,
537 SPIFMT_PARITYENA_MASK,
538 spi->chip_select);
539 else
540 clear_fmt_bits(davinci_spi->base,
541 SPIFMT_PARITYENA_MASK,
542 spi->chip_select);
543
544 if (davinci_spi->pdata->wait_enable)
545 set_fmt_bits(davinci_spi->base,
546 SPIFMT_WAITENA_MASK,
547 spi->chip_select);
548 else
549 clear_fmt_bits(davinci_spi->base,
550 SPIFMT_WAITENA_MASK,
551 spi->chip_select);
552
553 if (davinci_spi->pdata->timer_disable)
554 set_fmt_bits(davinci_spi->base,
555 SPIFMT_DISTIMER_MASK,
556 spi->chip_select);
557 else
558 clear_fmt_bits(davinci_spi->base,
559 SPIFMT_DISTIMER_MASK,
560 spi->chip_select);
561 }
562
563 retval = davinci_spi_setup_transfer(spi, NULL);
564
565 return retval;
566}
567
568static void davinci_spi_cleanup(struct spi_device *spi)
569{
570 struct davinci_spi *davinci_spi = spi_master_get_devdata(spi->master);
571 struct davinci_spi_dma *davinci_spi_dma;
572
573 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
574
575 if (use_dma && davinci_spi->dma_channels) {
576 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
577
578 if ((davinci_spi_dma->dma_rx_channel != -1)
579 && (davinci_spi_dma->dma_tx_channel != -1)) {
580 edma_free_channel(davinci_spi_dma->dma_tx_channel);
581 edma_free_channel(davinci_spi_dma->dma_rx_channel);
582 }
583 }
584}
585
586static int davinci_spi_bufs_prep(struct spi_device *spi,
587 struct davinci_spi *davinci_spi)
588{
589 int op_mode = 0;
590
591 /*
592 * REVISIT unless devices disagree about SPI_LOOP or
593 * SPI_READY (SPI_NO_CS only allows one device!), this
594 * should not need to be done before each message...
595 * optimize for both flags staying cleared.
596 */
597
598 op_mode = SPIPC0_DIFUN_MASK
599 | SPIPC0_DOFUN_MASK
600 | SPIPC0_CLKFUN_MASK;
601 if (!(spi->mode & SPI_NO_CS))
602 op_mode |= 1 << spi->chip_select;
603 if (spi->mode & SPI_READY)
604 op_mode |= SPIPC0_SPIENA_MASK;
605
606 iowrite32(op_mode, davinci_spi->base + SPIPC0);
607
608 if (spi->mode & SPI_LOOP)
609 set_io_bits(davinci_spi->base + SPIGCR1,
610 SPIGCR1_LOOPBACK_MASK);
611 else
612 clear_io_bits(davinci_spi->base + SPIGCR1,
613 SPIGCR1_LOOPBACK_MASK);
614
615 return 0;
616}
617
618static int davinci_spi_check_error(struct davinci_spi *davinci_spi,
619 int int_status)
620{
621 struct device *sdev = davinci_spi->bitbang.master->dev.parent;
622
623 if (int_status & SPIFLG_TIMEOUT_MASK) {
624 dev_dbg(sdev, "SPI Time-out Error\n");
625 return -ETIMEDOUT;
626 }
627 if (int_status & SPIFLG_DESYNC_MASK) {
628 dev_dbg(sdev, "SPI Desynchronization Error\n");
629 return -EIO;
630 }
631 if (int_status & SPIFLG_BITERR_MASK) {
632 dev_dbg(sdev, "SPI Bit error\n");
633 return -EIO;
634 }
635
636 if (davinci_spi->version == SPI_VERSION_2) {
637 if (int_status & SPIFLG_DLEN_ERR_MASK) {
638 dev_dbg(sdev, "SPI Data Length Error\n");
639 return -EIO;
640 }
641 if (int_status & SPIFLG_PARERR_MASK) {
642 dev_dbg(sdev, "SPI Parity Error\n");
643 return -EIO;
644 }
645 if (int_status & SPIFLG_OVRRUN_MASK) {
646 dev_dbg(sdev, "SPI Data Overrun error\n");
647 return -EIO;
648 }
649 if (int_status & SPIFLG_TX_INTR_MASK) {
650 dev_dbg(sdev, "SPI TX intr bit set\n");
651 return -EIO;
652 }
653 if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
654 dev_dbg(sdev, "SPI Buffer Init Active\n");
655 return -EBUSY;
656 }
657 }
658
659 return 0;
660}
661
662/**
663 * davinci_spi_bufs - functions which will handle transfer data
664 * @spi: spi device on which data transfer to be done
665 * @t: spi transfer in which transfer info is filled
666 *
667 * This function will put data to be transferred into data register
668 * of SPI controller and then wait until the completion will be marked
669 * by the IRQ Handler.
670 */
671static int davinci_spi_bufs_pio(struct spi_device *spi, struct spi_transfer *t)
672{
673 struct davinci_spi *davinci_spi;
674 int int_status, count, ret;
675 u8 conv, tmp;
676 u32 tx_data, data1_reg_val;
677 u32 buf_val, flg_val;
678 struct davinci_spi_platform_data *pdata;
679
680 davinci_spi = spi_master_get_devdata(spi->master);
681 pdata = davinci_spi->pdata;
682
683 davinci_spi->tx = t->tx_buf;
684 davinci_spi->rx = t->rx_buf;
685
686 /* convert len to words based on bits_per_word */
687 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
688 davinci_spi->count = t->len / conv;
689
690 INIT_COMPLETION(davinci_spi->done);
691
692 ret = davinci_spi_bufs_prep(spi, davinci_spi);
693 if (ret)
694 return ret;
695
696 /* Enable SPI */
697 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
698
699 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
700 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
701 davinci_spi->base + SPIDELAY);
702
703 count = davinci_spi->count;
704 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
705 tmp = ~(0x1 << spi->chip_select);
706
707 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
708
709 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
710
711 while ((ioread32(davinci_spi->base + SPIBUF)
712 & SPIBUF_RXEMPTY_MASK) == 0)
713 cpu_relax();
714
715 /* Determine the command to execute READ or WRITE */
716 if (t->tx_buf) {
717 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
718
719 while (1) {
720 tx_data = davinci_spi->get_tx(davinci_spi);
721
722 data1_reg_val &= ~(0xFFFF);
723 data1_reg_val |= (0xFFFF & tx_data);
724
725 buf_val = ioread32(davinci_spi->base + SPIBUF);
726 if ((buf_val & SPIBUF_TXFULL_MASK) == 0) {
727 iowrite32(data1_reg_val,
728 davinci_spi->base + SPIDAT1);
729
730 count--;
731 }
732 while (ioread32(davinci_spi->base + SPIBUF)
733 & SPIBUF_RXEMPTY_MASK)
734 cpu_relax();
735
736 /* getting the returned byte */
737 if (t->rx_buf) {
738 buf_val = ioread32(davinci_spi->base + SPIBUF);
739 davinci_spi->get_rx(buf_val, davinci_spi);
740 }
741 if (count <= 0)
742 break;
743 }
744 } else {
745 if (pdata->poll_mode) {
746 while (1) {
747 /* keeps the serial clock going */
748 if ((ioread32(davinci_spi->base + SPIBUF)
749 & SPIBUF_TXFULL_MASK) == 0)
750 iowrite32(data1_reg_val,
751 davinci_spi->base + SPIDAT1);
752
753 while (ioread32(davinci_spi->base + SPIBUF) &
754 SPIBUF_RXEMPTY_MASK)
755 cpu_relax();
756
757 flg_val = ioread32(davinci_spi->base + SPIFLG);
758 buf_val = ioread32(davinci_spi->base + SPIBUF);
759
760 davinci_spi->get_rx(buf_val, davinci_spi);
761
762 count--;
763 if (count <= 0)
764 break;
765 }
766 } else { /* Receive in Interrupt mode */
767 int i;
768
769 for (i = 0; i < davinci_spi->count; i++) {
770 set_io_bits(davinci_spi->base + SPIINT,
771 SPIINT_BITERR_INTR
772 | SPIINT_OVRRUN_INTR
773 | SPIINT_RX_INTR);
774
775 iowrite32(data1_reg_val,
776 davinci_spi->base + SPIDAT1);
777
778 while (ioread32(davinci_spi->base + SPIINT) &
779 SPIINT_RX_INTR)
780 cpu_relax();
781 }
782 iowrite32((data1_reg_val & 0x0ffcffff),
783 davinci_spi->base + SPIDAT1);
784 }
785 }
786
787 /*
788 * Check for bit error, desync error,parity error,timeout error and
789 * receive overflow errors
790 */
791 int_status = ioread32(davinci_spi->base + SPIFLG);
792
793 ret = davinci_spi_check_error(davinci_spi, int_status);
794 if (ret != 0)
795 return ret;
796
797 /* SPI Framework maintains the count only in bytes so convert back */
798 davinci_spi->count *= conv;
799
800 return t->len;
801}
802
803#define DAVINCI_DMA_DATA_TYPE_S8 0x01
804#define DAVINCI_DMA_DATA_TYPE_S16 0x02
805#define DAVINCI_DMA_DATA_TYPE_S32 0x04
806
807static int davinci_spi_bufs_dma(struct spi_device *spi, struct spi_transfer *t)
808{
809 struct davinci_spi *davinci_spi;
810 int int_status = 0;
811 int count, temp_count;
812 u8 conv = 1;
813 u8 tmp;
814 u32 data1_reg_val;
815 struct davinci_spi_dma *davinci_spi_dma;
816 int word_len, data_type, ret;
817 unsigned long tx_reg, rx_reg;
818 struct davinci_spi_platform_data *pdata;
819 struct device *sdev;
820
821 davinci_spi = spi_master_get_devdata(spi->master);
822 pdata = davinci_spi->pdata;
823 sdev = davinci_spi->bitbang.master->dev.parent;
824
825 davinci_spi_dma = &davinci_spi->dma_channels[spi->chip_select];
826
827 tx_reg = (unsigned long)davinci_spi->pbase + SPIDAT1;
828 rx_reg = (unsigned long)davinci_spi->pbase + SPIBUF;
829
830 davinci_spi->tx = t->tx_buf;
831 davinci_spi->rx = t->rx_buf;
832
833 /* convert len to words based on bits_per_word */
834 conv = davinci_spi->slave[spi->chip_select].bytes_per_word;
835 davinci_spi->count = t->len / conv;
836
837 INIT_COMPLETION(davinci_spi->done);
838
839 init_completion(&davinci_spi_dma->dma_rx_completion);
840 init_completion(&davinci_spi_dma->dma_tx_completion);
841
842 word_len = conv * 8;
843
844 if (word_len <= 8)
845 data_type = DAVINCI_DMA_DATA_TYPE_S8;
846 else if (word_len <= 16)
847 data_type = DAVINCI_DMA_DATA_TYPE_S16;
848 else if (word_len <= 32)
849 data_type = DAVINCI_DMA_DATA_TYPE_S32;
850 else
851 return -EINVAL;
852
853 ret = davinci_spi_bufs_prep(spi, davinci_spi);
854 if (ret)
855 return ret;
856
857 /* Put delay val if required */
858 iowrite32(0 | (pdata->c2tdelay << SPI_C2TDELAY_SHIFT) |
859 (pdata->t2cdelay << SPI_T2CDELAY_SHIFT),
860 davinci_spi->base + SPIDELAY);
861
862 count = davinci_spi->count; /* the number of elements */
863 data1_reg_val = pdata->cs_hold << SPIDAT1_CSHOLD_SHIFT;
864
865 /* CS default = 0xFF */
866 tmp = ~(0x1 << spi->chip_select);
867
868 clear_io_bits(davinci_spi->base + SPIDEF, ~tmp);
869
870 data1_reg_val |= tmp << SPIDAT1_CSNR_SHIFT;
871
872 /* disable all interrupts for dma transfers */
873 clear_io_bits(davinci_spi->base + SPIINT, SPIINT_MASKALL);
874 /* Disable SPI to write configuration bits in SPIDAT */
875 clear_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
876 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
877 /* Enable SPI */
878 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
879
880 while ((ioread32(davinci_spi->base + SPIBUF)
881 & SPIBUF_RXEMPTY_MASK) == 0)
882 cpu_relax();
883
884
885 if (t->tx_buf) {
886 t->tx_dma = dma_map_single(&spi->dev, (void *)t->tx_buf, count,
887 DMA_TO_DEVICE);
888 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
889 dev_dbg(sdev, "Unable to DMA map a %d bytes"
890 " TX buffer\n", count);
891 return -ENOMEM;
892 }
893 temp_count = count;
894 } else {
895 /* We need TX clocking for RX transaction */
896 t->tx_dma = dma_map_single(&spi->dev,
897 (void *)davinci_spi->tmp_buf, count + 1,
898 DMA_TO_DEVICE);
899 if (dma_mapping_error(&spi->dev, t->tx_dma)) {
900 dev_dbg(sdev, "Unable to DMA map a %d bytes"
901 " TX tmp buffer\n", count);
902 return -ENOMEM;
903 }
904 temp_count = count + 1;
905 }
906
907 edma_set_transfer_params(davinci_spi_dma->dma_tx_channel,
908 data_type, temp_count, 1, 0, ASYNC);
909 edma_set_dest(davinci_spi_dma->dma_tx_channel, tx_reg, INCR, W8BIT);
910 edma_set_src(davinci_spi_dma->dma_tx_channel, t->tx_dma, INCR, W8BIT);
911 edma_set_src_index(davinci_spi_dma->dma_tx_channel, data_type, 0);
912 edma_set_dest_index(davinci_spi_dma->dma_tx_channel, 0, 0);
913
914 if (t->rx_buf) {
915 /* initiate transaction */
916 iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
917
918 t->rx_dma = dma_map_single(&spi->dev, (void *)t->rx_buf, count,
919 DMA_FROM_DEVICE);
920 if (dma_mapping_error(&spi->dev, t->rx_dma)) {
921 dev_dbg(sdev, "Couldn't DMA map a %d bytes RX buffer\n",
922 count);
923 if (t->tx_buf != NULL)
924 dma_unmap_single(NULL, t->tx_dma,
925 count, DMA_TO_DEVICE);
926 return -ENOMEM;
927 }
928 edma_set_transfer_params(davinci_spi_dma->dma_rx_channel,
929 data_type, count, 1, 0, ASYNC);
930 edma_set_src(davinci_spi_dma->dma_rx_channel,
931 rx_reg, INCR, W8BIT);
932 edma_set_dest(davinci_spi_dma->dma_rx_channel,
933 t->rx_dma, INCR, W8BIT);
934 edma_set_src_index(davinci_spi_dma->dma_rx_channel, 0, 0);
935 edma_set_dest_index(davinci_spi_dma->dma_rx_channel,
936 data_type, 0);
937 }
938
939 if ((t->tx_buf) || (t->rx_buf))
940 edma_start(davinci_spi_dma->dma_tx_channel);
941
942 if (t->rx_buf)
943 edma_start(davinci_spi_dma->dma_rx_channel);
944
945 if ((t->rx_buf) || (t->tx_buf))
946 davinci_spi_set_dma_req(spi, 1);
947
948 if (t->tx_buf)
949 wait_for_completion_interruptible(
950 &davinci_spi_dma->dma_tx_completion);
951
952 if (t->rx_buf)
953 wait_for_completion_interruptible(
954 &davinci_spi_dma->dma_rx_completion);
955
956 dma_unmap_single(NULL, t->tx_dma, temp_count, DMA_TO_DEVICE);
957
958 if (t->rx_buf)
959 dma_unmap_single(NULL, t->rx_dma, count, DMA_FROM_DEVICE);
960
961 /*
962 * Check for bit error, desync error,parity error,timeout error and
963 * receive overflow errors
964 */
965 int_status = ioread32(davinci_spi->base + SPIFLG);
966
967 ret = davinci_spi_check_error(davinci_spi, int_status);
968 if (ret != 0)
969 return ret;
970
971 /* SPI Framework maintains the count only in bytes so convert back */
972 davinci_spi->count *= conv;
973
974 return t->len;
975}
976
977/**
978 * davinci_spi_irq - IRQ handler for DaVinci SPI
979 * @irq: IRQ number for this SPI Master
980 * @context_data: structure for SPI Master controller davinci_spi
981 */
982static irqreturn_t davinci_spi_irq(s32 irq, void *context_data)
983{
984 struct davinci_spi *davinci_spi = context_data;
985 u32 int_status, rx_data = 0;
986 irqreturn_t ret = IRQ_NONE;
987
988 int_status = ioread32(davinci_spi->base + SPIFLG);
989
990 while ((int_status & SPIFLG_RX_INTR_MASK)) {
991 if (likely(int_status & SPIFLG_RX_INTR_MASK)) {
992 ret = IRQ_HANDLED;
993
994 rx_data = ioread32(davinci_spi->base + SPIBUF);
995 davinci_spi->get_rx(rx_data, davinci_spi);
996
997 /* Disable Receive Interrupt */
998 iowrite32(~(SPIINT_RX_INTR | SPIINT_TX_INTR),
999 davinci_spi->base + SPIINT);
1000 } else
1001 (void)davinci_spi_check_error(davinci_spi, int_status);
1002
1003 int_status = ioread32(davinci_spi->base + SPIFLG);
1004 }
1005
1006 return ret;
1007}
1008
1009/**
1010 * davinci_spi_probe - probe function for SPI Master Controller
1011 * @pdev: platform_device structure which contains plateform specific data
1012 */
1013static int davinci_spi_probe(struct platform_device *pdev)
1014{
1015 struct spi_master *master;
1016 struct davinci_spi *davinci_spi;
1017 struct davinci_spi_platform_data *pdata;
1018 struct resource *r, *mem;
1019 resource_size_t dma_rx_chan = SPI_NO_RESOURCE;
1020 resource_size_t dma_tx_chan = SPI_NO_RESOURCE;
1021 resource_size_t dma_eventq = SPI_NO_RESOURCE;
1022 int i = 0, ret = 0;
1023
1024 pdata = pdev->dev.platform_data;
1025 if (pdata == NULL) {
1026 ret = -ENODEV;
1027 goto err;
1028 }
1029
1030 master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
1031 if (master == NULL) {
1032 ret = -ENOMEM;
1033 goto err;
1034 }
1035
1036 dev_set_drvdata(&pdev->dev, master);
1037
1038 davinci_spi = spi_master_get_devdata(master);
1039 if (davinci_spi == NULL) {
1040 ret = -ENOENT;
1041 goto free_master;
1042 }
1043
1044 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1045 if (r == NULL) {
1046 ret = -ENOENT;
1047 goto free_master;
1048 }
1049
1050 davinci_spi->pbase = r->start;
1051 davinci_spi->region_size = resource_size(r);
1052 davinci_spi->pdata = pdata;
1053
1054 mem = request_mem_region(r->start, davinci_spi->region_size,
1055 pdev->name);
1056 if (mem == NULL) {
1057 ret = -EBUSY;
1058 goto free_master;
1059 }
1060
1061 davinci_spi->base = (struct davinci_spi_reg __iomem *)
1062 ioremap(r->start, davinci_spi->region_size);
1063 if (davinci_spi->base == NULL) {
1064 ret = -ENOMEM;
1065 goto release_region;
1066 }
1067
1068 davinci_spi->irq = platform_get_irq(pdev, 0);
1069 if (davinci_spi->irq <= 0) {
1070 ret = -EINVAL;
1071 goto unmap_io;
1072 }
1073
1074 ret = request_irq(davinci_spi->irq, davinci_spi_irq, IRQF_DISABLED,
1075 dev_name(&pdev->dev), davinci_spi);
1076 if (ret)
1077 goto unmap_io;
1078
1079 /* Allocate tmp_buf for tx_buf */
1080 davinci_spi->tmp_buf = kzalloc(SPI_BUFSIZ, GFP_KERNEL);
1081 if (davinci_spi->tmp_buf == NULL) {
1082 ret = -ENOMEM;
1083 goto irq_free;
1084 }
1085
1086 davinci_spi->bitbang.master = spi_master_get(master);
1087 if (davinci_spi->bitbang.master == NULL) {
1088 ret = -ENODEV;
1089 goto free_tmp_buf;
1090 }
1091
1092 davinci_spi->clk = clk_get(&pdev->dev, NULL);
1093 if (IS_ERR(davinci_spi->clk)) {
1094 ret = -ENODEV;
1095 goto put_master;
1096 }
1097 clk_enable(davinci_spi->clk);
1098
1099
1100 master->bus_num = pdev->id;
1101 master->num_chipselect = pdata->num_chipselect;
1102 master->setup = davinci_spi_setup;
1103 master->cleanup = davinci_spi_cleanup;
1104
1105 davinci_spi->bitbang.chipselect = davinci_spi_chipselect;
1106 davinci_spi->bitbang.setup_transfer = davinci_spi_setup_transfer;
1107
1108 davinci_spi->version = pdata->version;
1109 use_dma = pdata->use_dma;
1110
1111 davinci_spi->bitbang.flags = SPI_NO_CS | SPI_LSB_FIRST | SPI_LOOP;
1112 if (davinci_spi->version == SPI_VERSION_2)
1113 davinci_spi->bitbang.flags |= SPI_READY;
1114
1115 if (use_dma) {
1116 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1117 if (r)
1118 dma_rx_chan = r->start;
1119 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1120 if (r)
1121 dma_tx_chan = r->start;
1122 r = platform_get_resource(pdev, IORESOURCE_DMA, 2);
1123 if (r)
1124 dma_eventq = r->start;
1125 }
1126
1127 if (!use_dma ||
1128 dma_rx_chan == SPI_NO_RESOURCE ||
1129 dma_tx_chan == SPI_NO_RESOURCE ||
1130 dma_eventq == SPI_NO_RESOURCE) {
1131 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_pio;
1132 use_dma = 0;
1133 } else {
1134 davinci_spi->bitbang.txrx_bufs = davinci_spi_bufs_dma;
1135 davinci_spi->dma_channels = kzalloc(master->num_chipselect
1136 * sizeof(struct davinci_spi_dma), GFP_KERNEL);
1137 if (davinci_spi->dma_channels == NULL) {
1138 ret = -ENOMEM;
1139 goto free_clk;
1140 }
1141
1142 for (i = 0; i < master->num_chipselect; i++) {
1143 davinci_spi->dma_channels[i].dma_rx_channel = -1;
1144 davinci_spi->dma_channels[i].dma_rx_sync_dev =
1145 dma_rx_chan;
1146 davinci_spi->dma_channels[i].dma_tx_channel = -1;
1147 davinci_spi->dma_channels[i].dma_tx_sync_dev =
1148 dma_tx_chan;
1149 davinci_spi->dma_channels[i].eventq = dma_eventq;
1150 }
1151 dev_info(&pdev->dev, "DaVinci SPI driver in EDMA mode\n"
1152 "Using RX channel = %d , TX channel = %d and "
1153 "event queue = %d", dma_rx_chan, dma_tx_chan,
1154 dma_eventq);
1155 }
1156
1157 davinci_spi->get_rx = davinci_spi_rx_buf_u8;
1158 davinci_spi->get_tx = davinci_spi_tx_buf_u8;
1159
1160 init_completion(&davinci_spi->done);
1161
1162 /* Reset In/OUT SPI module */
1163 iowrite32(0, davinci_spi->base + SPIGCR0);
1164 udelay(100);
1165 iowrite32(1, davinci_spi->base + SPIGCR0);
1166
1167 /* Clock internal */
1168 if (davinci_spi->pdata->clk_internal)
1169 set_io_bits(davinci_spi->base + SPIGCR1,
1170 SPIGCR1_CLKMOD_MASK);
1171 else
1172 clear_io_bits(davinci_spi->base + SPIGCR1,
1173 SPIGCR1_CLKMOD_MASK);
1174
1175 /* master mode default */
1176 set_io_bits(davinci_spi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
1177
1178 if (davinci_spi->pdata->intr_level)
1179 iowrite32(SPI_INTLVL_1, davinci_spi->base + SPILVL);
1180 else
1181 iowrite32(SPI_INTLVL_0, davinci_spi->base + SPILVL);
1182
1183 ret = spi_bitbang_start(&davinci_spi->bitbang);
1184 if (ret)
1185 goto free_clk;
1186
1187 dev_info(&pdev->dev, "Controller at 0x%p \n", davinci_spi->base);
1188
1189 if (!pdata->poll_mode)
1190 dev_info(&pdev->dev, "Operating in interrupt mode"
1191 " using IRQ %d\n", davinci_spi->irq);
1192
1193 return ret;
1194
1195free_clk:
1196 clk_disable(davinci_spi->clk);
1197 clk_put(davinci_spi->clk);
1198put_master:
1199 spi_master_put(master);
1200free_tmp_buf:
1201 kfree(davinci_spi->tmp_buf);
1202irq_free:
1203 free_irq(davinci_spi->irq, davinci_spi);
1204unmap_io:
1205 iounmap(davinci_spi->base);
1206release_region:
1207 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1208free_master:
1209 kfree(master);
1210err:
1211 return ret;
1212}
1213
1214/**
1215 * davinci_spi_remove - remove function for SPI Master Controller
1216 * @pdev: platform_device structure which contains plateform specific data
1217 *
1218 * This function will do the reverse action of davinci_spi_probe function
1219 * It will free the IRQ and SPI controller's memory region.
1220 * It will also call spi_bitbang_stop to destroy the work queue which was
1221 * created by spi_bitbang_start.
1222 */
1223static int __exit davinci_spi_remove(struct platform_device *pdev)
1224{
1225 struct davinci_spi *davinci_spi;
1226 struct spi_master *master;
1227
1228 master = dev_get_drvdata(&pdev->dev);
1229 davinci_spi = spi_master_get_devdata(master);
1230
1231 spi_bitbang_stop(&davinci_spi->bitbang);
1232
1233 clk_disable(davinci_spi->clk);
1234 clk_put(davinci_spi->clk);
1235 spi_master_put(master);
1236 kfree(davinci_spi->tmp_buf);
1237 free_irq(davinci_spi->irq, davinci_spi);
1238 iounmap(davinci_spi->base);
1239 release_mem_region(davinci_spi->pbase, davinci_spi->region_size);
1240
1241 return 0;
1242}
1243
1244static struct platform_driver davinci_spi_driver = {
1245 .driver.name = "spi_davinci",
1246 .remove = __exit_p(davinci_spi_remove),
1247};
1248
1249static int __init davinci_spi_init(void)
1250{
1251 return platform_driver_probe(&davinci_spi_driver, davinci_spi_probe);
1252}
1253module_init(davinci_spi_init);
1254
1255static void __exit davinci_spi_exit(void)
1256{
1257 platform_driver_unregister(&davinci_spi_driver);
1258}
1259module_exit(davinci_spi_exit);
1260
1261MODULE_DESCRIPTION("TI DaVinci SPI Master Controller Driver");
1262MODULE_LICENSE("GPL");
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