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Merge branch 'tmpreg' into devel
[net-next-2.6.git] / drivers / spi / amba-pl022.c
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b43d65f7
LW		 1/*
2 * drivers/spi/amba-pl022.c
3 *
4 * A driver for the ARM PL022 PrimeCell SSP/SPI bus master.
5 *
6 * Copyright (C) 2008-2009 ST-Ericsson AB
7 * Copyright (C) 2006 STMicroelectronics Pvt. Ltd.
8 *
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 *
11 * Initial version inspired by:
12 * linux-2.6.17-rc3-mm1/drivers/spi/pxa2xx_spi.c
13 * Initial adoption to PL022 by:
14 * Sachin Verma <sachin.verma@st.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27/*
28 * TODO:
29 * - add timeout on polled transfers
30 * - add generic DMA framework support
31 */
32
33#include <linux/init.h>
34#include <linux/module.h>
35#include <linux/device.h>
36#include <linux/ioport.h>
37#include <linux/errno.h>
38#include <linux/interrupt.h>
39#include <linux/spi/spi.h>
40#include <linux/workqueue.h>
b43d65f7
LW		 41#include <linux/delay.h>
42#include <linux/clk.h>
43#include <linux/err.h>
44#include <linux/amba/bus.h>
45#include <linux/amba/pl022.h>
46#include <linux/io.h>
b43d65f7
LW		 47
48/*
49 * This macro is used to define some register default values.
50 * reg is masked with mask, the OR:ed with an (again masked)
51 * val shifted sb steps to the left.
52 */
53#define SSP_WRITE_BITS(reg, val, mask, sb) \
54 ((reg) = (((reg) & ~(mask)) | (((val)<<(sb)) & (mask))))
55
56/*
57 * This macro is also used to define some default values.
58 * It will just shift val by sb steps to the left and mask
59 * the result with mask.
60 */
61#define GEN_MASK_BITS(val, mask, sb) \
62 (((val)<<(sb)) & (mask))
63
64#define DRIVE_TX 0
65#define DO_NOT_DRIVE_TX 1
66
67#define DO_NOT_QUEUE_DMA 0
68#define QUEUE_DMA 1
69
70#define RX_TRANSFER 1
71#define TX_TRANSFER 2
72
73/*
74 * Macros to access SSP Registers with their offsets
75 */
76#define SSP_CR0(r) (r + 0x000)
77#define SSP_CR1(r) (r + 0x004)
78#define SSP_DR(r) (r + 0x008)
79#define SSP_SR(r) (r + 0x00C)
80#define SSP_CPSR(r) (r + 0x010)
81#define SSP_IMSC(r) (r + 0x014)
82#define SSP_RIS(r) (r + 0x018)
83#define SSP_MIS(r) (r + 0x01C)
84#define SSP_ICR(r) (r + 0x020)
85#define SSP_DMACR(r) (r + 0x024)
86#define SSP_ITCR(r) (r + 0x080)
87#define SSP_ITIP(r) (r + 0x084)
88#define SSP_ITOP(r) (r + 0x088)
89#define SSP_TDR(r) (r + 0x08C)
90
91#define SSP_PID0(r) (r + 0xFE0)
92#define SSP_PID1(r) (r + 0xFE4)
93#define SSP_PID2(r) (r + 0xFE8)
94#define SSP_PID3(r) (r + 0xFEC)
95
96#define SSP_CID0(r) (r + 0xFF0)
97#define SSP_CID1(r) (r + 0xFF4)
98#define SSP_CID2(r) (r + 0xFF8)
99#define SSP_CID3(r) (r + 0xFFC)
100
101/*
102 * SSP Control Register 0 - SSP_CR0
103 */
104#define SSP_CR0_MASK_DSS (0x1FUL << 0)
105#define SSP_CR0_MASK_HALFDUP (0x1UL << 5)
106#define SSP_CR0_MASK_SPO (0x1UL << 6)
107#define SSP_CR0_MASK_SPH (0x1UL << 7)
108#define SSP_CR0_MASK_SCR (0xFFUL << 8)
109#define SSP_CR0_MASK_CSS (0x1FUL << 16)
110#define SSP_CR0_MASK_FRF (0x3UL << 21)
111
112/*
113 * SSP Control Register 0 - SSP_CR1
114 */
115#define SSP_CR1_MASK_LBM (0x1UL << 0)
116#define SSP_CR1_MASK_SSE (0x1UL << 1)
117#define SSP_CR1_MASK_MS (0x1UL << 2)
118#define SSP_CR1_MASK_SOD (0x1UL << 3)
119#define SSP_CR1_MASK_RENDN (0x1UL << 4)
120#define SSP_CR1_MASK_TENDN (0x1UL << 5)
121#define SSP_CR1_MASK_MWAIT (0x1UL << 6)
122#define SSP_CR1_MASK_RXIFLSEL (0x7UL << 7)
123#define SSP_CR1_MASK_TXIFLSEL (0x7UL << 10)
124
125/*
126 * SSP Data Register - SSP_DR
127 */
128#define SSP_DR_MASK_DATA 0xFFFFFFFF
129
130/*
131 * SSP Status Register - SSP_SR
132 */
133#define SSP_SR_MASK_TFE (0x1UL << 0) /* Transmit FIFO empty */
134#define SSP_SR_MASK_TNF (0x1UL << 1) /* Transmit FIFO not full */
135#define SSP_SR_MASK_RNE (0x1UL << 2) /* Receive FIFO not empty */
136#define SSP_SR_MASK_RFF (0x1UL << 3) /* Receive FIFO full */
137#define SSP_SR_MASK_BSY (0x1UL << 4) /* Busy Flag */
138
139/*
140 * SSP Clock Prescale Register - SSP_CPSR
141 */
142#define SSP_CPSR_MASK_CPSDVSR (0xFFUL << 0)
143
144/*
145 * SSP Interrupt Mask Set/Clear Register - SSP_IMSC
146 */
147#define SSP_IMSC_MASK_RORIM (0x1UL << 0) /* Receive Overrun Interrupt mask */
148#define SSP_IMSC_MASK_RTIM (0x1UL << 1) /* Receive timeout Interrupt mask */
149#define SSP_IMSC_MASK_RXIM (0x1UL << 2) /* Receive FIFO Interrupt mask */
150#define SSP_IMSC_MASK_TXIM (0x1UL << 3) /* Transmit FIFO Interrupt mask */
151
152/*
153 * SSP Raw Interrupt Status Register - SSP_RIS
154 */
155/* Receive Overrun Raw Interrupt status */
156#define SSP_RIS_MASK_RORRIS (0x1UL << 0)
157/* Receive Timeout Raw Interrupt status */
158#define SSP_RIS_MASK_RTRIS (0x1UL << 1)
159/* Receive FIFO Raw Interrupt status */
160#define SSP_RIS_MASK_RXRIS (0x1UL << 2)
161/* Transmit FIFO Raw Interrupt status */
162#define SSP_RIS_MASK_TXRIS (0x1UL << 3)
163
164/*
165 * SSP Masked Interrupt Status Register - SSP_MIS
166 */
167/* Receive Overrun Masked Interrupt status */
168#define SSP_MIS_MASK_RORMIS (0x1UL << 0)
169/* Receive Timeout Masked Interrupt status */
170#define SSP_MIS_MASK_RTMIS (0x1UL << 1)
171/* Receive FIFO Masked Interrupt status */
172#define SSP_MIS_MASK_RXMIS (0x1UL << 2)
173/* Transmit FIFO Masked Interrupt status */
174#define SSP_MIS_MASK_TXMIS (0x1UL << 3)
175
176/*
177 * SSP Interrupt Clear Register - SSP_ICR
178 */
179/* Receive Overrun Raw Clear Interrupt bit */
180#define SSP_ICR_MASK_RORIC (0x1UL << 0)
181/* Receive Timeout Clear Interrupt bit */
182#define SSP_ICR_MASK_RTIC (0x1UL << 1)
183
184/*
185 * SSP DMA Control Register - SSP_DMACR
186 */
187/* Receive DMA Enable bit */
188#define SSP_DMACR_MASK_RXDMAE (0x1UL << 0)
189/* Transmit DMA Enable bit */
190#define SSP_DMACR_MASK_TXDMAE (0x1UL << 1)
191
192/*
193 * SSP Integration Test control Register - SSP_ITCR
194 */
195#define SSP_ITCR_MASK_ITEN (0x1UL << 0)
196#define SSP_ITCR_MASK_TESTFIFO (0x1UL << 1)
197
198/*
199 * SSP Integration Test Input Register - SSP_ITIP
200 */
201#define ITIP_MASK_SSPRXD (0x1UL << 0)
202#define ITIP_MASK_SSPFSSIN (0x1UL << 1)
203#define ITIP_MASK_SSPCLKIN (0x1UL << 2)
204#define ITIP_MASK_RXDMAC (0x1UL << 3)
205#define ITIP_MASK_TXDMAC (0x1UL << 4)
206#define ITIP_MASK_SSPTXDIN (0x1UL << 5)
207
208/*
209 * SSP Integration Test output Register - SSP_ITOP
210 */
211#define ITOP_MASK_SSPTXD (0x1UL << 0)
212#define ITOP_MASK_SSPFSSOUT (0x1UL << 1)
213#define ITOP_MASK_SSPCLKOUT (0x1UL << 2)
214#define ITOP_MASK_SSPOEn (0x1UL << 3)
215#define ITOP_MASK_SSPCTLOEn (0x1UL << 4)
216#define ITOP_MASK_RORINTR (0x1UL << 5)
217#define ITOP_MASK_RTINTR (0x1UL << 6)
218#define ITOP_MASK_RXINTR (0x1UL << 7)
219#define ITOP_MASK_TXINTR (0x1UL << 8)
220#define ITOP_MASK_INTR (0x1UL << 9)
221#define ITOP_MASK_RXDMABREQ (0x1UL << 10)
222#define ITOP_MASK_RXDMASREQ (0x1UL << 11)
223#define ITOP_MASK_TXDMABREQ (0x1UL << 12)
224#define ITOP_MASK_TXDMASREQ (0x1UL << 13)
225
226/*
227 * SSP Test Data Register - SSP_TDR
228 */
229#define TDR_MASK_TESTDATA (0xFFFFFFFF)
230
231/*
232 * Message State
233 * we use the spi_message.state (void *) pointer to
234 * hold a single state value, that's why all this
235 * (void *) casting is done here.
236 */
237#define STATE_START ((void *) 0)
238#define STATE_RUNNING ((void *) 1)
239#define STATE_DONE ((void *) 2)
240#define STATE_ERROR ((void *) -1)
241
242/*
243 * Queue State
244 */
245#define QUEUE_RUNNING (0)
246#define QUEUE_STOPPED (1)
247/*
248 * SSP State - Whether Enabled or Disabled
249 */
250#define SSP_DISABLED (0)
251#define SSP_ENABLED (1)
252
253/*
254 * SSP DMA State - Whether DMA Enabled or Disabled
255 */
256#define SSP_DMA_DISABLED (0)
257#define SSP_DMA_ENABLED (1)
258
259/*
260 * SSP Clock Defaults
261 */
262#define NMDK_SSP_DEFAULT_CLKRATE 0x2
263#define NMDK_SSP_DEFAULT_PRESCALE 0x40
264
265/*
266 * SSP Clock Parameter ranges
267 */
268#define CPSDVR_MIN 0x02
269#define CPSDVR_MAX 0xFE
270#define SCR_MIN 0x00
271#define SCR_MAX 0xFF
272
273/*
274 * SSP Interrupt related Macros
275 */
276#define DEFAULT_SSP_REG_IMSC 0x0UL
277#define DISABLE_ALL_INTERRUPTS DEFAULT_SSP_REG_IMSC
278#define ENABLE_ALL_INTERRUPTS (~DEFAULT_SSP_REG_IMSC)
279
280#define CLEAR_ALL_INTERRUPTS 0x3
281
282
283/*
284 * The type of reading going on on this chip
285 */
286enum ssp_reading {
287 READING_NULL,
288 READING_U8,
289 READING_U16,
290 READING_U32
291};
292
293/**
294 * The type of writing going on on this chip
295 */
296enum ssp_writing {
297 WRITING_NULL,
298 WRITING_U8,
299 WRITING_U16,
300 WRITING_U32
301};
302
303/**
304 * struct vendor_data - vendor-specific config parameters
305 * for PL022 derivates
306 * @fifodepth: depth of FIFOs (both)
307 * @max_bpw: maximum number of bits per word
308 * @unidir: supports unidirection transfers
309 */
310struct vendor_data {
311 int fifodepth;
312 int max_bpw;
313 bool unidir;
314};
315
316/**
317 * struct pl022 - This is the private SSP driver data structure
318 * @adev: AMBA device model hookup
319 * @phybase: The physical memory where the SSP device resides
320 * @virtbase: The virtual memory where the SSP is mapped
321 * @master: SPI framework hookup
322 * @master_info: controller-specific data from machine setup
323 * @regs: SSP controller register's virtual address
324 * @pump_messages: Work struct for scheduling work to the workqueue
325 * @lock: spinlock to syncronise access to driver data
326 * @workqueue: a workqueue on which any spi_message request is queued
327 * @busy: workqueue is busy
328 * @run: workqueue is running
329 * @pump_transfers: Tasklet used in Interrupt Transfer mode
330 * @cur_msg: Pointer to current spi_message being processed
331 * @cur_transfer: Pointer to current spi_transfer
332 * @cur_chip: pointer to current clients chip(assigned from controller_state)
333 * @tx: current position in TX buffer to be read
334 * @tx_end: end position in TX buffer to be read
335 * @rx: current position in RX buffer to be written
336 * @rx_end: end position in RX buffer to be written
337 * @readingtype: the type of read currently going on
338 * @writingtype: the type or write currently going on
339 */
340struct pl022 {
341 struct amba_device *adev;
342 struct vendor_data *vendor;
343 resource_size_t phybase;
344 void __iomem *virtbase;
345 struct clk *clk;
346 struct spi_master *master;
347 struct pl022_ssp_controller *master_info;
348 /* Driver message queue */
349 struct workqueue_struct *workqueue;
350 struct work_struct pump_messages;
351 spinlock_t queue_lock;
352 struct list_head queue;
353 int busy;
354 int run;
355 /* Message transfer pump */
356 struct tasklet_struct pump_transfers;
357 struct spi_message *cur_msg;
358 struct spi_transfer *cur_transfer;
359 struct chip_data *cur_chip;
360 void *tx;
361 void *tx_end;
362 void *rx;
363 void *rx_end;
364 enum ssp_reading read;
365 enum ssp_writing write;
fc05475f 366 u32 exp_fifo_level;
b43d65f7
LW		 367};
368
369/**
370 * struct chip_data - To maintain runtime state of SSP for each client chip
371 * @cr0: Value of control register CR0 of SSP
372 * @cr1: Value of control register CR1 of SSP
373 * @dmacr: Value of DMA control Register of SSP
374 * @cpsr: Value of Clock prescale register
375 * @n_bytes: how many bytes(power of 2) reqd for a given data width of client
376 * @enable_dma: Whether to enable DMA or not
377 * @write: function ptr to be used to write when doing xfer for this chip
378 * @read: function ptr to be used to read when doing xfer for this chip
379 * @cs_control: chip select callback provided by chip
380 * @xfer_type: polling/interrupt/DMA
381 *
382 * Runtime state of the SSP controller, maintained per chip,
383 * This would be set according to the current message that would be served
384 */
385struct chip_data {
386 u16 cr0;
387 u16 cr1;
388 u16 dmacr;
389 u16 cpsr;
390 u8 n_bytes;
391 u8 enable_dma:1;
392 enum ssp_reading read;
393 enum ssp_writing write;
394 void (*cs_control) (u32 command);
395 int xfer_type;
396};
397
398/**
399 * null_cs_control - Dummy chip select function
400 * @command: select/delect the chip
401 *
402 * If no chip select function is provided by client this is used as dummy
403 * chip select
404 */
405static void null_cs_control(u32 command)
406{
407 pr_debug("pl022: dummy chip select control, CS=0x%x\n", command);
408}
409
410/**
411 * giveback - current spi_message is over, schedule next message and call
412 * callback of this message. Assumes that caller already
413 * set message->status; dma and pio irqs are blocked
414 * @pl022: SSP driver private data structure
415 */
416static void giveback(struct pl022 *pl022)
417{
418 struct spi_transfer *last_transfer;
419 unsigned long flags;
420 struct spi_message *msg;
421 void (*curr_cs_control) (u32 command);
422
423 /*
424 * This local reference to the chip select function
425 * is needed because we set curr_chip to NULL
426 * as a step toward termininating the message.
427 */
428 curr_cs_control = pl022->cur_chip->cs_control;
429 spin_lock_irqsave(&pl022->queue_lock, flags);
430 msg = pl022->cur_msg;
431 pl022->cur_msg = NULL;
432 pl022->cur_transfer = NULL;
433 pl022->cur_chip = NULL;
434 queue_work(pl022->workqueue, &pl022->pump_messages);
435 spin_unlock_irqrestore(&pl022->queue_lock, flags);
436
437 last_transfer = list_entry(msg->transfers.prev,
438 struct spi_transfer,
439 transfer_list);
440
441 /* Delay if requested before any change in chip select */
442 if (last_transfer->delay_usecs)
443 /*
444 * FIXME: This runs in interrupt context.
445 * Is this really smart?
446 */
447 udelay(last_transfer->delay_usecs);
448
449 /*
450 * Drop chip select UNLESS cs_change is true or we are returning
451 * a message with an error, or next message is for another chip
452 */
453 if (!last_transfer->cs_change)
454 curr_cs_control(SSP_CHIP_DESELECT);
455 else {
456 struct spi_message *next_msg;
457
458 /* Holding of cs was hinted, but we need to make sure
459 * the next message is for the same chip. Don't waste
460 * time with the following tests unless this was hinted.
461 *
462 * We cannot postpone this until pump_messages, because
463 * after calling msg->complete (below) the driver that
464 * sent the current message could be unloaded, which
465 * could invalidate the cs_control() callback...
466 */
467
468 /* get a pointer to the next message, if any */
469 spin_lock_irqsave(&pl022->queue_lock, flags);
470 if (list_empty(&pl022->queue))
471 next_msg = NULL;
472 else
473 next_msg = list_entry(pl022->queue.next,
474 struct spi_message, queue);
475 spin_unlock_irqrestore(&pl022->queue_lock, flags);
476
477 /* see if the next and current messages point
478 * to the same chip
479 */
480 if (next_msg && next_msg->spi != msg->spi)
481 next_msg = NULL;
482 if (!next_msg || msg->state == STATE_ERROR)
483 curr_cs_control(SSP_CHIP_DESELECT);
484 }
485 msg->state = NULL;
486 if (msg->complete)
487 msg->complete(msg->context);
488 /* This message is completed, so let's turn off the clock! */
489 clk_disable(pl022->clk);
490}
491
492/**
493 * flush - flush the FIFO to reach a clean state
494 * @pl022: SSP driver private data structure
495 */
496static int flush(struct pl022 *pl022)
497{
498 unsigned long limit = loops_per_jiffy << 1;
499
500 dev_dbg(&pl022->adev->dev, "flush\n");
501 do {
502 while (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
503 readw(SSP_DR(pl022->virtbase));
504 } while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_BSY) && limit--);
fc05475f
LW		 505
506 pl022->exp_fifo_level = 0;
507
b43d65f7
LW		 508 return limit;
509}
510
511/**
512 * restore_state - Load configuration of current chip
513 * @pl022: SSP driver private data structure
514 */
515static void restore_state(struct pl022 *pl022)
516{
517 struct chip_data *chip = pl022->cur_chip;
518
519 writew(chip->cr0, SSP_CR0(pl022->virtbase));
520 writew(chip->cr1, SSP_CR1(pl022->virtbase));
521 writew(chip->dmacr, SSP_DMACR(pl022->virtbase));
522 writew(chip->cpsr, SSP_CPSR(pl022->virtbase));
523 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
524 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
525}
526
527/**
528 * load_ssp_default_config - Load default configuration for SSP
529 * @pl022: SSP driver private data structure
530 */
531
532/*
533 * Default SSP Register Values
534 */
535#define DEFAULT_SSP_REG_CR0 ( \
536 GEN_MASK_BITS(SSP_DATA_BITS_12, SSP_CR0_MASK_DSS, 0) | \
537 GEN_MASK_BITS(SSP_MICROWIRE_CHANNEL_FULL_DUPLEX, SSP_CR0_MASK_HALFDUP, 5) | \
538 GEN_MASK_BITS(SSP_CLK_POL_IDLE_LOW, SSP_CR0_MASK_SPO, 6) | \
ee2b805c 539 GEN_MASK_BITS(SSP_CLK_SECOND_EDGE, SSP_CR0_MASK_SPH, 7) | \
b43d65f7
LW		 540 GEN_MASK_BITS(NMDK_SSP_DEFAULT_CLKRATE, SSP_CR0_MASK_SCR, 8) | \
541 GEN_MASK_BITS(SSP_BITS_8, SSP_CR0_MASK_CSS, 16) | \
542 GEN_MASK_BITS(SSP_INTERFACE_MOTOROLA_SPI, SSP_CR0_MASK_FRF, 21) \
543)
544
545#define DEFAULT_SSP_REG_CR1 ( \
546 GEN_MASK_BITS(LOOPBACK_DISABLED, SSP_CR1_MASK_LBM, 0) | \
547 GEN_MASK_BITS(SSP_DISABLED, SSP_CR1_MASK_SSE, 1) | \
548 GEN_MASK_BITS(SSP_MASTER, SSP_CR1_MASK_MS, 2) | \
549 GEN_MASK_BITS(DO_NOT_DRIVE_TX, SSP_CR1_MASK_SOD, 3) | \
550 GEN_MASK_BITS(SSP_RX_MSB, SSP_CR1_MASK_RENDN, 4) | \
551 GEN_MASK_BITS(SSP_TX_MSB, SSP_CR1_MASK_TENDN, 5) | \
552 GEN_MASK_BITS(SSP_MWIRE_WAIT_ZERO, SSP_CR1_MASK_MWAIT, 6) |\
553 GEN_MASK_BITS(SSP_RX_1_OR_MORE_ELEM, SSP_CR1_MASK_RXIFLSEL, 7) | \
554 GEN_MASK_BITS(SSP_TX_1_OR_MORE_EMPTY_LOC, SSP_CR1_MASK_TXIFLSEL, 10) \
555)
556
557#define DEFAULT_SSP_REG_CPSR ( \
558 GEN_MASK_BITS(NMDK_SSP_DEFAULT_PRESCALE, SSP_CPSR_MASK_CPSDVSR, 0) \
559)
560
561#define DEFAULT_SSP_REG_DMACR (\
562 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_RXDMAE, 0) | \
563 GEN_MASK_BITS(SSP_DMA_DISABLED, SSP_DMACR_MASK_TXDMAE, 1) \
564)
565
566
567static void load_ssp_default_config(struct pl022 *pl022)
568{
569 writew(DEFAULT_SSP_REG_CR0, SSP_CR0(pl022->virtbase));
570 writew(DEFAULT_SSP_REG_CR1, SSP_CR1(pl022->virtbase));
571 writew(DEFAULT_SSP_REG_DMACR, SSP_DMACR(pl022->virtbase));
572 writew(DEFAULT_SSP_REG_CPSR, SSP_CPSR(pl022->virtbase));
573 writew(DISABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
574 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
575}
576
577/**
578 * This will write to TX and read from RX according to the parameters
579 * set in pl022.
580 */
581static void readwriter(struct pl022 *pl022)
582{
583
584 /*
585 * The FIFO depth is different inbetween primecell variants.
586 * I believe filling in too much in the FIFO might cause
587 * errons in 8bit wide transfers on ARM variants (just 8 words
588 * FIFO, means only 8x8 = 64 bits in FIFO) at least.
589 *
fc05475f
LW		 590 * To prevent this issue, the TX FIFO is only filled to the
591 * unused RX FIFO fill length, regardless of what the TX
592 * FIFO status flag indicates.
b43d65f7
LW		 593 */
594 dev_dbg(&pl022->adev->dev,
595 "%s, rx: %p, rxend: %p, tx: %p, txend: %p\n",
596 __func__, pl022->rx, pl022->rx_end, pl022->tx, pl022->tx_end);
597
598 /* Read as much as you can */
599 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
600 && (pl022->rx < pl022->rx_end)) {
601 switch (pl022->read) {
602 case READING_NULL:
603 readw(SSP_DR(pl022->virtbase));
604 break;
605 case READING_U8:
606 *(u8 *) (pl022->rx) =
607 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
608 break;
609 case READING_U16:
610 *(u16 *) (pl022->rx) =
611 (u16) readw(SSP_DR(pl022->virtbase));
612 break;
613 case READING_U32:
614 *(u32 *) (pl022->rx) =
615 readl(SSP_DR(pl022->virtbase));
616 break;
617 }
618 pl022->rx += (pl022->cur_chip->n_bytes);
fc05475f 619 pl022->exp_fifo_level--;
b43d65f7
LW		 620 }
621 /*
fc05475f 622 * Write as much as possible up to the RX FIFO size
b43d65f7 623 */
fc05475f 624 while ((pl022->exp_fifo_level < pl022->vendor->fifodepth)
b43d65f7
LW		 625 && (pl022->tx < pl022->tx_end)) {
626 switch (pl022->write) {
627 case WRITING_NULL:
628 writew(0x0, SSP_DR(pl022->virtbase));
629 break;
630 case WRITING_U8:
631 writew(*(u8 *) (pl022->tx), SSP_DR(pl022->virtbase));
632 break;
633 case WRITING_U16:
634 writew((*(u16 *) (pl022->tx)), SSP_DR(pl022->virtbase));
635 break;
636 case WRITING_U32:
637 writel(*(u32 *) (pl022->tx), SSP_DR(pl022->virtbase));
638 break;
639 }
640 pl022->tx += (pl022->cur_chip->n_bytes);
fc05475f 641 pl022->exp_fifo_level++;
b43d65f7
LW		 642 /*
643 * This inner reader takes care of things appearing in the RX
644 * FIFO as we're transmitting. This will happen a lot since the
645 * clock starts running when you put things into the TX FIFO,
646 * and then things are continously clocked into the RX FIFO.
647 */
648 while ((readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RNE)
649 && (pl022->rx < pl022->rx_end)) {
650 switch (pl022->read) {
651 case READING_NULL:
652 readw(SSP_DR(pl022->virtbase));
653 break;
654 case READING_U8:
655 *(u8 *) (pl022->rx) =
656 readw(SSP_DR(pl022->virtbase)) & 0xFFU;
657 break;
658 case READING_U16:
659 *(u16 *) (pl022->rx) =
660 (u16) readw(SSP_DR(pl022->virtbase));
661 break;
662 case READING_U32:
663 *(u32 *) (pl022->rx) =
664 readl(SSP_DR(pl022->virtbase));
665 break;
666 }
667 pl022->rx += (pl022->cur_chip->n_bytes);
fc05475f 668 pl022->exp_fifo_level--;
b43d65f7
LW		 669 }
670 }
671 /*
672 * When we exit here the TX FIFO should be full and the RX FIFO
673 * should be empty
674 */
675}
676
677
678/**
679 * next_transfer - Move to the Next transfer in the current spi message
680 * @pl022: SSP driver private data structure
681 *
682 * This function moves though the linked list of spi transfers in the
683 * current spi message and returns with the state of current spi
684 * message i.e whether its last transfer is done(STATE_DONE) or
685 * Next transfer is ready(STATE_RUNNING)
686 */
687static void *next_transfer(struct pl022 *pl022)
688{
689 struct spi_message *msg = pl022->cur_msg;
690 struct spi_transfer *trans = pl022->cur_transfer;
691
692 /* Move to next transfer */
693 if (trans->transfer_list.next != &msg->transfers) {
694 pl022->cur_transfer =
695 list_entry(trans->transfer_list.next,
696 struct spi_transfer, transfer_list);
697 return STATE_RUNNING;
698 }
699 return STATE_DONE;
700}
701/**
702 * pl022_interrupt_handler - Interrupt handler for SSP controller
703 *
704 * This function handles interrupts generated for an interrupt based transfer.
705 * If a receive overrun (ROR) interrupt is there then we disable SSP, flag the
706 * current message's state as STATE_ERROR and schedule the tasklet
707 * pump_transfers which will do the postprocessing of the current message by
708 * calling giveback(). Otherwise it reads data from RX FIFO till there is no
709 * more data, and writes data in TX FIFO till it is not full. If we complete
710 * the transfer we move to the next transfer and schedule the tasklet.
711 */
712static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
713{
714 struct pl022 *pl022 = dev_id;
715 struct spi_message *msg = pl022->cur_msg;
716 u16 irq_status = 0;
717 u16 flag = 0;
718
719 if (unlikely(!msg)) {
720 dev_err(&pl022->adev->dev,
721 "bad message state in interrupt handler");
722 /* Never fail */
723 return IRQ_HANDLED;
724 }
725
726 /* Read the Interrupt Status Register */
727 irq_status = readw(SSP_MIS(pl022->virtbase));
728
729 if (unlikely(!irq_status))
730 return IRQ_NONE;
731
732 /* This handles the error code interrupts */
733 if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
734 /*
735 * Overrun interrupt - bail out since our Data has been
736 * corrupted
737 */
738 dev_err(&pl022->adev->dev,
739 "FIFO overrun\n");
740 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
741 dev_err(&pl022->adev->dev,
742 "RXFIFO is full\n");
743 if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_TNF)
744 dev_err(&pl022->adev->dev,
745 "TXFIFO is full\n");
746
747 /*
748 * Disable and clear interrupts, disable SSP,
749 * mark message with bad status so it can be
750 * retried.
751 */
752 writew(DISABLE_ALL_INTERRUPTS,
753 SSP_IMSC(pl022->virtbase));
754 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
755 writew((readw(SSP_CR1(pl022->virtbase)) &
756 (~SSP_CR1_MASK_SSE)), SSP_CR1(pl022->virtbase));
757 msg->state = STATE_ERROR;
758
759 /* Schedule message queue handler */
760 tasklet_schedule(&pl022->pump_transfers);
761 return IRQ_HANDLED;
762 }
763
764 readwriter(pl022);
765
766 if ((pl022->tx == pl022->tx_end) && (flag == 0)) {
767 flag = 1;
768 /* Disable Transmit interrupt */
769 writew(readw(SSP_IMSC(pl022->virtbase)) &
770 (~SSP_IMSC_MASK_TXIM),
771 SSP_IMSC(pl022->virtbase));
772 }
773
774 /*
775 * Since all transactions must write as much as shall be read,
776 * we can conclude the entire transaction once RX is complete.
777 * At this point, all TX will always be finished.
778 */
779 if (pl022->rx >= pl022->rx_end) {
780 writew(DISABLE_ALL_INTERRUPTS,
781 SSP_IMSC(pl022->virtbase));
782 writew(CLEAR_ALL_INTERRUPTS, SSP_ICR(pl022->virtbase));
783 if (unlikely(pl022->rx > pl022->rx_end)) {
784 dev_warn(&pl022->adev->dev, "read %u surplus "
785 "bytes (did you request an odd "
786 "number of bytes on a 16bit bus?)\n",
787 (u32) (pl022->rx - pl022->rx_end));
788 }
789 /* Update total bytes transfered */
790 msg->actual_length += pl022->cur_transfer->len;
791 if (pl022->cur_transfer->cs_change)
792 pl022->cur_chip->
793 cs_control(SSP_CHIP_DESELECT);
794 /* Move to next transfer */
795 msg->state = next_transfer(pl022);
796 tasklet_schedule(&pl022->pump_transfers);
797 return IRQ_HANDLED;
798 }
799
800 return IRQ_HANDLED;
801}
802
803/**
804 * This sets up the pointers to memory for the next message to
805 * send out on the SPI bus.
806 */
807static int set_up_next_transfer(struct pl022 *pl022,
808 struct spi_transfer *transfer)
809{
810 int residue;
811
812 /* Sanity check the message for this bus width */
813 residue = pl022->cur_transfer->len % pl022->cur_chip->n_bytes;
814 if (unlikely(residue != 0)) {
815 dev_err(&pl022->adev->dev,
816 "message of %u bytes to transmit but the current "
817 "chip bus has a data width of %u bytes!\n",
818 pl022->cur_transfer->len,
819 pl022->cur_chip->n_bytes);
820 dev_err(&pl022->adev->dev, "skipping this message\n");
821 return -EIO;
822 }
823 pl022->tx = (void *)transfer->tx_buf;
824 pl022->tx_end = pl022->tx + pl022->cur_transfer->len;
825 pl022->rx = (void *)transfer->rx_buf;
826 pl022->rx_end = pl022->rx + pl022->cur_transfer->len;
827 pl022->write =
828 pl022->tx ? pl022->cur_chip->write : WRITING_NULL;
829 pl022->read = pl022->rx ? pl022->cur_chip->read : READING_NULL;
830 return 0;
831}
832
833/**
834 * pump_transfers - Tasklet function which schedules next interrupt transfer
835 * when running in interrupt transfer mode.
836 * @data: SSP driver private data structure
837 *
838 */
839static void pump_transfers(unsigned long data)
840{
841 struct pl022 *pl022 = (struct pl022 *) data;
842 struct spi_message *message = NULL;
843 struct spi_transfer *transfer = NULL;
844 struct spi_transfer *previous = NULL;
845
846 /* Get current state information */
847 message = pl022->cur_msg;
848 transfer = pl022->cur_transfer;
849
850 /* Handle for abort */
851 if (message->state == STATE_ERROR) {
852 message->status = -EIO;
853 giveback(pl022);
854 return;
855 }
856
857 /* Handle end of message */
858 if (message->state == STATE_DONE) {
859 message->status = 0;
860 giveback(pl022);
861 return;
862 }
863
864 /* Delay if requested at end of transfer before CS change */
865 if (message->state == STATE_RUNNING) {
866 previous = list_entry(transfer->transfer_list.prev,
867 struct spi_transfer,
868 transfer_list);
869 if (previous->delay_usecs)
870 /*
871 * FIXME: This runs in interrupt context.
872 * Is this really smart?
873 */
874 udelay(previous->delay_usecs);
875
876 /* Drop chip select only if cs_change is requested */
877 if (previous->cs_change)
878 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
879 } else {
880 /* STATE_START */
881 message->state = STATE_RUNNING;
882 }
883
884 if (set_up_next_transfer(pl022, transfer)) {
885 message->state = STATE_ERROR;
886 message->status = -EIO;
887 giveback(pl022);
888 return;
889 }
890 /* Flush the FIFOs and let's go! */
891 flush(pl022);
892 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
893}
894
895/**
896 * NOT IMPLEMENTED
897 * configure_dma - It configures the DMA pipes for DMA transfers
898 * @data: SSP driver's private data structure
899 *
900 */
901static int configure_dma(void *data)
902{
903 struct pl022 *pl022 = data;
904 dev_dbg(&pl022->adev->dev, "configure DMA\n");
905 return -ENOTSUPP;
906}
907
908/**
909 * do_dma_transfer - It handles transfers of the current message
910 * if it is DMA xfer.
911 * NOT FULLY IMPLEMENTED
912 * @data: SSP driver's private data structure
913 */
914static void do_dma_transfer(void *data)
915{
916 struct pl022 *pl022 = data;
917
918 if (configure_dma(data)) {
919 dev_dbg(&pl022->adev->dev, "configuration of DMA Failed!\n");
920 goto err_config_dma;
921 }
922
923 /* TODO: Implememt DMA setup of pipes here */
924
925 /* Enable target chip, set up transfer */
926 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
927 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
928 /* Error path */
929 pl022->cur_msg->state = STATE_ERROR;
930 pl022->cur_msg->status = -EIO;
931 giveback(pl022);
932 return;
933 }
934 /* Enable SSP */
935 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
936 SSP_CR1(pl022->virtbase));
937
938 /* TODO: Enable the DMA transfer here */
939 return;
940
941 err_config_dma:
942 pl022->cur_msg->state = STATE_ERROR;
943 pl022->cur_msg->status = -EIO;
944 giveback(pl022);
945 return;
946}
947
948static void do_interrupt_transfer(void *data)
949{
950 struct pl022 *pl022 = data;
951
952 /* Enable target chip */
953 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
954 if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
955 /* Error path */
956 pl022->cur_msg->state = STATE_ERROR;
957 pl022->cur_msg->status = -EIO;
958 giveback(pl022);
959 return;
960 }
961 /* Enable SSP, turn on interrupts */
962 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
963 SSP_CR1(pl022->virtbase));
964 writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
965}
966
967static void do_polling_transfer(void *data)
968{
969 struct pl022 *pl022 = data;
970 struct spi_message *message = NULL;
971 struct spi_transfer *transfer = NULL;
972 struct spi_transfer *previous = NULL;
973 struct chip_data *chip;
974
975 chip = pl022->cur_chip;
976 message = pl022->cur_msg;
977
978 while (message->state != STATE_DONE) {
979 /* Handle for abort */
980 if (message->state == STATE_ERROR)
981 break;
982 transfer = pl022->cur_transfer;
983
984 /* Delay if requested at end of transfer */
985 if (message->state == STATE_RUNNING) {
986 previous =
987 list_entry(transfer->transfer_list.prev,
988 struct spi_transfer, transfer_list);
989 if (previous->delay_usecs)
990 udelay(previous->delay_usecs);
991 if (previous->cs_change)
992 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
993 } else {
994 /* STATE_START */
995 message->state = STATE_RUNNING;
996 pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
997 }
998
999 /* Configuration Changing Per Transfer */
1000 if (set_up_next_transfer(pl022, transfer)) {
1001 /* Error path */
1002 message->state = STATE_ERROR;
1003 break;
1004 }
1005 /* Flush FIFOs and enable SSP */
1006 flush(pl022);
1007 writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
1008 SSP_CR1(pl022->virtbase));
1009
1010 dev_dbg(&pl022->adev->dev, "POLLING TRANSFER ONGOING ... \n");
1011 /* FIXME: insert a timeout so we don't hang here indefinately */
1012 while (pl022->tx < pl022->tx_end || pl022->rx < pl022->rx_end)
1013 readwriter(pl022);
1014
1015 /* Update total byte transfered */
1016 message->actual_length += pl022->cur_transfer->len;
1017 if (pl022->cur_transfer->cs_change)
1018 pl022->cur_chip->cs_control(SSP_CHIP_DESELECT);
1019 /* Move to next transfer */
1020 message->state = next_transfer(pl022);
1021 }
1022
1023 /* Handle end of message */
1024 if (message->state == STATE_DONE)
1025 message->status = 0;
1026 else
1027 message->status = -EIO;
1028
1029 giveback(pl022);
1030 return;
1031}
1032
1033/**
1034 * pump_messages - Workqueue function which processes spi message queue
1035 * @data: pointer to private data of SSP driver
1036 *
1037 * This function checks if there is any spi message in the queue that
1038 * needs processing and delegate control to appropriate function
1039 * do_polling_transfer()/do_interrupt_transfer()/do_dma_transfer()
1040 * based on the kind of the transfer
1041 *
1042 */
1043static void pump_messages(struct work_struct *work)
1044{
1045 struct pl022 *pl022 =
1046 container_of(work, struct pl022, pump_messages);
1047 unsigned long flags;
1048
1049 /* Lock queue and check for queue work */
1050 spin_lock_irqsave(&pl022->queue_lock, flags);
1051 if (list_empty(&pl022->queue) || pl022->run == QUEUE_STOPPED) {
1052 pl022->busy = 0;
1053 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1054 return;
1055 }
1056 /* Make sure we are not already running a message */
1057 if (pl022->cur_msg) {
1058 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1059 return;
1060 }
1061 /* Extract head of queue */
1062 pl022->cur_msg =
1063 list_entry(pl022->queue.next, struct spi_message, queue);
1064
1065 list_del_init(&pl022->cur_msg->queue);
1066 pl022->busy = 1;
1067 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1068
1069 /* Initial message state */
1070 pl022->cur_msg->state = STATE_START;
1071 pl022->cur_transfer = list_entry(pl022->cur_msg->transfers.next,
1072 struct spi_transfer,
1073 transfer_list);
1074
1075 /* Setup the SPI using the per chip configuration */
1076 pl022->cur_chip = spi_get_ctldata(pl022->cur_msg->spi);
1077 /*
1078 * We enable the clock here, then the clock will be disabled when
1079 * giveback() is called in each method (poll/interrupt/DMA)
1080 */
1081 clk_enable(pl022->clk);
1082 restore_state(pl022);
1083 flush(pl022);
1084
1085 if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
1086 do_polling_transfer(pl022);
1087 else if (pl022->cur_chip->xfer_type == INTERRUPT_TRANSFER)
1088 do_interrupt_transfer(pl022);
1089 else
1090 do_dma_transfer(pl022);
1091}
1092
1093
1094static int __init init_queue(struct pl022 *pl022)
1095{
1096 INIT_LIST_HEAD(&pl022->queue);
1097 spin_lock_init(&pl022->queue_lock);
1098
1099 pl022->run = QUEUE_STOPPED;
1100 pl022->busy = 0;
1101
1102 tasklet_init(&pl022->pump_transfers,
1103 pump_transfers, (unsigned long)pl022);
1104
1105 INIT_WORK(&pl022->pump_messages, pump_messages);
1106 pl022->workqueue = create_singlethread_workqueue(
1107 dev_name(pl022->master->dev.parent));
1108 if (pl022->workqueue == NULL)
1109 return -EBUSY;
1110
1111 return 0;
1112}
1113
1114
1115static int start_queue(struct pl022 *pl022)
1116{
1117 unsigned long flags;
1118
1119 spin_lock_irqsave(&pl022->queue_lock, flags);
1120
1121 if (pl022->run == QUEUE_RUNNING || pl022->busy) {
1122 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1123 return -EBUSY;
1124 }
1125
1126 pl022->run = QUEUE_RUNNING;
1127 pl022->cur_msg = NULL;
1128 pl022->cur_transfer = NULL;
1129 pl022->cur_chip = NULL;
1130 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1131
1132 queue_work(pl022->workqueue, &pl022->pump_messages);
1133
1134 return 0;
1135}
1136
1137
1138static int stop_queue(struct pl022 *pl022)
1139{
1140 unsigned long flags;
1141 unsigned limit = 500;
1142 int status = 0;
1143
1144 spin_lock_irqsave(&pl022->queue_lock, flags);
1145
1146 /* This is a bit lame, but is optimized for the common execution path.
1147 * A wait_queue on the pl022->busy could be used, but then the common
1148 * execution path (pump_messages) would be required to call wake_up or
1149 * friends on every SPI message. Do this instead */
1150 pl022->run = QUEUE_STOPPED;
1151 while (!list_empty(&pl022->queue) && pl022->busy && limit--) {
1152 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1153 msleep(10);
1154 spin_lock_irqsave(&pl022->queue_lock, flags);
1155 }
1156
1157 if (!list_empty(&pl022->queue) || pl022->busy)
1158 status = -EBUSY;
1159
1160 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1161
1162 return status;
1163}
1164
1165static int destroy_queue(struct pl022 *pl022)
1166{
1167 int status;
1168
1169 status = stop_queue(pl022);
1170 /* we are unloading the module or failing to load (only two calls
1171 * to this routine), and neither call can handle a return value.
1172 * However, destroy_workqueue calls flush_workqueue, and that will
1173 * block until all work is done. If the reason that stop_queue
1174 * timed out is that the work will never finish, then it does no
1175 * good to call destroy_workqueue, so return anyway. */
1176 if (status != 0)
1177 return status;
1178
1179 destroy_workqueue(pl022->workqueue);
1180
1181 return 0;
1182}
1183
1184static int verify_controller_parameters(struct pl022 *pl022,
1185 struct pl022_config_chip *chip_info)
1186{
1187 if ((chip_info->lbm != LOOPBACK_ENABLED)
1188 && (chip_info->lbm != LOOPBACK_DISABLED)) {
1189 dev_err(chip_info->dev,
1190 "loopback Mode is configured incorrectly\n");
1191 return -EINVAL;
1192 }
1193 if ((chip_info->iface < SSP_INTERFACE_MOTOROLA_SPI)
1194 || (chip_info->iface > SSP_INTERFACE_UNIDIRECTIONAL)) {
1195 dev_err(chip_info->dev,
1196 "interface is configured incorrectly\n");
1197 return -EINVAL;
1198 }
1199 if ((chip_info->iface == SSP_INTERFACE_UNIDIRECTIONAL) &&
1200 (!pl022->vendor->unidir)) {
1201 dev_err(chip_info->dev,
1202 "unidirectional mode not supported in this "
1203 "hardware version\n");
1204 return -EINVAL;
1205 }
1206 if ((chip_info->hierarchy != SSP_MASTER)
1207 && (chip_info->hierarchy != SSP_SLAVE)) {
1208 dev_err(chip_info->dev,
1209 "hierarchy is configured incorrectly\n");
1210 return -EINVAL;
1211 }
1212 if (((chip_info->clk_freq).cpsdvsr < CPSDVR_MIN)
1213 || ((chip_info->clk_freq).cpsdvsr > CPSDVR_MAX)) {
1214 dev_err(chip_info->dev,
1215 "cpsdvsr is configured incorrectly\n");
1216 return -EINVAL;
1217 }
1218 if ((chip_info->endian_rx != SSP_RX_MSB)
1219 && (chip_info->endian_rx != SSP_RX_LSB)) {
1220 dev_err(chip_info->dev,
1221 "RX FIFO endianess is configured incorrectly\n");
1222 return -EINVAL;
1223 }
1224 if ((chip_info->endian_tx != SSP_TX_MSB)
1225 && (chip_info->endian_tx != SSP_TX_LSB)) {
1226 dev_err(chip_info->dev,
1227 "TX FIFO endianess is configured incorrectly\n");
1228 return -EINVAL;
1229 }
1230 if ((chip_info->data_size < SSP_DATA_BITS_4)
1231 || (chip_info->data_size > SSP_DATA_BITS_32)) {
1232 dev_err(chip_info->dev,
1233 "DATA Size is configured incorrectly\n");
1234 return -EINVAL;
1235 }
1236 if ((chip_info->com_mode != INTERRUPT_TRANSFER)
1237 && (chip_info->com_mode != DMA_TRANSFER)
1238 && (chip_info->com_mode != POLLING_TRANSFER)) {
1239 dev_err(chip_info->dev,
1240 "Communication mode is configured incorrectly\n");
1241 return -EINVAL;
1242 }
1243 if ((chip_info->rx_lev_trig < SSP_RX_1_OR_MORE_ELEM)
1244 || (chip_info->rx_lev_trig > SSP_RX_32_OR_MORE_ELEM)) {
1245 dev_err(chip_info->dev,
1246 "RX FIFO Trigger Level is configured incorrectly\n");
1247 return -EINVAL;
1248 }
1249 if ((chip_info->tx_lev_trig < SSP_TX_1_OR_MORE_EMPTY_LOC)
1250 || (chip_info->tx_lev_trig > SSP_TX_32_OR_MORE_EMPTY_LOC)) {
1251 dev_err(chip_info->dev,
1252 "TX FIFO Trigger Level is configured incorrectly\n");
1253 return -EINVAL;
1254 }
1255 if (chip_info->iface == SSP_INTERFACE_MOTOROLA_SPI) {
ee2b805c
LW		 1256 if ((chip_info->clk_phase != SSP_CLK_FIRST_EDGE)
1257 && (chip_info->clk_phase != SSP_CLK_SECOND_EDGE)) {
b43d65f7
LW		 1258 dev_err(chip_info->dev,
1259 "Clock Phase is configured incorrectly\n");
1260 return -EINVAL;
1261 }
1262 if ((chip_info->clk_pol != SSP_CLK_POL_IDLE_LOW)
1263 && (chip_info->clk_pol != SSP_CLK_POL_IDLE_HIGH)) {
1264 dev_err(chip_info->dev,
1265 "Clock Polarity is configured incorrectly\n");
1266 return -EINVAL;
1267 }
1268 }
1269 if (chip_info->iface == SSP_INTERFACE_NATIONAL_MICROWIRE) {
1270 if ((chip_info->ctrl_len < SSP_BITS_4)
1271 || (chip_info->ctrl_len > SSP_BITS_32)) {
1272 dev_err(chip_info->dev,
1273 "CTRL LEN is configured incorrectly\n");
1274 return -EINVAL;
1275 }
1276 if ((chip_info->wait_state != SSP_MWIRE_WAIT_ZERO)
1277 && (chip_info->wait_state != SSP_MWIRE_WAIT_ONE)) {
1278 dev_err(chip_info->dev,
1279 "Wait State is configured incorrectly\n");
1280 return -EINVAL;
1281 }
1282 if ((chip_info->duplex != SSP_MICROWIRE_CHANNEL_FULL_DUPLEX)
1283 && (chip_info->duplex !=
1284 SSP_MICROWIRE_CHANNEL_HALF_DUPLEX)) {
1285 dev_err(chip_info->dev,
1286 "DUPLEX is configured incorrectly\n");
1287 return -EINVAL;
1288 }
1289 }
1290 if (chip_info->cs_control == NULL) {
1291 dev_warn(chip_info->dev,
1292 "Chip Select Function is NULL for this chip\n");
1293 chip_info->cs_control = null_cs_control;
1294 }
1295 return 0;
1296}
1297
1298/**
1299 * pl022_transfer - transfer function registered to SPI master framework
1300 * @spi: spi device which is requesting transfer
1301 * @msg: spi message which is to handled is queued to driver queue
1302 *
1303 * This function is registered to the SPI framework for this SPI master
1304 * controller. It will queue the spi_message in the queue of driver if
1305 * the queue is not stopped and return.
1306 */
1307static int pl022_transfer(struct spi_device *spi, struct spi_message *msg)
1308{
1309 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1310 unsigned long flags;
1311
1312 spin_lock_irqsave(&pl022->queue_lock, flags);
1313
1314 if (pl022->run == QUEUE_STOPPED) {
1315 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1316 return -ESHUTDOWN;
1317 }
1318 msg->actual_length = 0;
1319 msg->status = -EINPROGRESS;
1320 msg->state = STATE_START;
1321
1322 list_add_tail(&msg->queue, &pl022->queue);
1323 if (pl022->run == QUEUE_RUNNING && !pl022->busy)
1324 queue_work(pl022->workqueue, &pl022->pump_messages);
1325
1326 spin_unlock_irqrestore(&pl022->queue_lock, flags);
1327 return 0;
1328}
1329
1330static int calculate_effective_freq(struct pl022 *pl022,
1331 int freq,
1332 struct ssp_clock_params *clk_freq)
1333{
1334 /* Lets calculate the frequency parameters */
1335 u16 cpsdvsr = 2;
1336 u16 scr = 0;
1337 bool freq_found = false;
1338 u32 rate;
1339 u32 max_tclk;
1340 u32 min_tclk;
1341
1342 rate = clk_get_rate(pl022->clk);
1343 /* cpsdvscr = 2 & scr 0 */
1344 max_tclk = (rate / (CPSDVR_MIN * (1 + SCR_MIN)));
1345 /* cpsdvsr = 254 & scr = 255 */
1346 min_tclk = (rate / (CPSDVR_MAX * (1 + SCR_MAX)));
1347
1348 if ((freq <= max_tclk) && (freq >= min_tclk)) {
1349 while (cpsdvsr <= CPSDVR_MAX && !freq_found) {
1350 while (scr <= SCR_MAX && !freq_found) {
1351 if ((rate /
1352 (cpsdvsr * (1 + scr))) > freq)
1353 scr += 1;
1354 else {
1355 /*
1356 * This bool is made true when
1357 * effective frequency >=
1358 * target frequency is found
1359 */
1360 freq_found = true;
1361 if ((rate /
1362 (cpsdvsr * (1 + scr))) != freq) {
1363 if (scr == SCR_MIN) {
1364 cpsdvsr -= 2;
1365 scr = SCR_MAX;
1366 } else
1367 scr -= 1;
1368 }
1369 }
1370 }
1371 if (!freq_found) {
1372 cpsdvsr += 2;
1373 scr = SCR_MIN;
1374 }
1375 }
1376 if (cpsdvsr != 0) {
1377 dev_dbg(&pl022->adev->dev,
1378 "SSP Effective Frequency is %u\n",
1379 (rate / (cpsdvsr * (1 + scr))));
1380 clk_freq->cpsdvsr = (u8) (cpsdvsr & 0xFF);
1381 clk_freq->scr = (u8) (scr & 0xFF);
1382 dev_dbg(&pl022->adev->dev,
1383 "SSP cpsdvsr = %d, scr = %d\n",
1384 clk_freq->cpsdvsr, clk_freq->scr);
1385 }
1386 } else {
1387 dev_err(&pl022->adev->dev,
1388 "controller data is incorrect: out of range frequency");
1389 return -EINVAL;
1390 }
1391 return 0;
1392}
1393
1394/**
1395 * NOT IMPLEMENTED
1396 * process_dma_info - Processes the DMA info provided by client drivers
1397 * @chip_info: chip info provided by client device
1398 * @chip: Runtime state maintained by the SSP controller for each spi device
1399 *
1400 * This function processes and stores DMA config provided by client driver
1401 * into the runtime state maintained by the SSP controller driver
1402 */
1403static int process_dma_info(struct pl022_config_chip *chip_info,
1404 struct chip_data *chip)
1405{
1406 dev_err(chip_info->dev,
1407 "cannot process DMA info, DMA not implemented!\n");
1408 return -ENOTSUPP;
1409}
1410
1411/**
1412 * pl022_setup - setup function registered to SPI master framework
1413 * @spi: spi device which is requesting setup
1414 *
1415 * This function is registered to the SPI framework for this SPI master
1416 * controller. If it is the first time when setup is called by this device,
1417 * this function will initialize the runtime state for this chip and save
1418 * the same in the device structure. Else it will update the runtime info
1419 * with the updated chip info. Nothing is really being written to the
1420 * controller hardware here, that is not done until the actual transfer
1421 * commence.
1422 */
1423
1424/* FIXME: JUST GUESSING the spi->mode bits understood by this driver */
1425#define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1426 | SPI_LSB_FIRST | SPI_LOOP)
1427
1428static int pl022_setup(struct spi_device *spi)
1429{
1430 struct pl022_config_chip *chip_info;
1431 struct chip_data *chip;
1432 int status = 0;
1433 struct pl022 *pl022 = spi_master_get_devdata(spi->master);
1434
1435 if (spi->mode & ~MODEBITS) {
1436 dev_dbg(&spi->dev, "unsupported mode bits %x\n",
1437 spi->mode & ~MODEBITS);
1438 return -EINVAL;
1439 }
1440
1441 if (!spi->max_speed_hz)
1442 return -EINVAL;
1443
1444 /* Get controller_state if one is supplied */
1445 chip = spi_get_ctldata(spi);
1446
1447 if (chip == NULL) {
1448 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1449 if (!chip) {
1450 dev_err(&spi->dev,
1451 "cannot allocate controller state\n");
1452 return -ENOMEM;
1453 }
1454 dev_dbg(&spi->dev,
1455 "allocated memory for controller's runtime state\n");
1456 }
1457
1458 /* Get controller data if one is supplied */
1459 chip_info = spi->controller_data;
1460
1461 if (chip_info == NULL) {
1462 /* spi_board_info.controller_data not is supplied */
1463 dev_dbg(&spi->dev,
1464 "using default controller_data settings\n");
1465
1466 chip_info =
1467 kzalloc(sizeof(struct pl022_config_chip), GFP_KERNEL);
1468
1469 if (!chip_info) {
1470 dev_err(&spi->dev,
1471 "cannot allocate controller data\n");
1472 status = -ENOMEM;
1473 goto err_first_setup;
1474 }
1475
1476 dev_dbg(&spi->dev, "allocated memory for controller data\n");
1477
1478 /* Pointer back to the SPI device */
1479 chip_info->dev = &spi->dev;
1480 /*
1481 * Set controller data default values:
1482 * Polling is supported by default
1483 */
1484 chip_info->lbm = LOOPBACK_DISABLED;
1485 chip_info->com_mode = POLLING_TRANSFER;
1486 chip_info->iface = SSP_INTERFACE_MOTOROLA_SPI;
1487 chip_info->hierarchy = SSP_SLAVE;
1488 chip_info->slave_tx_disable = DO_NOT_DRIVE_TX;
1489 chip_info->endian_tx = SSP_TX_LSB;
1490 chip_info->endian_rx = SSP_RX_LSB;
1491 chip_info->data_size = SSP_DATA_BITS_12;
1492 chip_info->rx_lev_trig = SSP_RX_1_OR_MORE_ELEM;
1493 chip_info->tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC;
ee2b805c 1494 chip_info->clk_phase = SSP_CLK_SECOND_EDGE;
b43d65f7
LW		 1495 chip_info->clk_pol = SSP_CLK_POL_IDLE_LOW;
1496 chip_info->ctrl_len = SSP_BITS_8;
1497 chip_info->wait_state = SSP_MWIRE_WAIT_ZERO;
1498 chip_info->duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX;
1499 chip_info->cs_control = null_cs_control;
1500 } else {
1501 dev_dbg(&spi->dev,
1502 "using user supplied controller_data settings\n");
1503 }
1504
1505 /*
1506 * We can override with custom divisors, else we use the board
1507 * frequency setting
1508 */
1509 if ((0 == chip_info->clk_freq.cpsdvsr)
1510 && (0 == chip_info->clk_freq.scr)) {
1511 status = calculate_effective_freq(pl022,
1512 spi->max_speed_hz,
1513 &chip_info->clk_freq);
1514 if (status < 0)
1515 goto err_config_params;
1516 } else {
1517 if ((chip_info->clk_freq.cpsdvsr % 2) != 0)
1518 chip_info->clk_freq.cpsdvsr =
1519 chip_info->clk_freq.cpsdvsr - 1;
1520 }
1521 status = verify_controller_parameters(pl022, chip_info);
1522 if (status) {
1523 dev_err(&spi->dev, "controller data is incorrect");
1524 goto err_config_params;
1525 }
1526 /* Now set controller state based on controller data */
1527 chip->xfer_type = chip_info->com_mode;
1528 chip->cs_control = chip_info->cs_control;
1529
1530 if (chip_info->data_size <= 8) {
1531 dev_dbg(&spi->dev, "1 <= n <=8 bits per word\n");
1532 chip->n_bytes = 1;
1533 chip->read = READING_U8;
1534 chip->write = WRITING_U8;
1535 } else if (chip_info->data_size <= 16) {
1536 dev_dbg(&spi->dev, "9 <= n <= 16 bits per word\n");
1537 chip->n_bytes = 2;
1538 chip->read = READING_U16;
1539 chip->write = WRITING_U16;
1540 } else {
1541 if (pl022->vendor->max_bpw >= 32) {
1542 dev_dbg(&spi->dev, "17 <= n <= 32 bits per word\n");
1543 chip->n_bytes = 4;
1544 chip->read = READING_U32;
1545 chip->write = WRITING_U32;
1546 } else {
1547 dev_err(&spi->dev,
1548 "illegal data size for this controller!\n");
1549 dev_err(&spi->dev,
1550 "a standard pl022 can only handle "
1551 "1 <= n <= 16 bit words\n");
1552 goto err_config_params;
1553 }
1554 }
1555
1556 /* Now Initialize all register settings required for this chip */
1557 chip->cr0 = 0;
1558 chip->cr1 = 0;
1559 chip->dmacr = 0;
1560 chip->cpsr = 0;
1561 if ((chip_info->com_mode == DMA_TRANSFER)
1562 && ((pl022->master_info)->enable_dma)) {
1563 chip->enable_dma = 1;
1564 dev_dbg(&spi->dev, "DMA mode set in controller state\n");
1565 status = process_dma_info(chip_info, chip);
1566 if (status < 0)
1567 goto err_config_params;
1568 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1569 SSP_DMACR_MASK_RXDMAE, 0);
1570 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
1571 SSP_DMACR_MASK_TXDMAE, 1);
1572 } else {
1573 chip->enable_dma = 0;
1574 dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
1575 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1576 SSP_DMACR_MASK_RXDMAE, 0);
1577 SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
1578 SSP_DMACR_MASK_TXDMAE, 1);
1579 }
1580
1581 chip->cpsr = chip_info->clk_freq.cpsdvsr;
1582
1583 SSP_WRITE_BITS(chip->cr0, chip_info->data_size, SSP_CR0_MASK_DSS, 0);
1584 SSP_WRITE_BITS(chip->cr0, chip_info->duplex, SSP_CR0_MASK_HALFDUP, 5);
1585 SSP_WRITE_BITS(chip->cr0, chip_info->clk_pol, SSP_CR0_MASK_SPO, 6);
1586 SSP_WRITE_BITS(chip->cr0, chip_info->clk_phase, SSP_CR0_MASK_SPH, 7);
1587 SSP_WRITE_BITS(chip->cr0, chip_info->clk_freq.scr, SSP_CR0_MASK_SCR, 8);
1588 SSP_WRITE_BITS(chip->cr0, chip_info->ctrl_len, SSP_CR0_MASK_CSS, 16);
1589 SSP_WRITE_BITS(chip->cr0, chip_info->iface, SSP_CR0_MASK_FRF, 21);
1590 SSP_WRITE_BITS(chip->cr1, chip_info->lbm, SSP_CR1_MASK_LBM, 0);
1591 SSP_WRITE_BITS(chip->cr1, SSP_DISABLED, SSP_CR1_MASK_SSE, 1);
1592 SSP_WRITE_BITS(chip->cr1, chip_info->hierarchy, SSP_CR1_MASK_MS, 2);
1593 SSP_WRITE_BITS(chip->cr1, chip_info->slave_tx_disable, SSP_CR1_MASK_SOD, 3);
1594 SSP_WRITE_BITS(chip->cr1, chip_info->endian_rx, SSP_CR1_MASK_RENDN, 4);
1595 SSP_WRITE_BITS(chip->cr1, chip_info->endian_tx, SSP_CR1_MASK_TENDN, 5);
1596 SSP_WRITE_BITS(chip->cr1, chip_info->wait_state, SSP_CR1_MASK_MWAIT, 6);
1597 SSP_WRITE_BITS(chip->cr1, chip_info->rx_lev_trig, SSP_CR1_MASK_RXIFLSEL, 7);
1598 SSP_WRITE_BITS(chip->cr1, chip_info->tx_lev_trig, SSP_CR1_MASK_TXIFLSEL, 10);
1599
1600 /* Save controller_state */
1601 spi_set_ctldata(spi, chip);
1602 return status;
1603 err_config_params:
1604 err_first_setup:
1605 kfree(chip);
1606 return status;
1607}
1608
1609/**
1610 * pl022_cleanup - cleanup function registered to SPI master framework
1611 * @spi: spi device which is requesting cleanup
1612 *
1613 * This function is registered to the SPI framework for this SPI master
1614 * controller. It will free the runtime state of chip.
1615 */
1616static void pl022_cleanup(struct spi_device *spi)
1617{
1618 struct chip_data *chip = spi_get_ctldata(spi);
1619
1620 spi_set_ctldata(spi, NULL);
1621 kfree(chip);
1622}
1623
1624
1625static int __init
1626pl022_probe(struct amba_device *adev, struct amba_id *id)
1627{
1628 struct device *dev = &adev->dev;
1629 struct pl022_ssp_controller *platform_info = adev->dev.platform_data;
1630 struct spi_master *master;
1631 struct pl022 *pl022 = NULL; /*Data for this driver */
1632 int status = 0;
1633
1634 dev_info(&adev->dev,
1635 "ARM PL022 driver, device ID: 0x%08x\n", adev->periphid);
1636 if (platform_info == NULL) {
1637 dev_err(&adev->dev, "probe - no platform data supplied\n");
1638 status = -ENODEV;
1639 goto err_no_pdata;
1640 }
1641
1642 /* Allocate master with space for data */
1643 master = spi_alloc_master(dev, sizeof(struct pl022));
1644 if (master == NULL) {
1645 dev_err(&adev->dev, "probe - cannot alloc SPI master\n");
1646 status = -ENOMEM;
1647 goto err_no_master;
1648 }
1649
1650 pl022 = spi_master_get_devdata(master);
1651 pl022->master = master;
1652 pl022->master_info = platform_info;
1653 pl022->adev = adev;
1654 pl022->vendor = id->data;
1655
1656 /*
1657 * Bus Number Which has been Assigned to this SSP controller
1658 * on this board
1659 */
1660 master->bus_num = platform_info->bus_id;
1661 master->num_chipselect = platform_info->num_chipselect;
1662 master->cleanup = pl022_cleanup;
1663 master->setup = pl022_setup;
1664 master->transfer = pl022_transfer;
1665
1666 dev_dbg(&adev->dev, "BUSNO: %d\n", master->bus_num);
1667
1668 status = amba_request_regions(adev, NULL);
1669 if (status)
1670 goto err_no_ioregion;
1671
1672 pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
1673 if (pl022->virtbase == NULL) {
1674 status = -ENOMEM;
1675 goto err_no_ioremap;
1676 }
1677 printk(KERN_INFO "pl022: mapped registers from 0x%08x to %p\n",
1678 adev->res.start, pl022->virtbase);
1679
1680 pl022->clk = clk_get(&adev->dev, NULL);
1681 if (IS_ERR(pl022->clk)) {
1682 status = PTR_ERR(pl022->clk);
1683 dev_err(&adev->dev, "could not retrieve SSP/SPI bus clock\n");
1684 goto err_no_clk;
1685 }
1686
1687 /* Disable SSP */
1688 clk_enable(pl022->clk);
1689 writew((readw(SSP_CR1(pl022->virtbase)) & (~SSP_CR1_MASK_SSE)),
1690 SSP_CR1(pl022->virtbase));
1691 load_ssp_default_config(pl022);
1692 clk_disable(pl022->clk);
1693
1694 status = request_irq(adev->irq[0], pl022_interrupt_handler, 0, "pl022",
1695 pl022);
1696 if (status < 0) {
1697 dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
1698 goto err_no_irq;
1699 }
1700 /* Initialize and start queue */
1701 status = init_queue(pl022);
1702 if (status != 0) {
1703 dev_err(&adev->dev, "probe - problem initializing queue\n");
1704 goto err_init_queue;
1705 }
1706 status = start_queue(pl022);
1707 if (status != 0) {
1708 dev_err(&adev->dev, "probe - problem starting queue\n");
1709 goto err_start_queue;
1710 }
1711 /* Register with the SPI framework */
1712 amba_set_drvdata(adev, pl022);
1713 status = spi_register_master(master);
1714 if (status != 0) {
1715 dev_err(&adev->dev,
1716 "probe - problem registering spi master\n");
1717 goto err_spi_register;
1718 }
1719 dev_dbg(dev, "probe succeded\n");
1720 return 0;
1721
1722 err_spi_register:
1723 err_start_queue:
1724 err_init_queue:
1725 destroy_queue(pl022);
1726 free_irq(adev->irq[0], pl022);
1727 err_no_irq:
1728 clk_put(pl022->clk);
1729 err_no_clk:
1730 iounmap(pl022->virtbase);
1731 err_no_ioremap:
1732 amba_release_regions(adev);
1733 err_no_ioregion:
1734 spi_master_put(master);
1735 err_no_master:
1736 err_no_pdata:
1737 return status;
1738}
1739
1740static int __exit
1741pl022_remove(struct amba_device *adev)
1742{
1743 struct pl022 *pl022 = amba_get_drvdata(adev);
1744 int status = 0;
1745 if (!pl022)
1746 return 0;
1747
1748 /* Remove the queue */
1749 status = destroy_queue(pl022);
1750 if (status != 0) {
1751 dev_err(&adev->dev,
1752 "queue remove failed (%d)\n", status);
1753 return status;
1754 }
1755 load_ssp_default_config(pl022);
1756 free_irq(adev->irq[0], pl022);
1757 clk_disable(pl022->clk);
1758 clk_put(pl022->clk);
1759 iounmap(pl022->virtbase);
1760 amba_release_regions(adev);
1761 tasklet_disable(&pl022->pump_transfers);
1762 spi_unregister_master(pl022->master);
1763 spi_master_put(pl022->master);
1764 amba_set_drvdata(adev, NULL);
1765 dev_dbg(&adev->dev, "remove succeded\n");
1766 return 0;
1767}
1768
1769#ifdef CONFIG_PM
1770static int pl022_suspend(struct amba_device *adev, pm_message_t state)
1771{
1772 struct pl022 *pl022 = amba_get_drvdata(adev);
1773 int status = 0;
1774
1775 status = stop_queue(pl022);
1776 if (status) {
1777 dev_warn(&adev->dev, "suspend cannot stop queue\n");
1778 return status;
1779 }
1780
1781 clk_enable(pl022->clk);
1782 load_ssp_default_config(pl022);
1783 clk_disable(pl022->clk);
1784 dev_dbg(&adev->dev, "suspended\n");
1785 return 0;
1786}
1787
1788static int pl022_resume(struct amba_device *adev)
1789{
1790 struct pl022 *pl022 = amba_get_drvdata(adev);
1791 int status = 0;
1792
1793 /* Start the queue running */
1794 status = start_queue(pl022);
1795 if (status)
1796 dev_err(&adev->dev, "problem starting queue (%d)\n", status);
1797 else
1798 dev_dbg(&adev->dev, "resumed\n");
1799
1800 return status;
1801}
1802#else
1803#define pl022_suspend NULL
1804#define pl022_resume NULL
1805#endif /* CONFIG_PM */
1806
1807static struct vendor_data vendor_arm = {
1808 .fifodepth = 8,
1809 .max_bpw = 16,
1810 .unidir = false,
1811};
1812
1813
1814static struct vendor_data vendor_st = {
1815 .fifodepth = 32,
1816 .max_bpw = 32,
1817 .unidir = false,
1818};
1819
1820static struct amba_id pl022_ids[] = {
1821 {
1822 /*
1823 * ARM PL022 variant, this has a 16bit wide
1824 * and 8 locations deep TX/RX FIFO
1825 */
1826 .id = 0x00041022,
1827 .mask = 0x000fffff,
1828 .data = &vendor_arm,
1829 },
1830 {
1831 /*
1832 * ST Micro derivative, this has 32bit wide
1833 * and 32 locations deep TX/RX FIFO
1834 */
e89e04fc 1835 .id = 0x01080022,
b43d65f7
LW		 1836 .mask = 0xffffffff,
1837 .data = &vendor_st,
1838 },
1839 { 0, 0 },
1840};
1841
1842static struct amba_driver pl022_driver = {
1843 .drv = {
1844 .name = "ssp-pl022",
1845 },
1846 .id_table = pl022_ids,
1847 .probe = pl022_probe,
1848 .remove = __exit_p(pl022_remove),
1849 .suspend = pl022_suspend,
1850 .resume = pl022_resume,
1851};
1852
1853
1854static int __init pl022_init(void)
1855{
1856 return amba_driver_register(&pl022_driver);
1857}
1858
1859module_init(pl022_init);
1860
1861static void __exit pl022_exit(void)
1862{
1863 amba_driver_unregister(&pl022_driver);
1864}
1865
1866module_exit(pl022_exit);
1867
1868MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1869MODULE_DESCRIPTION("PL022 SSP Controller Driver");
1870MODULE_LICENSE("GPL");
Clone of davem's net-next-2.6 tree