[net-next-2.6.git] / drivers / sh / pfc.c

/*
 * Pinmuxed GPIO support for SuperH.
 *
 * Copyright (C) 2008 Magnus Damm
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/list.h>
#include <linux/module.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/gpio.h>

static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
{
	if (enum_id < r->begin)
		return 0;

	if (enum_id > r->end)
		return 0;

	return 1;
}

static unsigned long gpio_read_raw_reg(unsigned long reg,
				       unsigned long reg_width)
{
	switch (reg_width) {
	case 8:
		return __raw_readb(reg);
	case 16:
		return __raw_readw(reg);
	case 32:
		return __raw_readl(reg);
	}

	BUG();
	return 0;
}

static void gpio_write_raw_reg(unsigned long reg,
			       unsigned long reg_width,
			       unsigned long data)
{
	switch (reg_width) {
	case 8:
		__raw_writeb(data, reg);
		return;
	case 16:
		__raw_writew(data, reg);
		return;
	case 32:
		__raw_writel(data, reg);
		return;
	}

	BUG();
}

static void gpio_write_bit(struct pinmux_data_reg *dr,
			   unsigned long in_pos, unsigned long value)
{
	unsigned long pos;

	pos = dr->reg_width - (in_pos + 1);

	pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
		 "r_width = %ld\n",
		 dr->reg, !!value, pos, dr->reg_width);

	if (value)
		set_bit(pos, &dr->reg_shadow);
	else
		clear_bit(pos, &dr->reg_shadow);

	gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
}

static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
			 unsigned long field_width, unsigned long in_pos)
{
	unsigned long data, mask, pos;

	data = 0;
	mask = (1 << field_width) - 1;
	pos = reg_width - ((in_pos + 1) * field_width);

	pr_debug("read_reg: addr = %lx, pos = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 reg, pos, reg_width, field_width);

	data = gpio_read_raw_reg(reg, reg_width);
	return (data >> pos) & mask;
}

static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
			   unsigned long field_width, unsigned long in_pos,
			   unsigned long value)
{
	unsigned long mask, pos;

	mask = (1 << field_width) - 1;
	pos = reg_width - ((in_pos + 1) * field_width);

	pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
		 "r_width = %ld, f_width = %ld\n",
		 reg, value, pos, reg_width, field_width);

	mask = ~(mask << pos);
	value = value << pos;

	switch (reg_width) {
	case 8:
		__raw_writeb((__raw_readb(reg) & mask) | value, reg);
		break;
	case 16:
		__raw_writew((__raw_readw(reg) & mask) | value, reg);
		break;
	case 32:
		__raw_writel((__raw_readl(reg) & mask) | value, reg);
		break;
	}
}

static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
{
	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	struct pinmux_data_reg *data_reg;
	int k, n;

	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
		return -1;

	k = 0;
	while (1) {
		data_reg = gpioc->data_regs + k;

		if (!data_reg->reg_width)
			break;

		for (n = 0; n < data_reg->reg_width; n++) {
			if (data_reg->enum_ids[n] == gpiop->enum_id) {
				gpiop->flags &= ~PINMUX_FLAG_DREG;
				gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
				gpiop->flags &= ~PINMUX_FLAG_DBIT;
				gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
				return 0;
			}
		}
		k++;
	}

	BUG();

	return -1;
}

static void setup_data_regs(struct pinmux_info *gpioc)
{
	struct pinmux_data_reg *drp;
	int k;

	for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
		setup_data_reg(gpioc, k);

	k = 0;
	while (1) {
		drp = gpioc->data_regs + k;

		if (!drp->reg_width)
			break;

		drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
		k++;
	}
}

static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
			struct pinmux_data_reg **drp, int *bitp)
{
	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	int k, n;

	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
		return -1;

	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
	*drp = gpioc->data_regs + k;
	*bitp = n;
	return 0;
}

static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
			  struct pinmux_cfg_reg **crp, int *indexp,
			  unsigned long **cntp)
{
	struct pinmux_cfg_reg *config_reg;
	unsigned long r_width, f_width;
	int k, n;

	k = 0;
	while (1) {
		config_reg = gpioc->cfg_regs + k;

		r_width = config_reg->reg_width;
		f_width = config_reg->field_width;

		if (!r_width)
			break;
		for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
			if (config_reg->enum_ids[n] == enum_id) {
				*crp = config_reg;
				*indexp = n;
				*cntp = &config_reg->cnt[n / (1 << f_width)];
				return 0;
			}
		}
		k++;
	}

	return -1;
}

static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
			    int pos, pinmux_enum_t *enum_idp)
{
	pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
	pinmux_enum_t *data = gpioc->gpio_data;
	int k;

	if (!enum_in_range(enum_id, &gpioc->data)) {
		if (!enum_in_range(enum_id, &gpioc->mark)) {
			pr_err("non data/mark enum_id for gpio %d\n", gpio);
			return -1;
		}
	}

	if (pos) {
		*enum_idp = data[pos + 1];
		return pos + 1;
	}

	for (k = 0; k < gpioc->gpio_data_size; k++) {
		if (data[k] == enum_id) {
			*enum_idp = data[k + 1];
			return k + 1;
		}
	}

	pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
	return -1;
}

static void write_config_reg(struct pinmux_info *gpioc,
			     struct pinmux_cfg_reg *crp,
			     int index)
{
	unsigned long ncomb, pos, value;

	ncomb = 1 << crp->field_width;
	pos = index / ncomb;
	value = index % ncomb;

	gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
}

static int check_config_reg(struct pinmux_info *gpioc,
			    struct pinmux_cfg_reg *crp,
			    int index)
{
	unsigned long ncomb, pos, value;

	ncomb = 1 << crp->field_width;
	pos = index / ncomb;
	value = index % ncomb;

	if (gpio_read_reg(crp->reg, crp->reg_width,
			  crp->field_width, pos) == value)
		return 0;

	return -1;
}

enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };

static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
			      int pinmux_type, int cfg_mode)
{
	struct pinmux_cfg_reg *cr = NULL;
	pinmux_enum_t enum_id;
	struct pinmux_range *range;
	int in_range, pos, index;
	unsigned long *cntp;

	switch (pinmux_type) {

	case PINMUX_TYPE_FUNCTION:
		range = NULL;
		break;

	case PINMUX_TYPE_OUTPUT:
		range = &gpioc->output;
		break;

	case PINMUX_TYPE_INPUT:
		range = &gpioc->input;
		break;

	case PINMUX_TYPE_INPUT_PULLUP:
		range = &gpioc->input_pu;
		break;

	case PINMUX_TYPE_INPUT_PULLDOWN:
		range = &gpioc->input_pd;
		break;

	default:
		goto out_err;
	}

	pos = 0;
	enum_id = 0;
	index = 0;
	while (1) {
		pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
		if (pos <= 0)
			goto out_err;

		if (!enum_id)
			break;

		/* first check if this is a function enum */
		in_range = enum_in_range(enum_id, &gpioc->function);
		if (!in_range) {
			/* not a function enum */
			if (range) {
				/*
				 * other range exists, so this pin is
				 * a regular GPIO pin that now is being
				 * bound to a specific direction.
				 *
				 * for this case we only allow function enums
				 * and the enums that match the other range.
				 */
				in_range = enum_in_range(enum_id, range);

				/*
				 * special case pass through for fixed
				 * input-only or output-only pins without
				 * function enum register association.
				 */
				if (in_range && enum_id == range->force)
					continue;
			} else {
				/*
				 * no other range exists, so this pin
				 * must then be of the function type.
				 *
				 * allow function type pins to select
				 * any combination of function/in/out
				 * in their MARK lists.
				 */
				in_range = 1;
			}
		}

		if (!in_range)
			continue;

		if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
			goto out_err;

		switch (cfg_mode) {
		case GPIO_CFG_DRYRUN:
			if (!*cntp || !check_config_reg(gpioc, cr, index))
				continue;
			break;

		case GPIO_CFG_REQ:
			write_config_reg(gpioc, cr, index);
			*cntp = *cntp + 1;
			break;

		case GPIO_CFG_FREE:
			*cntp = *cntp - 1;
			break;
		}
	}

	return 0;
 out_err:
	return -1;
}

static DEFINE_SPINLOCK(gpio_lock);

static struct pinmux_info *chip_to_pinmux(struct gpio_chip *chip)
{
	return container_of(chip, struct pinmux_info, chip);
}

static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	struct pinmux_info *gpioc = chip_to_pinmux(chip);
	struct pinmux_data_reg *dummy;
	unsigned long flags;
	int i, ret, pinmux_type;

	ret = -EINVAL;

	if (!gpioc)
		goto err_out;

	spin_lock_irqsave(&gpio_lock, flags);

	if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
		goto err_unlock;

	/* setup pin function here if no data is associated with pin */

	if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
		pinmux_type = PINMUX_TYPE_FUNCTION;
	else
		pinmux_type = PINMUX_TYPE_GPIO;

	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
		if (pinmux_config_gpio(gpioc, offset,
				       pinmux_type,
				       GPIO_CFG_DRYRUN) != 0)
			goto err_unlock;

		if (pinmux_config_gpio(gpioc, offset,
				       pinmux_type,
				       GPIO_CFG_REQ) != 0)
			BUG();
	}

	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[offset].flags |= pinmux_type;

	ret = 0;
 err_unlock:
	spin_unlock_irqrestore(&gpio_lock, flags);
 err_out:
	return ret;
}

static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
{
	struct pinmux_info *gpioc = chip_to_pinmux(chip);
	unsigned long flags;
	int pinmux_type;

	if (!gpioc)
		return;

	spin_lock_irqsave(&gpio_lock, flags);

	pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[offset].flags |= PINMUX_TYPE_NONE;

	spin_unlock_irqrestore(&gpio_lock, flags);
}

static int pinmux_direction(struct pinmux_info *gpioc,
			    unsigned gpio, int new_pinmux_type)
{
	int pinmux_type;
	int ret = -EINVAL;

	if (!gpioc)
		goto err_out;

	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;

	switch (pinmux_type) {
	case PINMUX_TYPE_GPIO:
		break;
	case PINMUX_TYPE_OUTPUT:
	case PINMUX_TYPE_INPUT:
	case PINMUX_TYPE_INPUT_PULLUP:
	case PINMUX_TYPE_INPUT_PULLDOWN:
		pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
		break;
	default:
		goto err_out;
	}

	if (pinmux_config_gpio(gpioc, gpio,
			       new_pinmux_type,
			       GPIO_CFG_DRYRUN) != 0)
		goto err_out;

	if (pinmux_config_gpio(gpioc, gpio,
			       new_pinmux_type,
			       GPIO_CFG_REQ) != 0)
		BUG();

	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
	gpioc->gpios[gpio].flags |= new_pinmux_type;

	ret = 0;
 err_out:
	return ret;
}

static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct pinmux_info *gpioc = chip_to_pinmux(chip);
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&gpio_lock, flags);
	ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
	spin_unlock_irqrestore(&gpio_lock, flags);

	return ret;
}

static void sh_gpio_set_value(struct pinmux_info *gpioc,
			     unsigned gpio, int value)
{
	struct pinmux_data_reg *dr = NULL;
	int bit = 0;

	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
		BUG();
	else
		gpio_write_bit(dr, bit, value);
}

static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
				    int value)
{
	struct pinmux_info *gpioc = chip_to_pinmux(chip);
	unsigned long flags;
	int ret;

	sh_gpio_set_value(gpioc, offset, value);
	spin_lock_irqsave(&gpio_lock, flags);
	ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
	spin_unlock_irqrestore(&gpio_lock, flags);

	return ret;
}

static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
{
	struct pinmux_data_reg *dr = NULL;
	int bit = 0;

	if (!gpioc || get_data_reg(gpioc, gpio, &dr, &bit) != 0)
		return -EINVAL;

	return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
}

static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return sh_gpio_get_value(chip_to_pinmux(chip), offset);
}

static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
}

int register_pinmux(struct pinmux_info *pip)
{
	struct gpio_chip *chip = &pip->chip;

	pr_info("%s handling gpio %d -> %d\n",
		pip->name, pip->first_gpio, pip->last_gpio);

	setup_data_regs(pip);

	chip->request = sh_gpio_request;
	chip->free = sh_gpio_free;
	chip->direction_input = sh_gpio_direction_input;
	chip->get = sh_gpio_get;
	chip->direction_output = sh_gpio_direction_output;
	chip->set = sh_gpio_set;

	WARN_ON(pip->first_gpio != 0); /* needs testing */

	chip->label = pip->name;
	chip->owner = THIS_MODULE;
	chip->base = pip->first_gpio;
	chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;

	return gpiochip_add(chip);
}

int unregister_pinmux(struct pinmux_info *pip)
{
	pr_info("%s deregistering\n", pip->name);

	return gpiochip_remove(&pip->chip);
}
Commit	Line	Data
2967dab1 MD	1	/*
	2	* Pinmuxed GPIO support for SuperH.
	3	*
	4	* Copyright (C) 2008 Magnus Damm
	5	*
	6	* This file is subject to the terms and conditions of the GNU General Public
	7	* License. See the file "COPYING" in the main directory of this archive
	8	* for more details.
	9	*/
b72421d8 PM	10	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
b72421d8 PM	11
2967dab1 MD	12	#include <linux/errno.h>
	13	#include <linux/kernel.h>
	14	#include <linux/list.h>
	15	#include <linux/module.h>
	16	#include <linux/clk.h>
	17	#include <linux/err.h>
	18	#include <linux/io.h>
	19	#include <linux/irq.h>
	20	#include <linux/bitops.h>
	21	#include <linux/gpio.h>
	22
2967dab1 MD	23	static int enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
	24	{
	25	if (enum_id < r->begin)
	26	return 0;
	27
	28	if (enum_id > r->end)
	29	return 0;
	30
	31	return 1;
	32	}
	33
3292094e MD	34	static unsigned long gpio_read_raw_reg(unsigned long reg,
	35	unsigned long reg_width)
	36	{
	37	switch (reg_width) {
	38	case 8:
9cdae914	39	return __raw_readb(reg);
3292094e	40	case 16:
9cdae914	41	return __raw_readw(reg);
3292094e	42	case 32:
9cdae914	43	return __raw_readl(reg);
3292094e MD	44	}
	45
	46	BUG();
	47	return 0;
	48	}
	49
	50	static void gpio_write_raw_reg(unsigned long reg,
	51	unsigned long reg_width,
	52	unsigned long data)
	53	{
	54	switch (reg_width) {
	55	case 8:
9cdae914	56	__raw_writeb(data, reg);
3292094e MD	57	return;
3292094e MD	58	case 16:
9cdae914	59	__raw_writew(data, reg);
3292094e MD	60	return;
3292094e MD	61	case 32:
9cdae914	62	__raw_writel(data, reg);
3292094e MD	63	return;
	64	}
	65
	66	BUG();
	67	}
	68
	69	static void gpio_write_bit(struct pinmux_data_reg *dr,
	70	unsigned long in_pos, unsigned long value)
	71	{
	72	unsigned long pos;
	73
	74	pos = dr->reg_width - (in_pos + 1);
	75
ca6f2d7f	76	pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
fd2cb0ce PM	77	"r_width = %ld\n",
fd2cb0ce PM	78	dr->reg, !!value, pos, dr->reg_width);
3292094e MD	79
	80	if (value)
	81	set_bit(pos, &dr->reg_shadow);
	82	else
	83	clear_bit(pos, &dr->reg_shadow);
	84
	85	gpio_write_raw_reg(dr->reg, dr->reg_width, dr->reg_shadow);
	86	}
	87
0fc64cc0 MD	88	static int gpio_read_reg(unsigned long reg, unsigned long reg_width,
0fc64cc0 MD	89	unsigned long field_width, unsigned long in_pos)
2967dab1 MD	90	{
	91	unsigned long data, mask, pos;
	92
	93	data = 0;
	94	mask = (1 << field_width) - 1;
	95	pos = reg_width - ((in_pos + 1) * field_width);
	96
fd2cb0ce PM	97	pr_debug("read_reg: addr = %lx, pos = %ld, "
	98	"r_width = %ld, f_width = %ld\n",
	99	reg, pos, reg_width, field_width);
2967dab1	100
3292094e	101	data = gpio_read_raw_reg(reg, reg_width);
0fc64cc0 MD	102	return (data >> pos) & mask;
	103	}
	104
	105	static void gpio_write_reg(unsigned long reg, unsigned long reg_width,
	106	unsigned long field_width, unsigned long in_pos,
	107	unsigned long value)
	108	{
	109	unsigned long mask, pos;
	110
	111	mask = (1 << field_width) - 1;
	112	pos = reg_width - ((in_pos + 1) * field_width);
2967dab1	113
fd2cb0ce PM	114	pr_debug("write_reg addr = %lx, value = %ld, pos = %ld, "
	115	"r_width = %ld, f_width = %ld\n",
	116	reg, value, pos, reg_width, field_width);
0fc64cc0 MD	117
	118	mask = ~(mask << pos);
	119	value = value << pos;
2967dab1 MD	120
	121	switch (reg_width) {
	122	case 8:
9cdae914	123	__raw_writeb((__raw_readb(reg) & mask) \| value, reg);
2967dab1 MD	124	break;
2967dab1 MD	125	case 16:
9cdae914	126	__raw_writew((__raw_readw(reg) & mask) \| value, reg);
2967dab1 MD	127	break;
2967dab1 MD	128	case 32:
9cdae914	129	__raw_writel((__raw_readl(reg) & mask) \| value, reg);
2967dab1 MD	130	break;
2967dab1 MD	131	}
2967dab1 MD	132	}
2967dab1 MD	133
18801be7	134	static int setup_data_reg(struct pinmux_info *gpioc, unsigned gpio)
2967dab1	135	{
18801be7	136	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
2967dab1 MD	137	struct pinmux_data_reg *data_reg;
	138	int k, n;
	139
18801be7	140	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
2967dab1 MD	141	return -1;
	142
	143	k = 0;
	144	while (1) {
	145	data_reg = gpioc->data_regs + k;
	146
	147	if (!data_reg->reg_width)
	148	break;
	149
	150	for (n = 0; n < data_reg->reg_width; n++) {
18801be7 MD	151	if (data_reg->enum_ids[n] == gpiop->enum_id) {
	152	gpiop->flags &= ~PINMUX_FLAG_DREG;
	153	gpiop->flags \|= (k << PINMUX_FLAG_DREG_SHIFT);
	154	gpiop->flags &= ~PINMUX_FLAG_DBIT;
	155	gpiop->flags \|= (n << PINMUX_FLAG_DBIT_SHIFT);
2967dab1	156	return 0;
2967dab1 MD	157	}
	158	}
	159	k++;
	160	}
	161
18801be7 MD	162	BUG();
18801be7 MD	163
2967dab1 MD	164	return -1;
	165	}
	166
3292094e MD	167	static void setup_data_regs(struct pinmux_info *gpioc)
	168	{
	169	struct pinmux_data_reg *drp;
	170	int k;
	171
	172	for (k = gpioc->first_gpio; k <= gpioc->last_gpio; k++)
	173	setup_data_reg(gpioc, k);
	174
	175	k = 0;
	176	while (1) {
	177	drp = gpioc->data_regs + k;
	178
	179	if (!drp->reg_width)
	180	break;
	181
	182	drp->reg_shadow = gpio_read_raw_reg(drp->reg, drp->reg_width);
	183	k++;
	184	}
	185	}
	186
18801be7 MD	187	static int get_data_reg(struct pinmux_info *gpioc, unsigned gpio,
	188	struct pinmux_data_reg *drp, int bitp)
	189	{
	190	struct pinmux_gpio *gpiop = &gpioc->gpios[gpio];
	191	int k, n;
	192
	193	if (!enum_in_range(gpiop->enum_id, &gpioc->data))
	194	return -1;
	195
	196	k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
	197	n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
	198	*drp = gpioc->data_regs + k;
	199	*bitp = n;
	200	return 0;
	201	}
	202
2967dab1 MD	203	static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
	204	struct pinmux_cfg_reg *crp, int indexp,
	205	unsigned long **cntp)
	206	{
	207	struct pinmux_cfg_reg *config_reg;
	208	unsigned long r_width, f_width;
	209	int k, n;
	210
	211	k = 0;
	212	while (1) {
	213	config_reg = gpioc->cfg_regs + k;
	214
	215	r_width = config_reg->reg_width;
	216	f_width = config_reg->field_width;
	217
	218	if (!r_width)
	219	break;
	220	for (n = 0; n < (r_width / f_width) * 1 << f_width; n++) {
	221	if (config_reg->enum_ids[n] == enum_id) {
	222	*crp = config_reg;
	223	*indexp = n;
	224	*cntp = &config_reg->cnt[n / (1 << f_width)];
	225	return 0;
	226	}
	227	}
	228	k++;
	229	}
	230
	231	return -1;
	232	}
	233
	234	static int get_gpio_enum_id(struct pinmux_info *gpioc, unsigned gpio,
	235	int pos, pinmux_enum_t *enum_idp)
	236	{
	237	pinmux_enum_t enum_id = gpioc->gpios[gpio].enum_id;
	238	pinmux_enum_t *data = gpioc->gpio_data;
	239	int k;
	240
	241	if (!enum_in_range(enum_id, &gpioc->data)) {
	242	if (!enum_in_range(enum_id, &gpioc->mark)) {
	243	pr_err("non data/mark enum_id for gpio %d\n", gpio);
	244	return -1;
	245	}
	246	}
	247
	248	if (pos) {
	249	*enum_idp = data[pos + 1];
	250	return pos + 1;
	251	}
	252
	253	for (k = 0; k < gpioc->gpio_data_size; k++) {
	254	if (data[k] == enum_id) {
	255	*enum_idp = data[k + 1];
	256	return k + 1;
	257	}
	258	}
	259
	260	pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio);
	261	return -1;
	262	}
	263
0fc64cc0 MD	264	static void write_config_reg(struct pinmux_info *gpioc,
	265	struct pinmux_cfg_reg *crp,
	266	int index)
2967dab1 MD	267	{
	268	unsigned long ncomb, pos, value;
	269
	270	ncomb = 1 << crp->field_width;
	271	pos = index / ncomb;
	272	value = index % ncomb;
	273
0fc64cc0	274	gpio_write_reg(crp->reg, crp->reg_width, crp->field_width, pos, value);
2967dab1 MD	275	}
	276
	277	static int check_config_reg(struct pinmux_info *gpioc,
	278	struct pinmux_cfg_reg *crp,
	279	int index)
	280	{
	281	unsigned long ncomb, pos, value;
	282
	283	ncomb = 1 << crp->field_width;
	284	pos = index / ncomb;
	285	value = index % ncomb;
	286
0fc64cc0 MD	287	if (gpio_read_reg(crp->reg, crp->reg_width,
0fc64cc0 MD	288	crp->field_width, pos) == value)
2967dab1 MD	289	return 0;
	290
	291	return -1;
	292	}
	293
	294	enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
	295
0fc64cc0 MD	296	static int pinmux_config_gpio(struct pinmux_info *gpioc, unsigned gpio,
0fc64cc0 MD	297	int pinmux_type, int cfg_mode)
2967dab1 MD	298	{
	299	struct pinmux_cfg_reg *cr = NULL;
	300	pinmux_enum_t enum_id;
	301	struct pinmux_range *range;
	302	int in_range, pos, index;
	303	unsigned long *cntp;
	304
	305	switch (pinmux_type) {
	306
	307	case PINMUX_TYPE_FUNCTION:
	308	range = NULL;
	309	break;
	310
	311	case PINMUX_TYPE_OUTPUT:
	312	range = &gpioc->output;
	313	break;
	314
	315	case PINMUX_TYPE_INPUT:
	316	range = &gpioc->input;
	317	break;
	318
	319	case PINMUX_TYPE_INPUT_PULLUP:
	320	range = &gpioc->input_pu;
	321	break;
	322
	323	case PINMUX_TYPE_INPUT_PULLDOWN:
	324	range = &gpioc->input_pd;
	325	break;
	326
	327	default:
	328	goto out_err;
	329	}
	330
	331	pos = 0;
	332	enum_id = 0;
	333	index = 0;
	334	while (1) {
	335	pos = get_gpio_enum_id(gpioc, gpio, pos, &enum_id);
	336	if (pos <= 0)
	337	goto out_err;
	338
	339	if (!enum_id)
	340	break;
	341
50dd3145	342	/* first check if this is a function enum */
2967dab1	343	in_range = enum_in_range(enum_id, &gpioc->function);
50dd3145 MD	344	if (!in_range) {
	345	/* not a function enum */
	346	if (range) {
	347	/*
	348	* other range exists, so this pin is
	349	* a regular GPIO pin that now is being
	350	* bound to a specific direction.
	351	*
	352	* for this case we only allow function enums
	353	* and the enums that match the other range.
	354	*/
	355	in_range = enum_in_range(enum_id, range);
	356
	357	/*
	358	* special case pass through for fixed
	359	* input-only or output-only pins without
	360	* function enum register association.
	361	*/
	362	if (in_range && enum_id == range->force)
	363	continue;
	364	} else {
	365	/*
	366	* no other range exists, so this pin
	367	* must then be of the function type.
	368	*
	369	* allow function type pins to select
	370	* any combination of function/in/out
	371	* in their MARK lists.
	372	*/
	373	in_range = 1;
	374	}
42eed42b MD	375	}
42eed42b MD	376
2967dab1 MD	377	if (!in_range)
	378	continue;
	379
	380	if (get_config_reg(gpioc, enum_id, &cr, &index, &cntp) != 0)
	381	goto out_err;
	382
	383	switch (cfg_mode) {
	384	case GPIO_CFG_DRYRUN:
	385	if (!*cntp \|\| !check_config_reg(gpioc, cr, index))
	386	continue;
	387	break;
	388
	389	case GPIO_CFG_REQ:
0fc64cc0	390	write_config_reg(gpioc, cr, index);
2967dab1 MD	391	cntp = cntp + 1;
	392	break;
	393
	394	case GPIO_CFG_FREE:
	395	cntp = cntp - 1;
	396	break;
	397	}
	398	}
	399
	400	return 0;
	401	out_err:
	402	return -1;
	403	}
	404
	405	static DEFINE_SPINLOCK(gpio_lock);
	406
69edbba0	407	static struct pinmux_info chip_to_pinmux(struct gpio_chip chip)
2967dab1	408	{
69edbba0 MD	409	return container_of(chip, struct pinmux_info, chip);
	410	}
	411
	412	static int sh_gpio_request(struct gpio_chip *chip, unsigned offset)
	413	{
	414	struct pinmux_info *gpioc = chip_to_pinmux(chip);
2967dab1 MD	415	struct pinmux_data_reg *dummy;
	416	unsigned long flags;
	417	int i, ret, pinmux_type;
	418
	419	ret = -EINVAL;
	420
	421	if (!gpioc)
	422	goto err_out;
	423
	424	spin_lock_irqsave(&gpio_lock, flags);
	425
69edbba0	426	if ((gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE) != PINMUX_TYPE_NONE)
2967dab1 MD	427	goto err_unlock;
	428
	429	/* setup pin function here if no data is associated with pin */
	430
69edbba0	431	if (get_data_reg(gpioc, offset, &dummy, &i) != 0)
2967dab1 MD	432	pinmux_type = PINMUX_TYPE_FUNCTION;
	433	else
	434	pinmux_type = PINMUX_TYPE_GPIO;
	435
	436	if (pinmux_type == PINMUX_TYPE_FUNCTION) {
69edbba0	437	if (pinmux_config_gpio(gpioc, offset,
2967dab1 MD	438	pinmux_type,
	439	GPIO_CFG_DRYRUN) != 0)
	440	goto err_unlock;
	441
69edbba0	442	if (pinmux_config_gpio(gpioc, offset,
2967dab1 MD	443	pinmux_type,
	444	GPIO_CFG_REQ) != 0)
	445	BUG();
	446	}
	447
69edbba0 MD	448	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
69edbba0 MD	449	gpioc->gpios[offset].flags \|= pinmux_type;
2967dab1 MD	450
	451	ret = 0;
	452	err_unlock:
	453	spin_unlock_irqrestore(&gpio_lock, flags);
	454	err_out:
	455	return ret;
	456	}
2967dab1	457
69edbba0	458	static void sh_gpio_free(struct gpio_chip *chip, unsigned offset)
2967dab1	459	{
69edbba0	460	struct pinmux_info *gpioc = chip_to_pinmux(chip);
2967dab1 MD	461	unsigned long flags;
	462	int pinmux_type;
	463
	464	if (!gpioc)
	465	return;
	466
	467	spin_lock_irqsave(&gpio_lock, flags);
	468
69edbba0 MD	469	pinmux_type = gpioc->gpios[offset].flags & PINMUX_FLAG_TYPE;
	470	pinmux_config_gpio(gpioc, offset, pinmux_type, GPIO_CFG_FREE);
	471	gpioc->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
	472	gpioc->gpios[offset].flags \|= PINMUX_TYPE_NONE;
2967dab1 MD	473
	474	spin_unlock_irqrestore(&gpio_lock, flags);
	475	}
2967dab1 MD	476
	477	static int pinmux_direction(struct pinmux_info *gpioc,
	478	unsigned gpio, int new_pinmux_type)
	479	{
0fc64cc0 MD	480	int pinmux_type;
	481	int ret = -EINVAL;
	482
	483	if (!gpioc)
	484	goto err_out;
2967dab1	485
2967dab1 MD	486	pinmux_type = gpioc->gpios[gpio].flags & PINMUX_FLAG_TYPE;
	487
	488	switch (pinmux_type) {
	489	case PINMUX_TYPE_GPIO:
	490	break;
	491	case PINMUX_TYPE_OUTPUT:
	492	case PINMUX_TYPE_INPUT:
	493	case PINMUX_TYPE_INPUT_PULLUP:
	494	case PINMUX_TYPE_INPUT_PULLDOWN:
	495	pinmux_config_gpio(gpioc, gpio, pinmux_type, GPIO_CFG_FREE);
	496	break;
	497	default:
	498	goto err_out;
	499	}
	500
	501	if (pinmux_config_gpio(gpioc, gpio,
	502	new_pinmux_type,
	503	GPIO_CFG_DRYRUN) != 0)
	504	goto err_out;
	505
	506	if (pinmux_config_gpio(gpioc, gpio,
	507	new_pinmux_type,
	508	GPIO_CFG_REQ) != 0)
	509	BUG();
	510
18801be7 MD	511	gpioc->gpios[gpio].flags &= ~PINMUX_FLAG_TYPE;
18801be7 MD	512	gpioc->gpios[gpio].flags \|= new_pinmux_type;
2967dab1 MD	513
	514	ret = 0;
	515	err_out:
	516	return ret;
	517	}
	518
69edbba0	519	static int sh_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
2967dab1	520	{
69edbba0	521	struct pinmux_info *gpioc = chip_to_pinmux(chip);
2967dab1	522	unsigned long flags;
0fc64cc0	523	int ret;
2967dab1 MD	524
2967dab1 MD	525	spin_lock_irqsave(&gpio_lock, flags);
69edbba0	526	ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_INPUT);
2967dab1	527	spin_unlock_irqrestore(&gpio_lock, flags);
0fc64cc0	528
2967dab1 MD	529	return ret;
2967dab1 MD	530	}
2967dab1	531
69edbba0	532	static void sh_gpio_set_value(struct pinmux_info *gpioc,
0fc64cc0	533	unsigned gpio, int value)
2967dab1 MD	534	{
	535	struct pinmux_data_reg *dr = NULL;
	536	int bit = 0;
	537
0fc64cc0	538	if (!gpioc \|\| get_data_reg(gpioc, gpio, &dr, &bit) != 0)
2967dab1 MD	539	BUG();
2967dab1 MD	540	else
3292094e	541	gpio_write_bit(dr, bit, value);
2967dab1 MD	542	}
2967dab1 MD	543
69edbba0 MD	544	static int sh_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
69edbba0 MD	545	int value)
2967dab1	546	{
69edbba0	547	struct pinmux_info *gpioc = chip_to_pinmux(chip);
2967dab1	548	unsigned long flags;
0fc64cc0	549	int ret;
2967dab1	550
69edbba0	551	sh_gpio_set_value(gpioc, offset, value);
3292094e	552	spin_lock_irqsave(&gpio_lock, flags);
69edbba0	553	ret = pinmux_direction(gpioc, offset, PINMUX_TYPE_OUTPUT);
2967dab1	554	spin_unlock_irqrestore(&gpio_lock, flags);
0fc64cc0	555
2967dab1 MD	556	return ret;
2967dab1 MD	557	}
2967dab1	558
69edbba0	559	static int sh_gpio_get_value(struct pinmux_info *gpioc, unsigned gpio)
2967dab1	560	{
0fc64cc0 MD	561	struct pinmux_data_reg *dr = NULL;
0fc64cc0 MD	562	int bit = 0;
2967dab1	563
e8184a47 PM	564	if (!gpioc \|\| get_data_reg(gpioc, gpio, &dr, &bit) != 0)
e8184a47 PM	565	return -EINVAL;
2967dab1	566
0fc64cc0 MD	567	return gpio_read_reg(dr->reg, dr->reg_width, 1, bit);
	568	}
	569
69edbba0	570	static int sh_gpio_get(struct gpio_chip *chip, unsigned offset)
0fc64cc0	571	{
69edbba0	572	return sh_gpio_get_value(chip_to_pinmux(chip), offset);
2967dab1	573	}
2967dab1	574
69edbba0	575	static void sh_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2967dab1	576	{
69edbba0	577	sh_gpio_set_value(chip_to_pinmux(chip), offset, value);
2967dab1	578	}
2967dab1 MD	579
	580	int register_pinmux(struct pinmux_info *pip)
	581	{
69edbba0 MD	582	struct gpio_chip *chip = &pip->chip;
69edbba0 MD	583
b72421d8	584	pr_info("%s handling gpio %d -> %d\n",
2967dab1 MD	585	pip->name, pip->first_gpio, pip->last_gpio);
2967dab1 MD	586
69edbba0 MD	587	setup_data_regs(pip);
	588
	589	chip->request = sh_gpio_request;
	590	chip->free = sh_gpio_free;
	591	chip->direction_input = sh_gpio_direction_input;
	592	chip->get = sh_gpio_get;
	593	chip->direction_output = sh_gpio_direction_output;
	594	chip->set = sh_gpio_set;
	595
	596	WARN_ON(pip->first_gpio != 0); /* needs testing */
	597
	598	chip->label = pip->name;
	599	chip->owner = THIS_MODULE;
	600	chip->base = pip->first_gpio;
	601	chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1;
	602
	603	return gpiochip_add(chip);
2967dab1	604	}
b72421d8 PM	605
	606	int unregister_pinmux(struct pinmux_info *pip)
	607	{
	608	pr_info("%s deregistering\n", pip->name);
	609
	610	return gpiochip_remove(&pip->chip);
	611	}