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Commit | Line | Data |
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02ab3f70 MD |
1 | /* |
2 | * Shared interrupt handling code for IPR and INTC2 types of IRQs. | |
3 | * | |
d58876e2 | 4 | * Copyright (C) 2007, 2008 Magnus Damm |
a8941dad | 5 | * Copyright (C) 2009, 2010 Paul Mundt |
02ab3f70 MD |
6 | * |
7 | * Based on intc2.c and ipr.c | |
8 | * | |
9 | * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi | |
10 | * Copyright (C) 2000 Kazumoto Kojima | |
11 | * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) | |
12 | * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> | |
13 | * Copyright (C) 2005, 2006 Paul Mundt | |
14 | * | |
15 | * This file is subject to the terms and conditions of the GNU General Public | |
16 | * License. See the file "COPYING" in the main directory of this archive | |
17 | * for more details. | |
18 | */ | |
ac422f94 PM |
19 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
20 | ||
02ab3f70 MD |
21 | #include <linux/init.h> |
22 | #include <linux/irq.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/io.h> | |
5a0e3ad6 | 25 | #include <linux/slab.h> |
02ab3f70 | 26 | #include <linux/interrupt.h> |
bbfbd8b1 | 27 | #include <linux/sh_intc.h> |
2dcec7a9 MD |
28 | #include <linux/sysdev.h> |
29 | #include <linux/list.h> | |
54ff328b | 30 | #include <linux/topology.h> |
1ce7b039 | 31 | #include <linux/bitmap.h> |
a8941dad | 32 | #include <linux/cpumask.h> |
43b8774d | 33 | #include <asm/sizes.h> |
73505b44 MD |
34 | |
35 | #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \ | |
36 | ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \ | |
37 | ((addr_e) << 16) | ((addr_d << 24))) | |
38 | ||
39 | #define _INTC_SHIFT(h) (h & 0x1f) | |
40 | #define _INTC_WIDTH(h) ((h >> 5) & 0xf) | |
41 | #define _INTC_FN(h) ((h >> 9) & 0xf) | |
42 | #define _INTC_MODE(h) ((h >> 13) & 0x7) | |
43 | #define _INTC_ADDR_E(h) ((h >> 16) & 0xff) | |
44 | #define _INTC_ADDR_D(h) ((h >> 24) & 0xff) | |
45 | ||
46 | struct intc_handle_int { | |
47 | unsigned int irq; | |
48 | unsigned long handle; | |
49 | }; | |
02ab3f70 | 50 | |
dec710b7 MD |
51 | struct intc_window { |
52 | phys_addr_t phys; | |
53 | void __iomem *virt; | |
54 | unsigned long size; | |
55 | }; | |
56 | ||
73505b44 | 57 | struct intc_desc_int { |
2dcec7a9 MD |
58 | struct list_head list; |
59 | struct sys_device sysdev; | |
7fd87b3f | 60 | pm_message_t state; |
73505b44 | 61 | unsigned long *reg; |
f18d533e MD |
62 | #ifdef CONFIG_SMP |
63 | unsigned long *smp; | |
64 | #endif | |
73505b44 MD |
65 | unsigned int nr_reg; |
66 | struct intc_handle_int *prio; | |
67 | unsigned int nr_prio; | |
68 | struct intc_handle_int *sense; | |
69 | unsigned int nr_sense; | |
dec710b7 MD |
70 | struct intc_window *window; |
71 | unsigned int nr_windows; | |
73505b44 MD |
72 | struct irq_chip chip; |
73 | }; | |
02ab3f70 | 74 | |
2dcec7a9 MD |
75 | static LIST_HEAD(intc_list); |
76 | ||
1ce7b039 PM |
77 | /* |
78 | * The intc_irq_map provides a global map of bound IRQ vectors for a | |
79 | * given platform. Allocation of IRQs are either static through the CPU | |
80 | * vector map, or dynamic in the case of board mux vectors or MSI. | |
81 | * | |
82 | * As this is a central point for all IRQ controllers on the system, | |
83 | * each of the available sources are mapped out here. This combined with | |
84 | * sparseirq makes it quite trivial to keep the vector map tightly packed | |
85 | * when dynamically creating IRQs, as well as tying in to otherwise | |
86 | * unused irq_desc positions in the sparse array. | |
87 | */ | |
88 | static DECLARE_BITMAP(intc_irq_map, NR_IRQS); | |
89 | static DEFINE_SPINLOCK(vector_lock); | |
90 | ||
f18d533e MD |
91 | #ifdef CONFIG_SMP |
92 | #define IS_SMP(x) x.smp | |
93 | #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c)) | |
94 | #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1) | |
95 | #else | |
96 | #define IS_SMP(x) 0 | |
97 | #define INTC_REG(d, x, c) (d->reg[(x)]) | |
98 | #define SMP_NR(d, x) 1 | |
99 | #endif | |
100 | ||
43b8774d PM |
101 | static unsigned int intc_prio_level[NR_IRQS]; /* for now */ |
102 | static unsigned int default_prio_level = 2; /* 2 - 16 */ | |
d58876e2 | 103 | static unsigned long ack_handle[NR_IRQS]; |
dc825b17 PM |
104 | #ifdef CONFIG_INTC_BALANCING |
105 | static unsigned long dist_handle[NR_IRQS]; | |
106 | #endif | |
02ab3f70 | 107 | |
73505b44 | 108 | static inline struct intc_desc_int *get_intc_desc(unsigned int irq) |
02ab3f70 MD |
109 | { |
110 | struct irq_chip *chip = get_irq_chip(irq); | |
6000fc4d | 111 | return container_of(chip, struct intc_desc_int, chip); |
02ab3f70 MD |
112 | } |
113 | ||
dc825b17 PM |
114 | static unsigned long intc_phys_to_virt(struct intc_desc_int *d, |
115 | unsigned long address) | |
116 | { | |
117 | struct intc_window *window; | |
118 | int k; | |
119 | ||
120 | /* scan through physical windows and convert address */ | |
121 | for (k = 0; k < d->nr_windows; k++) { | |
122 | window = d->window + k; | |
123 | ||
124 | if (address < window->phys) | |
125 | continue; | |
126 | ||
127 | if (address >= (window->phys + window->size)) | |
128 | continue; | |
129 | ||
130 | address -= window->phys; | |
131 | address += (unsigned long)window->virt; | |
132 | ||
133 | return address; | |
134 | } | |
135 | ||
136 | /* no windows defined, register must be 1:1 mapped virt:phys */ | |
137 | return address; | |
138 | } | |
139 | ||
140 | static unsigned int intc_get_reg(struct intc_desc_int *d, unsigned long address) | |
141 | { | |
142 | unsigned int k; | |
143 | ||
144 | address = intc_phys_to_virt(d, address); | |
145 | ||
146 | for (k = 0; k < d->nr_reg; k++) { | |
147 | if (d->reg[k] == address) | |
148 | return k; | |
149 | } | |
150 | ||
151 | BUG(); | |
152 | return 0; | |
153 | } | |
154 | ||
02ab3f70 MD |
155 | static inline unsigned int set_field(unsigned int value, |
156 | unsigned int field_value, | |
73505b44 | 157 | unsigned int handle) |
02ab3f70 | 158 | { |
73505b44 MD |
159 | unsigned int width = _INTC_WIDTH(handle); |
160 | unsigned int shift = _INTC_SHIFT(handle); | |
161 | ||
02ab3f70 MD |
162 | value &= ~(((1 << width) - 1) << shift); |
163 | value |= field_value << shift; | |
164 | return value; | |
165 | } | |
166 | ||
73505b44 | 167 | static void write_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 168 | { |
62429e03 | 169 | __raw_writeb(set_field(0, data, h), addr); |
6000fc4d | 170 | (void)__raw_readb(addr); /* Defeat write posting */ |
02ab3f70 MD |
171 | } |
172 | ||
73505b44 | 173 | static void write_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 174 | { |
62429e03 | 175 | __raw_writew(set_field(0, data, h), addr); |
6000fc4d | 176 | (void)__raw_readw(addr); /* Defeat write posting */ |
02ab3f70 MD |
177 | } |
178 | ||
73505b44 | 179 | static void write_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 180 | { |
62429e03 | 181 | __raw_writel(set_field(0, data, h), addr); |
6000fc4d | 182 | (void)__raw_readl(addr); /* Defeat write posting */ |
02ab3f70 MD |
183 | } |
184 | ||
73505b44 | 185 | static void modify_8(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 186 | { |
4370fe1c MD |
187 | unsigned long flags; |
188 | local_irq_save(flags); | |
62429e03 | 189 | __raw_writeb(set_field(__raw_readb(addr), data, h), addr); |
6000fc4d | 190 | (void)__raw_readb(addr); /* Defeat write posting */ |
4370fe1c | 191 | local_irq_restore(flags); |
02ab3f70 MD |
192 | } |
193 | ||
73505b44 | 194 | static void modify_16(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 195 | { |
4370fe1c MD |
196 | unsigned long flags; |
197 | local_irq_save(flags); | |
62429e03 | 198 | __raw_writew(set_field(__raw_readw(addr), data, h), addr); |
6000fc4d | 199 | (void)__raw_readw(addr); /* Defeat write posting */ |
4370fe1c | 200 | local_irq_restore(flags); |
02ab3f70 MD |
201 | } |
202 | ||
73505b44 | 203 | static void modify_32(unsigned long addr, unsigned long h, unsigned long data) |
02ab3f70 | 204 | { |
4370fe1c MD |
205 | unsigned long flags; |
206 | local_irq_save(flags); | |
62429e03 | 207 | __raw_writel(set_field(__raw_readl(addr), data, h), addr); |
6000fc4d | 208 | (void)__raw_readl(addr); /* Defeat write posting */ |
4370fe1c | 209 | local_irq_restore(flags); |
02ab3f70 MD |
210 | } |
211 | ||
73505b44 MD |
212 | enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 }; |
213 | ||
214 | static void (*intc_reg_fns[])(unsigned long addr, | |
215 | unsigned long h, | |
216 | unsigned long data) = { | |
217 | [REG_FN_WRITE_BASE + 0] = write_8, | |
218 | [REG_FN_WRITE_BASE + 1] = write_16, | |
219 | [REG_FN_WRITE_BASE + 3] = write_32, | |
220 | [REG_FN_MODIFY_BASE + 0] = modify_8, | |
221 | [REG_FN_MODIFY_BASE + 1] = modify_16, | |
222 | [REG_FN_MODIFY_BASE + 3] = modify_32, | |
223 | }; | |
02ab3f70 | 224 | |
73505b44 MD |
225 | enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */ |
226 | MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */ | |
227 | MODE_DUAL_REG, /* Two registers, set bit to enable / disable */ | |
228 | MODE_PRIO_REG, /* Priority value written to enable interrupt */ | |
229 | MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */ | |
230 | }; | |
02ab3f70 | 231 | |
73505b44 MD |
232 | static void intc_mode_field(unsigned long addr, |
233 | unsigned long handle, | |
234 | void (*fn)(unsigned long, | |
235 | unsigned long, | |
236 | unsigned long), | |
237 | unsigned int irq) | |
02ab3f70 | 238 | { |
73505b44 | 239 | fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1)); |
02ab3f70 MD |
240 | } |
241 | ||
73505b44 MD |
242 | static void intc_mode_zero(unsigned long addr, |
243 | unsigned long handle, | |
244 | void (*fn)(unsigned long, | |
245 | unsigned long, | |
246 | unsigned long), | |
247 | unsigned int irq) | |
51da6426 | 248 | { |
73505b44 | 249 | fn(addr, handle, 0); |
51da6426 MD |
250 | } |
251 | ||
73505b44 MD |
252 | static void intc_mode_prio(unsigned long addr, |
253 | unsigned long handle, | |
254 | void (*fn)(unsigned long, | |
255 | unsigned long, | |
256 | unsigned long), | |
257 | unsigned int irq) | |
51da6426 | 258 | { |
73505b44 | 259 | fn(addr, handle, intc_prio_level[irq]); |
51da6426 MD |
260 | } |
261 | ||
73505b44 MD |
262 | static void (*intc_enable_fns[])(unsigned long addr, |
263 | unsigned long handle, | |
264 | void (*fn)(unsigned long, | |
265 | unsigned long, | |
266 | unsigned long), | |
267 | unsigned int irq) = { | |
268 | [MODE_ENABLE_REG] = intc_mode_field, | |
269 | [MODE_MASK_REG] = intc_mode_zero, | |
270 | [MODE_DUAL_REG] = intc_mode_field, | |
271 | [MODE_PRIO_REG] = intc_mode_prio, | |
272 | [MODE_PCLR_REG] = intc_mode_prio, | |
273 | }; | |
51da6426 | 274 | |
73505b44 MD |
275 | static void (*intc_disable_fns[])(unsigned long addr, |
276 | unsigned long handle, | |
277 | void (*fn)(unsigned long, | |
278 | unsigned long, | |
279 | unsigned long), | |
280 | unsigned int irq) = { | |
281 | [MODE_ENABLE_REG] = intc_mode_zero, | |
282 | [MODE_MASK_REG] = intc_mode_field, | |
283 | [MODE_DUAL_REG] = intc_mode_field, | |
284 | [MODE_PRIO_REG] = intc_mode_zero, | |
285 | [MODE_PCLR_REG] = intc_mode_field, | |
286 | }; | |
51da6426 | 287 | |
dc825b17 PM |
288 | #ifdef CONFIG_INTC_BALANCING |
289 | static inline void intc_balancing_enable(unsigned int irq) | |
290 | { | |
291 | struct intc_desc_int *d = get_intc_desc(irq); | |
292 | unsigned long handle = dist_handle[irq]; | |
293 | unsigned long addr; | |
294 | ||
295 | if (irq_balancing_disabled(irq) || !handle) | |
296 | return; | |
297 | ||
298 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
299 | intc_reg_fns[_INTC_FN(handle)](addr, handle, 1); | |
300 | } | |
301 | ||
302 | static inline void intc_balancing_disable(unsigned int irq) | |
303 | { | |
304 | struct intc_desc_int *d = get_intc_desc(irq); | |
305 | unsigned long handle = dist_handle[irq]; | |
306 | unsigned long addr; | |
307 | ||
308 | if (irq_balancing_disabled(irq) || !handle) | |
309 | return; | |
310 | ||
311 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
312 | intc_reg_fns[_INTC_FN(handle)](addr, handle, 0); | |
313 | } | |
314 | ||
315 | static unsigned int intc_dist_data(struct intc_desc *desc, | |
316 | struct intc_desc_int *d, | |
317 | intc_enum enum_id) | |
318 | { | |
319 | struct intc_mask_reg *mr = desc->hw.mask_regs; | |
320 | unsigned int i, j, fn, mode; | |
321 | unsigned long reg_e, reg_d; | |
322 | ||
323 | for (i = 0; mr && enum_id && i < desc->hw.nr_mask_regs; i++) { | |
324 | mr = desc->hw.mask_regs + i; | |
325 | ||
326 | /* | |
327 | * Skip this entry if there's no auto-distribution | |
328 | * register associated with it. | |
329 | */ | |
330 | if (!mr->dist_reg) | |
331 | continue; | |
332 | ||
333 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
334 | if (mr->enum_ids[j] != enum_id) | |
335 | continue; | |
336 | ||
337 | fn = REG_FN_MODIFY_BASE; | |
338 | mode = MODE_ENABLE_REG; | |
339 | reg_e = mr->dist_reg; | |
340 | reg_d = mr->dist_reg; | |
341 | ||
342 | fn += (mr->reg_width >> 3) - 1; | |
343 | return _INTC_MK(fn, mode, | |
344 | intc_get_reg(d, reg_e), | |
345 | intc_get_reg(d, reg_d), | |
346 | 1, | |
347 | (mr->reg_width - 1) - j); | |
348 | } | |
349 | } | |
350 | ||
351 | /* | |
352 | * It's possible we've gotten here with no distribution options | |
353 | * available for the IRQ in question, so we just skip over those. | |
354 | */ | |
355 | return 0; | |
356 | } | |
357 | #else | |
358 | static inline void intc_balancing_enable(unsigned int irq) | |
359 | { | |
360 | } | |
361 | ||
362 | static inline void intc_balancing_disable(unsigned int irq) | |
363 | { | |
364 | } | |
365 | #endif | |
366 | ||
73505b44 | 367 | static inline void _intc_enable(unsigned int irq, unsigned long handle) |
51da6426 | 368 | { |
73505b44 | 369 | struct intc_desc_int *d = get_intc_desc(irq); |
f18d533e MD |
370 | unsigned long addr; |
371 | unsigned int cpu; | |
51da6426 | 372 | |
f18d533e | 373 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { |
a8941dad PM |
374 | #ifdef CONFIG_SMP |
375 | if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity)) | |
376 | continue; | |
377 | #endif | |
f18d533e MD |
378 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); |
379 | intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\ | |
380 | [_INTC_FN(handle)], irq); | |
381 | } | |
dc825b17 PM |
382 | |
383 | intc_balancing_enable(irq); | |
51da6426 MD |
384 | } |
385 | ||
02ab3f70 MD |
386 | static void intc_enable(unsigned int irq) |
387 | { | |
73505b44 | 388 | _intc_enable(irq, (unsigned long)get_irq_chip_data(irq)); |
02ab3f70 MD |
389 | } |
390 | ||
391 | static void intc_disable(unsigned int irq) | |
392 | { | |
f18d533e | 393 | struct intc_desc_int *d = get_intc_desc(irq); |
dc825b17 | 394 | unsigned long handle = (unsigned long)get_irq_chip_data(irq); |
f18d533e MD |
395 | unsigned long addr; |
396 | unsigned int cpu; | |
02ab3f70 | 397 | |
dc825b17 PM |
398 | intc_balancing_disable(irq); |
399 | ||
f18d533e | 400 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { |
a8941dad PM |
401 | #ifdef CONFIG_SMP |
402 | if (!cpumask_test_cpu(cpu, irq_to_desc(irq)->affinity)) | |
403 | continue; | |
404 | #endif | |
f18d533e MD |
405 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); |
406 | intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\ | |
407 | [_INTC_FN(handle)], irq); | |
408 | } | |
02ab3f70 MD |
409 | } |
410 | ||
d5190953 MD |
411 | static void (*intc_enable_noprio_fns[])(unsigned long addr, |
412 | unsigned long handle, | |
413 | void (*fn)(unsigned long, | |
414 | unsigned long, | |
415 | unsigned long), | |
416 | unsigned int irq) = { | |
417 | [MODE_ENABLE_REG] = intc_mode_field, | |
418 | [MODE_MASK_REG] = intc_mode_zero, | |
419 | [MODE_DUAL_REG] = intc_mode_field, | |
420 | [MODE_PRIO_REG] = intc_mode_field, | |
421 | [MODE_PCLR_REG] = intc_mode_field, | |
422 | }; | |
423 | ||
424 | static void intc_enable_disable(struct intc_desc_int *d, | |
425 | unsigned long handle, int do_enable) | |
426 | { | |
427 | unsigned long addr; | |
428 | unsigned int cpu; | |
429 | void (*fn)(unsigned long, unsigned long, | |
430 | void (*)(unsigned long, unsigned long, unsigned long), | |
431 | unsigned int); | |
432 | ||
433 | if (do_enable) { | |
434 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) { | |
435 | addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu); | |
436 | fn = intc_enable_noprio_fns[_INTC_MODE(handle)]; | |
437 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | |
438 | } | |
439 | } else { | |
440 | for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) { | |
441 | addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu); | |
442 | fn = intc_disable_fns[_INTC_MODE(handle)]; | |
443 | fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0); | |
444 | } | |
445 | } | |
446 | } | |
447 | ||
2dcec7a9 MD |
448 | static int intc_set_wake(unsigned int irq, unsigned int on) |
449 | { | |
450 | return 0; /* allow wakeup, but setup hardware in intc_suspend() */ | |
451 | } | |
452 | ||
a8941dad PM |
453 | #ifdef CONFIG_SMP |
454 | /* | |
455 | * This is held with the irq desc lock held, so we don't require any | |
456 | * additional locking here at the intc desc level. The affinity mask is | |
457 | * later tested in the enable/disable paths. | |
458 | */ | |
459 | static int intc_set_affinity(unsigned int irq, const struct cpumask *cpumask) | |
460 | { | |
461 | if (!cpumask_intersects(cpumask, cpu_online_mask)) | |
462 | return -1; | |
463 | ||
464 | cpumask_copy(irq_to_desc(irq)->affinity, cpumask); | |
465 | ||
466 | return 0; | |
467 | } | |
468 | #endif | |
469 | ||
d58876e2 MD |
470 | static void intc_mask_ack(unsigned int irq) |
471 | { | |
472 | struct intc_desc_int *d = get_intc_desc(irq); | |
473 | unsigned long handle = ack_handle[irq]; | |
474 | unsigned long addr; | |
475 | ||
476 | intc_disable(irq); | |
477 | ||
dc825b17 | 478 | /* read register and write zero only to the associated bit */ |
d58876e2 MD |
479 | if (handle) { |
480 | addr = INTC_REG(d, _INTC_ADDR_D(handle), 0); | |
6bdfb22a YS |
481 | switch (_INTC_FN(handle)) { |
482 | case REG_FN_MODIFY_BASE + 0: /* 8bit */ | |
62429e03 PM |
483 | __raw_readb(addr); |
484 | __raw_writeb(0xff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
485 | break; |
486 | case REG_FN_MODIFY_BASE + 1: /* 16bit */ | |
62429e03 PM |
487 | __raw_readw(addr); |
488 | __raw_writew(0xffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
489 | break; |
490 | case REG_FN_MODIFY_BASE + 3: /* 32bit */ | |
62429e03 PM |
491 | __raw_readl(addr); |
492 | __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr); | |
6bdfb22a YS |
493 | break; |
494 | default: | |
495 | BUG(); | |
496 | break; | |
497 | } | |
d58876e2 MD |
498 | } |
499 | } | |
d58876e2 | 500 | |
73505b44 MD |
501 | static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp, |
502 | unsigned int nr_hp, | |
503 | unsigned int irq) | |
02ab3f70 | 504 | { |
73505b44 MD |
505 | int i; |
506 | ||
dc825b17 PM |
507 | /* |
508 | * this doesn't scale well, but... | |
3d37d94e MD |
509 | * |
510 | * this function should only be used for cerain uncommon | |
511 | * operations such as intc_set_priority() and intc_set_sense() | |
512 | * and in those rare cases performance doesn't matter that much. | |
513 | * keeping the memory footprint low is more important. | |
514 | * | |
515 | * one rather simple way to speed this up and still keep the | |
516 | * memory footprint down is to make sure the array is sorted | |
517 | * and then perform a bisect to lookup the irq. | |
518 | */ | |
73505b44 MD |
519 | for (i = 0; i < nr_hp; i++) { |
520 | if ((hp + i)->irq != irq) | |
521 | continue; | |
522 | ||
523 | return hp + i; | |
524 | } | |
02ab3f70 | 525 | |
73505b44 | 526 | return NULL; |
02ab3f70 MD |
527 | } |
528 | ||
73505b44 | 529 | int intc_set_priority(unsigned int irq, unsigned int prio) |
02ab3f70 | 530 | { |
73505b44 MD |
531 | struct intc_desc_int *d = get_intc_desc(irq); |
532 | struct intc_handle_int *ihp; | |
533 | ||
534 | if (!intc_prio_level[irq] || prio <= 1) | |
535 | return -EINVAL; | |
536 | ||
537 | ihp = intc_find_irq(d->prio, d->nr_prio, irq); | |
538 | if (ihp) { | |
3d37d94e | 539 | if (prio >= (1 << _INTC_WIDTH(ihp->handle))) |
73505b44 | 540 | return -EINVAL; |
02ab3f70 | 541 | |
73505b44 MD |
542 | intc_prio_level[irq] = prio; |
543 | ||
544 | /* | |
545 | * only set secondary masking method directly | |
546 | * primary masking method is using intc_prio_level[irq] | |
547 | * priority level will be set during next enable() | |
548 | */ | |
3d37d94e | 549 | if (_INTC_FN(ihp->handle) != REG_FN_ERR) |
73505b44 MD |
550 | _intc_enable(irq, ihp->handle); |
551 | } | |
552 | return 0; | |
02ab3f70 MD |
553 | } |
554 | ||
555 | #define VALID(x) (x | 0x80) | |
556 | ||
557 | static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { | |
558 | [IRQ_TYPE_EDGE_FALLING] = VALID(0), | |
559 | [IRQ_TYPE_EDGE_RISING] = VALID(1), | |
560 | [IRQ_TYPE_LEVEL_LOW] = VALID(2), | |
720be990 MD |
561 | /* SH7706, SH7707 and SH7709 do not support high level triggered */ |
562 | #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \ | |
563 | !defined(CONFIG_CPU_SUBTYPE_SH7707) && \ | |
564 | !defined(CONFIG_CPU_SUBTYPE_SH7709) | |
02ab3f70 | 565 | [IRQ_TYPE_LEVEL_HIGH] = VALID(3), |
720be990 | 566 | #endif |
02ab3f70 MD |
567 | }; |
568 | ||
569 | static int intc_set_sense(unsigned int irq, unsigned int type) | |
570 | { | |
73505b44 | 571 | struct intc_desc_int *d = get_intc_desc(irq); |
02ab3f70 | 572 | unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; |
73505b44 MD |
573 | struct intc_handle_int *ihp; |
574 | unsigned long addr; | |
02ab3f70 | 575 | |
73505b44 | 576 | if (!value) |
02ab3f70 MD |
577 | return -EINVAL; |
578 | ||
73505b44 MD |
579 | ihp = intc_find_irq(d->sense, d->nr_sense, irq); |
580 | if (ihp) { | |
f18d533e | 581 | addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0); |
73505b44 | 582 | intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value); |
02ab3f70 | 583 | } |
73505b44 | 584 | return 0; |
02ab3f70 MD |
585 | } |
586 | ||
73505b44 MD |
587 | static intc_enum __init intc_grp_id(struct intc_desc *desc, |
588 | intc_enum enum_id) | |
680c4598 | 589 | { |
577cd758 | 590 | struct intc_group *g = desc->hw.groups; |
680c4598 MD |
591 | unsigned int i, j; |
592 | ||
577cd758 MD |
593 | for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) { |
594 | g = desc->hw.groups + i; | |
680c4598 MD |
595 | |
596 | for (j = 0; g->enum_ids[j]; j++) { | |
597 | if (g->enum_ids[j] != enum_id) | |
598 | continue; | |
599 | ||
600 | return g->enum_id; | |
601 | } | |
602 | } | |
603 | ||
604 | return 0; | |
605 | } | |
606 | ||
d5190953 MD |
607 | static unsigned int __init _intc_mask_data(struct intc_desc *desc, |
608 | struct intc_desc_int *d, | |
609 | intc_enum enum_id, | |
610 | unsigned int *reg_idx, | |
611 | unsigned int *fld_idx) | |
02ab3f70 | 612 | { |
577cd758 | 613 | struct intc_mask_reg *mr = desc->hw.mask_regs; |
d5190953 | 614 | unsigned int fn, mode; |
73505b44 | 615 | unsigned long reg_e, reg_d; |
02ab3f70 | 616 | |
d5190953 MD |
617 | while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { |
618 | mr = desc->hw.mask_regs + *reg_idx; | |
02ab3f70 | 619 | |
d5190953 MD |
620 | for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) { |
621 | if (mr->enum_ids[*fld_idx] != enum_id) | |
02ab3f70 MD |
622 | continue; |
623 | ||
73505b44 MD |
624 | if (mr->set_reg && mr->clr_reg) { |
625 | fn = REG_FN_WRITE_BASE; | |
626 | mode = MODE_DUAL_REG; | |
627 | reg_e = mr->clr_reg; | |
628 | reg_d = mr->set_reg; | |
629 | } else { | |
630 | fn = REG_FN_MODIFY_BASE; | |
631 | if (mr->set_reg) { | |
632 | mode = MODE_ENABLE_REG; | |
633 | reg_e = mr->set_reg; | |
634 | reg_d = mr->set_reg; | |
635 | } else { | |
636 | mode = MODE_MASK_REG; | |
637 | reg_e = mr->clr_reg; | |
638 | reg_d = mr->clr_reg; | |
639 | } | |
51da6426 MD |
640 | } |
641 | ||
73505b44 MD |
642 | fn += (mr->reg_width >> 3) - 1; |
643 | return _INTC_MK(fn, mode, | |
644 | intc_get_reg(d, reg_e), | |
645 | intc_get_reg(d, reg_d), | |
646 | 1, | |
d5190953 | 647 | (mr->reg_width - 1) - *fld_idx); |
02ab3f70 | 648 | } |
d5190953 MD |
649 | |
650 | *fld_idx = 0; | |
651 | (*reg_idx)++; | |
02ab3f70 MD |
652 | } |
653 | ||
d5190953 MD |
654 | return 0; |
655 | } | |
656 | ||
657 | static unsigned int __init intc_mask_data(struct intc_desc *desc, | |
658 | struct intc_desc_int *d, | |
659 | intc_enum enum_id, int do_grps) | |
660 | { | |
661 | unsigned int i = 0; | |
662 | unsigned int j = 0; | |
663 | unsigned int ret; | |
664 | ||
665 | ret = _intc_mask_data(desc, d, enum_id, &i, &j); | |
666 | if (ret) | |
667 | return ret; | |
668 | ||
680c4598 | 669 | if (do_grps) |
73505b44 | 670 | return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0); |
680c4598 | 671 | |
02ab3f70 MD |
672 | return 0; |
673 | } | |
674 | ||
d5190953 MD |
675 | static unsigned int __init _intc_prio_data(struct intc_desc *desc, |
676 | struct intc_desc_int *d, | |
677 | intc_enum enum_id, | |
678 | unsigned int *reg_idx, | |
679 | unsigned int *fld_idx) | |
02ab3f70 | 680 | { |
577cd758 | 681 | struct intc_prio_reg *pr = desc->hw.prio_regs; |
d5190953 | 682 | unsigned int fn, n, mode, bit; |
73505b44 | 683 | unsigned long reg_e, reg_d; |
02ab3f70 | 684 | |
d5190953 MD |
685 | while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { |
686 | pr = desc->hw.prio_regs + *reg_idx; | |
02ab3f70 | 687 | |
d5190953 MD |
688 | for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) { |
689 | if (pr->enum_ids[*fld_idx] != enum_id) | |
02ab3f70 MD |
690 | continue; |
691 | ||
73505b44 MD |
692 | if (pr->set_reg && pr->clr_reg) { |
693 | fn = REG_FN_WRITE_BASE; | |
694 | mode = MODE_PCLR_REG; | |
695 | reg_e = pr->set_reg; | |
696 | reg_d = pr->clr_reg; | |
697 | } else { | |
698 | fn = REG_FN_MODIFY_BASE; | |
699 | mode = MODE_PRIO_REG; | |
700 | if (!pr->set_reg) | |
701 | BUG(); | |
702 | reg_e = pr->set_reg; | |
703 | reg_d = pr->set_reg; | |
704 | } | |
02ab3f70 | 705 | |
73505b44 | 706 | fn += (pr->reg_width >> 3) - 1; |
d5190953 | 707 | n = *fld_idx + 1; |
02ab3f70 | 708 | |
d5190953 | 709 | BUG_ON(n * pr->field_width > pr->reg_width); |
b21a9104 | 710 | |
d5190953 | 711 | bit = pr->reg_width - (n * pr->field_width); |
02ab3f70 | 712 | |
73505b44 MD |
713 | return _INTC_MK(fn, mode, |
714 | intc_get_reg(d, reg_e), | |
715 | intc_get_reg(d, reg_d), | |
716 | pr->field_width, bit); | |
02ab3f70 | 717 | } |
d5190953 MD |
718 | |
719 | *fld_idx = 0; | |
720 | (*reg_idx)++; | |
02ab3f70 MD |
721 | } |
722 | ||
d5190953 MD |
723 | return 0; |
724 | } | |
725 | ||
726 | static unsigned int __init intc_prio_data(struct intc_desc *desc, | |
727 | struct intc_desc_int *d, | |
728 | intc_enum enum_id, int do_grps) | |
729 | { | |
730 | unsigned int i = 0; | |
731 | unsigned int j = 0; | |
732 | unsigned int ret; | |
733 | ||
734 | ret = _intc_prio_data(desc, d, enum_id, &i, &j); | |
735 | if (ret) | |
736 | return ret; | |
737 | ||
680c4598 | 738 | if (do_grps) |
73505b44 MD |
739 | return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0); |
740 | ||
741 | return 0; | |
742 | } | |
743 | ||
d5190953 MD |
744 | static void __init intc_enable_disable_enum(struct intc_desc *desc, |
745 | struct intc_desc_int *d, | |
746 | intc_enum enum_id, int enable) | |
747 | { | |
748 | unsigned int i, j, data; | |
749 | ||
750 | /* go through and enable/disable all mask bits */ | |
751 | i = j = 0; | |
752 | do { | |
753 | data = _intc_mask_data(desc, d, enum_id, &i, &j); | |
754 | if (data) | |
755 | intc_enable_disable(d, data, enable); | |
756 | j++; | |
757 | } while (data); | |
758 | ||
759 | /* go through and enable/disable all priority fields */ | |
760 | i = j = 0; | |
761 | do { | |
762 | data = _intc_prio_data(desc, d, enum_id, &i, &j); | |
763 | if (data) | |
764 | intc_enable_disable(d, data, enable); | |
765 | ||
766 | j++; | |
767 | } while (data); | |
768 | } | |
769 | ||
d58876e2 MD |
770 | static unsigned int __init intc_ack_data(struct intc_desc *desc, |
771 | struct intc_desc_int *d, | |
772 | intc_enum enum_id) | |
773 | { | |
577cd758 | 774 | struct intc_mask_reg *mr = desc->hw.ack_regs; |
d58876e2 MD |
775 | unsigned int i, j, fn, mode; |
776 | unsigned long reg_e, reg_d; | |
777 | ||
577cd758 MD |
778 | for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) { |
779 | mr = desc->hw.ack_regs + i; | |
d58876e2 MD |
780 | |
781 | for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) { | |
782 | if (mr->enum_ids[j] != enum_id) | |
783 | continue; | |
784 | ||
785 | fn = REG_FN_MODIFY_BASE; | |
786 | mode = MODE_ENABLE_REG; | |
787 | reg_e = mr->set_reg; | |
788 | reg_d = mr->set_reg; | |
789 | ||
790 | fn += (mr->reg_width >> 3) - 1; | |
791 | return _INTC_MK(fn, mode, | |
792 | intc_get_reg(d, reg_e), | |
793 | intc_get_reg(d, reg_d), | |
794 | 1, | |
795 | (mr->reg_width - 1) - j); | |
796 | } | |
797 | } | |
798 | ||
799 | return 0; | |
800 | } | |
d58876e2 | 801 | |
73505b44 MD |
802 | static unsigned int __init intc_sense_data(struct intc_desc *desc, |
803 | struct intc_desc_int *d, | |
804 | intc_enum enum_id) | |
805 | { | |
577cd758 | 806 | struct intc_sense_reg *sr = desc->hw.sense_regs; |
73505b44 MD |
807 | unsigned int i, j, fn, bit; |
808 | ||
577cd758 MD |
809 | for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) { |
810 | sr = desc->hw.sense_regs + i; | |
73505b44 MD |
811 | |
812 | for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) { | |
813 | if (sr->enum_ids[j] != enum_id) | |
814 | continue; | |
815 | ||
816 | fn = REG_FN_MODIFY_BASE; | |
817 | fn += (sr->reg_width >> 3) - 1; | |
73505b44 | 818 | |
b21a9104 | 819 | BUG_ON((j + 1) * sr->field_width > sr->reg_width); |
820 | ||
821 | bit = sr->reg_width - ((j + 1) * sr->field_width); | |
73505b44 MD |
822 | |
823 | return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg), | |
824 | 0, sr->field_width, bit); | |
825 | } | |
826 | } | |
680c4598 | 827 | |
02ab3f70 MD |
828 | return 0; |
829 | } | |
830 | ||
73505b44 MD |
831 | static void __init intc_register_irq(struct intc_desc *desc, |
832 | struct intc_desc_int *d, | |
833 | intc_enum enum_id, | |
02ab3f70 MD |
834 | unsigned int irq) |
835 | { | |
3d37d94e | 836 | struct intc_handle_int *hp; |
680c4598 MD |
837 | unsigned int data[2], primary; |
838 | ||
1ce7b039 PM |
839 | /* |
840 | * Register the IRQ position with the global IRQ map | |
841 | */ | |
842 | set_bit(irq, intc_irq_map); | |
843 | ||
dc825b17 PM |
844 | /* |
845 | * Prefer single interrupt source bitmap over other combinations: | |
846 | * | |
680c4598 MD |
847 | * 1. bitmap, single interrupt source |
848 | * 2. priority, single interrupt source | |
849 | * 3. bitmap, multiple interrupt sources (groups) | |
850 | * 4. priority, multiple interrupt sources (groups) | |
851 | */ | |
73505b44 MD |
852 | data[0] = intc_mask_data(desc, d, enum_id, 0); |
853 | data[1] = intc_prio_data(desc, d, enum_id, 0); | |
680c4598 MD |
854 | |
855 | primary = 0; | |
856 | if (!data[0] && data[1]) | |
857 | primary = 1; | |
858 | ||
bdaa6e80 | 859 | if (!data[0] && !data[1]) |
ac422f94 PM |
860 | pr_warning("missing unique irq mask for irq %d (vect 0x%04x)\n", |
861 | irq, irq2evt(irq)); | |
bdaa6e80 | 862 | |
73505b44 MD |
863 | data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1); |
864 | data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1); | |
680c4598 MD |
865 | |
866 | if (!data[primary]) | |
867 | primary ^= 1; | |
868 | ||
869 | BUG_ON(!data[primary]); /* must have primary masking method */ | |
02ab3f70 MD |
870 | |
871 | disable_irq_nosync(irq); | |
73505b44 | 872 | set_irq_chip_and_handler_name(irq, &d->chip, |
02ab3f70 | 873 | handle_level_irq, "level"); |
680c4598 | 874 | set_irq_chip_data(irq, (void *)data[primary]); |
02ab3f70 | 875 | |
dc825b17 PM |
876 | /* |
877 | * set priority level | |
7f3edee8 MD |
878 | * - this needs to be at least 2 for 5-bit priorities on 7780 |
879 | */ | |
43b8774d | 880 | intc_prio_level[irq] = default_prio_level; |
73505b44 | 881 | |
680c4598 MD |
882 | /* enable secondary masking method if present */ |
883 | if (data[!primary]) | |
73505b44 MD |
884 | _intc_enable(irq, data[!primary]); |
885 | ||
886 | /* add irq to d->prio list if priority is available */ | |
887 | if (data[1]) { | |
3d37d94e MD |
888 | hp = d->prio + d->nr_prio; |
889 | hp->irq = irq; | |
890 | hp->handle = data[1]; | |
891 | ||
892 | if (primary) { | |
893 | /* | |
894 | * only secondary priority should access registers, so | |
895 | * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority() | |
896 | */ | |
3d37d94e MD |
897 | hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0); |
898 | hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0); | |
899 | } | |
73505b44 MD |
900 | d->nr_prio++; |
901 | } | |
902 | ||
903 | /* add irq to d->sense list if sense is available */ | |
904 | data[0] = intc_sense_data(desc, d, enum_id); | |
905 | if (data[0]) { | |
906 | (d->sense + d->nr_sense)->irq = irq; | |
907 | (d->sense + d->nr_sense)->handle = data[0]; | |
908 | d->nr_sense++; | |
909 | } | |
02ab3f70 MD |
910 | |
911 | /* irq should be disabled by default */ | |
73505b44 | 912 | d->chip.mask(irq); |
d58876e2 | 913 | |
577cd758 | 914 | if (desc->hw.ack_regs) |
d58876e2 | 915 | ack_handle[irq] = intc_ack_data(desc, d, enum_id); |
65a5b28f | 916 | |
dc825b17 PM |
917 | #ifdef CONFIG_INTC_BALANCING |
918 | if (desc->hw.mask_regs) | |
919 | dist_handle[irq] = intc_dist_data(desc, d, enum_id); | |
920 | #endif | |
921 | ||
65a5b28f MD |
922 | #ifdef CONFIG_ARM |
923 | set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ | |
924 | #endif | |
02ab3f70 MD |
925 | } |
926 | ||
f18d533e MD |
927 | static unsigned int __init save_reg(struct intc_desc_int *d, |
928 | unsigned int cnt, | |
929 | unsigned long value, | |
930 | unsigned int smp) | |
931 | { | |
932 | if (value) { | |
dec710b7 MD |
933 | value = intc_phys_to_virt(d, value); |
934 | ||
f18d533e MD |
935 | d->reg[cnt] = value; |
936 | #ifdef CONFIG_SMP | |
937 | d->smp[cnt] = smp; | |
938 | #endif | |
939 | return 1; | |
940 | } | |
941 | ||
942 | return 0; | |
943 | } | |
944 | ||
05ecd5a1 | 945 | static void intc_redirect_irq(unsigned int irq, struct irq_desc *desc) |
bdaa6e80 | 946 | { |
05ecd5a1 | 947 | generic_handle_irq((unsigned int)get_irq_data(irq)); |
bdaa6e80 | 948 | } |
f18d533e | 949 | |
01e9651a | 950 | int __init register_intc_controller(struct intc_desc *desc) |
02ab3f70 | 951 | { |
54ff328b | 952 | unsigned int i, k, smp; |
577cd758 | 953 | struct intc_hw_desc *hw = &desc->hw; |
73505b44 | 954 | struct intc_desc_int *d; |
dec710b7 | 955 | struct resource *res; |
73505b44 | 956 | |
ac422f94 | 957 | pr_info("Registered controller '%s' with %u IRQs\n", |
12129fea PM |
958 | desc->name, hw->nr_vectors); |
959 | ||
11b6aa95 | 960 | d = kzalloc(sizeof(*d), GFP_NOWAIT); |
01e9651a MD |
961 | if (!d) |
962 | goto err0; | |
73505b44 | 963 | |
2dcec7a9 MD |
964 | INIT_LIST_HEAD(&d->list); |
965 | list_add(&d->list, &intc_list); | |
966 | ||
dec710b7 MD |
967 | if (desc->num_resources) { |
968 | d->nr_windows = desc->num_resources; | |
969 | d->window = kzalloc(d->nr_windows * sizeof(*d->window), | |
970 | GFP_NOWAIT); | |
971 | if (!d->window) | |
972 | goto err1; | |
973 | ||
974 | for (k = 0; k < d->nr_windows; k++) { | |
975 | res = desc->resource + k; | |
976 | WARN_ON(resource_type(res) != IORESOURCE_MEM); | |
977 | d->window[k].phys = res->start; | |
978 | d->window[k].size = resource_size(res); | |
979 | d->window[k].virt = ioremap_nocache(res->start, | |
980 | resource_size(res)); | |
981 | if (!d->window[k].virt) | |
982 | goto err2; | |
983 | } | |
984 | } | |
985 | ||
577cd758 | 986 | d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0; |
dc825b17 PM |
987 | #ifdef CONFIG_INTC_BALANCING |
988 | if (d->nr_reg) | |
989 | d->nr_reg += hw->nr_mask_regs; | |
990 | #endif | |
577cd758 MD |
991 | d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0; |
992 | d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0; | |
993 | d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0; | |
9b798d50 | 994 | |
11b6aa95 | 995 | d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT); |
01e9651a | 996 | if (!d->reg) |
dec710b7 | 997 | goto err2; |
01e9651a | 998 | |
f18d533e | 999 | #ifdef CONFIG_SMP |
11b6aa95 | 1000 | d->smp = kzalloc(d->nr_reg * sizeof(*d->smp), GFP_NOWAIT); |
01e9651a | 1001 | if (!d->smp) |
dec710b7 | 1002 | goto err3; |
f18d533e | 1003 | #endif |
73505b44 MD |
1004 | k = 0; |
1005 | ||
577cd758 MD |
1006 | if (hw->mask_regs) { |
1007 | for (i = 0; i < hw->nr_mask_regs; i++) { | |
1008 | smp = IS_SMP(hw->mask_regs[i]); | |
1009 | k += save_reg(d, k, hw->mask_regs[i].set_reg, smp); | |
1010 | k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp); | |
dc825b17 PM |
1011 | #ifdef CONFIG_INTC_BALANCING |
1012 | k += save_reg(d, k, hw->mask_regs[i].dist_reg, 0); | |
1013 | #endif | |
73505b44 MD |
1014 | } |
1015 | } | |
1016 | ||
577cd758 MD |
1017 | if (hw->prio_regs) { |
1018 | d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio), | |
1019 | GFP_NOWAIT); | |
01e9651a | 1020 | if (!d->prio) |
dec710b7 | 1021 | goto err4; |
73505b44 | 1022 | |
577cd758 MD |
1023 | for (i = 0; i < hw->nr_prio_regs; i++) { |
1024 | smp = IS_SMP(hw->prio_regs[i]); | |
1025 | k += save_reg(d, k, hw->prio_regs[i].set_reg, smp); | |
1026 | k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp); | |
73505b44 MD |
1027 | } |
1028 | } | |
1029 | ||
577cd758 MD |
1030 | if (hw->sense_regs) { |
1031 | d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense), | |
1032 | GFP_NOWAIT); | |
01e9651a | 1033 | if (!d->sense) |
dec710b7 | 1034 | goto err5; |
73505b44 | 1035 | |
577cd758 MD |
1036 | for (i = 0; i < hw->nr_sense_regs; i++) |
1037 | k += save_reg(d, k, hw->sense_regs[i].reg, 0); | |
73505b44 MD |
1038 | } |
1039 | ||
73505b44 MD |
1040 | d->chip.name = desc->name; |
1041 | d->chip.mask = intc_disable; | |
1042 | d->chip.unmask = intc_enable; | |
1043 | d->chip.mask_ack = intc_disable; | |
f7dd2548 MD |
1044 | d->chip.enable = intc_enable; |
1045 | d->chip.disable = intc_disable; | |
1046 | d->chip.shutdown = intc_disable; | |
73505b44 | 1047 | d->chip.set_type = intc_set_sense; |
2dcec7a9 | 1048 | d->chip.set_wake = intc_set_wake; |
a8941dad PM |
1049 | #ifdef CONFIG_SMP |
1050 | d->chip.set_affinity = intc_set_affinity; | |
1051 | #endif | |
02ab3f70 | 1052 | |
577cd758 MD |
1053 | if (hw->ack_regs) { |
1054 | for (i = 0; i < hw->nr_ack_regs; i++) | |
1055 | k += save_reg(d, k, hw->ack_regs[i].set_reg, 0); | |
d58876e2 MD |
1056 | |
1057 | d->chip.mask_ack = intc_mask_ack; | |
1058 | } | |
d58876e2 | 1059 | |
d85429a3 MD |
1060 | /* disable bits matching force_disable before registering irqs */ |
1061 | if (desc->force_disable) | |
1062 | intc_enable_disable_enum(desc, d, desc->force_disable, 0); | |
d5190953 MD |
1063 | |
1064 | /* disable bits matching force_enable before registering irqs */ | |
1065 | if (desc->force_enable) | |
1066 | intc_enable_disable_enum(desc, d, desc->force_enable, 0); | |
1067 | ||
d58876e2 MD |
1068 | BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */ |
1069 | ||
bdaa6e80 | 1070 | /* register the vectors one by one */ |
577cd758 MD |
1071 | for (i = 0; i < hw->nr_vectors; i++) { |
1072 | struct intc_vect *vect = hw->vectors + i; | |
05ff3004 PM |
1073 | unsigned int irq = evt2irq(vect->vect); |
1074 | struct irq_desc *irq_desc; | |
54ff328b | 1075 | |
bdaa6e80 MD |
1076 | if (!vect->enum_id) |
1077 | continue; | |
1078 | ||
54ff328b | 1079 | irq_desc = irq_to_desc_alloc_node(irq, numa_node_id()); |
05ff3004 | 1080 | if (unlikely(!irq_desc)) { |
12129fea | 1081 | pr_err("can't get irq_desc for %d\n", irq); |
05ff3004 PM |
1082 | continue; |
1083 | } | |
1084 | ||
1085 | intc_register_irq(desc, d, vect->enum_id, irq); | |
05ecd5a1 | 1086 | |
577cd758 MD |
1087 | for (k = i + 1; k < hw->nr_vectors; k++) { |
1088 | struct intc_vect *vect2 = hw->vectors + k; | |
05ecd5a1 PM |
1089 | unsigned int irq2 = evt2irq(vect2->vect); |
1090 | ||
1091 | if (vect->enum_id != vect2->enum_id) | |
1092 | continue; | |
1093 | ||
1279b7f1 PM |
1094 | /* |
1095 | * In the case of multi-evt handling and sparse | |
1096 | * IRQ support, each vector still needs to have | |
1097 | * its own backing irq_desc. | |
1098 | */ | |
1099 | irq_desc = irq_to_desc_alloc_node(irq2, numa_node_id()); | |
1100 | if (unlikely(!irq_desc)) { | |
12129fea | 1101 | pr_err("can't get irq_desc for %d\n", irq2); |
1279b7f1 PM |
1102 | continue; |
1103 | } | |
1104 | ||
05ecd5a1 PM |
1105 | vect2->enum_id = 0; |
1106 | ||
1107 | /* redirect this interrupts to the first one */ | |
4d2185d9 | 1108 | set_irq_chip(irq2, &dummy_irq_chip); |
e6f07759 | 1109 | set_irq_chained_handler(irq2, intc_redirect_irq); |
05ecd5a1 PM |
1110 | set_irq_data(irq2, (void *)irq); |
1111 | } | |
02ab3f70 | 1112 | } |
d5190953 MD |
1113 | |
1114 | /* enable bits matching force_enable after registering irqs */ | |
1115 | if (desc->force_enable) | |
1116 | intc_enable_disable_enum(desc, d, desc->force_enable, 1); | |
01e9651a MD |
1117 | |
1118 | return 0; | |
dec710b7 | 1119 | err5: |
01e9651a | 1120 | kfree(d->prio); |
dec710b7 | 1121 | err4: |
01e9651a MD |
1122 | #ifdef CONFIG_SMP |
1123 | kfree(d->smp); | |
dec710b7 | 1124 | err3: |
01e9651a MD |
1125 | #endif |
1126 | kfree(d->reg); | |
dec710b7 MD |
1127 | err2: |
1128 | for (k = 0; k < d->nr_windows; k++) | |
1129 | if (d->window[k].virt) | |
1130 | iounmap(d->window[k].virt); | |
1131 | ||
1132 | kfree(d->window); | |
1133 | err1: | |
01e9651a | 1134 | kfree(d); |
dec710b7 | 1135 | err0: |
01e9651a MD |
1136 | pr_err("unable to allocate INTC memory\n"); |
1137 | ||
1138 | return -ENOMEM; | |
02ab3f70 | 1139 | } |
2dcec7a9 | 1140 | |
43b8774d PM |
1141 | #ifdef CONFIG_INTC_USERIMASK |
1142 | static void __iomem *uimask; | |
1143 | ||
1144 | int register_intc_userimask(unsigned long addr) | |
1145 | { | |
1146 | if (unlikely(uimask)) | |
1147 | return -EBUSY; | |
1148 | ||
1149 | uimask = ioremap_nocache(addr, SZ_4K); | |
1150 | if (unlikely(!uimask)) | |
1151 | return -ENOMEM; | |
1152 | ||
ac422f94 | 1153 | pr_info("userimask support registered for levels 0 -> %d\n", |
43b8774d PM |
1154 | default_prio_level - 1); |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
1159 | static ssize_t | |
1160 | show_intc_userimask(struct sysdev_class *cls, | |
1161 | struct sysdev_class_attribute *attr, char *buf) | |
1162 | { | |
1163 | return sprintf(buf, "%d\n", (__raw_readl(uimask) >> 4) & 0xf); | |
1164 | } | |
1165 | ||
1166 | static ssize_t | |
1167 | store_intc_userimask(struct sysdev_class *cls, | |
1168 | struct sysdev_class_attribute *attr, | |
1169 | const char *buf, size_t count) | |
1170 | { | |
1171 | unsigned long level; | |
1172 | ||
1173 | level = simple_strtoul(buf, NULL, 10); | |
1174 | ||
1175 | /* | |
1176 | * Minimal acceptable IRQ levels are in the 2 - 16 range, but | |
1177 | * these are chomped so as to not interfere with normal IRQs. | |
1178 | * | |
1179 | * Level 1 is a special case on some CPUs in that it's not | |
1180 | * directly settable, but given that USERIMASK cuts off below a | |
1181 | * certain level, we don't care about this limitation here. | |
1182 | * Level 0 on the other hand equates to user masking disabled. | |
1183 | * | |
1184 | * We use default_prio_level as a cut off so that only special | |
1185 | * case opt-in IRQs can be mangled. | |
1186 | */ | |
1187 | if (level >= default_prio_level) | |
1188 | return -EINVAL; | |
1189 | ||
1190 | __raw_writel(0xa5 << 24 | level << 4, uimask); | |
1191 | ||
1192 | return count; | |
1193 | } | |
1194 | ||
1195 | static SYSDEV_CLASS_ATTR(userimask, S_IRUSR | S_IWUSR, | |
1196 | show_intc_userimask, store_intc_userimask); | |
1197 | #endif | |
1198 | ||
0ded7542 PM |
1199 | static ssize_t |
1200 | show_intc_name(struct sys_device *dev, struct sysdev_attribute *attr, char *buf) | |
1201 | { | |
1202 | struct intc_desc_int *d; | |
1203 | ||
1204 | d = container_of(dev, struct intc_desc_int, sysdev); | |
1205 | ||
1206 | return sprintf(buf, "%s\n", d->chip.name); | |
1207 | } | |
1208 | ||
1209 | static SYSDEV_ATTR(name, S_IRUGO, show_intc_name, NULL); | |
1210 | ||
2dcec7a9 MD |
1211 | static int intc_suspend(struct sys_device *dev, pm_message_t state) |
1212 | { | |
1213 | struct intc_desc_int *d; | |
1214 | struct irq_desc *desc; | |
1215 | int irq; | |
1216 | ||
1217 | /* get intc controller associated with this sysdev */ | |
1218 | d = container_of(dev, struct intc_desc_int, sysdev); | |
1219 | ||
7fd87b3f FV |
1220 | switch (state.event) { |
1221 | case PM_EVENT_ON: | |
1222 | if (d->state.event != PM_EVENT_FREEZE) | |
1223 | break; | |
1224 | for_each_irq_desc(irq, desc) { | |
87a705dd | 1225 | if (desc->handle_irq == intc_redirect_irq) |
0a753d58 | 1226 | continue; |
7fd87b3f FV |
1227 | if (desc->chip != &d->chip) |
1228 | continue; | |
1229 | if (desc->status & IRQ_DISABLED) | |
1230 | intc_disable(irq); | |
1231 | else | |
1232 | intc_enable(irq); | |
1233 | } | |
1234 | break; | |
1235 | case PM_EVENT_FREEZE: | |
1236 | /* nothing has to be done */ | |
1237 | break; | |
1238 | case PM_EVENT_SUSPEND: | |
1239 | /* enable wakeup irqs belonging to this intc controller */ | |
1240 | for_each_irq_desc(irq, desc) { | |
1241 | if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip)) | |
1242 | intc_enable(irq); | |
1243 | } | |
1244 | break; | |
2dcec7a9 | 1245 | } |
7fd87b3f | 1246 | d->state = state; |
2dcec7a9 MD |
1247 | |
1248 | return 0; | |
1249 | } | |
1250 | ||
7fd87b3f FV |
1251 | static int intc_resume(struct sys_device *dev) |
1252 | { | |
1253 | return intc_suspend(dev, PMSG_ON); | |
1254 | } | |
1255 | ||
2dcec7a9 MD |
1256 | static struct sysdev_class intc_sysdev_class = { |
1257 | .name = "intc", | |
1258 | .suspend = intc_suspend, | |
7fd87b3f | 1259 | .resume = intc_resume, |
2dcec7a9 MD |
1260 | }; |
1261 | ||
1262 | /* register this intc as sysdev to allow suspend/resume */ | |
1263 | static int __init register_intc_sysdevs(void) | |
1264 | { | |
1265 | struct intc_desc_int *d; | |
1266 | int error; | |
1267 | int id = 0; | |
1268 | ||
1269 | error = sysdev_class_register(&intc_sysdev_class); | |
43b8774d PM |
1270 | #ifdef CONFIG_INTC_USERIMASK |
1271 | if (!error && uimask) | |
1272 | error = sysdev_class_create_file(&intc_sysdev_class, | |
1273 | &attr_userimask); | |
1274 | #endif | |
2dcec7a9 MD |
1275 | if (!error) { |
1276 | list_for_each_entry(d, &intc_list, list) { | |
1277 | d->sysdev.id = id; | |
1278 | d->sysdev.cls = &intc_sysdev_class; | |
1279 | error = sysdev_register(&d->sysdev); | |
0ded7542 PM |
1280 | if (error == 0) |
1281 | error = sysdev_create_file(&d->sysdev, | |
1282 | &attr_name); | |
2dcec7a9 MD |
1283 | if (error) |
1284 | break; | |
0ded7542 | 1285 | |
2dcec7a9 MD |
1286 | id++; |
1287 | } | |
1288 | } | |
1289 | ||
1290 | if (error) | |
ac422f94 | 1291 | pr_err("sysdev registration error\n"); |
2dcec7a9 MD |
1292 | |
1293 | return error; | |
1294 | } | |
2dcec7a9 | 1295 | device_initcall(register_intc_sysdevs); |
1ce7b039 PM |
1296 | |
1297 | /* | |
1298 | * Dynamic IRQ allocation and deallocation | |
1299 | */ | |
e9867c56 | 1300 | unsigned int create_irq_nr(unsigned int irq_want, int node) |
1ce7b039 PM |
1301 | { |
1302 | unsigned int irq = 0, new; | |
1303 | unsigned long flags; | |
1304 | struct irq_desc *desc; | |
1305 | ||
1306 | spin_lock_irqsave(&vector_lock, flags); | |
1307 | ||
1308 | /* | |
e9867c56 | 1309 | * First try the wanted IRQ |
1ce7b039 | 1310 | */ |
e9867c56 PM |
1311 | if (test_and_set_bit(irq_want, intc_irq_map) == 0) { |
1312 | new = irq_want; | |
1313 | } else { | |
1314 | /* .. then fall back to scanning. */ | |
1ce7b039 PM |
1315 | new = find_first_zero_bit(intc_irq_map, nr_irqs); |
1316 | if (unlikely(new == nr_irqs)) | |
1317 | goto out_unlock; | |
1318 | ||
1ce7b039 | 1319 | __set_bit(new, intc_irq_map); |
1ce7b039 PM |
1320 | } |
1321 | ||
e9867c56 PM |
1322 | desc = irq_to_desc_alloc_node(new, node); |
1323 | if (unlikely(!desc)) { | |
12129fea | 1324 | pr_err("can't get irq_desc for %d\n", new); |
e9867c56 PM |
1325 | goto out_unlock; |
1326 | } | |
1327 | ||
1328 | desc = move_irq_desc(desc, node); | |
1329 | irq = new; | |
1330 | ||
1ce7b039 PM |
1331 | out_unlock: |
1332 | spin_unlock_irqrestore(&vector_lock, flags); | |
1333 | ||
65a5b28f | 1334 | if (irq > 0) { |
1ce7b039 | 1335 | dynamic_irq_init(irq); |
65a5b28f MD |
1336 | #ifdef CONFIG_ARM |
1337 | set_irq_flags(irq, IRQF_VALID); /* Enable IRQ on ARM systems */ | |
1338 | #endif | |
1339 | } | |
1ce7b039 PM |
1340 | |
1341 | return irq; | |
1342 | } | |
1343 | ||
1344 | int create_irq(void) | |
1345 | { | |
1346 | int nid = cpu_to_node(smp_processor_id()); | |
1347 | int irq; | |
1348 | ||
e9867c56 | 1349 | irq = create_irq_nr(NR_IRQS_LEGACY, nid); |
1ce7b039 PM |
1350 | if (irq == 0) |
1351 | irq = -1; | |
1352 | ||
1353 | return irq; | |
1354 | } | |
1355 | ||
1356 | void destroy_irq(unsigned int irq) | |
1357 | { | |
1358 | unsigned long flags; | |
1359 | ||
1360 | dynamic_irq_cleanup(irq); | |
1361 | ||
1362 | spin_lock_irqsave(&vector_lock, flags); | |
1363 | __clear_bit(irq, intc_irq_map); | |
1364 | spin_unlock_irqrestore(&vector_lock, flags); | |
1365 | } | |
45b9deaf PM |
1366 | |
1367 | int reserve_irq_vector(unsigned int irq) | |
1368 | { | |
1369 | unsigned long flags; | |
1370 | int ret = 0; | |
1371 | ||
1372 | spin_lock_irqsave(&vector_lock, flags); | |
1373 | if (test_and_set_bit(irq, intc_irq_map)) | |
1374 | ret = -EBUSY; | |
1375 | spin_unlock_irqrestore(&vector_lock, flags); | |
1376 | ||
1377 | return ret; | |
1378 | } | |
1379 | ||
1380 | void reserve_irq_legacy(void) | |
1381 | { | |
1382 | unsigned long flags; | |
1383 | int i, j; | |
1384 | ||
1385 | spin_lock_irqsave(&vector_lock, flags); | |
1386 | j = find_first_bit(intc_irq_map, nr_irqs); | |
1387 | for (i = 0; i < j; i++) | |
1388 | __set_bit(i, intc_irq_map); | |
1389 | spin_unlock_irqrestore(&vector_lock, flags); | |
1390 | } |