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[SCTP]: Set sk_err so that poll wakes up after a non-blocking connect failure.
[net-next-2.6.git] / drivers / serial / sunsu.c
CommitLineData
1da177e4
LT		 1/* $Id: su.c,v 1.55 2002/01/08 16:00:16 davem Exp $
2 * su.c: Small serial driver for keyboard/mouse interface on sparc32/PCI
3 *
4 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1998-1999 Pete Zaitcev (zaitcev@yahoo.com)
6 *
7 * This is mainly a variation of 8250.c, credits go to authors mentioned
8 * therein. In fact this driver should be merged into the generic 8250.c
9 * infrastructure perhaps using a 8250_sparc.c module.
10 *
11 * Fixed to use tty_get_baud_rate().
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Converted to new 2.5.x UART layer.
15 * David S. Miller (davem@redhat.com), 2002-Jul-29
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/spinlock.h>
23#include <linux/errno.h>
24#include <linux/tty.h>
25#include <linux/tty_flip.h>
26#include <linux/major.h>
27#include <linux/string.h>
28#include <linux/ptrace.h>
29#include <linux/ioport.h>
30#include <linux/circ_buf.h>
31#include <linux/serial.h>
32#include <linux/sysrq.h>
33#include <linux/console.h>
34#ifdef CONFIG_SERIO
35#include <linux/serio.h>
36#endif
37#include <linux/serial_reg.h>
38#include <linux/init.h>
39#include <linux/delay.h>
40
41#include <asm/io.h>
42#include <asm/irq.h>
43#include <asm/oplib.h>
44#include <asm/ebus.h>
45#ifdef CONFIG_SPARC64
46#include <asm/isa.h>
47#endif
48
49#if defined(CONFIG_SERIAL_SUNSU_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
50#define SUPPORT_SYSRQ
51#endif
52
53#include <linux/serial_core.h>
54
55#include "suncore.h"
56
57/* We are on a NS PC87303 clocked with 24.0 MHz, which results
58 * in a UART clock of 1.8462 MHz.
59 */
60#define SU_BASE_BAUD (1846200 / 16)
61
62enum su_type { SU_PORT_NONE, SU_PORT_MS, SU_PORT_KBD, SU_PORT_PORT };
63static char *su_typev[] = { "su(???)", "su(mouse)", "su(kbd)", "su(serial)" };
64
65/*
66 * Here we define the default xmit fifo size used for each type of UART.
67 */
68static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
69 { "unknown", 1, 0 },
70 { "8250", 1, 0 },
71 { "16450", 1, 0 },
72 { "16550", 1, 0 },
73 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
74 { "Cirrus", 1, 0 },
75 { "ST16650", 1, UART_CLEAR_FIFO | UART_STARTECH },
76 { "ST16650V2", 32, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
77 { "TI16750", 64, UART_CLEAR_FIFO | UART_USE_FIFO },
78 { "Startech", 1, 0 },
79 { "16C950/954", 128, UART_CLEAR_FIFO | UART_USE_FIFO },
80 { "ST16654", 64, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
81 { "XR16850", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
82 { "RSA", 2048, UART_CLEAR_FIFO | UART_USE_FIFO }
83};
84
85struct uart_sunsu_port {
86 struct uart_port port;
87 unsigned char acr;
88 unsigned char ier;
89 unsigned short rev;
90 unsigned char lcr;
91 unsigned int lsr_break_flag;
92 unsigned int cflag;
93
94 /* Probing information. */
95 enum su_type su_type;
96 unsigned int type_probed; /* XXX Stupid */
97 int port_node;
98
99#ifdef CONFIG_SERIO
100 struct serio *serio;
101 int serio_open;
102#endif
103};
104
41c28ff1 105static unsigned int serial_in(struct uart_sunsu_port *up, int offset)
1da177e4
LT		 106{
107 offset <<= up->port.regshift;
108
109 switch (up->port.iotype) {
9b4a1617 110 case UPIO_HUB6:
1da177e4
LT		 111 outb(up->port.hub6 - 1 + offset, up->port.iobase);
112 return inb(up->port.iobase + 1);
113
9b4a1617 114 case UPIO_MEM:
1da177e4
LT		 115 return readb(up->port.membase + offset);
116
117 default:
118 return inb(up->port.iobase + offset);
119 }
120}
121
41c28ff1 122static void serial_out(struct uart_sunsu_port *up, int offset, int value)
1da177e4
LT		 123{
124#ifndef CONFIG_SPARC64
125 /*
126 * MrCoffee has weird schematics: IRQ4 & P10(?) pins of SuperIO are
127 * connected with a gate then go to SlavIO. When IRQ4 goes tristated
128 * gate outputs a logical one. Since we use level triggered interrupts
129 * we have lockup and watchdog reset. We cannot mask IRQ because
130 * keyboard shares IRQ with us (Word has it as Bob Smelik's design).
131 * This problem is similar to what Alpha people suffer, see serial.c.
132 */
133 if (offset == UART_MCR)
134 value |= UART_MCR_OUT2;
135#endif
136 offset <<= up->port.regshift;
137
138 switch (up->port.iotype) {
9b4a1617 139 case UPIO_HUB6:
1da177e4
LT		 140 outb(up->port.hub6 - 1 + offset, up->port.iobase);
141 outb(value, up->port.iobase + 1);
142 break;
143
9b4a1617 144 case UPIO_MEM:
1da177e4
LT		 145 writeb(value, up->port.membase + offset);
146 break;
147
148 default:
149 outb(value, up->port.iobase + offset);
150 }
151}
152
153/*
154 * We used to support using pause I/O for certain machines. We
155 * haven't supported this for a while, but just in case it's badly
156 * needed for certain old 386 machines, I've left these #define's
157 * in....
158 */
159#define serial_inp(up, offset) serial_in(up, offset)
160#define serial_outp(up, offset, value) serial_out(up, offset, value)
161
162
163/*
164 * For the 16C950
165 */
166static void serial_icr_write(struct uart_sunsu_port *up, int offset, int value)
167{
168 serial_out(up, UART_SCR, offset);
169 serial_out(up, UART_ICR, value);
170}
171
172#if 0 /* Unused currently */
173static unsigned int serial_icr_read(struct uart_sunsu_port *up, int offset)
174{
175 unsigned int value;
176
177 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
178 serial_out(up, UART_SCR, offset);
179 value = serial_in(up, UART_ICR);
180 serial_icr_write(up, UART_ACR, up->acr);
181
182 return value;
183}
184#endif
185
186#ifdef CONFIG_SERIAL_8250_RSA
187/*
188 * Attempts to turn on the RSA FIFO. Returns zero on failure.
189 * We set the port uart clock rate if we succeed.
190 */
191static int __enable_rsa(struct uart_sunsu_port *up)
192{
193 unsigned char mode;
194 int result;
195
196 mode = serial_inp(up, UART_RSA_MSR);
197 result = mode & UART_RSA_MSR_FIFO;
198
199 if (!result) {
200 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
201 mode = serial_inp(up, UART_RSA_MSR);
202 result = mode & UART_RSA_MSR_FIFO;
203 }
204
205 if (result)
206 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
207
208 return result;
209}
210
211static void enable_rsa(struct uart_sunsu_port *up)
212{
213 if (up->port.type == PORT_RSA) {
214 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
215 spin_lock_irq(&up->port.lock);
216 __enable_rsa(up);
217 spin_unlock_irq(&up->port.lock);
218 }
219 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
220 serial_outp(up, UART_RSA_FRR, 0);
221 }
222}
223
224/*
225 * Attempts to turn off the RSA FIFO. Returns zero on failure.
226 * It is unknown why interrupts were disabled in here. However,
227 * the caller is expected to preserve this behaviour by grabbing
228 * the spinlock before calling this function.
229 */
230static void disable_rsa(struct uart_sunsu_port *up)
231{
232 unsigned char mode;
233 int result;
234
235 if (up->port.type == PORT_RSA &&
236 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
237 spin_lock_irq(&up->port.lock);
238
239 mode = serial_inp(up, UART_RSA_MSR);
240 result = !(mode & UART_RSA_MSR_FIFO);
241
242 if (!result) {
243 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
244 mode = serial_inp(up, UART_RSA_MSR);
245 result = !(mode & UART_RSA_MSR_FIFO);
246 }
247
248 if (result)
249 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
250 spin_unlock_irq(&up->port.lock);
251 }
252}
253#endif /* CONFIG_SERIAL_8250_RSA */
254
b129a8cc
RK		 255static inline void __stop_tx(struct uart_sunsu_port *p)
256{
257 if (p->ier & UART_IER_THRI) {
258 p->ier &= ~UART_IER_THRI;
259 serial_out(p, UART_IER, p->ier);
260 }
261}
262
263static void sunsu_stop_tx(struct uart_port *port)
1da177e4
LT		 264{
265 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
266
b129a8cc
RK		 267 __stop_tx(up);
268
3d9c9948
AV		 269 /*
270 * We really want to stop the transmitter from sending.
271 */
272 if (up->port.type == PORT_16C950) {
1da177e4
LT		 273 up->acr |= UART_ACR_TXDIS;
274 serial_icr_write(up, UART_ACR, up->acr);
275 }
276}
277
b129a8cc 278static void sunsu_start_tx(struct uart_port *port)
1da177e4
LT		 279{
280 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
281
282 if (!(up->ier & UART_IER_THRI)) {
283 up->ier |= UART_IER_THRI;
284 serial_out(up, UART_IER, up->ier);
285 }
3d9c9948 286
1da177e4 287 /*
3d9c9948 288 * Re-enable the transmitter if we disabled it.
1da177e4 289 */
3d9c9948 290 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 291 up->acr &= ~UART_ACR_TXDIS;
292 serial_icr_write(up, UART_ACR, up->acr);
293 }
294}
295
296static void sunsu_stop_rx(struct uart_port *port)
297{
298 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
1da177e4 299
1da177e4
LT		 300 up->ier &= ~UART_IER_RLSI;
301 up->port.read_status_mask &= ~UART_LSR_DR;
302 serial_out(up, UART_IER, up->ier);
1da177e4
LT		 303}
304
305static void sunsu_enable_ms(struct uart_port *port)
306{
307 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
308 unsigned long flags;
309
310 spin_lock_irqsave(&up->port.lock, flags);
311 up->ier |= UART_IER_MSI;
312 serial_out(up, UART_IER, up->ier);
313 spin_unlock_irqrestore(&up->port.lock, flags);
314}
315
41c28ff1 316static struct tty_struct *
1da177e4
LT		 317receive_chars(struct uart_sunsu_port *up, unsigned char *status, struct pt_regs *regs)
318{
319 struct tty_struct *tty = up->port.info->tty;
33f0f88f 320 unsigned char ch, flag;
1da177e4
LT		 321 int max_count = 256;
322 int saw_console_brk = 0;
323
324 do {
1da177e4 325 ch = serial_inp(up, UART_RX);
33f0f88f 326 flag = TTY_NORMAL;
1da177e4
LT		 327 up->port.icount.rx++;
328
329 if (unlikely(*status & (UART_LSR_BI | UART_LSR_PE |
330 UART_LSR_FE | UART_LSR_OE))) {
331 /*
332 * For statistics only
333 */
334 if (*status & UART_LSR_BI) {
335 *status &= ~(UART_LSR_FE | UART_LSR_PE);
336 up->port.icount.brk++;
337 if (up->port.cons != NULL &&
338 up->port.line == up->port.cons->index)
339 saw_console_brk = 1;
340 /*
341 * We do the SysRQ and SAK checking
342 * here because otherwise the break
343 * may get masked by ignore_status_mask
344 * or read_status_mask.
345 */
346 if (uart_handle_break(&up->port))
347 goto ignore_char;
348 } else if (*status & UART_LSR_PE)
349 up->port.icount.parity++;
350 else if (*status & UART_LSR_FE)
351 up->port.icount.frame++;
352 if (*status & UART_LSR_OE)
353 up->port.icount.overrun++;
354
355 /*
356 * Mask off conditions which should be ingored.
357 */
358 *status &= up->port.read_status_mask;
359
360 if (up->port.cons != NULL &&
361 up->port.line == up->port.cons->index) {
362 /* Recover the break flag from console xmit */
363 *status |= up->lsr_break_flag;
364 up->lsr_break_flag = 0;
365 }
366
367 if (*status & UART_LSR_BI) {
33f0f88f 368 flag = TTY_BREAK;
1da177e4 369 } else if (*status & UART_LSR_PE)
33f0f88f 370 flag = TTY_PARITY;
1da177e4 371 else if (*status & UART_LSR_FE)
33f0f88f 372 flag = TTY_FRAME;
1da177e4
LT		 373 }
374 if (uart_handle_sysrq_char(&up->port, ch, regs))
375 goto ignore_char;
33f0f88f
AC		 376 if ((*status & up->port.ignore_status_mask) == 0)
377 tty_insert_flip_char(tty, ch, flag);
378 if (*status & UART_LSR_OE)
1da177e4
LT		 379 /*
380 * Overrun is special, since it's reported
381 * immediately, and doesn't affect the current
382 * character.
383 */
33f0f88f 384 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1da177e4
LT		 385 ignore_char:
386 *status = serial_inp(up, UART_LSR);
387 } while ((*status & UART_LSR_DR) && (max_count-- > 0));
388
389 if (saw_console_brk)
390 sun_do_break();
391
392 return tty;
393}
394
41c28ff1 395static void transmit_chars(struct uart_sunsu_port *up)
1da177e4
LT		 396{
397 struct circ_buf *xmit = &up->port.info->xmit;
398 int count;
399
400 if (up->port.x_char) {
401 serial_outp(up, UART_TX, up->port.x_char);
402 up->port.icount.tx++;
403 up->port.x_char = 0;
404 return;
405 }
b129a8cc
RK		 406 if (uart_tx_stopped(&up->port)) {
407 sunsu_stop_tx(&up->port);
408 return;
409 }
410 if (uart_circ_empty(xmit)) {
411 __stop_tx(up);
1da177e4
LT		 412 return;
413 }
414
415 count = up->port.fifosize;
416 do {
417 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
418 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
419 up->port.icount.tx++;
420 if (uart_circ_empty(xmit))
421 break;
422 } while (--count > 0);
423
424 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
425 uart_write_wakeup(&up->port);
426
427 if (uart_circ_empty(xmit))
b129a8cc 428 __stop_tx(up);
1da177e4
LT		 429}
430
41c28ff1 431static void check_modem_status(struct uart_sunsu_port *up)
1da177e4
LT		 432{
433 int status;
434
435 status = serial_in(up, UART_MSR);
436
437 if ((status & UART_MSR_ANY_DELTA) == 0)
438 return;
439
440 if (status & UART_MSR_TERI)
441 up->port.icount.rng++;
442 if (status & UART_MSR_DDSR)
443 up->port.icount.dsr++;
444 if (status & UART_MSR_DDCD)
445 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
446 if (status & UART_MSR_DCTS)
447 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
448
449 wake_up_interruptible(&up->port.info->delta_msr_wait);
450}
451
452static irqreturn_t sunsu_serial_interrupt(int irq, void *dev_id, struct pt_regs *regs)
453{
454 struct uart_sunsu_port *up = dev_id;
455 unsigned long flags;
456 unsigned char status;
457
458 spin_lock_irqsave(&up->port.lock, flags);
459
460 do {
461 struct tty_struct *tty;
462
463 status = serial_inp(up, UART_LSR);
464 tty = NULL;
465 if (status & UART_LSR_DR)
466 tty = receive_chars(up, &status, regs);
467 check_modem_status(up);
468 if (status & UART_LSR_THRE)
469 transmit_chars(up);
470
471 spin_unlock_irqrestore(&up->port.lock, flags);
472
473 if (tty)
474 tty_flip_buffer_push(tty);
475
476 spin_lock_irqsave(&up->port.lock, flags);
477
478 } while (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT));
479
480 spin_unlock_irqrestore(&up->port.lock, flags);
481
482 return IRQ_HANDLED;
483}
484
485/* Separate interrupt handling path for keyboard/mouse ports. */
486
487static void
488sunsu_change_speed(struct uart_port *port, unsigned int cflag,
489 unsigned int iflag, unsigned int quot);
490
491static void sunsu_change_mouse_baud(struct uart_sunsu_port *up)
492{
493 unsigned int cur_cflag = up->cflag;
494 int quot, new_baud;
495
496 up->cflag &= ~CBAUD;
497 up->cflag |= suncore_mouse_baud_cflag_next(cur_cflag, &new_baud);
498
499 quot = up->port.uartclk / (16 * new_baud);
500
1da177e4 501 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1da177e4
LT		 502}
503
504static void receive_kbd_ms_chars(struct uart_sunsu_port *up, struct pt_regs *regs, int is_break)
505{
506 do {
507 unsigned char ch = serial_inp(up, UART_RX);
508
509 /* Stop-A is handled by drivers/char/keyboard.c now. */
510 if (up->su_type == SU_PORT_KBD) {
511#ifdef CONFIG_SERIO
512 serio_interrupt(up->serio, ch, 0, regs);
513#endif
514 } else if (up->su_type == SU_PORT_MS) {
515 int ret = suncore_mouse_baud_detection(ch, is_break);
516
517 switch (ret) {
518 case 2:
519 sunsu_change_mouse_baud(up);
520 /* fallthru */
521 case 1:
522 break;
523
524 case 0:
525#ifdef CONFIG_SERIO
526 serio_interrupt(up->serio, ch, 0, regs);
527#endif
528 break;
529 };
530 }
531 } while (serial_in(up, UART_LSR) & UART_LSR_DR);
532}
533
534static irqreturn_t sunsu_kbd_ms_interrupt(int irq, void *dev_id, struct pt_regs *regs)
535{
536 struct uart_sunsu_port *up = dev_id;
537
538 if (!(serial_in(up, UART_IIR) & UART_IIR_NO_INT)) {
539 unsigned char status = serial_inp(up, UART_LSR);
540
541 if ((status & UART_LSR_DR) || (status & UART_LSR_BI))
542 receive_kbd_ms_chars(up, regs,
543 (status & UART_LSR_BI) != 0);
544 }
545
546 return IRQ_HANDLED;
547}
548
549static unsigned int sunsu_tx_empty(struct uart_port *port)
550{
551 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
552 unsigned long flags;
553 unsigned int ret;
554
555 spin_lock_irqsave(&up->port.lock, flags);
556 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
557 spin_unlock_irqrestore(&up->port.lock, flags);
558
559 return ret;
560}
561
562static unsigned int sunsu_get_mctrl(struct uart_port *port)
563{
564 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
1da177e4
LT		 565 unsigned char status;
566 unsigned int ret;
567
1da177e4 568 status = serial_in(up, UART_MSR);
1da177e4
LT		 569
570 ret = 0;
571 if (status & UART_MSR_DCD)
572 ret |= TIOCM_CAR;
573 if (status & UART_MSR_RI)
574 ret |= TIOCM_RNG;
575 if (status & UART_MSR_DSR)
576 ret |= TIOCM_DSR;
577 if (status & UART_MSR_CTS)
578 ret |= TIOCM_CTS;
579 return ret;
580}
581
582static void sunsu_set_mctrl(struct uart_port *port, unsigned int mctrl)
583{
584 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
585 unsigned char mcr = 0;
586
587 if (mctrl & TIOCM_RTS)
588 mcr |= UART_MCR_RTS;
589 if (mctrl & TIOCM_DTR)
590 mcr |= UART_MCR_DTR;
591 if (mctrl & TIOCM_OUT1)
592 mcr |= UART_MCR_OUT1;
593 if (mctrl & TIOCM_OUT2)
594 mcr |= UART_MCR_OUT2;
595 if (mctrl & TIOCM_LOOP)
596 mcr |= UART_MCR_LOOP;
597
598 serial_out(up, UART_MCR, mcr);
599}
600
601static void sunsu_break_ctl(struct uart_port *port, int break_state)
602{
603 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
604 unsigned long flags;
605
606 spin_lock_irqsave(&up->port.lock, flags);
607 if (break_state == -1)
608 up->lcr |= UART_LCR_SBC;
609 else
610 up->lcr &= ~UART_LCR_SBC;
611 serial_out(up, UART_LCR, up->lcr);
612 spin_unlock_irqrestore(&up->port.lock, flags);
613}
614
615static int sunsu_startup(struct uart_port *port)
616{
617 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
618 unsigned long flags;
619 int retval;
620
621 if (up->port.type == PORT_16C950) {
622 /* Wake up and initialize UART */
623 up->acr = 0;
624 serial_outp(up, UART_LCR, 0xBF);
625 serial_outp(up, UART_EFR, UART_EFR_ECB);
626 serial_outp(up, UART_IER, 0);
627 serial_outp(up, UART_LCR, 0);
628 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
629 serial_outp(up, UART_LCR, 0xBF);
630 serial_outp(up, UART_EFR, UART_EFR_ECB);
631 serial_outp(up, UART_LCR, 0);
632 }
633
634#ifdef CONFIG_SERIAL_8250_RSA
635 /*
636 * If this is an RSA port, see if we can kick it up to the
637 * higher speed clock.
638 */
639 enable_rsa(up);
640#endif
641
642 /*
643 * Clear the FIFO buffers and disable them.
7f927fcc 644 * (they will be reenabled in set_termios())
1da177e4
LT		 645 */
646 if (uart_config[up->port.type].flags & UART_CLEAR_FIFO) {
647 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
648 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
649 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
650 serial_outp(up, UART_FCR, 0);
651 }
652
653 /*
654 * Clear the interrupt registers.
655 */
656 (void) serial_inp(up, UART_LSR);
657 (void) serial_inp(up, UART_RX);
658 (void) serial_inp(up, UART_IIR);
659 (void) serial_inp(up, UART_MSR);
660
661 /*
662 * At this point, there's no way the LSR could still be 0xff;
663 * if it is, then bail out, because there's likely no UART
664 * here.
665 */
ce8337cb 666 if (!(up->port.flags & UPF_BUGGY_UART) &&
1da177e4
LT		 667 (serial_inp(up, UART_LSR) == 0xff)) {
668 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
669 return -ENODEV;
670 }
671
672 if (up->su_type != SU_PORT_PORT) {
673 retval = request_irq(up->port.irq, sunsu_kbd_ms_interrupt,
674 SA_SHIRQ, su_typev[up->su_type], up);
675 } else {
676 retval = request_irq(up->port.irq, sunsu_serial_interrupt,
677 SA_SHIRQ, su_typev[up->su_type], up);
678 }
679 if (retval) {
680 printk("su: Cannot register IRQ %d\n", up->port.irq);
681 return retval;
682 }
683
684 /*
685 * Now, initialize the UART
686 */
687 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
688
689 spin_lock_irqsave(&up->port.lock, flags);
690
691 up->port.mctrl |= TIOCM_OUT2;
692
693 sunsu_set_mctrl(&up->port, up->port.mctrl);
694 spin_unlock_irqrestore(&up->port.lock, flags);
695
696 /*
697 * Finally, enable interrupts. Note: Modem status interrupts
698 * are set via set_termios(), which will be occurring imminently
699 * anyway, so we don't enable them here.
700 */
701 up->ier = UART_IER_RLSI | UART_IER_RDI;
702 serial_outp(up, UART_IER, up->ier);
703
ce8337cb 704 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 705 unsigned int icp;
706 /*
707 * Enable interrupts on the AST Fourport board
708 */
709 icp = (up->port.iobase & 0xfe0) | 0x01f;
710 outb_p(0x80, icp);
711 (void) inb_p(icp);
712 }
713
714 /*
715 * And clear the interrupt registers again for luck.
716 */
717 (void) serial_inp(up, UART_LSR);
718 (void) serial_inp(up, UART_RX);
719 (void) serial_inp(up, UART_IIR);
720 (void) serial_inp(up, UART_MSR);
721
722 return 0;
723}
724
725static void sunsu_shutdown(struct uart_port *port)
726{
727 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
728 unsigned long flags;
729
730 /*
731 * Disable interrupts from this port
732 */
733 up->ier = 0;
734 serial_outp(up, UART_IER, 0);
735
736 spin_lock_irqsave(&up->port.lock, flags);
ce8337cb 737 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 738 /* reset interrupts on the AST Fourport board */
739 inb((up->port.iobase & 0xfe0) | 0x1f);
740 up->port.mctrl |= TIOCM_OUT1;
741 } else
742 up->port.mctrl &= ~TIOCM_OUT2;
743
744 sunsu_set_mctrl(&up->port, up->port.mctrl);
745 spin_unlock_irqrestore(&up->port.lock, flags);
746
747 /*
748 * Disable break condition and FIFOs
749 */
750 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
751 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
752 UART_FCR_CLEAR_RCVR |
753 UART_FCR_CLEAR_XMIT);
754 serial_outp(up, UART_FCR, 0);
755
756#ifdef CONFIG_SERIAL_8250_RSA
757 /*
758 * Reset the RSA board back to 115kbps compat mode.
759 */
760 disable_rsa(up);
761#endif
762
763 /*
764 * Read data port to reset things.
765 */
766 (void) serial_in(up, UART_RX);
767
768 free_irq(up->port.irq, up);
769}
770
771static void
772sunsu_change_speed(struct uart_port *port, unsigned int cflag,
773 unsigned int iflag, unsigned int quot)
774{
775 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
776 unsigned char cval, fcr = 0;
777 unsigned long flags;
778
779 switch (cflag & CSIZE) {
780 case CS5:
781 cval = 0x00;
782 break;
783 case CS6:
784 cval = 0x01;
785 break;
786 case CS7:
787 cval = 0x02;
788 break;
789 default:
790 case CS8:
791 cval = 0x03;
792 break;
793 }
794
795 if (cflag & CSTOPB)
796 cval |= 0x04;
797 if (cflag & PARENB)
798 cval |= UART_LCR_PARITY;
799 if (!(cflag & PARODD))
800 cval |= UART_LCR_EPAR;
801#ifdef CMSPAR
802 if (cflag & CMSPAR)
803 cval |= UART_LCR_SPAR;
804#endif
805
806 /*
807 * Work around a bug in the Oxford Semiconductor 952 rev B
808 * chip which causes it to seriously miscalculate baud rates
809 * when DLL is 0.
810 */
811 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
812 up->rev == 0x5201)
813 quot ++;
814
815 if (uart_config[up->port.type].flags & UART_USE_FIFO) {
816 if ((up->port.uartclk / quot) < (2400 * 16))
817 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
818#ifdef CONFIG_SERIAL_8250_RSA
819 else if (up->port.type == PORT_RSA)
820 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_14;
821#endif
822 else
823 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_8;
824 }
825 if (up->port.type == PORT_16750)
826 fcr |= UART_FCR7_64BYTE;
827
828 /*
829 * Ok, we're now changing the port state. Do it with
830 * interrupts disabled.
831 */
832 spin_lock_irqsave(&up->port.lock, flags);
833
834 /*
835 * Update the per-port timeout.
836 */
837 uart_update_timeout(port, cflag, (port->uartclk / (16 * quot)));
838
839 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
840 if (iflag & INPCK)
841 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
842 if (iflag & (BRKINT | PARMRK))
843 up->port.read_status_mask |= UART_LSR_BI;
844
845 /*
846 * Characteres to ignore
847 */
848 up->port.ignore_status_mask = 0;
849 if (iflag & IGNPAR)
850 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
851 if (iflag & IGNBRK) {
852 up->port.ignore_status_mask |= UART_LSR_BI;
853 /*
854 * If we're ignoring parity and break indicators,
855 * ignore overruns too (for real raw support).
856 */
857 if (iflag & IGNPAR)
858 up->port.ignore_status_mask |= UART_LSR_OE;
859 }
860
861 /*
862 * ignore all characters if CREAD is not set
863 */
864 if ((cflag & CREAD) == 0)
865 up->port.ignore_status_mask |= UART_LSR_DR;
866
867 /*
868 * CTS flow control flag and modem status interrupts
869 */
870 up->ier &= ~UART_IER_MSI;
871 if (UART_ENABLE_MS(&up->port, cflag))
872 up->ier |= UART_IER_MSI;
873
874 serial_out(up, UART_IER, up->ier);
875
876 if (uart_config[up->port.type].flags & UART_STARTECH) {
877 serial_outp(up, UART_LCR, 0xBF);
878 serial_outp(up, UART_EFR, cflag & CRTSCTS ? UART_EFR_CTS :0);
879 }
880 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
881 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
882 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
883 if (up->port.type == PORT_16750)
884 serial_outp(up, UART_FCR, fcr); /* set fcr */
885 serial_outp(up, UART_LCR, cval); /* reset DLAB */
886 up->lcr = cval; /* Save LCR */
887 if (up->port.type != PORT_16750) {
888 if (fcr & UART_FCR_ENABLE_FIFO) {
889 /* emulated UARTs (Lucent Venus 167x) need two steps */
890 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
891 }
892 serial_outp(up, UART_FCR, fcr); /* set fcr */
893 }
894
895 up->cflag = cflag;
896
897 spin_unlock_irqrestore(&up->port.lock, flags);
898}
899
900static void
901sunsu_set_termios(struct uart_port *port, struct termios *termios,
902 struct termios *old)
903{
904 unsigned int baud, quot;
905
906 /*
907 * Ask the core to calculate the divisor for us.
908 */
909 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
910 quot = uart_get_divisor(port, baud);
911
912 sunsu_change_speed(port, termios->c_cflag, termios->c_iflag, quot);
913}
914
915static void sunsu_release_port(struct uart_port *port)
916{
917}
918
919static int sunsu_request_port(struct uart_port *port)
920{
921 return 0;
922}
923
924static void sunsu_config_port(struct uart_port *port, int flags)
925{
926 struct uart_sunsu_port *up = (struct uart_sunsu_port *) port;
927
928 if (flags & UART_CONFIG_TYPE) {
929 /*
930 * We are supposed to call autoconfig here, but this requires
931 * splitting all the OBP probing crap from the UART probing.
932 * We'll do it when we kill sunsu.c altogether.
933 */
934 port->type = up->type_probed; /* XXX */
935 }
936}
937
938static int
939sunsu_verify_port(struct uart_port *port, struct serial_struct *ser)
940{
941 return -EINVAL;
942}
943
944static const char *
945sunsu_type(struct uart_port *port)
946{
947 int type = port->type;
948
949 if (type >= ARRAY_SIZE(uart_config))
950 type = 0;
951 return uart_config[type].name;
952}
953
954static struct uart_ops sunsu_pops = {
955 .tx_empty = sunsu_tx_empty,
956 .set_mctrl = sunsu_set_mctrl,
957 .get_mctrl = sunsu_get_mctrl,
958 .stop_tx = sunsu_stop_tx,
959 .start_tx = sunsu_start_tx,
960 .stop_rx = sunsu_stop_rx,
961 .enable_ms = sunsu_enable_ms,
962 .break_ctl = sunsu_break_ctl,
963 .startup = sunsu_startup,
964 .shutdown = sunsu_shutdown,
965 .set_termios = sunsu_set_termios,
966 .type = sunsu_type,
967 .release_port = sunsu_release_port,
968 .request_port = sunsu_request_port,
969 .config_port = sunsu_config_port,
970 .verify_port = sunsu_verify_port,
971};
972
973#define UART_NR 4
974
975static struct uart_sunsu_port sunsu_ports[UART_NR];
976
977#ifdef CONFIG_SERIO
978
979static DEFINE_SPINLOCK(sunsu_serio_lock);
980
981static int sunsu_serio_write(struct serio *serio, unsigned char ch)
982{
983 struct uart_sunsu_port *up = serio->port_data;
984 unsigned long flags;
985 int lsr;
986
987 spin_lock_irqsave(&sunsu_serio_lock, flags);
988
989 do {
990 lsr = serial_in(up, UART_LSR);
991 } while (!(lsr & UART_LSR_THRE));
992
993 /* Send the character out. */
994 serial_out(up, UART_TX, ch);
995
996 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
997
998 return 0;
999}
1000
1001static int sunsu_serio_open(struct serio *serio)
1002{
1003 struct uart_sunsu_port *up = serio->port_data;
1004 unsigned long flags;
1005 int ret;
1006
1007 spin_lock_irqsave(&sunsu_serio_lock, flags);
1008 if (!up->serio_open) {
1009 up->serio_open = 1;
1010 ret = 0;
1011 } else
1012 ret = -EBUSY;
1013 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1014
1015 return ret;
1016}
1017
1018static void sunsu_serio_close(struct serio *serio)
1019{
1020 struct uart_sunsu_port *up = serio->port_data;
1021 unsigned long flags;
1022
1023 spin_lock_irqsave(&sunsu_serio_lock, flags);
1024 up->serio_open = 0;
1025 spin_unlock_irqrestore(&sunsu_serio_lock, flags);
1026}
1027
1028#endif /* CONFIG_SERIO */
1029
1030static void sunsu_autoconfig(struct uart_sunsu_port *up)
1031{
1032 unsigned char status1, status2, scratch, scratch2, scratch3;
1033 unsigned char save_lcr, save_mcr;
1034 struct linux_ebus_device *dev = NULL;
1035 struct linux_ebus *ebus;
1036#ifdef CONFIG_SPARC64
1037 struct sparc_isa_bridge *isa_br;
1038 struct sparc_isa_device *isa_dev;
1039#endif
1040#ifndef CONFIG_SPARC64
1041 struct linux_prom_registers reg0;
1042#endif
1043 unsigned long flags;
1044
1045 if (!up->port_node || !up->su_type)
1046 return;
1047
1048 up->type_probed = PORT_UNKNOWN;
9b4a1617 1049 up->port.iotype = UPIO_MEM;
1da177e4
LT		 1050
1051 /*
1052 * First we look for Ebus-bases su's
1053 */
1054 for_each_ebus(ebus) {
1055 for_each_ebusdev(dev, ebus) {
1056 if (dev->prom_node == up->port_node) {
1057 /*
1058 * The EBus is broken on sparc; it delivers
1059 * virtual addresses in resources. Oh well...
1060 * This is correct on sparc64, though.
1061 */
1062 up->port.membase = (char *) dev->resource[0].start;
1063 /*
1064 * This is correct on both architectures.
1065 */
1066 up->port.mapbase = dev->resource[0].start;
1067 up->port.irq = dev->irqs[0];
1068 goto ebus_done;
1069 }
1070 }
1071 }
1072
1073#ifdef CONFIG_SPARC64
1074 for_each_isa(isa_br) {
1075 for_each_isadev(isa_dev, isa_br) {
1076 if (isa_dev->prom_node == up->port_node) {
1077 /* Same on sparc64. Cool architecure... */
1078 up->port.membase = (char *) isa_dev->resource.start;
1079 up->port.mapbase = isa_dev->resource.start;
1080 up->port.irq = isa_dev->irq;
1081 goto ebus_done;
1082 }
1083 }
1084 }
1085#endif
1086
1087#ifdef CONFIG_SPARC64
1088 /*
1089 * Not on Ebus, bailing.
1090 */
1091 return;
1092#else
1093 /*
1094 * Not on Ebus, must be OBIO.
1095 */
1096 if (prom_getproperty(up->port_node, "reg",
1097 (char *)&reg0, sizeof(reg0)) == -1) {
1098 prom_printf("sunsu: no \"reg\" property\n");
1099 return;
1100 }
1101 prom_apply_obio_ranges(&reg0, 1);
1102 if (reg0.which_io != 0) { /* Just in case... */
1103 prom_printf("sunsu: bus number nonzero: 0x%x:%x\n",
1104 reg0.which_io, reg0.phys_addr);
1105 return;
1106 }
1107 up->port.mapbase = reg0.phys_addr;
1108 if ((up->port.membase = ioremap(reg0.phys_addr, reg0.reg_size)) == 0) {
1109 prom_printf("sunsu: Cannot map registers.\n");
1110 return;
1111 }
1112
1113 /*
1114 * 0x20 is sun4m thing, Dave Redman heritage.
1115 * See arch/sparc/kernel/irq.c.
1116 */
1117#define IRQ_4M(n) ((n)|0x20)
1118
1119 /*
1120 * There is no intr property on MrCoffee, so hardwire it.
1121 */
1122 up->port.irq = IRQ_4M(13);
1123#endif
1124
1125ebus_done:
1126
1127 spin_lock_irqsave(&up->port.lock, flags);
1128
ce8337cb 1129 if (!(up->port.flags & UPF_BUGGY_UART)) {
1da177e4
LT		 1130 /*
1131 * Do a simple existence test first; if we fail this, there's
1132 * no point trying anything else.
1133 *
1134 * 0x80 is used as a nonsense port to prevent against false
1135 * positives due to ISA bus float. The assumption is that
1136 * 0x80 is a non-existent port; which should be safe since
1137 * include/asm/io.h also makes this assumption.
1138 */
1139 scratch = serial_inp(up, UART_IER);
1140 serial_outp(up, UART_IER, 0);
1141#ifdef __i386__
1142 outb(0xff, 0x080);
1143#endif
1144 scratch2 = serial_inp(up, UART_IER);
1145 serial_outp(up, UART_IER, 0x0f);
1146#ifdef __i386__
1147 outb(0, 0x080);
1148#endif
1149 scratch3 = serial_inp(up, UART_IER);
1150 serial_outp(up, UART_IER, scratch);
1151 if (scratch2 != 0 || scratch3 != 0x0F)
1152 goto out; /* We failed; there's nothing here */
1153 }
1154
1155 save_mcr = serial_in(up, UART_MCR);
1156 save_lcr = serial_in(up, UART_LCR);
1157
1158 /*
1159 * Check to see if a UART is really there. Certain broken
1160 * internal modems based on the Rockwell chipset fail this
1161 * test, because they apparently don't implement the loopback
1162 * test mode. So this test is skipped on the COM 1 through
1163 * COM 4 ports. This *should* be safe, since no board
1164 * manufacturer would be stupid enough to design a board
1165 * that conflicts with COM 1-4 --- we hope!
1166 */
ce8337cb 1167 if (!(up->port.flags & UPF_SKIP_TEST)) {
1da177e4
LT		 1168 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1169 status1 = serial_inp(up, UART_MSR) & 0xF0;
1170 serial_outp(up, UART_MCR, save_mcr);
1171 if (status1 != 0x90)
1172 goto out; /* We failed loopback test */
1173 }
1174 serial_outp(up, UART_LCR, 0xBF); /* set up for StarTech test */
1175 serial_outp(up, UART_EFR, 0); /* EFR is the same as FCR */
1176 serial_outp(up, UART_LCR, 0);
1177 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1178 scratch = serial_in(up, UART_IIR) >> 6;
1179 switch (scratch) {
1180 case 0:
1181 up->port.type = PORT_16450;
1182 break;
1183 case 1:
1184 up->port.type = PORT_UNKNOWN;
1185 break;
1186 case 2:
1187 up->port.type = PORT_16550;
1188 break;
1189 case 3:
1190 up->port.type = PORT_16550A;
1191 break;
1192 }
1193 if (up->port.type == PORT_16550A) {
1194 /* Check for Startech UART's */
1195 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1196 if (serial_in(up, UART_EFR) == 0) {
1197 up->port.type = PORT_16650;
1198 } else {
1199 serial_outp(up, UART_LCR, 0xBF);
1200 if (serial_in(up, UART_EFR) == 0)
1201 up->port.type = PORT_16650V2;
1202 }
1203 }
1204 if (up->port.type == PORT_16550A) {
1205 /* Check for TI 16750 */
1206 serial_outp(up, UART_LCR, save_lcr | UART_LCR_DLAB);
1207 serial_outp(up, UART_FCR,
1208 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1209 scratch = serial_in(up, UART_IIR) >> 5;
1210 if (scratch == 7) {
1211 /*
1212 * If this is a 16750, and not a cheap UART
1213 * clone, then it should only go into 64 byte
1214 * mode if the UART_FCR7_64BYTE bit was set
1215 * while UART_LCR_DLAB was latched.
1216 */
1217 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1218 serial_outp(up, UART_LCR, 0);
1219 serial_outp(up, UART_FCR,
1220 UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1221 scratch = serial_in(up, UART_IIR) >> 5;
1222 if (scratch == 6)
1223 up->port.type = PORT_16750;
1224 }
1225 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1226 }
1227 serial_outp(up, UART_LCR, save_lcr);
1228 if (up->port.type == PORT_16450) {
1229 scratch = serial_in(up, UART_SCR);
1230 serial_outp(up, UART_SCR, 0xa5);
1231 status1 = serial_in(up, UART_SCR);
1232 serial_outp(up, UART_SCR, 0x5a);
1233 status2 = serial_in(up, UART_SCR);
1234 serial_outp(up, UART_SCR, scratch);
1235
1236 if ((status1 != 0xa5) || (status2 != 0x5a))
1237 up->port.type = PORT_8250;
1238 }
1239
1240 up->port.fifosize = uart_config[up->port.type].dfl_xmit_fifo_size;
1241
1242 if (up->port.type == PORT_UNKNOWN)
1243 goto out;
1244 up->type_probed = up->port.type; /* XXX */
1245
1246 /*
1247 * Reset the UART.
1248 */
1249#ifdef CONFIG_SERIAL_8250_RSA
1250 if (up->port.type == PORT_RSA)
1251 serial_outp(up, UART_RSA_FRR, 0);
1252#endif
1253 serial_outp(up, UART_MCR, save_mcr);
1254 serial_outp(up, UART_FCR, (UART_FCR_ENABLE_FIFO |
1255 UART_FCR_CLEAR_RCVR |
1256 UART_FCR_CLEAR_XMIT));
1257 serial_outp(up, UART_FCR, 0);
1258 (void)serial_in(up, UART_RX);
1259 serial_outp(up, UART_IER, 0);
1260
1261out:
1262 spin_unlock_irqrestore(&up->port.lock, flags);
1263}
1264
1265static struct uart_driver sunsu_reg = {
1266 .owner = THIS_MODULE,
1267 .driver_name = "serial",
1268 .devfs_name = "tts/",
1269 .dev_name = "ttyS",
1270 .major = TTY_MAJOR,
1271};
1272
1273static int __init sunsu_kbd_ms_init(struct uart_sunsu_port *up, int channel)
1274{
623f41eb 1275 int quot, baud;
1da177e4
LT		 1276#ifdef CONFIG_SERIO
1277 struct serio *serio;
1278#endif
1279
a858f1ca 1280 spin_lock_init(&up->port.lock);
1da177e4
LT		 1281 up->port.line = channel;
1282 up->port.type = PORT_UNKNOWN;
1283 up->port.uartclk = (SU_BASE_BAUD * 16);
1284
623f41eb 1285 if (up->su_type == SU_PORT_KBD) {
1da177e4 1286 up->cflag = B1200 | CS8 | CLOCAL | CREAD;
623f41eb
DM		 1287 baud = 1200;
1288 } else {
1da177e4 1289 up->cflag = B4800 | CS8 | CLOCAL | CREAD;
623f41eb
DM		 1290 baud = 4800;
1291 }
1292 quot = up->port.uartclk / (16 * baud);
1da177e4
LT		 1293
1294 sunsu_autoconfig(up);
1295 if (up->port.type == PORT_UNKNOWN)
1296 return -1;
1297
1298 printk(KERN_INFO "su%d at 0x%p (irq = %s) is a %s\n",
1299 channel,
1300 up->port.membase, __irq_itoa(up->port.irq),
1301 sunsu_type(&up->port));
1302
1303#ifdef CONFIG_SERIO
1304 up->serio = serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
1305 if (serio) {
1306 memset(serio, 0, sizeof(*serio));
1307
1308 serio->port_data = up;
1309
1310 serio->id.type = SERIO_RS232;
1311 if (up->su_type == SU_PORT_KBD) {
1312 serio->id.proto = SERIO_SUNKBD;
1313 strlcpy(serio->name, "sukbd", sizeof(serio->name));
1314 } else {
1315 serio->id.proto = SERIO_SUN;
1316 serio->id.extra = 1;
1317 strlcpy(serio->name, "sums", sizeof(serio->name));
1318 }
1319 strlcpy(serio->phys, (channel == 0 ? "su/serio0" : "su/serio1"),
1320 sizeof(serio->phys));
1321
1322 serio->write = sunsu_serio_write;
1323 serio->open = sunsu_serio_open;
1324 serio->close = sunsu_serio_close;
1325
1326 serio_register_port(serio);
1327 } else {
1328 printk(KERN_WARNING "su%d: not enough memory for serio port\n",
1329 channel);
1330 }
1331#endif
1332
623f41eb
DM		 1333 sunsu_change_speed(&up->port, up->cflag, 0, quot);
1334
1da177e4
LT		 1335 sunsu_startup(&up->port);
1336 return 0;
1337}
1338
1339/*
1340 * ------------------------------------------------------------
1341 * Serial console driver
1342 * ------------------------------------------------------------
1343 */
1344
1345#ifdef CONFIG_SERIAL_SUNSU_CONSOLE
1346
1347#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1348
1349/*
1350 * Wait for transmitter & holding register to empty
1351 */
1352static __inline__ void wait_for_xmitr(struct uart_sunsu_port *up)
1353{
1354 unsigned int status, tmout = 10000;
1355
1356 /* Wait up to 10ms for the character(s) to be sent. */
1357 do {
1358 status = serial_in(up, UART_LSR);
1359
1360 if (status & UART_LSR_BI)
1361 up->lsr_break_flag = UART_LSR_BI;
1362
1363 if (--tmout == 0)
1364 break;
1365 udelay(1);
1366 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1367
1368 /* Wait up to 1s for flow control if necessary */
ce8337cb 1369 if (up->port.flags & UPF_CONS_FLOW) {
1da177e4
LT		 1370 tmout = 1000000;
1371 while (--tmout &&
1372 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
1373 udelay(1);
1374 }
1375}
1376
d358788f
RK		 1377static void sunsu_console_putchar(struct uart_port *port, int ch)
1378{
1379 struct uart_sunsu_port *up = (struct uart_sunsu_port *)port;
1380
1381 wait_for_xmitr(up);
1382 serial_out(up, UART_TX, ch);
1383}
1384
1da177e4
LT		 1385/*
1386 * Print a string to the serial port trying not to disturb
1387 * any possible real use of the port...
1388 */
1389static void sunsu_console_write(struct console *co, const char *s,
1390 unsigned int count)
1391{
1392 struct uart_sunsu_port *up = &sunsu_ports[co->index];
1393 unsigned int ier;
1da177e4
LT		 1394
1395 /*
1396 * First save the UER then disable the interrupts
1397 */
1398 ier = serial_in(up, UART_IER);
1399 serial_out(up, UART_IER, 0);
1400
d358788f 1401 uart_console_write(&up->port, s, count, sunsu_console_putchar);
1da177e4
LT		 1402
1403 /*
1404 * Finally, wait for transmitter to become empty
1405 * and restore the IER
1406 */
1407 wait_for_xmitr(up);
1408 serial_out(up, UART_IER, ier);
1409}
1410
1411/*
1412 * Setup initial baud/bits/parity. We do two things here:
1413 * - construct a cflag setting for the first su_open()
1414 * - initialize the serial port
1415 * Return non-zero if we didn't find a serial port.
1416 */
48377246 1417static int sunsu_console_setup(struct console *co, char *options)
1da177e4
LT		 1418{
1419 struct uart_port *port;
1420 int baud = 9600;
1421 int bits = 8;
1422 int parity = 'n';
1423 int flow = 'n';
1424
1425 printk("Console: ttyS%d (SU)\n",
1426 (sunsu_reg.minor - 64) + co->index);
1427
1428 /*
1429 * Check whether an invalid uart number has been specified, and
1430 * if so, search for the first available port that does have
1431 * console support.
1432 */
1433 if (co->index >= UART_NR)
1434 co->index = 0;
1435 port = &sunsu_ports[co->index].port;
1436
1437 /*
1438 * Temporary fix.
1439 */
1440 spin_lock_init(&port->lock);
1441
1442 if (options)
1443 uart_parse_options(options, &baud, &parity, &bits, &flow);
1444
1445 return uart_set_options(port, co, baud, parity, bits, flow);
1446}
1447
1448static struct console sunsu_cons = {
1449 .name = "ttyS",
1450 .write = sunsu_console_write,
1451 .device = uart_console_device,
1452 .setup = sunsu_console_setup,
1453 .flags = CON_PRINTBUFFER,
1454 .index = -1,
1455 .data = &sunsu_reg,
1456};
1da177e4
LT		 1457
1458/*
1459 * Register console.
1460 */
1461
1ddb7c98 1462static inline struct console *SUNSU_CONSOLE(void)
1da177e4
LT		 1463{
1464 int i;
1465
1466 if (con_is_present())
1ddb7c98 1467 return NULL;
1da177e4
LT		 1468
1469 for (i = 0; i < UART_NR; i++) {
1470 int this_minor = sunsu_reg.minor + i;
1471
1472 if ((this_minor - 64) == (serial_console - 1))
1473 break;
1474 }
1475 if (i == UART_NR)
1ddb7c98 1476 return NULL;
1da177e4 1477 if (sunsu_ports[i].port_node == 0)
1ddb7c98 1478 return NULL;
1da177e4
LT		 1479
1480 sunsu_cons.index = i;
1ddb7c98
DM		 1481
1482 return &sunsu_cons;
1da177e4
LT		 1483}
1484#else
1ddb7c98 1485#define SUNSU_CONSOLE() (NULL)
1da177e4
LT		 1486#define sunsu_serial_console_init() do { } while (0)
1487#endif
1488
1489static int __init sunsu_serial_init(void)
1490{
1491 int instance, ret, i;
1492
1493 /* How many instances do we need? */
1494 instance = 0;
1495 for (i = 0; i < UART_NR; i++) {
1496 struct uart_sunsu_port *up = &sunsu_ports[i];
1497
1498 if (up->su_type == SU_PORT_MS ||
1499 up->su_type == SU_PORT_KBD)
1500 continue;
1501
a858f1ca 1502 spin_lock_init(&up->port.lock);
ce8337cb 1503 up->port.flags |= UPF_BOOT_AUTOCONF;
1da177e4
LT		 1504 up->port.type = PORT_UNKNOWN;
1505 up->port.uartclk = (SU_BASE_BAUD * 16);
1506
1507 sunsu_autoconfig(up);
1508 if (up->port.type == PORT_UNKNOWN)
1509 continue;
1510
1511 up->port.line = instance++;
1512 up->port.ops = &sunsu_pops;
1513 }
1514
1515 sunsu_reg.minor = sunserial_current_minor;
1da177e4
LT		 1516
1517 sunsu_reg.nr = instance;
1da177e4
LT		 1518
1519 ret = uart_register_driver(&sunsu_reg);
1520 if (ret < 0)
1521 return ret;
1522
f5deb807
DM		 1523 sunsu_reg.tty_driver->name_base = sunsu_reg.minor - 64;
1524
1ddb7c98
DM		 1525 sunserial_current_minor += instance;
1526
1527 sunsu_reg.cons = SUNSU_CONSOLE();
1528
1da177e4
LT		 1529 for (i = 0; i < UART_NR; i++) {
1530 struct uart_sunsu_port *up = &sunsu_ports[i];
1531
1532 /* Do not register Keyboard/Mouse lines with UART
1533 * layer.
1534 */
1535 if (up->su_type == SU_PORT_MS ||
1536 up->su_type == SU_PORT_KBD)
1537 continue;
1538
1539 if (up->port.type == PORT_UNKNOWN)
1540 continue;
1541
1542 uart_add_one_port(&sunsu_reg, &up->port);
1543 }
1544
1545 return 0;
1546}
1547
1548static int su_node_ok(int node, char *name, int namelen)
1549{
1550 if (strncmp(name, "su", namelen) == 0 ||
1551 strncmp(name, "su_pnp", namelen) == 0)
1552 return 1;
1553
1554 if (strncmp(name, "serial", namelen) == 0) {
1555 char compat[32];
1556 int clen;
1557
1558 /* Is it _really_ a 'su' device? */
1559 clen = prom_getproperty(node, "compatible", compat, sizeof(compat));
1560 if (clen > 0) {
1561 if (strncmp(compat, "sab82532", 8) == 0) {
1562 /* Nope, Siemens serial, not for us. */
1563 return 0;
1564 }
1565 }
1566 return 1;
1567 }
1568
1569 return 0;
1570}
1571
1572#define SU_PROPSIZE 128
1573
1574/*
1575 * Scan status structure.
1576 * "prop" is a local variable but it eats stack to keep it in each
1577 * stack frame of a recursive procedure.
1578 */
1579struct su_probe_scan {
1580 int msnode, kbnode; /* PROM nodes for mouse and keyboard */
1581 int msx, kbx; /* minors for mouse and keyboard */
1582 int devices; /* scan index */
1583 char prop[SU_PROPSIZE];
1584};
1585
1586/*
1587 * We have several platforms which present 'su' in different parts
1588 * of the device tree. 'su' may be found under obio, ebus, isa and pci.
1589 * We walk over the tree and find them wherever PROM hides them.
1590 */
1591static void __init su_probe_any(struct su_probe_scan *t, int sunode)
1592{
1593 struct uart_sunsu_port *up;
1594 int len;
1595
1596 if (t->devices >= UART_NR)
1597 return;
1598
1599 for (; sunode != 0; sunode = prom_getsibling(sunode)) {
1600 len = prom_getproperty(sunode, "name", t->prop, SU_PROPSIZE);
1601 if (len <= 1)
1602 continue; /* Broken PROM node */
1603
1604 if (su_node_ok(sunode, t->prop, len)) {
1605 up = &sunsu_ports[t->devices];
1606 if (t->kbnode != 0 && sunode == t->kbnode) {
1607 t->kbx = t->devices;
1608 up->su_type = SU_PORT_KBD;
1609 } else if (t->msnode != 0 && sunode == t->msnode) {
1610 t->msx = t->devices;
1611 up->su_type = SU_PORT_MS;
1612 } else {
1613#ifdef CONFIG_SPARC64
1614 /*
1615 * Do not attempt to use the truncated
1616 * keyboard/mouse ports as serial ports
1617 * on Ultras with PC keyboard attached.
1618 */
1619 if (prom_getbool(sunode, "mouse"))
1620 continue;
1621 if (prom_getbool(sunode, "keyboard"))
1622 continue;
1623#endif
1624 up->su_type = SU_PORT_PORT;
1625 }
1626 up->port_node = sunode;
1627 ++t->devices;
1628 } else {
1629 su_probe_any(t, prom_getchild(sunode));
1630 }
1631 }
1632}
1633
1634static int __init sunsu_probe(void)
1635{
1636 int node;
1637 int len;
1638 struct su_probe_scan scan;
1639
1640 /*
1641 * First, we scan the tree.
1642 */
1643 scan.devices = 0;
1644 scan.msx = -1;
1645 scan.kbx = -1;
1646 scan.kbnode = 0;
1647 scan.msnode = 0;
1648
1649 /*
1650 * Get the nodes for keyboard and mouse from 'aliases'...
1651 */
1652 node = prom_getchild(prom_root_node);
1653 node = prom_searchsiblings(node, "aliases");
1654 if (node != 0) {
1655 len = prom_getproperty(node, "keyboard", scan.prop, SU_PROPSIZE);
1656 if (len > 0) {
1657 scan.prop[len] = 0;
1658 scan.kbnode = prom_finddevice(scan.prop);
1659 }
1660
1661 len = prom_getproperty(node, "mouse", scan.prop, SU_PROPSIZE);
1662 if (len > 0) {
1663 scan.prop[len] = 0;
1664 scan.msnode = prom_finddevice(scan.prop);
1665 }
1666 }
1667
1668 su_probe_any(&scan, prom_getchild(prom_root_node));
1669
1670 /*
1671 * Second, we process the special case of keyboard and mouse.
1672 *
1673 * Currently if we got keyboard and mouse hooked to "su" ports
1674 * we do not use any possible remaining "su" as a serial port.
1675 * Thus, we ignore values of .msx and .kbx, then compact ports.
1676 */
1677 if (scan.msx != -1 && scan.kbx != -1) {
1678 sunsu_ports[0].su_type = SU_PORT_MS;
1679 sunsu_ports[0].port_node = scan.msnode;
1680 sunsu_kbd_ms_init(&sunsu_ports[0], 0);
1681
1682 sunsu_ports[1].su_type = SU_PORT_KBD;
1683 sunsu_ports[1].port_node = scan.kbnode;
1684 sunsu_kbd_ms_init(&sunsu_ports[1], 1);
1685
1686 return 0;
1687 }
1688
1689 if (scan.msx != -1 || scan.kbx != -1) {
1690 printk("sunsu_probe: cannot match keyboard and mouse, confused\n");
1691 return -ENODEV;
1692 }
1693
1694 if (scan.devices == 0)
1695 return -ENODEV;
1696
1697 /*
1698 * Console must be initiated after the generic initialization.
1699 */
1700 sunsu_serial_init();
1701
1702 return 0;
1703}
1704
1705static void __exit sunsu_exit(void)
1706{
1707 int i, saw_uart;
1708
1709 saw_uart = 0;
1710 for (i = 0; i < UART_NR; i++) {
1711 struct uart_sunsu_port *up = &sunsu_ports[i];
1712
1713 if (up->su_type == SU_PORT_MS ||
1714 up->su_type == SU_PORT_KBD) {
1715#ifdef CONFIG_SERIO
1716 if (up->serio) {
1717 serio_unregister_port(up->serio);
1718 up->serio = NULL;
1719 }
1720#endif
1721 } else if (up->port.type != PORT_UNKNOWN) {
1722 uart_remove_one_port(&sunsu_reg, &up->port);
1723 saw_uart++;
1724 }
1725 }
1726
1727 if (saw_uart)
1728 uart_unregister_driver(&sunsu_reg);
1729}
1730
1731module_init(sunsu_probe);
1732module_exit(sunsu_exit);
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