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[SPARC64]: Program IRQ registers correctly on sun4v.
[net-next-2.6.git] / drivers / serial / sunsab.c
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1da177e4
LT		 1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@redhat.com>
16 */
17
18#include <linux/config.h>
19#include <linux/module.h>
20#include <linux/kernel.h>
21#include <linux/sched.h>
22#include <linux/errno.h>
23#include <linux/tty.h>
24#include <linux/tty_flip.h>
25#include <linux/major.h>
26#include <linux/string.h>
27#include <linux/ptrace.h>
28#include <linux/ioport.h>
29#include <linux/circ_buf.h>
30#include <linux/serial.h>
31#include <linux/sysrq.h>
32#include <linux/console.h>
33#include <linux/spinlock.h>
34#include <linux/slab.h>
35#include <linux/delay.h>
36#include <linux/init.h>
37
38#include <asm/io.h>
39#include <asm/irq.h>
40#include <asm/oplib.h>
41#include <asm/ebus.h>
42
43#if defined(CONFIG_SERIAL_SUNZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
44#define SUPPORT_SYSRQ
45#endif
46
47#include <linux/serial_core.h>
48
49#include "suncore.h"
50#include "sunsab.h"
51
52struct uart_sunsab_port {
53 struct uart_port port; /* Generic UART port */
54 union sab82532_async_regs __iomem *regs; /* Chip registers */
55 unsigned long irqflags; /* IRQ state flags */
56 int dsr; /* Current DSR state */
57 unsigned int cec_timeout; /* Chip poll timeout... */
58 unsigned int tec_timeout; /* likewise */
59 unsigned char interrupt_mask0;/* ISR0 masking */
60 unsigned char interrupt_mask1;/* ISR1 masking */
61 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
62 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
63 int type; /* SAB82532 version */
e4fdee8e
DM		 64
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
69 */
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
1da177e4
LT		 74};
75
76/*
77 * This assumes you have a 29.4912 MHz clock for your UART.
78 */
79#define SAB_BASE_BAUD ( 29491200 / 16 )
80
81static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
86};
87
88#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90
91#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92#define SAB82532_XMIT_FIFO_SIZE 32
93
94static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
95{
96 int timeout = up->tec_timeout;
97
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 udelay(1);
100}
101
102static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103{
104 int timeout = up->cec_timeout;
105
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107 udelay(1);
108}
109
110static struct tty_struct *
111receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat,
113 struct pt_regs *regs)
114{
115 struct tty_struct *tty = NULL;
116 unsigned char buf[32];
117 int saw_console_brk = 0;
118 int free_fifo = 0;
119 int count = 0;
120 int i;
121
122 if (up->port.info != NULL) /* Unopened serial console */
123 tty = up->port.info->tty;
124
125 /* Read number of BYTES (Character + Status) available. */
126 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
127 count = SAB82532_RECV_FIFO_SIZE;
128 free_fifo++;
129 }
130
131 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
132 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
133 free_fifo++;
134 }
135
136 /* Issue a FIFO read command in case we where idle. */
137 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
138 sunsab_cec_wait(up);
139 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
140 return tty;
141 }
142
143 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
144 free_fifo++;
145
146 /* Read the FIFO. */
147 for (i = 0; i < count; i++)
148 buf[i] = readb(&up->regs->r.rfifo[i]);
149
150 /* Issue Receive Message Complete command. */
151 if (free_fifo) {
152 sunsab_cec_wait(up);
153 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
154 }
155
156 /* Count may be zero for BRK, so we check for it here */
157 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
158 (up->port.line == up->port.cons->index))
159 saw_console_brk = 1;
160
161 for (i = 0; i < count; i++) {
33f0f88f 162 unsigned char ch = buf[i], flag;
1da177e4
LT		 163
164 if (tty == NULL) {
165 uart_handle_sysrq_char(&up->port, ch, regs);
166 continue;
167 }
168
33f0f88f 169 flag = TTY_NORMAL;
1da177e4
LT		 170 up->port.icount.rx++;
171
172 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
173 SAB82532_ISR0_FERR |
174 SAB82532_ISR0_RFO)) ||
175 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
176 /*
177 * For statistics only
178 */
179 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
180 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
181 SAB82532_ISR0_FERR);
182 up->port.icount.brk++;
183 /*
184 * We do the SysRQ and SAK checking
185 * here because otherwise the break
186 * may get masked by ignore_status_mask
187 * or read_status_mask.
188 */
189 if (uart_handle_break(&up->port))
190 continue;
191 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
192 up->port.icount.parity++;
193 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
194 up->port.icount.frame++;
195 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
196 up->port.icount.overrun++;
197
198 /*
199 * Mask off conditions which should be ingored.
200 */
201 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
202 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
203
204 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
33f0f88f 205 flag = TTY_BREAK;
1da177e4 206 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
33f0f88f 207 flag = TTY_PARITY;
1da177e4 208 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
33f0f88f 209 flag = TTY_FRAME;
1da177e4
LT		 210 }
211
212 if (uart_handle_sysrq_char(&up->port, ch, regs))
213 continue;
214
215 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
33f0f88f
AC		 216 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
217 tty_insert_flip_char(tty, ch, flag);
218 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
219 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1da177e4
LT		 220 }
221
222 if (saw_console_brk)
223 sun_do_break();
224
225 return tty;
226}
227
b129a8cc 228static void sunsab_stop_tx(struct uart_port *);
e4fdee8e 229static void sunsab_tx_idle(struct uart_sunsab_port *);
1da177e4
LT		 230
231static void transmit_chars(struct uart_sunsab_port *up,
232 union sab82532_irq_status *stat)
233{
234 struct circ_buf *xmit = &up->port.info->xmit;
235 int i;
236
237 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
238 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
239 writeb(up->interrupt_mask1, &up->regs->w.imr1);
240 set_bit(SAB82532_ALLS, &up->irqflags);
241 }
242
243#if 0 /* bde@nwlink.com says this check causes problems */
244 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
245 return;
246#endif
247
248 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
249 return;
250
251 set_bit(SAB82532_XPR, &up->irqflags);
e4fdee8e 252 sunsab_tx_idle(up);
1da177e4
LT		 253
254 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
255 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
256 writeb(up->interrupt_mask1, &up->regs->w.imr1);
1da177e4
LT		 257 return;
258 }
259
260 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
261 writeb(up->interrupt_mask1, &up->regs->w.imr1);
262 clear_bit(SAB82532_ALLS, &up->irqflags);
263
264 /* Stuff 32 bytes into Transmit FIFO. */
265 clear_bit(SAB82532_XPR, &up->irqflags);
266 for (i = 0; i < up->port.fifosize; i++) {
267 writeb(xmit->buf[xmit->tail],
268 &up->regs->w.xfifo[i]);
269 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
270 up->port.icount.tx++;
271 if (uart_circ_empty(xmit))
272 break;
273 }
274
275 /* Issue a Transmit Frame command. */
276 sunsab_cec_wait(up);
277 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
278
279 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
280 uart_write_wakeup(&up->port);
281
282 if (uart_circ_empty(xmit))
b129a8cc 283 sunsab_stop_tx(&up->port);
1da177e4
LT		 284}
285
286static void check_status(struct uart_sunsab_port *up,
287 union sab82532_irq_status *stat)
288{
289 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
290 uart_handle_dcd_change(&up->port,
291 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
292
293 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
294 uart_handle_cts_change(&up->port,
295 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
296
297 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
298 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
299 up->port.icount.dsr++;
300 }
301
302 wake_up_interruptible(&up->port.info->delta_msr_wait);
303}
304
305static irqreturn_t sunsab_interrupt(int irq, void *dev_id, struct pt_regs *regs)
306{
307 struct uart_sunsab_port *up = dev_id;
308 struct tty_struct *tty;
309 union sab82532_irq_status status;
310 unsigned long flags;
311
312 spin_lock_irqsave(&up->port.lock, flags);
313
314 status.stat = 0;
315 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA0)
316 status.sreg.isr0 = readb(&up->regs->r.isr0);
317 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISA1)
318 status.sreg.isr1 = readb(&up->regs->r.isr1);
319
320 tty = NULL;
321 if (status.stat) {
322 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
323 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
324 (status.sreg.isr1 & SAB82532_ISR1_BRK))
325 tty = receive_chars(up, &status, regs);
326 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
327 (status.sreg.isr1 & SAB82532_ISR1_CSC))
328 check_status(up, &status);
329 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
330 transmit_chars(up, &status);
331 }
332
333 spin_unlock(&up->port.lock);
334
335 if (tty)
336 tty_flip_buffer_push(tty);
337
338 up++;
339
340 spin_lock(&up->port.lock);
341
342 status.stat = 0;
343 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB0)
344 status.sreg.isr0 = readb(&up->regs->r.isr0);
345 if (readb(&up->regs->r.gis) & SAB82532_GIS_ISB1)
346 status.sreg.isr1 = readb(&up->regs->r.isr1);
347
348 tty = NULL;
349 if (status.stat) {
350 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
351 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
352 (status.sreg.isr1 & SAB82532_ISR1_BRK))
353
354 tty = receive_chars(up, &status, regs);
355 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
356 (status.sreg.isr1 & (SAB82532_ISR1_BRK | SAB82532_ISR1_CSC)))
357 check_status(up, &status);
358 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
359 transmit_chars(up, &status);
360 }
361
362 spin_unlock_irqrestore(&up->port.lock, flags);
363
364 if (tty)
365 tty_flip_buffer_push(tty);
366
367 return IRQ_HANDLED;
368}
369
370/* port->lock is not held. */
371static unsigned int sunsab_tx_empty(struct uart_port *port)
372{
373 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
374 int ret;
375
376 /* Do not need a lock for a state test like this. */
377 if (test_bit(SAB82532_ALLS, &up->irqflags))
378 ret = TIOCSER_TEMT;
379 else
380 ret = 0;
381
382 return ret;
383}
384
385/* port->lock held by caller. */
386static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
387{
388 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
389
390 if (mctrl & TIOCM_RTS) {
e4fdee8e
DM		 391 up->cached_mode &= ~SAB82532_MODE_FRTS;
392 up->cached_mode |= SAB82532_MODE_RTS;
1da177e4 393 } else {
e4fdee8e
DM		 394 up->cached_mode |= (SAB82532_MODE_FRTS |
395 SAB82532_MODE_RTS);
1da177e4
LT		 396 }
397 if (mctrl & TIOCM_DTR) {
e4fdee8e 398 up->cached_pvr &= ~(up->pvr_dtr_bit);
1da177e4 399 } else {
e4fdee8e 400 up->cached_pvr |= up->pvr_dtr_bit;
1da177e4 401 }
e4fdee8e
DM		 402
403 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
404 if (test_bit(SAB82532_XPR, &up->irqflags))
405 sunsab_tx_idle(up);
1da177e4
LT		 406}
407
c5f4644e 408/* port->lock is held by caller and interrupts are disabled. */
1da177e4
LT		 409static unsigned int sunsab_get_mctrl(struct uart_port *port)
410{
411 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
1da177e4
LT		 412 unsigned char val;
413 unsigned int result;
414
415 result = 0;
416
1da177e4
LT		 417 val = readb(&up->regs->r.pvr);
418 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
419
420 val = readb(&up->regs->r.vstr);
421 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
422
423 val = readb(&up->regs->r.star);
424 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
425
1da177e4
LT		 426 return result;
427}
428
429/* port->lock held by caller. */
b129a8cc 430static void sunsab_stop_tx(struct uart_port *port)
1da177e4
LT		 431{
432 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
433
434 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
435 writeb(up->interrupt_mask1, &up->regs->w.imr1);
436}
437
e4fdee8e
DM		 438/* port->lock held by caller. */
439static void sunsab_tx_idle(struct uart_sunsab_port *up)
440{
441 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
442 u8 tmp;
443
444 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
445 writeb(up->cached_mode, &up->regs->rw.mode);
446 writeb(up->cached_pvr, &up->regs->rw.pvr);
447 writeb(up->cached_dafo, &up->regs->w.dafo);
448
449 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
450 tmp = readb(&up->regs->rw.ccr2);
451 tmp &= ~0xc0;
452 tmp |= (up->cached_ebrg >> 2) & 0xc0;
453 writeb(tmp, &up->regs->rw.ccr2);
454 }
455}
456
1da177e4 457/* port->lock held by caller. */
b129a8cc 458static void sunsab_start_tx(struct uart_port *port)
1da177e4
LT		 459{
460 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
461 struct circ_buf *xmit = &up->port.info->xmit;
462 int i;
463
464 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
465 writeb(up->interrupt_mask1, &up->regs->w.imr1);
466
467 if (!test_bit(SAB82532_XPR, &up->irqflags))
468 return;
469
470 clear_bit(SAB82532_ALLS, &up->irqflags);
471 clear_bit(SAB82532_XPR, &up->irqflags);
472
473 for (i = 0; i < up->port.fifosize; i++) {
474 writeb(xmit->buf[xmit->tail],
475 &up->regs->w.xfifo[i]);
476 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
477 up->port.icount.tx++;
478 if (uart_circ_empty(xmit))
479 break;
480 }
481
482 /* Issue a Transmit Frame command. */
483 sunsab_cec_wait(up);
484 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
485}
486
487/* port->lock is not held. */
488static void sunsab_send_xchar(struct uart_port *port, char ch)
489{
490 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
491 unsigned long flags;
492
493 spin_lock_irqsave(&up->port.lock, flags);
494
495 sunsab_tec_wait(up);
496 writeb(ch, &up->regs->w.tic);
497
498 spin_unlock_irqrestore(&up->port.lock, flags);
499}
500
501/* port->lock held by caller. */
502static void sunsab_stop_rx(struct uart_port *port)
503{
504 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
505
506 up->interrupt_mask0 |= SAB82532_ISR0_TCD;
507 writeb(up->interrupt_mask1, &up->regs->w.imr0);
508}
509
510/* port->lock held by caller. */
511static void sunsab_enable_ms(struct uart_port *port)
512{
513 /* For now we always receive these interrupts. */
514}
515
516/* port->lock is not held. */
517static void sunsab_break_ctl(struct uart_port *port, int break_state)
518{
519 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
520 unsigned long flags;
521 unsigned char val;
522
523 spin_lock_irqsave(&up->port.lock, flags);
524
e4fdee8e 525 val = up->cached_dafo;
1da177e4
LT		 526 if (break_state)
527 val |= SAB82532_DAFO_XBRK;
528 else
529 val &= ~SAB82532_DAFO_XBRK;
e4fdee8e
DM		 530 up->cached_dafo = val;
531
532 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
533 if (test_bit(SAB82532_XPR, &up->irqflags))
534 sunsab_tx_idle(up);
1da177e4
LT		 535
536 spin_unlock_irqrestore(&up->port.lock, flags);
537}
538
539/* port->lock is not held. */
540static int sunsab_startup(struct uart_port *port)
541{
542 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
543 unsigned long flags;
544 unsigned char tmp;
545
546 spin_lock_irqsave(&up->port.lock, flags);
547
548 /*
549 * Wait for any commands or immediate characters
550 */
551 sunsab_cec_wait(up);
552 sunsab_tec_wait(up);
553
554 /*
555 * Clear the FIFO buffers.
556 */
557 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
558 sunsab_cec_wait(up);
559 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
560
561 /*
562 * Clear the interrupt registers.
563 */
564 (void) readb(&up->regs->r.isr0);
565 (void) readb(&up->regs->r.isr1);
566
567 /*
568 * Now, initialize the UART
569 */
570 writeb(0, &up->regs->w.ccr0); /* power-down */
571 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
572 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
573 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
574 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
575 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
576 writeb(0, &up->regs->w.ccr3);
577 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
e4fdee8e
DM		 578 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
579 SAB82532_MODE_RAC);
580 writeb(up->cached_mode, &up->regs->w.mode);
1da177e4
LT		 581 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
582
583 tmp = readb(&up->regs->rw.ccr0);
584 tmp |= SAB82532_CCR0_PU; /* power-up */
585 writeb(tmp, &up->regs->rw.ccr0);
586
587 /*
588 * Finally, enable interrupts
589 */
590 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
591 SAB82532_IMR0_PLLA);
592 writeb(up->interrupt_mask0, &up->regs->w.imr0);
593 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
594 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
595 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
596 SAB82532_IMR1_XPR);
597 writeb(up->interrupt_mask1, &up->regs->w.imr1);
598 set_bit(SAB82532_ALLS, &up->irqflags);
599 set_bit(SAB82532_XPR, &up->irqflags);
600
601 spin_unlock_irqrestore(&up->port.lock, flags);
602
603 return 0;
604}
605
606/* port->lock is not held. */
607static void sunsab_shutdown(struct uart_port *port)
608{
609 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
610 unsigned long flags;
1da177e4
LT		 611
612 spin_lock_irqsave(&up->port.lock, flags);
613
614 /* Disable Interrupts */
615 up->interrupt_mask0 = 0xff;
616 writeb(up->interrupt_mask0, &up->regs->w.imr0);
617 up->interrupt_mask1 = 0xff;
618 writeb(up->interrupt_mask1, &up->regs->w.imr1);
619
620 /* Disable break condition */
e4fdee8e
DM		 621 up->cached_dafo = readb(&up->regs->rw.dafo);
622 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
623 writeb(up->cached_dafo, &up->regs->rw.dafo);
1da177e4
LT		 624
625 /* Disable Receiver */
e4fdee8e
DM		 626 up->cached_mode &= ~SAB82532_MODE_RAC;
627 writeb(up->cached_mode, &up->regs->rw.mode);
1da177e4
LT		 628
629 /*
630 * XXX FIXME
631 *
632 * If the chip is powered down here the system hangs/crashes during
633 * reboot or shutdown. This needs to be investigated further,
634 * similar behaviour occurs in 2.4 when the driver is configured
635 * as a module only. One hint may be that data is sometimes
636 * transmitted at 9600 baud during shutdown (regardless of the
637 * speed the chip was configured for when the port was open).
638 */
639#if 0
640 /* Power Down */
641 tmp = readb(&up->regs->rw.ccr0);
642 tmp &= ~SAB82532_CCR0_PU;
643 writeb(tmp, &up->regs->rw.ccr0);
644#endif
645
646 spin_unlock_irqrestore(&up->port.lock, flags);
647}
648
649/*
650 * This is used to figure out the divisor speeds.
651 *
652 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
653 *
654 * with 0 <= N < 64 and 0 <= M < 16
655 */
656
657static void calc_ebrg(int baud, int *n_ret, int *m_ret)
658{
659 int n, m;
660
661 if (baud == 0) {
662 *n_ret = 0;
663 *m_ret = 0;
664 return;
665 }
666
667 /*
668 * We scale numbers by 10 so that we get better accuracy
669 * without having to use floating point. Here we increment m
670 * until n is within the valid range.
671 */
672 n = (SAB_BASE_BAUD * 10) / baud;
673 m = 0;
674 while (n >= 640) {
675 n = n / 2;
676 m++;
677 }
678 n = (n+5) / 10;
679 /*
680 * We try very hard to avoid speeds with M == 0 since they may
681 * not work correctly for XTAL frequences above 10 MHz.
682 */
683 if ((m == 0) && ((n & 1) == 0)) {
684 n = n / 2;
685 m++;
686 }
687 *n_ret = n - 1;
688 *m_ret = m;
689}
690
691/* Internal routine, port->lock is held and local interrupts are disabled. */
692static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
b179fb8c
DM		 693 unsigned int iflag, unsigned int baud,
694 unsigned int quot)
1da177e4 695{
1da177e4
LT		 696 unsigned char dafo;
697 int bits, n, m;
698
699 /* Byte size and parity */
700 switch (cflag & CSIZE) {
701 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
702 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
703 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
704 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
705 /* Never happens, but GCC is too dumb to figure it out */
706 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
707 }
708
709 if (cflag & CSTOPB) {
710 dafo |= SAB82532_DAFO_STOP;
711 bits++;
712 }
713
714 if (cflag & PARENB) {
715 dafo |= SAB82532_DAFO_PARE;
716 bits++;
717 }
718
719 if (cflag & PARODD) {
720 dafo |= SAB82532_DAFO_PAR_ODD;
721 } else {
722 dafo |= SAB82532_DAFO_PAR_EVEN;
723 }
e4fdee8e 724 up->cached_dafo = dafo;
1da177e4
LT		 725
726 calc_ebrg(baud, &n, &m);
727
e4fdee8e 728 up->cached_ebrg = n | (m << 6);
1da177e4
LT		 729
730 up->tec_timeout = (10 * 1000000) / baud;
731 up->cec_timeout = up->tec_timeout >> 2;
732
733 /* CTS flow control flags */
734 /* We encode read_status_mask and ignore_status_mask like so:
735 *
736 * ---------------------
737 * | ... | ISR1 | ISR0 |
738 * ---------------------
739 * .. 15 8 7 0
740 */
741
742 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
743 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
744 SAB82532_ISR0_CDSC);
745 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
746 SAB82532_ISR1_ALLS |
747 SAB82532_ISR1_XPR) << 8;
748 if (iflag & INPCK)
749 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
750 SAB82532_ISR0_FERR);
751 if (iflag & (BRKINT | PARMRK))
752 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
753
754 /*
755 * Characteres to ignore
756 */
757 up->port.ignore_status_mask = 0;
758 if (iflag & IGNPAR)
759 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
760 SAB82532_ISR0_FERR);
761 if (iflag & IGNBRK) {
762 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
763 /*
764 * If we're ignoring parity and break indicators,
765 * ignore overruns too (for real raw support).
766 */
767 if (iflag & IGNPAR)
768 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
769 }
770
771 /*
772 * ignore all characters if CREAD is not set
773 */
774 if ((cflag & CREAD) == 0)
775 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
776 SAB82532_ISR0_TCD);
777
b179fb8c
DM		 778 uart_update_timeout(&up->port, cflag,
779 (up->port.uartclk / (16 * quot)));
780
e4fdee8e
DM		 781 /* Now schedule a register update when the chip's
782 * transmitter is idle.
783 */
784 up->cached_mode |= SAB82532_MODE_RAC;
785 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
786 if (test_bit(SAB82532_XPR, &up->irqflags))
787 sunsab_tx_idle(up);
1da177e4
LT		 788}
789
790/* port->lock is not held. */
791static void sunsab_set_termios(struct uart_port *port, struct termios *termios,
792 struct termios *old)
793{
794 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
795 unsigned long flags;
b179fb8c
DM		 796 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
797 unsigned int quot = uart_get_divisor(port, baud);
1da177e4
LT		 798
799 spin_lock_irqsave(&up->port.lock, flags);
b179fb8c 800 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
1da177e4
LT		 801 spin_unlock_irqrestore(&up->port.lock, flags);
802}
803
804static const char *sunsab_type(struct uart_port *port)
805{
806 struct uart_sunsab_port *up = (void *)port;
807 static char buf[36];
808
809 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
810 return buf;
811}
812
813static void sunsab_release_port(struct uart_port *port)
814{
815}
816
817static int sunsab_request_port(struct uart_port *port)
818{
819 return 0;
820}
821
822static void sunsab_config_port(struct uart_port *port, int flags)
823{
824}
825
826static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
827{
828 return -EINVAL;
829}
830
831static struct uart_ops sunsab_pops = {
832 .tx_empty = sunsab_tx_empty,
833 .set_mctrl = sunsab_set_mctrl,
834 .get_mctrl = sunsab_get_mctrl,
835 .stop_tx = sunsab_stop_tx,
836 .start_tx = sunsab_start_tx,
837 .send_xchar = sunsab_send_xchar,
838 .stop_rx = sunsab_stop_rx,
839 .enable_ms = sunsab_enable_ms,
840 .break_ctl = sunsab_break_ctl,
841 .startup = sunsab_startup,
842 .shutdown = sunsab_shutdown,
843 .set_termios = sunsab_set_termios,
844 .type = sunsab_type,
845 .release_port = sunsab_release_port,
846 .request_port = sunsab_request_port,
847 .config_port = sunsab_config_port,
848 .verify_port = sunsab_verify_port,
849};
850
851static struct uart_driver sunsab_reg = {
852 .owner = THIS_MODULE,
853 .driver_name = "serial",
854 .devfs_name = "tts/",
855 .dev_name = "ttyS",
856 .major = TTY_MAJOR,
857};
858
859static struct uart_sunsab_port *sunsab_ports;
860static int num_channels;
861
862#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
863
864static __inline__ void sunsab_console_putchar(struct uart_sunsab_port *up, char c)
865{
866 unsigned long flags;
867
868 spin_lock_irqsave(&up->port.lock, flags);
869
870 sunsab_tec_wait(up);
871 writeb(c, &up->regs->w.tic);
872
873 spin_unlock_irqrestore(&up->port.lock, flags);
874}
875
876static void sunsab_console_write(struct console *con, const char *s, unsigned n)
877{
878 struct uart_sunsab_port *up = &sunsab_ports[con->index];
879 int i;
880
881 for (i = 0; i < n; i++) {
882 if (*s == '\n')
883 sunsab_console_putchar(up, '\r');
884 sunsab_console_putchar(up, *s++);
885 }
886 sunsab_tec_wait(up);
887}
888
889static int sunsab_console_setup(struct console *con, char *options)
890{
891 struct uart_sunsab_port *up = &sunsab_ports[con->index];
892 unsigned long flags;
b179fb8c 893 unsigned int baud, quot;
1da177e4
LT		 894
895 printk("Console: ttyS%d (SAB82532)\n",
896 (sunsab_reg.minor - 64) + con->index);
897
898 sunserial_console_termios(con);
899
1da177e4
LT		 900 switch (con->cflag & CBAUD) {
901 case B150: baud = 150; break;
902 case B300: baud = 300; break;
903 case B600: baud = 600; break;
904 case B1200: baud = 1200; break;
905 case B2400: baud = 2400; break;
906 case B4800: baud = 4800; break;
907 default: case B9600: baud = 9600; break;
908 case B19200: baud = 19200; break;
909 case B38400: baud = 38400; break;
c126cf80
ED		 910 case B57600: baud = 57600; break;
911 case B115200: baud = 115200; break;
912 case B230400: baud = 230400; break;
913 case B460800: baud = 460800; break;
1da177e4
LT		 914 };
915
916 /*
917 * Temporary fix.
918 */
919 spin_lock_init(&up->port.lock);
920
921 /*
922 * Initialize the hardware
923 */
924 sunsab_startup(&up->port);
925
926 spin_lock_irqsave(&up->port.lock, flags);
927
928 /*
929 * Finally, enable interrupts
930 */
931 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
932 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
933 writeb(up->interrupt_mask0, &up->regs->w.imr0);
934 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
935 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
936 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
937 SAB82532_IMR1_XPR;
938 writeb(up->interrupt_mask1, &up->regs->w.imr1);
939
b179fb8c
DM		 940 quot = uart_get_divisor(&up->port, baud);
941 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
1da177e4
LT		 942 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
943
944 spin_unlock_irqrestore(&up->port.lock, flags);
945
946 return 0;
947}
948
949static struct console sunsab_console = {
950 .name = "ttyS",
951 .write = sunsab_console_write,
952 .device = uart_console_device,
953 .setup = sunsab_console_setup,
954 .flags = CON_PRINTBUFFER,
955 .index = -1,
956 .data = &sunsab_reg,
957};
958#define SUNSAB_CONSOLE (&sunsab_console)
959
960static void __init sunsab_console_init(void)
961{
962 int i;
963
964 if (con_is_present())
965 return;
966
967 for (i = 0; i < num_channels; i++) {
968 int this_minor = sunsab_reg.minor + i;
969
970 if ((this_minor - 64) == (serial_console - 1))
971 break;
972 }
973 if (i == num_channels)
974 return;
975
976 sunsab_console.index = i;
977 register_console(&sunsab_console);
978}
979#else
980#define SUNSAB_CONSOLE (NULL)
981#define sunsab_console_init() do { } while (0)
982#endif
983
984static void __init for_each_sab_edev(void (*callback)(struct linux_ebus_device *, void *), void *arg)
985{
986 struct linux_ebus *ebus;
987 struct linux_ebus_device *edev = NULL;
988
989 for_each_ebus(ebus) {
990 for_each_ebusdev(edev, ebus) {
991 if (!strcmp(edev->prom_name, "se")) {
992 callback(edev, arg);
993 continue;
994 } else if (!strcmp(edev->prom_name, "serial")) {
995 char compat[32];
996 int clen;
997
998 /* On RIO this can be an SE, check it. We could
999 * just check ebus->is_rio, but this is more portable.
1000 */
1001 clen = prom_getproperty(edev->prom_node, "compatible",
1002 compat, sizeof(compat));
1003 if (clen > 0) {
1004 if (strncmp(compat, "sab82532", 8) == 0) {
1005 callback(edev, arg);
1006 continue;
1007 }
1008 }
1009 }
1010 }
1011 }
1012}
1013
1014static void __init sab_count_callback(struct linux_ebus_device *edev, void *arg)
1015{
1016 int *count_p = arg;
1017
1018 (*count_p)++;
1019}
1020
1021static void __init sab_attach_callback(struct linux_ebus_device *edev, void *arg)
1022{
1023 int *instance_p = arg;
1024 struct uart_sunsab_port *up;
1025 unsigned long regs, offset;
1026 int i;
1027
1028 /* Note: ports are located in reverse order */
1029 regs = edev->resource[0].start;
1030 offset = sizeof(union sab82532_async_regs);
1031 for (i = 0; i < 2; i++) {
1032 up = &sunsab_ports[(*instance_p * 2) + 1 - i];
1033
1034 memset(up, 0, sizeof(*up));
1035 up->regs = ioremap(regs + offset, sizeof(union sab82532_async_regs));
1036 up->port.irq = edev->irqs[0];
1037 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
1038 up->port.mapbase = (unsigned long)up->regs;
9b4a1617 1039 up->port.iotype = UPIO_MEM;
1da177e4
LT		 1040
1041 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
1042
1043 offset -= sizeof(union sab82532_async_regs);
1044 }
1045
1046 (*instance_p)++;
1047}
1048
1049static int __init probe_for_sabs(void)
1050{
1051 int this_sab = 0;
1052
1053 /* Find device instances. */
1054 for_each_sab_edev(&sab_count_callback, &this_sab);
1055 if (!this_sab)
1056 return -ENODEV;
1057
1058 /* Allocate tables. */
1059 sunsab_ports = kmalloc(sizeof(struct uart_sunsab_port) * this_sab * 2,
1060 GFP_KERNEL);
1061 if (!sunsab_ports)
1062 return -ENOMEM;
1063
1064 num_channels = this_sab * 2;
1065
1066 this_sab = 0;
1067 for_each_sab_edev(&sab_attach_callback, &this_sab);
1068 return 0;
1069}
1070
1071static void __init sunsab_init_hw(void)
1072{
1073 int i;
1074
1075 for (i = 0; i < num_channels; i++) {
1076 struct uart_sunsab_port *up = &sunsab_ports[i];
1077
1078 up->port.line = i;
1079 up->port.ops = &sunsab_pops;
1080 up->port.type = PORT_SUNSAB;
1081 up->port.uartclk = SAB_BASE_BAUD;
1082
1083 up->type = readb(&up->regs->r.vstr) & 0x0f;
1084 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
1085 writeb(0xff, &up->regs->w.pim);
1086 if (up->port.line == 0) {
1087 up->pvr_dsr_bit = (1 << 0);
1088 up->pvr_dtr_bit = (1 << 1);
1089 } else {
1090 up->pvr_dsr_bit = (1 << 3);
1091 up->pvr_dtr_bit = (1 << 2);
1092 }
e4fdee8e
DM		 1093 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
1094 writeb(up->cached_pvr, &up->regs->w.pvr);
1095 up->cached_mode = readb(&up->regs->rw.mode);
1096 up->cached_mode |= SAB82532_MODE_FRTS;
1097 writeb(up->cached_mode, &up->regs->rw.mode);
1098 up->cached_mode |= SAB82532_MODE_RTS;
1099 writeb(up->cached_mode, &up->regs->rw.mode);
1da177e4
LT		 1100
1101 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1102 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1103
1104 if (!(up->port.line & 0x01)) {
1105 if (request_irq(up->port.irq, sunsab_interrupt,
1106 SA_SHIRQ, "serial(sab82532)", up)) {
1107 printk("sunsab%d: can't get IRQ %x\n",
1108 i, up->port.irq);
1109 continue;
1110 }
1111 }
1112 }
1113}
1114
1115static int __init sunsab_init(void)
1116{
1117 int ret = probe_for_sabs();
1118 int i;
1119
1120 if (ret < 0)
1121 return ret;
1122
1123 sunsab_init_hw();
1124
1125 sunsab_reg.minor = sunserial_current_minor;
1126 sunsab_reg.nr = num_channels;
1127 sunsab_reg.cons = SUNSAB_CONSOLE;
1128
1129 ret = uart_register_driver(&sunsab_reg);
1130 if (ret < 0) {
1131 int i;
1132
1133 for (i = 0; i < num_channels; i++) {
1134 struct uart_sunsab_port *up = &sunsab_ports[i];
1135
1136 if (!(up->port.line & 0x01))
1137 free_irq(up->port.irq, up);
1138 iounmap(up->regs);
1139 }
1140 kfree(sunsab_ports);
1141 sunsab_ports = NULL;
1142
1143 return ret;
1144 }
1145
1146 sunserial_current_minor += num_channels;
1147
1148 sunsab_console_init();
1149
1150 for (i = 0; i < num_channels; i++) {
1151 struct uart_sunsab_port *up = &sunsab_ports[i];
1152
1153 uart_add_one_port(&sunsab_reg, &up->port);
1154 }
1155
1156 return 0;
1157}
1158
1159static void __exit sunsab_exit(void)
1160{
1161 int i;
1162
1163 for (i = 0; i < num_channels; i++) {
1164 struct uart_sunsab_port *up = &sunsab_ports[i];
1165
1166 uart_remove_one_port(&sunsab_reg, &up->port);
1167
1168 if (!(up->port.line & 0x01))
1169 free_irq(up->port.irq, up);
1170 iounmap(up->regs);
1171 }
1172
1173 sunserial_current_minor -= num_channels;
1174 uart_unregister_driver(&sunsab_reg);
1175
1176 kfree(sunsab_ports);
1177 sunsab_ports = NULL;
1178}
1179
1180module_init(sunsab_init);
1181module_exit(sunsab_exit);
1182
1183MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1184MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1185MODULE_LICENSE("GPL");
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