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pata_legacy: fix CONFIG_PATA_WINBOND_VLB_MODULE test
[net-next-2.6.git] / drivers / serial / sh-sci.h
CommitLineData
1da177e4 1#include <linux/serial_core.h>
edad1f20 2#include <linux/io.h>
69edbba0 3#include <linux/gpio.h>
3ea6bc3d 4
1da177e4
LT		 5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
1da177e4 11
0fbde950
MD		 12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4
LT		 19#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
20# define SCIF0 0xA4400000
21# define SCIF2 0xA4410000
b7a76e4b
PM		 22# define SCSMR_Ir 0xA44A0000
23# define IRDA_SCIF SCIF0
1da177e4
LT		 24# define SCPCR 0xA4000116
25# define SCPDR 0xA4000136
26
27/* Set the clock source,
28 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
29 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
30 */
31# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
31a49c4b 32#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0 33 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
8d099d44
MD		 34 defined(CONFIG_ARCH_SH7367) || \
35 defined(CONFIG_ARCH_SH7377) || \
36 defined(CONFIG_ARCH_SH7372)
3ea6bc3d 37# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
fd88cac9
PM		 38# define PORT_PTCR 0xA405011EUL
39# define PORT_PVCR 0xA4050122UL
40# define SCIF_ORER 0x0200 /* overrun error bit */
1da177e4 41#elif defined(CONFIG_SH_RTS7751R2D)
7abc404a 42# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
1da177e4
LT		 43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
44# define SCIF_ORER 0x0001 /* overrun error bit */
45# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
05627486
PM		 46#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
47 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
48 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
49 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
50 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
51 defined(CONFIG_CPU_SUBTYPE_SH7751R)
1da177e4
LT		 52# define SCSPTR1 0xffe0001c /* 8 bit SCI */
53# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
54# define SCIF_ORER 0x0001 /* overrun error bit */
55# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
56 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
57 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
1da177e4 58#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
b7a76e4b
PM		 59# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
60# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
61# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
1da177e4
LT		 62# define SCIF_ORER 0x0001 /* overrun error bit */
63# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2b1bd1ac 64#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
e108b2ca 65# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
9465a54f
NI		 66# define SCIF_ORER 0x0001 /* overrun error bit */
67# define PACR 0xa4050100
68# define PBCR 0xa4050102
69# define SCSCR_INIT(port) 0x3B
e108b2ca
PM		 70#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
71# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
72# define SCSPTR1 0xffe10010 /* 16 bit SCIF */
73# define SCSPTR2 0xffe20010 /* 16 bit SCIF */
74# define SCSPTR3 0xffe30010 /* 16 bit SCIF */
75# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
41504c39 76#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
346b7463
MD		 77# define PADR 0xA4050120
78# define PSDR 0xA405013e
79# define PWDR 0xA4050166
80# define PSCR 0xA405011E
41504c39
PM		 81# define SCIF_ORER 0x0001 /* overrun error bit */
82# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9109a30e
MD		 83#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
84# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
85# define SCSPTR0 SCPDR0
86# define SCIF_ORER 0x0001 /* overrun error bit */
87# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
178dd0cd
PM		 88#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
89# define SCSPTR0 0xa4050160
90# define SCSPTR1 0xa405013e
91# define SCSPTR2 0xa4050160
92# define SCSPTR3 0xa405013e
93# define SCSPTR4 0xa4050128
94# define SCSPTR5 0xa4050128
95# define SCIF_ORER 0x0001 /* overrun error bit */
96# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
47948d2b
KM		 97#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
98# define SCIF_ORER 0x0001 /* overrun error bit */
d7bbf7f5
GL		 99# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \
100 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
101 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
1da177e4 102#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
1da177e4
LT		 103# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
104# define SCIF_ORER 0x0001 /* overrun error bit */
105# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4 106#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
1da177e4
LT		 107# define SCIF_BASE_ADDR 0x01030000
108# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
109# define SCIF_PTR2_OFFS 0x0000020
110# define SCIF_LSR2_OFFS 0x0000024
1da177e4
LT		 111# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
112# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
f9669187 113# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
1da177e4 114#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
1da177e4 115# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4
LT		 116# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
117#elif defined(CONFIG_H8S2678)
1da177e4 118# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
1da177e4 119# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
c01f0f1a
YS		 120#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
121# define SCSPTR0 0xfe4b0020
122# define SCSPTR1 0xfe4b0020
123# define SCSPTR2 0xfe4b0020
124# define SCIF_ORER 0x0001
125# define SCSCR_INIT(port) 0x38
126# define SCIF_ONLY
7d740a06
YS		 127#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
128# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
129# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
c63847a3 130# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
7d740a06 131# define SCIF_ORER 0x0001 /* overrun error bit */
c63847a3 132# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
b7a76e4b
PM		 133#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
134# define SCSPTR0 0xff923020 /* 16 bit SCIF */
135# define SCSPTR1 0xff924020 /* 16 bit SCIF */
136# define SCSPTR2 0xff925020 /* 16 bit SCIF */
137# define SCIF_ORER 0x0001 /* overrun error bit */
138# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
b7a76e4b
PM		 139#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
140# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
141# define SCSPTR1 0xffe10024 /* 16 bit SCIF */
e108b2ca 142# define SCIF_ORER 0x0001 /* Overrun error bit */
3a598264
HM		 143
144#if defined(CONFIG_SH_SH2007)
145/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */
146# define SCSCR_INIT(port) 0x38
147#else
148/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */
149# define SCSCR_INIT(port) 0x3a
150#endif
151
55ba99eb
KM		 152#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
153 defined(CONFIG_CPU_SUBTYPE_SH7786)
32351a28
PM		 154# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
155# define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
156# define SCSPTR2 0xffec0024 /* 16 bit SCIF */
157# define SCSPTR3 0xffed0024 /* 16 bit SCIF */
158# define SCSPTR4 0xffee0024 /* 16 bit SCIF */
159# define SCSPTR5 0xffef0024 /* 16 bit SCIF */
34aeb43e 160# define SCIF_ORER 0x0001 /* Overrun error bit */
32351a28 161# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2825999e
PG		 162#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
163 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
a8f67f4b
PM		 164 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
165 defined(CONFIG_CPU_SUBTYPE_SH7263)
9d4436a6
YS		 166# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
167# define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
168# define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
169# define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
2825999e
PG		 170# if defined(CONFIG_CPU_SUBTYPE_SH7201)
171# define SCSPTR4 0xfffeA020 /* 16 bit SCIF */
172# define SCSPTR5 0xfffeA820 /* 16 bit SCIF */
173# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */
174# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */
175# endif
9d4436a6 176# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
9d4436a6
YS		 177#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
178# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
179# define SCSPTR1 0xf8410020 /* 16 bit SCIF */
180# define SCSPTR2 0xf8420020 /* 16 bit SCIF */
181# define SCIF_ORER 0x0001 /* overrun error bit */
182# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
2b1bd1ac
PM		 183#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
184# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
185# define SCSPTR1 0xffc40020 /* 16 bit SCIF */
186# define SCSPTR2 0xffc50020 /* 16 bit SCIF */
187# define SCSPTR3 0xffc60020 /* 16 bit SCIF */
188# define SCIF_ORER 0x0001 /* Overrun error bit */
189# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
1da177e4
LT		 190#else
191# error CPU subtype not defined
192#endif
193
194/* SCSCR */
195#define SCI_CTRL_FLAGS_TIE 0x80 /* all */
196#define SCI_CTRL_FLAGS_RIE 0x40 /* all */
197#define SCI_CTRL_FLAGS_TE 0x20 /* all */
198#define SCI_CTRL_FLAGS_RE 0x10 /* all */
05627486
PM		 199#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
200 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
201 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
a8884e34 202 defined(CONFIG_CPU_SUBTYPE_SH7722) || \
05627486
PM		 203 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
204 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
205 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
c63847a3 206 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
05627486 207 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
2b1bd1ac 208 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
55ba99eb 209 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
2b1bd1ac 210 defined(CONFIG_CPU_SUBTYPE_SHX3)
1da177e4 211#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
d7bbf7f5
GL		 212#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
213#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8)
1da177e4
LT		 214#else
215#define SCI_CTRL_FLAGS_REIE 0
216#endif
217/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
218/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
219/* SCI_CTRL_FLAGS_CKE1 0x02 * all */
220/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
221
222/* SCxSR SCI */
223#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
224#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
225#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
226#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
227#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
228#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
229/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
230/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
231
232#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
233
234/* SCxSR SCIF */
235#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
236#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
237#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
238#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
239#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
240#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
241#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
242#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
243
3ea6bc3d 244#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 245 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0 246 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
8d099d44
MD		 247 defined(CONFIG_ARCH_SH7367) || \
248 defined(CONFIG_ARCH_SH7377) || \
249 defined(CONFIG_ARCH_SH7372)
c63847a3
NI		 250# define SCIF_ORER 0x0200
251# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
252# define SCIF_RFDC_MASK 0x007f
253# define SCIF_TXROOM_MAX 64
254#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
255# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
256# define SCIF_RFDC_MASK 0x007f
257# define SCIF_TXROOM_MAX 64
258/* SH7763 SCIF2 support */
259# define SCIF2_RFDC_MASK 0x001f
260# define SCIF2_TXROOM_MAX 16
1da177e4 261#else
c63847a3
NI		 262# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
263# define SCIF_RFDC_MASK 0x001f
264# define SCIF_TXROOM_MAX 16
1da177e4
LT		 265#endif
266
d830fa45
PM		 267#ifndef SCIF_ORER
268#define SCIF_ORER 0x0000
269#endif
270
15c73aaa
PM		 271#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
272#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
273#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
274#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
275#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
276#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
277#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
d830fa45 278#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
15c73aaa 279
3ea6bc3d 280#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 281 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0 282 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
8d099d44
MD		 283 defined(CONFIG_ARCH_SH7367) || \
284 defined(CONFIG_ARCH_SH7377) || \
285 defined(CONFIG_ARCH_SH7372)
15c73aaa
PM		 286# define SCxSR_RDxF_CLEAR(port) (sci_in(port, SCxSR) & 0xfffc)
287# define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
288# define SCxSR_TDxE_CLEAR(port) (sci_in(port, SCxSR) & 0xffdf)
289# define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
1da177e4 290#else
1da177e4
LT		 291# define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
292# define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
293# define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
294# define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
295#endif
296
297/* SCFCR */
298#define SCFCR_RFRST 0x0002
299#define SCFCR_TFRST 0x0004
300#define SCFCR_TCRST 0x4000
301#define SCFCR_MCE 0x0008
302
303#define SCI_MAJOR 204
304#define SCI_MINOR_START 8
305
306/* Generic serial flags */
307#define SCI_RX_THROTTLE 0x0000001
308
309#define SCI_MAGIC 0xbabeface
310
311/*
312 * Events are used to schedule things to happen at timer-interrupt
313 * time, instead of at rs interrupt time.
314 */
315#define SCI_EVENT_WRITE_WAKEUP 0
316
1da177e4 317#define SCI_IN(size, offset) \
b7a76e4b 318 if ((size) == 8) { \
7ff731ae 319 return ioread8(port->membase + (offset)); \
b7a76e4b 320 } else { \
7ff731ae 321 return ioread16(port->membase + (offset)); \
1da177e4
LT		 322 }
323#define SCI_OUT(size, offset, value) \
b7a76e4b 324 if ((size) == 8) { \
7ff731ae 325 iowrite8(value, port->membase + (offset)); \
3d2c2f3e 326 } else if ((size) == 16) { \
7ff731ae 327 iowrite16(value, port->membase + (offset)); \
1da177e4
LT		 328 }
329
330#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
331 static inline unsigned int sci_##name##_in(struct uart_port *port) \
332 { \
d1d4b10c 333 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
1a22f08d
YS		 334 SCI_IN(scif_size, scif_offset) \
335 } else { /* PORT_SCI or PORT_SCIFA */ \
336 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 337 } \
338 } \
339 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
340 { \
d1d4b10c 341 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
1a22f08d
YS		 342 SCI_OUT(scif_size, scif_offset, value) \
343 } else { /* PORT_SCI or PORT_SCIFA */ \
344 SCI_OUT(sci_size, sci_offset, value); \
1da177e4
LT		 345 } \
346 }
347
168f3623
YS		 348#ifdef CONFIG_H8300
349/* h8300 don't have SCIF */
350#define CPU_SCIF_FNS(name) \
351 static inline unsigned int sci_##name##_in(struct uart_port *port) \
352 { \
353 return 0; \
354 } \
355 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
356 { \
357 }
358#else
359#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
1da177e4
LT		 360 static inline unsigned int sci_##name##_in(struct uart_port *port) \
361 { \
b7a76e4b 362 SCI_IN(scif_size, scif_offset); \
1da177e4
LT		 363 } \
364 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
365 { \
366 SCI_OUT(scif_size, scif_offset, value); \
367 }
168f3623 368#endif
1da177e4
LT		 369
370#define CPU_SCI_FNS(name, sci_offset, sci_size) \
371 static inline unsigned int sci_##name##_in(struct uart_port* port) \
372 { \
b7a76e4b 373 SCI_IN(sci_size, sci_offset); \
1da177e4
LT		 374 } \
375 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
376 { \
377 SCI_OUT(sci_size, sci_offset, value); \
378 }
379
8d099d44
MD		 380#if defined(CONFIG_CPU_SH3) || \
381 defined(CONFIG_ARCH_SH7367) || \
382 defined(CONFIG_ARCH_SH7377) || \
383 defined(CONFIG_ARCH_SH7372)
9465a54f
NI		 384#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
385#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
386 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
387 h8_sci_offset, h8_sci_size) \
388 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
389#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
390 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
3ea6bc3d 391#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 392 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0 393 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
8d099d44 394 defined(CONFIG_ARCH_SH7367) || \
d1d4b10c
GL		 395 defined(CONFIG_ARCH_SH7377)
396#define SCIF_FNS(name, scif_offset, scif_size) \
397 CPU_SCIF_FNS(name, scif_offset, scif_size)
398#elif defined(CONFIG_ARCH_SH7372)
399#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
400 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
1da177e4
LT		 401#define SCIF_FNS(name, scif_offset, scif_size) \
402 CPU_SCIF_FNS(name, scif_offset, scif_size)
403#else
404#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
405 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
406 h8_sci_offset, h8_sci_size) \
407 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
408#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
409 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
410#endif
411#elif defined(__H8300H__) || defined(__H8300S__)
412#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
413 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
414 h8_sci_offset, h8_sci_size) \
415 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
168f3623
YS		 416#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
417 CPU_SCIF_FNS(name)
47948d2b
KM		 418#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
419 defined(CONFIG_CPU_SUBTYPE_SH7724)
178dd0cd
PM		 420 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
421 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
422 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
423 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
1da177e4
LT		 424#else
425#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
426 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
427 h8_sci_offset, h8_sci_size) \
428 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
429#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
430 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
431#endif
432
3ea6bc3d 433#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 434 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0 435 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
8d099d44 436 defined(CONFIG_ARCH_SH7367) || \
d1d4b10c 437 defined(CONFIG_ARCH_SH7377)
9465a54f 438
1da177e4
LT		 439SCIF_FNS(SCSMR, 0x00, 16)
440SCIF_FNS(SCBRR, 0x04, 8)
441SCIF_FNS(SCSCR, 0x08, 16)
442SCIF_FNS(SCTDSR, 0x0c, 8)
443SCIF_FNS(SCFER, 0x10, 16)
444SCIF_FNS(SCxSR, 0x14, 16)
445SCIF_FNS(SCFCR, 0x18, 16)
446SCIF_FNS(SCFDR, 0x1c, 16)
447SCIF_FNS(SCxTDR, 0x20, 8)
448SCIF_FNS(SCxRDR, 0x24, 8)
8a77b8d0 449SCIF_FNS(SCLSR, 0x00, 0)
d1d4b10c
GL		 450#elif defined(CONFIG_ARCH_SH7372)
451SCIF_FNS(SCSMR, 0x00, 16)
452SCIF_FNS(SCBRR, 0x04, 8)
453SCIF_FNS(SCSCR, 0x08, 16)
454SCIF_FNS(SCTDSR, 0x0c, 16)
455SCIF_FNS(SCFER, 0x10, 16)
456SCIF_FNS(SCxSR, 0x14, 16)
457SCIF_FNS(SCFCR, 0x18, 16)
458SCIF_FNS(SCFDR, 0x1c, 16)
459SCIF_FNS(SCTFDR, 0x38, 16)
460SCIF_FNS(SCRFDR, 0x3c, 16)
461SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
462SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
463SCIF_FNS(SCLSR, 0x00, 0)
47948d2b
KM		 464#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
465 defined(CONFIG_CPU_SUBTYPE_SH7724)
178dd0cd
PM		 466SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
467SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
468SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
469SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
470SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
471SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
f686359e 472SCIx_FNS(SCSPTR, 0, 0, 0, 0)
178dd0cd
PM		 473SCIF_FNS(SCTDSR, 0x0c, 8)
474SCIF_FNS(SCFER, 0x10, 16)
475SCIF_FNS(SCFCR, 0x18, 16)
476SCIF_FNS(SCFDR, 0x1c, 16)
477SCIF_FNS(SCLSR, 0x24, 16)
1da177e4
LT		 478#else
479/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
480/* name off sz off sz off sz off sz off sz*/
481SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
482SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
483SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
484SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
485SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
486SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
487SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
32351a28
PM		 488#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
489 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
55ba99eb
KM		 490 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
491 defined(CONFIG_CPU_SUBTYPE_SH7786)
c2697968 492SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
b7a76e4b
PM		 493SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
494SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
495SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
496SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
c2697968 497#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
c63847a3
NI		 498SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
499SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16)
c2697968
PM		 500SCIF_FNS(SCLSR2, 0, 0, 0x24, 16)
501SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
502SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
503SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
504SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
b7a76e4b 505#else
1da177e4 506SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
9b4e466f
MD		 507#if defined(CONFIG_CPU_SUBTYPE_SH7722)
508SCIF_FNS(SCSPTR, 0, 0, 0, 0)
509#else
1da177e4 510SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
9b4e466f 511#endif
1da177e4
LT		 512SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
513#endif
b7a76e4b 514#endif
1da177e4
LT		 515#define sci_in(port, reg) sci_##reg##_in(port)
516#define sci_out(port, reg, value) sci_##reg##_out(port, value)
517
518/* H8/300 series SCI pins assignment */
519#if defined(__H8300H__) || defined(__H8300S__)
520static const struct __attribute__((packed)) {
521 int port; /* GPIO port no */
522 unsigned short rx,tx; /* GPIO bit no */
523} h8300_sci_pins[] = {
524#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
525 { /* SCI0 */
526 .port = H8300_GPIO_P9,
527 .rx = H8300_GPIO_B2,
528 .tx = H8300_GPIO_B0,
529 },
530 { /* SCI1 */
531 .port = H8300_GPIO_P9,
532 .rx = H8300_GPIO_B3,
533 .tx = H8300_GPIO_B1,
534 },
535 { /* SCI2 */
536 .port = H8300_GPIO_PB,
537 .rx = H8300_GPIO_B7,
538 .tx = H8300_GPIO_B6,
539 }
540#elif defined(CONFIG_H8S2678)
541 { /* SCI0 */
542 .port = H8300_GPIO_P3,
543 .rx = H8300_GPIO_B2,
544 .tx = H8300_GPIO_B0,
545 },
546 { /* SCI1 */
547 .port = H8300_GPIO_P3,
548 .rx = H8300_GPIO_B3,
549 .tx = H8300_GPIO_B1,
550 },
551 { /* SCI2 */
552 .port = H8300_GPIO_P5,
553 .rx = H8300_GPIO_B1,
554 .tx = H8300_GPIO_B0,
555 }
556#endif
557};
558#endif
559
0fbde950
MD		 560#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
561 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
562 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
563 defined(CONFIG_CPU_SUBTYPE_SH7709)
1da177e4
LT		 564static inline int sci_rxd_in(struct uart_port *port)
565{
566 if (port->mapbase == 0xfffffe80)
32b53076 567 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
3ea6bc3d
MB		 568 return 1;
569}
05627486
PM		 570#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
571 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
572 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
573 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
574 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
961e9ff9 575 defined(CONFIG_CPU_SUBTYPE_SH7091)
1da177e4
LT		 576static inline int sci_rxd_in(struct uart_port *port)
577{
1da177e4 578 if (port->mapbase == 0xffe00000)
32b53076 579 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
47948d2b
KM		 580 return 1;
581}
1da177e4
LT		 582#elif defined(__H8300H__) || defined(__H8300S__)
583static inline int sci_rxd_in(struct uart_port *port)
584{
585 int ch = (port->mapbase - SMR0) >> 3;
586 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
587}
9e9622d1 588#else /* default case for non-SCI processors */
2b1bd1ac
PM		 589static inline int sci_rxd_in(struct uart_port *port)
590{
1760b7d7 591 return 1;
2b1bd1ac 592}
1da177e4
LT		 593#endif
594
595/*
596 * Values for the BitRate Register (SCBRR)
597 *
598 * The values are actually divisors for a frequency which can
599 * be internal to the SH3 (14.7456MHz) or derived from an external
600 * clock source. This driver assumes the internal clock is used;
601 * to support using an external clock source, config options or
602 * possibly command-line options would need to be added.
603 *
604 * Also, to support speeds below 2400 (why?) the lower 2 bits of
605 * the SCSMR register would also need to be set to non-zero values.
606 *
607 * -- Greg Banks 27Feb2000
608 *
609 * Answer: The SCBRR register is only eight bits, and the value in
610 * it gets larger with lower baud rates. At around 2400 (depending on
611 * the peripherial module clock) you run out of bits. However the
612 * lower two bits of SCSMR allow the module clock to be divided down,
613 * scaling the value which is needed in SCBRR.
614 *
615 * -- Stuart Menefy - 23 May 2000
616 *
617 * I meant, why would anyone bother with bitrates below 2400.
618 *
619 * -- Greg Banks - 7Jul2000
620 *
621 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
622 * tape reader as a console!
623 *
624 * -- Mitch Davis - 15 Jul 2000
625 */
626
3a598264
HM		 627#if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \
628 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
629 defined(CONFIG_CPU_SUBTYPE_SH7786)) && \
630 !defined(CONFIG_SH_SH2007)
b7a76e4b 631#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
3ea6bc3d 632#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31a49c4b 633 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
8a77b8d0 634 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
8d099d44
MD		 635 defined(CONFIG_ARCH_SH7367) || \
636 defined(CONFIG_ARCH_SH7377) || \
637 defined(CONFIG_ARCH_SH7372)
b7a76e4b 638#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
47948d2b
KM		 639#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
640 defined(CONFIG_CPU_SUBTYPE_SH7724)
ba1d2818
NI		 641static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
642{
643 if (port->type == PORT_SCIF)
644 return (clk+16*bps)/(32*bps)-1;
645 else
646 return ((clk*2)+16*bps)/(16*bps)-1;
647}
648#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
b7a76e4b 649#elif defined(__H8300H__) || defined(__H8300S__)
a2159b52 650#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
b7a76e4b
PM		 651#else /* Generic SH */
652#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
1da177e4 653#endif
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