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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/serial/sh-sci.c | |
3 | * | |
4 | * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO) | |
5 | * | |
7ff731ae | 6 | * Copyright (C) 2002 - 2008 Paul Mundt |
3ea6bc3d | 7 | * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007). |
1da177e4 LT |
8 | * |
9 | * based off of the old drivers/char/sh-sci.c by: | |
10 | * | |
11 | * Copyright (C) 1999, 2000 Niibe Yutaka | |
12 | * Copyright (C) 2000 Sugioka Toshinobu | |
13 | * Modified to support multiple serial ports. Stuart Menefy (May 2000). | |
14 | * Modified to support SecureEdge. David McCullough (2002) | |
15 | * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003). | |
d89ddd1c | 16 | * Removed SH7300 support (Jul 2007). |
1da177e4 LT |
17 | * |
18 | * This file is subject to the terms and conditions of the GNU General Public | |
19 | * License. See the file "COPYING" in the main directory of this archive | |
20 | * for more details. | |
21 | */ | |
0b3d4ef6 PM |
22 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) |
23 | #define SUPPORT_SYSRQ | |
24 | #endif | |
1da177e4 LT |
25 | |
26 | #undef DEBUG | |
27 | ||
1da177e4 LT |
28 | #include <linux/module.h> |
29 | #include <linux/errno.h> | |
1da177e4 LT |
30 | #include <linux/timer.h> |
31 | #include <linux/interrupt.h> | |
32 | #include <linux/tty.h> | |
33 | #include <linux/tty_flip.h> | |
34 | #include <linux/serial.h> | |
35 | #include <linux/major.h> | |
36 | #include <linux/string.h> | |
37 | #include <linux/sysrq.h> | |
1da177e4 LT |
38 | #include <linux/ioport.h> |
39 | #include <linux/mm.h> | |
1da177e4 LT |
40 | #include <linux/init.h> |
41 | #include <linux/delay.h> | |
42 | #include <linux/console.h> | |
e108b2ca | 43 | #include <linux/platform_device.h> |
96de1a8f | 44 | #include <linux/serial_sci.h> |
1da177e4 LT |
45 | #include <linux/notifier.h> |
46 | #include <linux/cpufreq.h> | |
85f094ec | 47 | #include <linux/clk.h> |
fa5da2f7 | 48 | #include <linux/ctype.h> |
7ff731ae | 49 | #include <linux/err.h> |
85f094ec PM |
50 | |
51 | #ifdef CONFIG_SUPERH | |
b7a76e4b | 52 | #include <asm/clock.h> |
1da177e4 | 53 | #include <asm/sh_bios.h> |
e108b2ca | 54 | #include <asm/kgdb.h> |
1da177e4 LT |
55 | #endif |
56 | ||
1da177e4 LT |
57 | #include "sh-sci.h" |
58 | ||
e108b2ca PM |
59 | struct sci_port { |
60 | struct uart_port port; | |
61 | ||
62 | /* Port type */ | |
63 | unsigned int type; | |
64 | ||
65 | /* Port IRQs: ERI, RXI, TXI, BRI (optional) */ | |
32351a28 | 66 | unsigned int irqs[SCIx_NR_IRQS]; |
e108b2ca PM |
67 | |
68 | /* Port pin configuration */ | |
69 | void (*init_pins)(struct uart_port *port, | |
70 | unsigned int cflag); | |
1da177e4 | 71 | |
e108b2ca PM |
72 | /* Port enable callback */ |
73 | void (*enable)(struct uart_port *port); | |
74 | ||
75 | /* Port disable callback */ | |
76 | void (*disable)(struct uart_port *port); | |
77 | ||
78 | /* Break timer */ | |
79 | struct timer_list break_timer; | |
80 | int break_flag; | |
1534a3b3 | 81 | |
a2159b52 | 82 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 83 | /* Port clock */ |
84 | struct clk *clk; | |
005a336e | 85 | #endif |
e108b2ca PM |
86 | }; |
87 | ||
88 | #ifdef CONFIG_SH_KGDB | |
1da177e4 | 89 | static struct sci_port *kgdb_sci_port; |
e108b2ca | 90 | #endif |
1da177e4 LT |
91 | |
92 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE | |
e108b2ca PM |
93 | static struct sci_port *serial_console_port; |
94 | #endif | |
1da177e4 LT |
95 | |
96 | /* Function prototypes */ | |
b129a8cc | 97 | static void sci_stop_tx(struct uart_port *port); |
1da177e4 | 98 | |
e108b2ca | 99 | #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS |
b7a76e4b | 100 | |
e108b2ca PM |
101 | static struct sci_port sci_ports[SCI_NPORTS]; |
102 | static struct uart_driver sci_uart_driver; | |
1da177e4 | 103 | |
e108b2ca PM |
104 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && \ |
105 | defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) | |
106 | static inline void handle_error(struct uart_port *port) | |
107 | { | |
108 | /* Clear error flags */ | |
1da177e4 LT |
109 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); |
110 | } | |
111 | ||
112 | static int get_char(struct uart_port *port) | |
113 | { | |
114 | unsigned long flags; | |
115 | unsigned short status; | |
116 | int c; | |
117 | ||
e108b2ca PM |
118 | spin_lock_irqsave(&port->lock, flags); |
119 | do { | |
1da177e4 LT |
120 | status = sci_in(port, SCxSR); |
121 | if (status & SCxSR_ERRORS(port)) { | |
122 | handle_error(port); | |
123 | continue; | |
124 | } | |
125 | } while (!(status & SCxSR_RDxF(port))); | |
126 | c = sci_in(port, SCxRDR); | |
127 | sci_in(port, SCxSR); /* Dummy read */ | |
128 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
e108b2ca | 129 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
130 | |
131 | return c; | |
132 | } | |
1da177e4 LT |
133 | #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ |
134 | ||
e108b2ca | 135 | #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || defined(CONFIG_SH_KGDB) |
1da177e4 LT |
136 | static void put_char(struct uart_port *port, char c) |
137 | { | |
138 | unsigned long flags; | |
139 | unsigned short status; | |
140 | ||
e108b2ca | 141 | spin_lock_irqsave(&port->lock, flags); |
1da177e4 LT |
142 | |
143 | do { | |
144 | status = sci_in(port, SCxSR); | |
145 | } while (!(status & SCxSR_TDxE(port))); | |
146 | ||
147 | sci_out(port, SCxTDR, c); | |
148 | sci_in(port, SCxSR); /* Dummy read */ | |
149 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
150 | ||
e108b2ca | 151 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 | 152 | } |
e108b2ca | 153 | #endif |
1da177e4 | 154 | |
e108b2ca | 155 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE |
1da177e4 LT |
156 | static void put_string(struct sci_port *sci_port, const char *buffer, int count) |
157 | { | |
158 | struct uart_port *port = &sci_port->port; | |
159 | const unsigned char *p = buffer; | |
160 | int i; | |
161 | ||
162 | #if defined(CONFIG_SH_STANDARD_BIOS) || defined(CONFIG_SH_KGDB) | |
163 | int checksum; | |
164 | int usegdb=0; | |
165 | ||
166 | #ifdef CONFIG_SH_STANDARD_BIOS | |
b7a76e4b | 167 | /* This call only does a trap the first time it is |
1da177e4 LT |
168 | * called, and so is safe to do here unconditionally |
169 | */ | |
170 | usegdb |= sh_bios_in_gdb_mode(); | |
171 | #endif | |
172 | #ifdef CONFIG_SH_KGDB | |
fa5da2f7 | 173 | usegdb |= (kgdb_in_gdb_mode && (sci_port == kgdb_sci_port)); |
1da177e4 LT |
174 | #endif |
175 | ||
176 | if (usegdb) { | |
177 | /* $<packet info>#<checksum>. */ | |
178 | do { | |
179 | unsigned char c; | |
180 | put_char(port, '$'); | |
181 | put_char(port, 'O'); /* 'O'utput to console */ | |
182 | checksum = 'O'; | |
183 | ||
184 | for (i=0; i<count; i++) { /* Don't use run length encoding */ | |
185 | int h, l; | |
186 | ||
187 | c = *p++; | |
bfd3c7a7 HH |
188 | h = hex_asc_hi(c); |
189 | l = hex_asc_lo(c); | |
1da177e4 LT |
190 | put_char(port, h); |
191 | put_char(port, l); | |
192 | checksum += h + l; | |
193 | } | |
194 | put_char(port, '#'); | |
bfd3c7a7 HH |
195 | put_char(port, hex_asc_hi(checksum)); |
196 | put_char(port, hex_asc_lo(checksum)); | |
1da177e4 LT |
197 | } while (get_char(port) != '+'); |
198 | } else | |
199 | #endif /* CONFIG_SH_STANDARD_BIOS || CONFIG_SH_KGDB */ | |
200 | for (i=0; i<count; i++) { | |
201 | if (*p == 10) | |
202 | put_char(port, '\r'); | |
203 | put_char(port, *p++); | |
204 | } | |
205 | } | |
206 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
207 | ||
1da177e4 | 208 | #ifdef CONFIG_SH_KGDB |
1da177e4 LT |
209 | static int kgdb_sci_getchar(void) |
210 | { | |
e108b2ca | 211 | int c; |
1da177e4 LT |
212 | |
213 | /* Keep trying to read a character, this could be neater */ | |
fa5da2f7 | 214 | while ((c = get_char(&kgdb_sci_port->port)) < 0) |
e108b2ca | 215 | cpu_relax(); |
1da177e4 LT |
216 | |
217 | return c; | |
218 | } | |
219 | ||
e108b2ca | 220 | static inline void kgdb_sci_putchar(int c) |
1da177e4 | 221 | { |
fa5da2f7 | 222 | put_char(&kgdb_sci_port->port, c); |
1da177e4 | 223 | } |
1da177e4 LT |
224 | #endif /* CONFIG_SH_KGDB */ |
225 | ||
226 | #if defined(__H8300S__) | |
227 | enum { sci_disable, sci_enable }; | |
228 | ||
e108b2ca | 229 | static void h8300_sci_config(struct uart_port* port, unsigned int ctrl) |
1da177e4 LT |
230 | { |
231 | volatile unsigned char *mstpcrl=(volatile unsigned char *)MSTPCRL; | |
232 | int ch = (port->mapbase - SMR0) >> 3; | |
233 | unsigned char mask = 1 << (ch+1); | |
234 | ||
235 | if (ctrl == sci_disable) { | |
236 | *mstpcrl |= mask; | |
237 | } else { | |
238 | *mstpcrl &= ~mask; | |
239 | } | |
240 | } | |
e108b2ca PM |
241 | |
242 | static inline void h8300_sci_enable(struct uart_port *port) | |
243 | { | |
244 | h8300_sci_config(port, sci_enable); | |
245 | } | |
246 | ||
247 | static inline void h8300_sci_disable(struct uart_port *port) | |
248 | { | |
249 | h8300_sci_config(port, sci_disable); | |
250 | } | |
1da177e4 LT |
251 | #endif |
252 | ||
e108b2ca PM |
253 | #if defined(SCI_ONLY) || defined(SCI_AND_SCIF) && \ |
254 | defined(__H8300H__) || defined(__H8300S__) | |
1da177e4 LT |
255 | static void sci_init_pins_sci(struct uart_port* port, unsigned int cflag) |
256 | { | |
257 | int ch = (port->mapbase - SMR0) >> 3; | |
258 | ||
259 | /* set DDR regs */ | |
e108b2ca PM |
260 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, |
261 | h8300_sci_pins[ch].rx, | |
262 | H8300_GPIO_INPUT); | |
263 | H8300_GPIO_DDR(h8300_sci_pins[ch].port, | |
264 | h8300_sci_pins[ch].tx, | |
265 | H8300_GPIO_OUTPUT); | |
266 | ||
1da177e4 LT |
267 | /* tx mark output*/ |
268 | H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx; | |
269 | } | |
e108b2ca PM |
270 | #else |
271 | #define sci_init_pins_sci NULL | |
272 | #endif | |
273 | ||
274 | #if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) | |
275 | static void sci_init_pins_irda(struct uart_port *port, unsigned int cflag) | |
276 | { | |
277 | unsigned int fcr_val = 0; | |
278 | ||
279 | if (cflag & CRTSCTS) | |
280 | fcr_val |= SCFCR_MCE; | |
281 | ||
282 | sci_out(port, SCFCR, fcr_val); | |
283 | } | |
284 | #else | |
285 | #define sci_init_pins_irda NULL | |
1da177e4 | 286 | #endif |
e108b2ca PM |
287 | |
288 | #ifdef SCI_ONLY | |
289 | #define sci_init_pins_scif NULL | |
1da177e4 LT |
290 | #endif |
291 | ||
292 | #if defined(SCIF_ONLY) || defined(SCI_AND_SCIF) | |
d89ddd1c | 293 | #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
9465a54f NI |
294 | static void sci_init_pins_scif(struct uart_port* port, unsigned int cflag) |
295 | { | |
296 | unsigned int fcr_val = 0; | |
297 | ||
298 | set_sh771x_scif_pfc(port); | |
299 | if (cflag & CRTSCTS) { | |
300 | fcr_val |= SCFCR_MCE; | |
301 | } | |
302 | sci_out(port, SCFCR, fcr_val); | |
303 | } | |
31a49c4b | 304 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721) |
3ea6bc3d MB |
305 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
306 | { | |
307 | unsigned int fcr_val = 0; | |
308 | unsigned short data; | |
309 | ||
310 | if (cflag & CRTSCTS) { | |
311 | /* enable RTS/CTS */ | |
312 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
313 | /* Clear PTCR bit 9-2; enable all scif pins but sck */ | |
314 | data = ctrl_inw(PORT_PTCR); | |
315 | ctrl_outw((data & 0xfc03), PORT_PTCR); | |
316 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | |
317 | /* Clear PVCR bit 9-2 */ | |
318 | data = ctrl_inw(PORT_PVCR); | |
319 | ctrl_outw((data & 0xfc03), PORT_PVCR); | |
320 | } | |
321 | fcr_val |= SCFCR_MCE; | |
322 | } else { | |
323 | if (port->mapbase == 0xa4430000) { /* SCIF0 */ | |
324 | /* Clear PTCR bit 5-2; enable only tx and rx */ | |
325 | data = ctrl_inw(PORT_PTCR); | |
326 | ctrl_outw((data & 0xffc3), PORT_PTCR); | |
327 | } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ | |
328 | /* Clear PVCR bit 5-2 */ | |
329 | data = ctrl_inw(PORT_PVCR); | |
330 | ctrl_outw((data & 0xffc3), PORT_PVCR); | |
331 | } | |
332 | } | |
333 | sci_out(port, SCFCR, fcr_val); | |
334 | } | |
b7a76e4b | 335 | #elif defined(CONFIG_CPU_SH3) |
e108b2ca | 336 | /* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */ |
1da177e4 LT |
337 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) |
338 | { | |
339 | unsigned int fcr_val = 0; | |
b7a76e4b PM |
340 | unsigned short data; |
341 | ||
342 | /* We need to set SCPCR to enable RTS/CTS */ | |
343 | data = ctrl_inw(SCPCR); | |
344 | /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ | |
345 | ctrl_outw(data & 0x0fcf, SCPCR); | |
1da177e4 | 346 | |
1da177e4 LT |
347 | if (cflag & CRTSCTS) |
348 | fcr_val |= SCFCR_MCE; | |
349 | else { | |
1da177e4 LT |
350 | /* We need to set SCPCR to enable RTS/CTS */ |
351 | data = ctrl_inw(SCPCR); | |
352 | /* Clear out SCP7MD1,0, SCP4MD1,0, | |
353 | Set SCP6MD1,0 = {01} (output) */ | |
b7a76e4b | 354 | ctrl_outw((data & 0x0fcf) | 0x1000, SCPCR); |
1da177e4 LT |
355 | |
356 | data = ctrl_inb(SCPDR); | |
357 | /* Set /RTS2 (bit6) = 0 */ | |
b7a76e4b | 358 | ctrl_outb(data & 0xbf, SCPDR); |
1da177e4 | 359 | } |
b7a76e4b | 360 | |
1da177e4 LT |
361 | sci_out(port, SCFCR, fcr_val); |
362 | } | |
41504c39 PM |
363 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
364 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
365 | { | |
366 | unsigned int fcr_val = 0; | |
346b7463 | 367 | unsigned short data; |
41504c39 | 368 | |
346b7463 MD |
369 | if (port->mapbase == 0xffe00000) { |
370 | data = ctrl_inw(PSCR); | |
371 | data &= ~0x03cf; | |
372 | if (cflag & CRTSCTS) | |
373 | fcr_val |= SCFCR_MCE; | |
374 | else | |
375 | data |= 0x0340; | |
41504c39 | 376 | |
346b7463 | 377 | ctrl_outw(data, PSCR); |
41504c39 | 378 | } |
346b7463 | 379 | /* SCIF1 and SCIF2 should be setup by board code */ |
41504c39 PM |
380 | |
381 | sci_out(port, SCFCR, fcr_val); | |
382 | } | |
178dd0cd PM |
383 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
384 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
385 | { | |
386 | /* Nothing to do here.. */ | |
387 | sci_out(port, SCFCR, 0); | |
388 | } | |
1da177e4 | 389 | #else |
1da177e4 LT |
390 | /* For SH7750 */ |
391 | static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) | |
392 | { | |
393 | unsigned int fcr_val = 0; | |
394 | ||
395 | if (cflag & CRTSCTS) { | |
396 | fcr_val |= SCFCR_MCE; | |
397 | } else { | |
9109a30e | 398 | #if defined(CONFIG_CPU_SUBTYPE_SH7343) || defined(CONFIG_CPU_SUBTYPE_SH7366) |
e108b2ca | 399 | /* Nothing */ |
7d740a06 YS |
400 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ |
401 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
2b1bd1ac PM |
402 | defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
403 | defined(CONFIG_CPU_SUBTYPE_SHX3) | |
b7a76e4b PM |
404 | ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ |
405 | #else | |
1da177e4 | 406 | ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ |
b7a76e4b | 407 | #endif |
1da177e4 LT |
408 | } |
409 | sci_out(port, SCFCR, fcr_val); | |
410 | } | |
e108b2ca PM |
411 | #endif |
412 | ||
32351a28 PM |
413 | #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ |
414 | defined(CONFIG_CPU_SUBTYPE_SH7780) || \ | |
415 | defined(CONFIG_CPU_SUBTYPE_SH7785) | |
e108b2ca PM |
416 | static inline int scif_txroom(struct uart_port *port) |
417 | { | |
cae167d3 | 418 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); |
e108b2ca PM |
419 | } |
420 | ||
421 | static inline int scif_rxroom(struct uart_port *port) | |
422 | { | |
cae167d3 | 423 | return sci_in(port, SCRFDR) & 0xff; |
e108b2ca | 424 | } |
c63847a3 NI |
425 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
426 | static inline int scif_txroom(struct uart_port *port) | |
427 | { | |
428 | if((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) /* SCIF0/1*/ | |
429 | return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff); | |
430 | else /* SCIF2 */ | |
431 | return SCIF2_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
432 | } | |
433 | ||
434 | static inline int scif_rxroom(struct uart_port *port) | |
435 | { | |
436 | if((port->mapbase == 0xffe00000) || (port->mapbase == 0xffe08000)) /* SCIF0/1*/ | |
437 | return sci_in(port, SCRFDR) & 0xff; | |
438 | else /* SCIF2 */ | |
439 | return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; | |
440 | } | |
e108b2ca PM |
441 | #else |
442 | static inline int scif_txroom(struct uart_port *port) | |
443 | { | |
444 | return SCIF_TXROOM_MAX - (sci_in(port, SCFDR) >> 8); | |
445 | } | |
1da177e4 | 446 | |
e108b2ca PM |
447 | static inline int scif_rxroom(struct uart_port *port) |
448 | { | |
449 | return sci_in(port, SCFDR) & SCIF_RFDC_MASK; | |
450 | } | |
1da177e4 LT |
451 | #endif |
452 | #endif /* SCIF_ONLY || SCI_AND_SCIF */ | |
453 | ||
e108b2ca PM |
454 | static inline int sci_txroom(struct uart_port *port) |
455 | { | |
456 | return ((sci_in(port, SCxSR) & SCI_TDRE) != 0); | |
457 | } | |
458 | ||
459 | static inline int sci_rxroom(struct uart_port *port) | |
460 | { | |
461 | return ((sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0); | |
462 | } | |
463 | ||
1da177e4 LT |
464 | /* ********************************************************************** * |
465 | * the interrupt related routines * | |
466 | * ********************************************************************** */ | |
467 | ||
468 | static void sci_transmit_chars(struct uart_port *port) | |
469 | { | |
470 | struct circ_buf *xmit = &port->info->xmit; | |
471 | unsigned int stopped = uart_tx_stopped(port); | |
1da177e4 LT |
472 | unsigned short status; |
473 | unsigned short ctrl; | |
e108b2ca | 474 | int count; |
1da177e4 LT |
475 | |
476 | status = sci_in(port, SCxSR); | |
477 | if (!(status & SCxSR_TDxE(port))) { | |
1da177e4 LT |
478 | ctrl = sci_in(port, SCSCR); |
479 | if (uart_circ_empty(xmit)) { | |
480 | ctrl &= ~SCI_CTRL_FLAGS_TIE; | |
481 | } else { | |
482 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
483 | } | |
484 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
485 | return; |
486 | } | |
487 | ||
e108b2ca PM |
488 | #ifndef SCI_ONLY |
489 | if (port->type == PORT_SCIF) | |
490 | count = scif_txroom(port); | |
491 | else | |
1da177e4 | 492 | #endif |
e108b2ca | 493 | count = sci_txroom(port); |
1da177e4 LT |
494 | |
495 | do { | |
496 | unsigned char c; | |
497 | ||
498 | if (port->x_char) { | |
499 | c = port->x_char; | |
500 | port->x_char = 0; | |
501 | } else if (!uart_circ_empty(xmit) && !stopped) { | |
502 | c = xmit->buf[xmit->tail]; | |
503 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
504 | } else { | |
505 | break; | |
506 | } | |
507 | ||
508 | sci_out(port, SCxTDR, c); | |
509 | ||
510 | port->icount.tx++; | |
511 | } while (--count > 0); | |
512 | ||
513 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
514 | ||
515 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
516 | uart_write_wakeup(port); | |
517 | if (uart_circ_empty(xmit)) { | |
b129a8cc | 518 | sci_stop_tx(port); |
1da177e4 | 519 | } else { |
1da177e4 LT |
520 | ctrl = sci_in(port, SCSCR); |
521 | ||
522 | #if !defined(SCI_ONLY) | |
523 | if (port->type == PORT_SCIF) { | |
524 | sci_in(port, SCxSR); /* Dummy read */ | |
525 | sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port)); | |
526 | } | |
527 | #endif | |
528 | ||
529 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
530 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
531 | } |
532 | } | |
533 | ||
534 | /* On SH3, SCIF may read end-of-break as a space->mark char */ | |
535 | #define STEPFN(c) ({int __c=(c); (((__c-1)|(__c)) == -1); }) | |
536 | ||
7d12e780 | 537 | static inline void sci_receive_chars(struct uart_port *port) |
1da177e4 | 538 | { |
e108b2ca | 539 | struct sci_port *sci_port = (struct sci_port *)port; |
a88487c7 | 540 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
541 | int i, count, copied = 0; |
542 | unsigned short status; | |
33f0f88f | 543 | unsigned char flag; |
1da177e4 LT |
544 | |
545 | status = sci_in(port, SCxSR); | |
546 | if (!(status & SCxSR_RDxF(port))) | |
547 | return; | |
548 | ||
549 | while (1) { | |
550 | #if !defined(SCI_ONLY) | |
e108b2ca PM |
551 | if (port->type == PORT_SCIF) |
552 | count = scif_rxroom(port); | |
553 | else | |
1da177e4 | 554 | #endif |
e108b2ca | 555 | count = sci_rxroom(port); |
1da177e4 LT |
556 | |
557 | /* Don't copy more bytes than there is room for in the buffer */ | |
33f0f88f | 558 | count = tty_buffer_request_room(tty, count); |
1da177e4 LT |
559 | |
560 | /* If for any reason we can't copy more data, we're done! */ | |
561 | if (count == 0) | |
562 | break; | |
563 | ||
564 | if (port->type == PORT_SCI) { | |
565 | char c = sci_in(port, SCxRDR); | |
7d12e780 | 566 | if (uart_handle_sysrq_char(port, c) || sci_port->break_flag) |
1da177e4 | 567 | count = 0; |
e108b2ca PM |
568 | else { |
569 | tty_insert_flip_char(tty, c, TTY_NORMAL); | |
1da177e4 LT |
570 | } |
571 | } else { | |
572 | for (i=0; i<count; i++) { | |
573 | char c = sci_in(port, SCxRDR); | |
574 | status = sci_in(port, SCxSR); | |
575 | #if defined(CONFIG_CPU_SH3) | |
576 | /* Skip "chars" during break */ | |
e108b2ca | 577 | if (sci_port->break_flag) { |
1da177e4 LT |
578 | if ((c == 0) && |
579 | (status & SCxSR_FER(port))) { | |
580 | count--; i--; | |
581 | continue; | |
582 | } | |
e108b2ca | 583 | |
1da177e4 LT |
584 | /* Nonzero => end-of-break */ |
585 | pr_debug("scif: debounce<%02x>\n", c); | |
e108b2ca PM |
586 | sci_port->break_flag = 0; |
587 | ||
1da177e4 LT |
588 | if (STEPFN(c)) { |
589 | count--; i--; | |
590 | continue; | |
591 | } | |
592 | } | |
593 | #endif /* CONFIG_CPU_SH3 */ | |
7d12e780 | 594 | if (uart_handle_sysrq_char(port, c)) { |
1da177e4 LT |
595 | count--; i--; |
596 | continue; | |
597 | } | |
598 | ||
599 | /* Store data and status */ | |
1da177e4 | 600 | if (status&SCxSR_FER(port)) { |
33f0f88f | 601 | flag = TTY_FRAME; |
1da177e4 LT |
602 | pr_debug("sci: frame error\n"); |
603 | } else if (status&SCxSR_PER(port)) { | |
33f0f88f | 604 | flag = TTY_PARITY; |
1da177e4 | 605 | pr_debug("sci: parity error\n"); |
33f0f88f AC |
606 | } else |
607 | flag = TTY_NORMAL; | |
608 | tty_insert_flip_char(tty, c, flag); | |
1da177e4 LT |
609 | } |
610 | } | |
611 | ||
612 | sci_in(port, SCxSR); /* dummy read */ | |
613 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
614 | ||
1da177e4 LT |
615 | copied += count; |
616 | port->icount.rx += count; | |
617 | } | |
618 | ||
619 | if (copied) { | |
620 | /* Tell the rest of the system the news. New characters! */ | |
621 | tty_flip_buffer_push(tty); | |
622 | } else { | |
623 | sci_in(port, SCxSR); /* dummy read */ | |
624 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
625 | } | |
626 | } | |
627 | ||
628 | #define SCI_BREAK_JIFFIES (HZ/20) | |
629 | /* The sci generates interrupts during the break, | |
630 | * 1 per millisecond or so during the break period, for 9600 baud. | |
631 | * So dont bother disabling interrupts. | |
632 | * But dont want more than 1 break event. | |
633 | * Use a kernel timer to periodically poll the rx line until | |
634 | * the break is finished. | |
635 | */ | |
636 | static void sci_schedule_break_timer(struct sci_port *port) | |
637 | { | |
638 | port->break_timer.expires = jiffies + SCI_BREAK_JIFFIES; | |
639 | add_timer(&port->break_timer); | |
640 | } | |
641 | /* Ensure that two consecutive samples find the break over. */ | |
642 | static void sci_break_timer(unsigned long data) | |
643 | { | |
e108b2ca PM |
644 | struct sci_port *port = (struct sci_port *)data; |
645 | ||
646 | if (sci_rxd_in(&port->port) == 0) { | |
1da177e4 | 647 | port->break_flag = 1; |
e108b2ca PM |
648 | sci_schedule_break_timer(port); |
649 | } else if (port->break_flag == 1) { | |
1da177e4 LT |
650 | /* break is over. */ |
651 | port->break_flag = 2; | |
e108b2ca PM |
652 | sci_schedule_break_timer(port); |
653 | } else | |
654 | port->break_flag = 0; | |
1da177e4 LT |
655 | } |
656 | ||
657 | static inline int sci_handle_errors(struct uart_port *port) | |
658 | { | |
659 | int copied = 0; | |
660 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 661 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 | 662 | |
e108b2ca | 663 | if (status & SCxSR_ORER(port)) { |
1da177e4 | 664 | /* overrun error */ |
e108b2ca | 665 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) |
33f0f88f | 666 | copied++; |
1da177e4 LT |
667 | pr_debug("sci: overrun error\n"); |
668 | } | |
669 | ||
e108b2ca | 670 | if (status & SCxSR_FER(port)) { |
1da177e4 LT |
671 | if (sci_rxd_in(port) == 0) { |
672 | /* Notify of BREAK */ | |
e108b2ca PM |
673 | struct sci_port *sci_port = (struct sci_port *)port; |
674 | ||
675 | if (!sci_port->break_flag) { | |
676 | sci_port->break_flag = 1; | |
677 | sci_schedule_break_timer(sci_port); | |
678 | ||
1da177e4 | 679 | /* Do sysrq handling. */ |
e108b2ca | 680 | if (uart_handle_break(port)) |
1da177e4 | 681 | return 0; |
1da177e4 | 682 | pr_debug("sci: BREAK detected\n"); |
e108b2ca | 683 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 684 | copied++; |
1da177e4 | 685 | } |
e108b2ca | 686 | } else { |
1da177e4 | 687 | /* frame error */ |
e108b2ca | 688 | if (tty_insert_flip_char(tty, 0, TTY_FRAME)) |
33f0f88f | 689 | copied++; |
1da177e4 LT |
690 | pr_debug("sci: frame error\n"); |
691 | } | |
692 | } | |
693 | ||
e108b2ca | 694 | if (status & SCxSR_PER(port)) { |
1da177e4 | 695 | /* parity error */ |
e108b2ca PM |
696 | if (tty_insert_flip_char(tty, 0, TTY_PARITY)) |
697 | copied++; | |
1da177e4 LT |
698 | pr_debug("sci: parity error\n"); |
699 | } | |
700 | ||
33f0f88f | 701 | if (copied) |
1da177e4 | 702 | tty_flip_buffer_push(tty); |
1da177e4 LT |
703 | |
704 | return copied; | |
705 | } | |
706 | ||
707 | static inline int sci_handle_breaks(struct uart_port *port) | |
708 | { | |
709 | int copied = 0; | |
710 | unsigned short status = sci_in(port, SCxSR); | |
a88487c7 | 711 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
712 | struct sci_port *s = &sci_ports[port->line]; |
713 | ||
0b3d4ef6 PM |
714 | if (uart_handle_break(port)) |
715 | return 0; | |
716 | ||
b7a76e4b | 717 | if (!s->break_flag && status & SCxSR_BRK(port)) { |
1da177e4 LT |
718 | #if defined(CONFIG_CPU_SH3) |
719 | /* Debounce break */ | |
720 | s->break_flag = 1; | |
721 | #endif | |
722 | /* Notify of BREAK */ | |
e108b2ca | 723 | if (tty_insert_flip_char(tty, 0, TTY_BREAK)) |
33f0f88f | 724 | copied++; |
1da177e4 LT |
725 | pr_debug("sci: BREAK detected\n"); |
726 | } | |
727 | ||
728 | #if defined(SCIF_ORER) | |
729 | /* XXX: Handle SCIF overrun error */ | |
730 | if (port->type == PORT_SCIF && (sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
731 | sci_out(port, SCLSR, 0); | |
e108b2ca | 732 | if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) { |
1da177e4 | 733 | copied++; |
1da177e4 LT |
734 | pr_debug("sci: overrun error\n"); |
735 | } | |
736 | } | |
737 | #endif | |
738 | ||
33f0f88f | 739 | if (copied) |
1da177e4 | 740 | tty_flip_buffer_push(tty); |
e108b2ca | 741 | |
1da177e4 LT |
742 | return copied; |
743 | } | |
744 | ||
7d12e780 | 745 | static irqreturn_t sci_rx_interrupt(int irq, void *port) |
1da177e4 | 746 | { |
1da177e4 LT |
747 | /* I think sci_receive_chars has to be called irrespective |
748 | * of whether the I_IXOFF is set, otherwise, how is the interrupt | |
749 | * to be disabled? | |
750 | */ | |
7d12e780 | 751 | sci_receive_chars(port); |
1da177e4 LT |
752 | |
753 | return IRQ_HANDLED; | |
754 | } | |
755 | ||
7d12e780 | 756 | static irqreturn_t sci_tx_interrupt(int irq, void *ptr) |
1da177e4 LT |
757 | { |
758 | struct uart_port *port = ptr; | |
759 | ||
e108b2ca | 760 | spin_lock_irq(&port->lock); |
1da177e4 | 761 | sci_transmit_chars(port); |
e108b2ca | 762 | spin_unlock_irq(&port->lock); |
1da177e4 LT |
763 | |
764 | return IRQ_HANDLED; | |
765 | } | |
766 | ||
7d12e780 | 767 | static irqreturn_t sci_er_interrupt(int irq, void *ptr) |
1da177e4 LT |
768 | { |
769 | struct uart_port *port = ptr; | |
770 | ||
771 | /* Handle errors */ | |
772 | if (port->type == PORT_SCI) { | |
773 | if (sci_handle_errors(port)) { | |
774 | /* discard character in rx buffer */ | |
775 | sci_in(port, SCxSR); | |
776 | sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); | |
777 | } | |
778 | } else { | |
779 | #if defined(SCIF_ORER) | |
780 | if((sci_in(port, SCLSR) & SCIF_ORER) != 0) { | |
a88487c7 | 781 | struct tty_struct *tty = port->info->port.tty; |
1da177e4 LT |
782 | |
783 | sci_out(port, SCLSR, 0); | |
33f0f88f AC |
784 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); |
785 | tty_flip_buffer_push(tty); | |
786 | pr_debug("scif: overrun error\n"); | |
1da177e4 LT |
787 | } |
788 | #endif | |
7d12e780 | 789 | sci_rx_interrupt(irq, ptr); |
1da177e4 LT |
790 | } |
791 | ||
792 | sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); | |
793 | ||
794 | /* Kick the transmission */ | |
7d12e780 | 795 | sci_tx_interrupt(irq, ptr); |
1da177e4 LT |
796 | |
797 | return IRQ_HANDLED; | |
798 | } | |
799 | ||
7d12e780 | 800 | static irqreturn_t sci_br_interrupt(int irq, void *ptr) |
1da177e4 LT |
801 | { |
802 | struct uart_port *port = ptr; | |
803 | ||
804 | /* Handle BREAKs */ | |
805 | sci_handle_breaks(port); | |
806 | sci_out(port, SCxSR, SCxSR_BREAK_CLEAR(port)); | |
807 | ||
808 | return IRQ_HANDLED; | |
809 | } | |
810 | ||
7d12e780 | 811 | static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr) |
1da177e4 LT |
812 | { |
813 | unsigned short ssr_status, scr_status; | |
814 | struct uart_port *port = ptr; | |
815 | ||
816 | ssr_status = sci_in(port,SCxSR); | |
817 | scr_status = sci_in(port,SCSCR); | |
818 | ||
819 | /* Tx Interrupt */ | |
e108b2ca | 820 | if ((ssr_status & 0x0020) && (scr_status & 0x0080)) |
7d12e780 | 821 | sci_tx_interrupt(irq, ptr); |
1da177e4 | 822 | /* Rx Interrupt */ |
e108b2ca | 823 | if ((ssr_status & 0x0002) && (scr_status & 0x0040)) |
7d12e780 | 824 | sci_rx_interrupt(irq, ptr); |
1da177e4 | 825 | /* Error Interrupt */ |
e108b2ca | 826 | if ((ssr_status & 0x0080) && (scr_status & 0x0400)) |
7d12e780 | 827 | sci_er_interrupt(irq, ptr); |
1da177e4 | 828 | /* Break Interrupt */ |
e108b2ca | 829 | if ((ssr_status & 0x0010) && (scr_status & 0x0200)) |
7d12e780 | 830 | sci_br_interrupt(irq, ptr); |
1da177e4 LT |
831 | |
832 | return IRQ_HANDLED; | |
833 | } | |
834 | ||
a2159b52 | 835 | #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) |
1da177e4 LT |
836 | /* |
837 | * Here we define a transistion notifier so that we can update all of our | |
838 | * ports' baud rate when the peripheral clock changes. | |
839 | */ | |
e108b2ca PM |
840 | static int sci_notifier(struct notifier_block *self, |
841 | unsigned long phase, void *p) | |
1da177e4 LT |
842 | { |
843 | struct cpufreq_freqs *freqs = p; | |
844 | int i; | |
845 | ||
846 | if ((phase == CPUFREQ_POSTCHANGE) || | |
847 | (phase == CPUFREQ_RESUMECHANGE)){ | |
848 | for (i = 0; i < SCI_NPORTS; i++) { | |
849 | struct uart_port *port = &sci_ports[i].port; | |
b7a76e4b | 850 | struct clk *clk; |
1da177e4 LT |
851 | |
852 | /* | |
853 | * Update the uartclk per-port if frequency has | |
854 | * changed, since it will no longer necessarily be | |
855 | * consistent with the old frequency. | |
856 | * | |
857 | * Really we want to be able to do something like | |
858 | * uart_change_speed() or something along those lines | |
859 | * here to implicitly reset the per-port baud rate.. | |
860 | * | |
861 | * Clean this up later.. | |
862 | */ | |
1d118562 | 863 | clk = clk_get(NULL, "module_clk"); |
a2159b52 | 864 | port->uartclk = clk_get_rate(clk); |
b7a76e4b | 865 | clk_put(clk); |
1da177e4 LT |
866 | } |
867 | ||
e108b2ca PM |
868 | printk(KERN_INFO "%s: got a postchange notification " |
869 | "for cpu %d (old %d, new %d)\n", | |
71cc2c21 | 870 | __func__, freqs->cpu, freqs->old, freqs->new); |
1da177e4 LT |
871 | } |
872 | ||
873 | return NOTIFY_OK; | |
874 | } | |
875 | ||
876 | static struct notifier_block sci_nb = { &sci_notifier, NULL, 0 }; | |
a2159b52 | 877 | #endif /* CONFIG_CPU_FREQ && CONFIG_HAVE_CLK */ |
1da177e4 LT |
878 | |
879 | static int sci_request_irq(struct sci_port *port) | |
880 | { | |
881 | int i; | |
7d12e780 | 882 | irqreturn_t (*handlers[4])(int irq, void *ptr) = { |
1da177e4 LT |
883 | sci_er_interrupt, sci_rx_interrupt, sci_tx_interrupt, |
884 | sci_br_interrupt, | |
885 | }; | |
886 | const char *desc[] = { "SCI Receive Error", "SCI Receive Data Full", | |
887 | "SCI Transmit Data Empty", "SCI Break" }; | |
888 | ||
889 | if (port->irqs[0] == port->irqs[1]) { | |
890 | if (!port->irqs[0]) { | |
891 | printk(KERN_ERR "sci: Cannot allocate irq.(IRQ=0)\n"); | |
892 | return -ENODEV; | |
893 | } | |
e108b2ca PM |
894 | |
895 | if (request_irq(port->irqs[0], sci_mpxed_interrupt, | |
35f3c518 | 896 | IRQF_DISABLED, "sci", port)) { |
1da177e4 LT |
897 | printk(KERN_ERR "sci: Cannot allocate irq.\n"); |
898 | return -ENODEV; | |
899 | } | |
900 | } else { | |
901 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { | |
902 | if (!port->irqs[i]) | |
903 | continue; | |
e108b2ca | 904 | if (request_irq(port->irqs[i], handlers[i], |
35f3c518 | 905 | IRQF_DISABLED, desc[i], port)) { |
1da177e4 LT |
906 | printk(KERN_ERR "sci: Cannot allocate irq.\n"); |
907 | return -ENODEV; | |
908 | } | |
909 | } | |
910 | } | |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
915 | static void sci_free_irq(struct sci_port *port) | |
916 | { | |
917 | int i; | |
918 | ||
919 | if (port->irqs[0] == port->irqs[1]) { | |
920 | if (!port->irqs[0]) | |
921 | printk("sci: sci_free_irq error\n"); | |
922 | else | |
923 | free_irq(port->irqs[0], port); | |
924 | } else { | |
925 | for (i = 0; i < ARRAY_SIZE(port->irqs); i++) { | |
926 | if (!port->irqs[i]) | |
927 | continue; | |
928 | ||
929 | free_irq(port->irqs[i], port); | |
930 | } | |
931 | } | |
932 | } | |
933 | ||
934 | static unsigned int sci_tx_empty(struct uart_port *port) | |
935 | { | |
936 | /* Can't detect */ | |
937 | return TIOCSER_TEMT; | |
938 | } | |
939 | ||
940 | static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
941 | { | |
942 | /* This routine is used for seting signals of: DTR, DCD, CTS/RTS */ | |
943 | /* We use SCIF's hardware for CTS/RTS, so don't need any for that. */ | |
944 | /* If you have signals for DTR and DCD, please implement here. */ | |
945 | } | |
946 | ||
947 | static unsigned int sci_get_mctrl(struct uart_port *port) | |
948 | { | |
949 | /* This routine is used for geting signals of: DTR, DCD, DSR, RI, | |
950 | and CTS/RTS */ | |
951 | ||
952 | return TIOCM_DTR | TIOCM_RTS | TIOCM_DSR; | |
953 | } | |
954 | ||
b129a8cc | 955 | static void sci_start_tx(struct uart_port *port) |
1da177e4 | 956 | { |
e108b2ca | 957 | unsigned short ctrl; |
1da177e4 | 958 | |
e108b2ca PM |
959 | /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */ |
960 | ctrl = sci_in(port, SCSCR); | |
961 | ctrl |= SCI_CTRL_FLAGS_TIE; | |
962 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
963 | } |
964 | ||
b129a8cc | 965 | static void sci_stop_tx(struct uart_port *port) |
1da177e4 | 966 | { |
1da177e4 LT |
967 | unsigned short ctrl; |
968 | ||
969 | /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
970 | ctrl = sci_in(port, SCSCR); |
971 | ctrl &= ~SCI_CTRL_FLAGS_TIE; | |
972 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
973 | } |
974 | ||
975 | static void sci_start_rx(struct uart_port *port, unsigned int tty_start) | |
976 | { | |
1da177e4 LT |
977 | unsigned short ctrl; |
978 | ||
979 | /* Set RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
980 | ctrl = sci_in(port, SCSCR); |
981 | ctrl |= SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE; | |
982 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
983 | } |
984 | ||
985 | static void sci_stop_rx(struct uart_port *port) | |
986 | { | |
1da177e4 LT |
987 | unsigned short ctrl; |
988 | ||
989 | /* Clear RIE (Receive Interrupt Enable) bit in SCSCR */ | |
1da177e4 LT |
990 | ctrl = sci_in(port, SCSCR); |
991 | ctrl &= ~(SCI_CTRL_FLAGS_RIE | SCI_CTRL_FLAGS_REIE); | |
992 | sci_out(port, SCSCR, ctrl); | |
1da177e4 LT |
993 | } |
994 | ||
995 | static void sci_enable_ms(struct uart_port *port) | |
996 | { | |
997 | /* Nothing here yet .. */ | |
998 | } | |
999 | ||
1000 | static void sci_break_ctl(struct uart_port *port, int break_state) | |
1001 | { | |
1002 | /* Nothing here yet .. */ | |
1003 | } | |
1004 | ||
1005 | static int sci_startup(struct uart_port *port) | |
1006 | { | |
1007 | struct sci_port *s = &sci_ports[port->line]; | |
1008 | ||
e108b2ca PM |
1009 | if (s->enable) |
1010 | s->enable(port); | |
1da177e4 | 1011 | |
a2159b52 | 1012 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 1013 | s->clk = clk_get(NULL, "module_clk"); |
005a336e | 1014 | #endif |
1534a3b3 | 1015 | |
1da177e4 | 1016 | sci_request_irq(s); |
d656901b | 1017 | sci_start_tx(port); |
1da177e4 LT |
1018 | sci_start_rx(port, 1); |
1019 | ||
1020 | return 0; | |
1021 | } | |
1022 | ||
1023 | static void sci_shutdown(struct uart_port *port) | |
1024 | { | |
1025 | struct sci_port *s = &sci_ports[port->line]; | |
1026 | ||
1027 | sci_stop_rx(port); | |
b129a8cc | 1028 | sci_stop_tx(port); |
1da177e4 LT |
1029 | sci_free_irq(s); |
1030 | ||
e108b2ca PM |
1031 | if (s->disable) |
1032 | s->disable(port); | |
1534a3b3 | 1033 | |
a2159b52 | 1034 | #ifdef CONFIG_HAVE_CLK |
1534a3b3 | 1035 | clk_put(s->clk); |
1036 | s->clk = NULL; | |
005a336e | 1037 | #endif |
1da177e4 LT |
1038 | } |
1039 | ||
606d099c AC |
1040 | static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
1041 | struct ktermios *old) | |
1da177e4 LT |
1042 | { |
1043 | struct sci_port *s = &sci_ports[port->line]; | |
1044 | unsigned int status, baud, smr_val; | |
a2159b52 | 1045 | int t = -1; |
1da177e4 LT |
1046 | |
1047 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
a2159b52 PM |
1048 | if (likely(baud)) |
1049 | t = SCBRR_VALUE(baud, port->uartclk); | |
e108b2ca | 1050 | |
1da177e4 LT |
1051 | do { |
1052 | status = sci_in(port, SCxSR); | |
1053 | } while (!(status & SCxSR_TEND(port))); | |
1054 | ||
1055 | sci_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */ | |
1056 | ||
1057 | #if !defined(SCI_ONLY) | |
e108b2ca | 1058 | if (port->type == PORT_SCIF) |
1da177e4 | 1059 | sci_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST); |
1da177e4 LT |
1060 | #endif |
1061 | ||
1062 | smr_val = sci_in(port, SCSMR) & 3; | |
1063 | if ((termios->c_cflag & CSIZE) == CS7) | |
1064 | smr_val |= 0x40; | |
1065 | if (termios->c_cflag & PARENB) | |
1066 | smr_val |= 0x20; | |
1067 | if (termios->c_cflag & PARODD) | |
1068 | smr_val |= 0x30; | |
1069 | if (termios->c_cflag & CSTOPB) | |
1070 | smr_val |= 0x08; | |
1071 | ||
1072 | uart_update_timeout(port, termios->c_cflag, baud); | |
1073 | ||
1074 | sci_out(port, SCSMR, smr_val); | |
1075 | ||
1da177e4 LT |
1076 | if (t > 0) { |
1077 | if(t >= 256) { | |
1078 | sci_out(port, SCSMR, (sci_in(port, SCSMR) & ~3) | 1); | |
1079 | t >>= 2; | |
1080 | } else { | |
1081 | sci_out(port, SCSMR, sci_in(port, SCSMR) & ~3); | |
1082 | } | |
1083 | sci_out(port, SCBRR, t); | |
1084 | udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */ | |
1085 | } | |
1086 | ||
b7a76e4b PM |
1087 | if (likely(s->init_pins)) |
1088 | s->init_pins(port, termios->c_cflag); | |
1089 | ||
1da177e4 LT |
1090 | sci_out(port, SCSCR, SCSCR_INIT(port)); |
1091 | ||
1092 | if ((termios->c_cflag & CREAD) != 0) | |
1093 | sci_start_rx(port,0); | |
1da177e4 LT |
1094 | } |
1095 | ||
1096 | static const char *sci_type(struct uart_port *port) | |
1097 | { | |
1098 | switch (port->type) { | |
1099 | case PORT_SCI: return "sci"; | |
1100 | case PORT_SCIF: return "scif"; | |
1101 | case PORT_IRDA: return "irda"; | |
1102 | } | |
1103 | ||
fa43972f | 1104 | return NULL; |
1da177e4 LT |
1105 | } |
1106 | ||
1107 | static void sci_release_port(struct uart_port *port) | |
1108 | { | |
1109 | /* Nothing here yet .. */ | |
1110 | } | |
1111 | ||
1112 | static int sci_request_port(struct uart_port *port) | |
1113 | { | |
1114 | /* Nothing here yet .. */ | |
1115 | return 0; | |
1116 | } | |
1117 | ||
1118 | static void sci_config_port(struct uart_port *port, int flags) | |
1119 | { | |
1120 | struct sci_port *s = &sci_ports[port->line]; | |
1121 | ||
1122 | port->type = s->type; | |
1123 | ||
e108b2ca PM |
1124 | switch (port->type) { |
1125 | case PORT_SCI: | |
1126 | s->init_pins = sci_init_pins_sci; | |
1127 | break; | |
1128 | case PORT_SCIF: | |
1129 | s->init_pins = sci_init_pins_scif; | |
1130 | break; | |
1131 | case PORT_IRDA: | |
1132 | s->init_pins = sci_init_pins_irda; | |
1133 | break; | |
1134 | } | |
1135 | ||
7ff731ae PM |
1136 | if (port->flags & UPF_IOREMAP && !port->membase) { |
1137 | #if defined(CONFIG_SUPERH64) | |
1da177e4 | 1138 | port->mapbase = onchip_remap(SCIF_ADDR_SH5, 1024, "SCIF"); |
7ff731ae PM |
1139 | port->membase = (void __iomem *)port->mapbase; |
1140 | #else | |
1141 | port->membase = ioremap_nocache(port->mapbase, 0x40); | |
1da177e4 | 1142 | #endif |
7ff731ae PM |
1143 | |
1144 | printk(KERN_ERR "sci: can't remap port#%d\n", port->line); | |
1145 | } | |
1da177e4 LT |
1146 | } |
1147 | ||
1148 | static int sci_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1149 | { | |
1150 | struct sci_port *s = &sci_ports[port->line]; | |
1151 | ||
1152 | if (ser->irq != s->irqs[SCIx_TXI_IRQ] || ser->irq > NR_IRQS) | |
1153 | return -EINVAL; | |
1154 | if (ser->baud_base < 2400) | |
1155 | /* No paper tape reader for Mitch.. */ | |
1156 | return -EINVAL; | |
1157 | ||
1158 | return 0; | |
1159 | } | |
1160 | ||
1161 | static struct uart_ops sci_uart_ops = { | |
1162 | .tx_empty = sci_tx_empty, | |
1163 | .set_mctrl = sci_set_mctrl, | |
1164 | .get_mctrl = sci_get_mctrl, | |
1165 | .start_tx = sci_start_tx, | |
1166 | .stop_tx = sci_stop_tx, | |
1167 | .stop_rx = sci_stop_rx, | |
1168 | .enable_ms = sci_enable_ms, | |
1169 | .break_ctl = sci_break_ctl, | |
1170 | .startup = sci_startup, | |
1171 | .shutdown = sci_shutdown, | |
1172 | .set_termios = sci_set_termios, | |
1173 | .type = sci_type, | |
1174 | .release_port = sci_release_port, | |
1175 | .request_port = sci_request_port, | |
1176 | .config_port = sci_config_port, | |
1177 | .verify_port = sci_verify_port, | |
1178 | }; | |
1179 | ||
e108b2ca PM |
1180 | static void __init sci_init_ports(void) |
1181 | { | |
1182 | static int first = 1; | |
1183 | int i; | |
1184 | ||
1185 | if (!first) | |
1186 | return; | |
1187 | ||
1188 | first = 0; | |
1189 | ||
1190 | for (i = 0; i < SCI_NPORTS; i++) { | |
1191 | sci_ports[i].port.ops = &sci_uart_ops; | |
1192 | sci_ports[i].port.iotype = UPIO_MEM; | |
1193 | sci_ports[i].port.line = i; | |
1194 | sci_ports[i].port.fifosize = 1; | |
1195 | ||
1196 | #if defined(__H8300H__) || defined(__H8300S__) | |
1197 | #ifdef __H8300S__ | |
1198 | sci_ports[i].enable = h8300_sci_enable; | |
1199 | sci_ports[i].disable = h8300_sci_disable; | |
1200 | #endif | |
1201 | sci_ports[i].port.uartclk = CONFIG_CPU_CLOCK; | |
a2159b52 | 1202 | #elif defined(CONFIG_HAVE_CLK) |
e108b2ca PM |
1203 | /* |
1204 | * XXX: We should use a proper SCI/SCIF clock | |
1205 | */ | |
1206 | { | |
1d118562 | 1207 | struct clk *clk = clk_get(NULL, "module_clk"); |
a2159b52 | 1208 | sci_ports[i].port.uartclk = clk_get_rate(clk); |
e108b2ca PM |
1209 | clk_put(clk); |
1210 | } | |
a2159b52 PM |
1211 | #else |
1212 | #error "Need a valid uartclk" | |
1da177e4 | 1213 | #endif |
e108b2ca PM |
1214 | |
1215 | sci_ports[i].break_timer.data = (unsigned long)&sci_ports[i]; | |
1216 | sci_ports[i].break_timer.function = sci_break_timer; | |
1217 | ||
1218 | init_timer(&sci_ports[i].break_timer); | |
1219 | } | |
1220 | } | |
1221 | ||
1222 | int __init early_sci_setup(struct uart_port *port) | |
1223 | { | |
1224 | if (unlikely(port->line > SCI_NPORTS)) | |
1225 | return -ENODEV; | |
1226 | ||
1227 | sci_init_ports(); | |
1228 | ||
1229 | sci_ports[port->line].port.membase = port->membase; | |
1230 | sci_ports[port->line].port.mapbase = port->mapbase; | |
1231 | sci_ports[port->line].port.type = port->type; | |
1232 | ||
1233 | return 0; | |
1234 | } | |
1da177e4 LT |
1235 | |
1236 | #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE | |
1237 | /* | |
1238 | * Print a string to the serial port trying not to disturb | |
1239 | * any possible real use of the port... | |
1240 | */ | |
1241 | static void serial_console_write(struct console *co, const char *s, | |
1242 | unsigned count) | |
1243 | { | |
1244 | put_string(serial_console_port, s, count); | |
1245 | } | |
1246 | ||
1247 | static int __init serial_console_setup(struct console *co, char *options) | |
1248 | { | |
1249 | struct uart_port *port; | |
1250 | int baud = 115200; | |
1251 | int bits = 8; | |
1252 | int parity = 'n'; | |
1253 | int flow = 'n'; | |
1254 | int ret; | |
1255 | ||
e108b2ca PM |
1256 | /* |
1257 | * Check whether an invalid uart number has been specified, and | |
1258 | * if so, search for the first available port that does have | |
1259 | * console support. | |
1260 | */ | |
1261 | if (co->index >= SCI_NPORTS) | |
1262 | co->index = 0; | |
1263 | ||
1da177e4 LT |
1264 | serial_console_port = &sci_ports[co->index]; |
1265 | port = &serial_console_port->port; | |
1da177e4 LT |
1266 | |
1267 | /* | |
e108b2ca PM |
1268 | * Also need to check port->type, we don't actually have any |
1269 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1270 | * it anyways if we don't have a port available by the time this is | |
1271 | * called. | |
1da177e4 | 1272 | */ |
e108b2ca PM |
1273 | if (!port->type) |
1274 | return -ENODEV; | |
1275 | if (!port->membase || !port->mapbase) | |
1276 | return -ENODEV; | |
1277 | ||
e108b2ca PM |
1278 | port->type = serial_console_port->type; |
1279 | ||
a2159b52 | 1280 | #ifdef CONFIG_HAVE_CLK |
005a336e PM |
1281 | if (!serial_console_port->clk) |
1282 | serial_console_port->clk = clk_get(NULL, "module_clk"); | |
1283 | #endif | |
1284 | ||
e108b2ca PM |
1285 | if (port->flags & UPF_IOREMAP) |
1286 | sci_config_port(port, 0); | |
1287 | ||
1288 | if (serial_console_port->enable) | |
1289 | serial_console_port->enable(port); | |
b7a76e4b | 1290 | |
1da177e4 LT |
1291 | if (options) |
1292 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1293 | ||
1294 | ret = uart_set_options(port, co, baud, parity, bits, flow); | |
1295 | #if defined(__H8300H__) || defined(__H8300S__) | |
1296 | /* disable rx interrupt */ | |
1297 | if (ret == 0) | |
1298 | sci_stop_rx(port); | |
1299 | #endif | |
1300 | return ret; | |
1301 | } | |
1302 | ||
1303 | static struct console serial_console = { | |
1304 | .name = "ttySC", | |
1305 | .device = uart_console_device, | |
1306 | .write = serial_console_write, | |
1307 | .setup = serial_console_setup, | |
fa5da2f7 | 1308 | .flags = CON_PRINTBUFFER, |
1da177e4 LT |
1309 | .index = -1, |
1310 | .data = &sci_uart_driver, | |
1311 | }; | |
1312 | ||
1313 | static int __init sci_console_init(void) | |
1314 | { | |
e108b2ca | 1315 | sci_init_ports(); |
1da177e4 LT |
1316 | register_console(&serial_console); |
1317 | return 0; | |
1318 | } | |
1da177e4 LT |
1319 | console_initcall(sci_console_init); |
1320 | #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */ | |
1321 | ||
68362e08 | 1322 | #ifdef CONFIG_SH_KGDB_CONSOLE |
1da177e4 LT |
1323 | /* |
1324 | * FIXME: Most of this can go away.. at the moment, we rely on | |
1325 | * arch/sh/kernel/setup.c to do the command line parsing for kgdb, though | |
1326 | * most of that can easily be done here instead. | |
1327 | * | |
1328 | * For the time being, just accept the values that were parsed earlier.. | |
1329 | */ | |
1330 | static void __init kgdb_console_get_options(struct uart_port *port, int *baud, | |
1331 | int *parity, int *bits) | |
1332 | { | |
1333 | *baud = kgdb_baud; | |
1334 | *parity = tolower(kgdb_parity); | |
1335 | *bits = kgdb_bits - '0'; | |
1336 | } | |
1337 | ||
1338 | /* | |
1339 | * The naming here is somewhat misleading, since kgdb_console_setup() takes | |
1340 | * care of the early-on initialization for kgdb, regardless of whether we | |
1341 | * actually use kgdb as a console or not. | |
1342 | * | |
1343 | * On the plus side, this lets us kill off the old kgdb_sci_setup() nonsense. | |
1344 | */ | |
1345 | int __init kgdb_console_setup(struct console *co, char *options) | |
1346 | { | |
1347 | struct uart_port *port = &sci_ports[kgdb_portnum].port; | |
1348 | int baud = 38400; | |
1349 | int bits = 8; | |
1350 | int parity = 'n'; | |
1351 | int flow = 'n'; | |
1352 | ||
b7a76e4b | 1353 | if (co->index != kgdb_portnum) |
1da177e4 LT |
1354 | co->index = kgdb_portnum; |
1355 | ||
fa5da2f7 PM |
1356 | kgdb_sci_port = &sci_ports[co->index]; |
1357 | port = &kgdb_sci_port->port; | |
1358 | ||
1359 | /* | |
1360 | * Also need to check port->type, we don't actually have any | |
1361 | * UPIO_PORT ports, but uart_report_port() handily misreports | |
1362 | * it anyways if we don't have a port available by the time this is | |
1363 | * called. | |
1364 | */ | |
1365 | if (!port->type) | |
1366 | return -ENODEV; | |
1367 | if (!port->membase || !port->mapbase) | |
1368 | return -ENODEV; | |
1369 | ||
1da177e4 LT |
1370 | if (options) |
1371 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1372 | else | |
1373 | kgdb_console_get_options(port, &baud, &parity, &bits); | |
1374 | ||
1375 | kgdb_getchar = kgdb_sci_getchar; | |
1376 | kgdb_putchar = kgdb_sci_putchar; | |
1377 | ||
1378 | return uart_set_options(port, co, baud, parity, bits, flow); | |
1379 | } | |
1da177e4 | 1380 | |
1da177e4 | 1381 | static struct console kgdb_console = { |
fa5da2f7 PM |
1382 | .name = "ttySC", |
1383 | .device = uart_console_device, | |
1384 | .write = kgdb_console_write, | |
1385 | .setup = kgdb_console_setup, | |
1386 | .flags = CON_PRINTBUFFER, | |
1387 | .index = -1, | |
1da177e4 LT |
1388 | .data = &sci_uart_driver, |
1389 | }; | |
1390 | ||
1391 | /* Register the KGDB console so we get messages (d'oh!) */ | |
1392 | static int __init kgdb_console_init(void) | |
1393 | { | |
e108b2ca | 1394 | sci_init_ports(); |
1da177e4 LT |
1395 | register_console(&kgdb_console); |
1396 | return 0; | |
1397 | } | |
1da177e4 LT |
1398 | console_initcall(kgdb_console_init); |
1399 | #endif /* CONFIG_SH_KGDB_CONSOLE */ | |
1400 | ||
1401 | #if defined(CONFIG_SH_KGDB_CONSOLE) | |
1402 | #define SCI_CONSOLE &kgdb_console | |
1403 | #elif defined(CONFIG_SERIAL_SH_SCI_CONSOLE) | |
1404 | #define SCI_CONSOLE &serial_console | |
1405 | #else | |
b7a76e4b | 1406 | #define SCI_CONSOLE 0 |
1da177e4 LT |
1407 | #endif |
1408 | ||
1409 | static char banner[] __initdata = | |
1410 | KERN_INFO "SuperH SCI(F) driver initialized\n"; | |
1411 | ||
1412 | static struct uart_driver sci_uart_driver = { | |
1413 | .owner = THIS_MODULE, | |
1414 | .driver_name = "sci", | |
1da177e4 LT |
1415 | .dev_name = "ttySC", |
1416 | .major = SCI_MAJOR, | |
1417 | .minor = SCI_MINOR_START, | |
e108b2ca | 1418 | .nr = SCI_NPORTS, |
1da177e4 LT |
1419 | .cons = SCI_CONSOLE, |
1420 | }; | |
1421 | ||
e108b2ca PM |
1422 | /* |
1423 | * Register a set of serial devices attached to a platform device. The | |
1424 | * list is terminated with a zero flags entry, which means we expect | |
1425 | * all entries to have at least UPF_BOOT_AUTOCONF set. Platforms that need | |
1426 | * remapping (such as sh64) should also set UPF_IOREMAP. | |
1427 | */ | |
1428 | static int __devinit sci_probe(struct platform_device *dev) | |
1da177e4 | 1429 | { |
e108b2ca | 1430 | struct plat_sci_port *p = dev->dev.platform_data; |
7ff731ae | 1431 | int i, ret = -EINVAL; |
1da177e4 | 1432 | |
32351a28 | 1433 | for (i = 0; p && p->flags != 0; p++, i++) { |
e108b2ca | 1434 | struct sci_port *sciport = &sci_ports[i]; |
1da177e4 | 1435 | |
32351a28 PM |
1436 | /* Sanity check */ |
1437 | if (unlikely(i == SCI_NPORTS)) { | |
1438 | dev_notice(&dev->dev, "Attempting to register port " | |
1439 | "%d when only %d are available.\n", | |
1440 | i+1, SCI_NPORTS); | |
1441 | dev_notice(&dev->dev, "Consider bumping " | |
1442 | "CONFIG_SERIAL_SH_SCI_NR_UARTS!\n"); | |
1443 | break; | |
1444 | } | |
1445 | ||
e108b2ca | 1446 | sciport->port.mapbase = p->mapbase; |
b7a76e4b | 1447 | |
7ff731ae PM |
1448 | if (p->mapbase && !p->membase) { |
1449 | if (p->flags & UPF_IOREMAP) { | |
1450 | p->membase = ioremap_nocache(p->mapbase, 0x40); | |
1451 | if (IS_ERR(p->membase)) { | |
1452 | ret = PTR_ERR(p->membase); | |
1453 | goto err_unreg; | |
1454 | } | |
1455 | } else { | |
1456 | /* | |
1457 | * For the simple (and majority of) cases | |
1458 | * where we don't need to do any remapping, | |
1459 | * just cast the cookie directly. | |
1460 | */ | |
1461 | p->membase = (void __iomem *)p->mapbase; | |
1462 | } | |
1463 | } | |
1da177e4 | 1464 | |
e108b2ca PM |
1465 | sciport->port.membase = p->membase; |
1466 | ||
1467 | sciport->port.irq = p->irqs[SCIx_TXI_IRQ]; | |
1468 | sciport->port.flags = p->flags; | |
1469 | sciport->port.dev = &dev->dev; | |
1470 | ||
1471 | sciport->type = sciport->port.type = p->type; | |
1472 | ||
1473 | memcpy(&sciport->irqs, &p->irqs, sizeof(p->irqs)); | |
1474 | ||
1475 | uart_add_one_port(&sci_uart_driver, &sciport->port); | |
1da177e4 LT |
1476 | } |
1477 | ||
fa5da2f7 PM |
1478 | #if defined(CONFIG_SH_KGDB) && !defined(CONFIG_SH_KGDB_CONSOLE) |
1479 | kgdb_sci_port = &sci_ports[kgdb_portnum]; | |
1480 | kgdb_getchar = kgdb_sci_getchar; | |
1481 | kgdb_putchar = kgdb_sci_putchar; | |
1482 | #endif | |
1483 | ||
a2159b52 | 1484 | #if defined(CONFIG_CPU_FREQ) && defined(CONFIG_HAVE_CLK) |
1da177e4 | 1485 | cpufreq_register_notifier(&sci_nb, CPUFREQ_TRANSITION_NOTIFIER); |
e289fd97 | 1486 | dev_info(&dev->dev, "CPU frequency notifier registered\n"); |
1da177e4 LT |
1487 | #endif |
1488 | ||
1489 | #ifdef CONFIG_SH_STANDARD_BIOS | |
1490 | sh_bios_gdb_detach(); | |
1491 | #endif | |
1492 | ||
e108b2ca | 1493 | return 0; |
7ff731ae PM |
1494 | |
1495 | err_unreg: | |
1496 | for (i = i - 1; i >= 0; i--) | |
1497 | uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); | |
1498 | ||
1499 | return ret; | |
1da177e4 LT |
1500 | } |
1501 | ||
e108b2ca PM |
1502 | static int __devexit sci_remove(struct platform_device *dev) |
1503 | { | |
1504 | int i; | |
1505 | ||
1506 | for (i = 0; i < SCI_NPORTS; i++) | |
1507 | uart_remove_one_port(&sci_uart_driver, &sci_ports[i].port); | |
1508 | ||
1509 | return 0; | |
1510 | } | |
1511 | ||
1512 | static int sci_suspend(struct platform_device *dev, pm_message_t state) | |
1da177e4 | 1513 | { |
e108b2ca PM |
1514 | int i; |
1515 | ||
1516 | for (i = 0; i < SCI_NPORTS; i++) { | |
1517 | struct sci_port *p = &sci_ports[i]; | |
1518 | ||
1519 | if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) | |
1520 | uart_suspend_port(&sci_uart_driver, &p->port); | |
1521 | } | |
1da177e4 | 1522 | |
e108b2ca PM |
1523 | return 0; |
1524 | } | |
1da177e4 | 1525 | |
e108b2ca PM |
1526 | static int sci_resume(struct platform_device *dev) |
1527 | { | |
1528 | int i; | |
1529 | ||
1530 | for (i = 0; i < SCI_NPORTS; i++) { | |
1531 | struct sci_port *p = &sci_ports[i]; | |
1532 | ||
1533 | if (p->type != PORT_UNKNOWN && p->port.dev == &dev->dev) | |
1534 | uart_resume_port(&sci_uart_driver, &p->port); | |
1535 | } | |
1536 | ||
1537 | return 0; | |
1538 | } | |
1539 | ||
1540 | static struct platform_driver sci_driver = { | |
1541 | .probe = sci_probe, | |
1542 | .remove = __devexit_p(sci_remove), | |
1543 | .suspend = sci_suspend, | |
1544 | .resume = sci_resume, | |
1545 | .driver = { | |
1546 | .name = "sh-sci", | |
1547 | .owner = THIS_MODULE, | |
1548 | }, | |
1549 | }; | |
1550 | ||
1551 | static int __init sci_init(void) | |
1552 | { | |
1553 | int ret; | |
1554 | ||
1555 | printk(banner); | |
1556 | ||
1557 | sci_init_ports(); | |
1558 | ||
1559 | ret = uart_register_driver(&sci_uart_driver); | |
1560 | if (likely(ret == 0)) { | |
1561 | ret = platform_driver_register(&sci_driver); | |
1562 | if (unlikely(ret)) | |
1563 | uart_unregister_driver(&sci_uart_driver); | |
1564 | } | |
1565 | ||
1566 | return ret; | |
1567 | } | |
1568 | ||
1569 | static void __exit sci_exit(void) | |
1570 | { | |
1571 | platform_driver_unregister(&sci_driver); | |
1da177e4 LT |
1572 | uart_unregister_driver(&sci_uart_driver); |
1573 | } | |
1574 | ||
1575 | module_init(sci_init); | |
1576 | module_exit(sci_exit); | |
1577 | ||
e108b2ca | 1578 | MODULE_LICENSE("GPL"); |
e169c139 | 1579 | MODULE_ALIAS("platform:sh-sci"); |