[net-next-2.6.git] / drivers / serial / sc26xx.c

/*
 * SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
 *
 * Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
 */

#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/major.h>
#include <linux/circ_buf.h>
#include <linux/serial.h>
#include <linux/sysrq.h>
#include <linux/console.h>
#include <linux/spinlock.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/irq.h>

#if defined(CONFIG_MAGIC_SYSRQ)
#define SUPPORT_SYSRQ
#endif

#include <linux/serial_core.h>

#define SC26XX_MAJOR         204
#define SC26XX_MINOR_START   205
#define SC26XX_NR            2

struct uart_sc26xx_port {
	struct uart_port      port[2];
	u8     dsr_mask[2];
	u8     cts_mask[2];
	u8     dcd_mask[2];
	u8     ri_mask[2];
	u8     dtr_mask[2];
	u8     rts_mask[2];
	u8     imr;
};

/* register common to both ports */
#define RD_ISR      0x14
#define RD_IPR      0x34

#define WR_ACR      0x10
#define WR_IMR      0x14
#define WR_OPCR     0x34
#define WR_OPR_SET  0x38
#define WR_OPR_CLR  0x3C

/* access common register */
#define READ_SC(p, r)        readb((p)->membase + RD_##r)
#define WRITE_SC(p, r, v)    writeb((v), (p)->membase + WR_##r)

/* register per port */
#define RD_PORT_MRx 0x00
#define RD_PORT_SR  0x04
#define RD_PORT_RHR 0x0c

#define WR_PORT_MRx 0x00
#define WR_PORT_CSR 0x04
#define WR_PORT_CR  0x08
#define WR_PORT_THR 0x0c

/* SR bits */
#define SR_BREAK    (1 << 7)
#define SR_FRAME    (1 << 6)
#define SR_PARITY   (1 << 5)
#define SR_OVERRUN  (1 << 4)
#define SR_TXRDY    (1 << 2)
#define SR_RXRDY    (1 << 0)

#define CR_RES_MR   (1 << 4)
#define CR_RES_RX   (2 << 4)
#define CR_RES_TX   (3 << 4)
#define CR_STRT_BRK (6 << 4)
#define CR_STOP_BRK (7 << 4)
#define CR_DIS_TX   (1 << 3)
#define CR_ENA_TX   (1 << 2)
#define CR_DIS_RX   (1 << 1)
#define CR_ENA_RX   (1 << 0)

/* ISR bits */
#define ISR_RXRDYB  (1 << 5)
#define ISR_TXRDYB  (1 << 4)
#define ISR_RXRDYA  (1 << 1)
#define ISR_TXRDYA  (1 << 0)

/* IMR bits */
#define IMR_RXRDY   (1 << 1)
#define IMR_TXRDY   (1 << 0)

/* access port register */
static inline u8 read_sc_port(struct uart_port *p, u8 reg)
{
	return readb(p->membase + p->line * 0x20 + reg);
}

static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
{
	writeb(val, p->membase + p->line * 0x20 + reg);
}

#define READ_SC_PORT(p, r)     read_sc_port(p, RD_PORT_##r)
#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)

static void sc26xx_enable_irq(struct uart_port *port, int mask)
{
	struct uart_sc26xx_port *up;
	int line = port->line;

	port -= line;
	up = container_of(port, struct uart_sc26xx_port, port[0]);

	up->imr |= mask << (line * 4);
	WRITE_SC(port, IMR, up->imr);
}

static void sc26xx_disable_irq(struct uart_port *port, int mask)
{
	struct uart_sc26xx_port *up;
	int line = port->line;

	port -= line;
	up = container_of(port, struct uart_sc26xx_port, port[0]);

	up->imr &= ~(mask << (line * 4));
	WRITE_SC(port, IMR, up->imr);
}

static struct tty_struct *receive_chars(struct uart_port *port)
{
	struct tty_struct *tty = NULL;
	int limit = 10000;
	unsigned char ch;
	char flag;
	u8 status;

	if (port->state != NULL)		/* Unopened serial console */
		tty = port->state->port.tty;

	while (limit-- > 0) {
		status = READ_SC_PORT(port, SR);
		if (!(status & SR_RXRDY))
			break;
		ch = READ_SC_PORT(port, RHR);

		flag = TTY_NORMAL;
		port->icount.rx++;

		if (unlikely(status & (SR_BREAK | SR_FRAME |
				       SR_PARITY | SR_OVERRUN))) {
			if (status & SR_BREAK) {
				status &= ~(SR_PARITY | SR_FRAME);
				port->icount.brk++;
				if (uart_handle_break(port))
					continue;
			} else if (status & SR_PARITY)
				port->icount.parity++;
			else if (status & SR_FRAME)
				port->icount.frame++;
			if (status & SR_OVERRUN)
				port->icount.overrun++;

			status &= port->read_status_mask;
			if (status & SR_BREAK)
				flag = TTY_BREAK;
			else if (status & SR_PARITY)
				flag = TTY_PARITY;
			else if (status & SR_FRAME)
				flag = TTY_FRAME;
		}

		if (uart_handle_sysrq_char(port, ch))
			continue;

		if (status & port->ignore_status_mask)
			continue;

		tty_insert_flip_char(tty, ch, flag);
	}
	return tty;
}

static void transmit_chars(struct uart_port *port)
{
	struct circ_buf *xmit;

	if (!port->state)
		return;

	xmit = &port->state->xmit;
	if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
		sc26xx_disable_irq(port, IMR_TXRDY);
		return;
	}
	while (!uart_circ_empty(xmit)) {
		if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
			break;

		WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;
	}
	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
		uart_write_wakeup(port);
}

static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
{
	struct uart_sc26xx_port *up = dev_id;
	struct tty_struct *tty;
	unsigned long flags;
	u8 isr;

	spin_lock_irqsave(&up->port[0].lock, flags);

	tty = NULL;
	isr = READ_SC(&up->port[0], ISR);
	if (isr & ISR_TXRDYA)
	    transmit_chars(&up->port[0]);
	if (isr & ISR_RXRDYA)
	    tty = receive_chars(&up->port[0]);

	spin_unlock(&up->port[0].lock);

	if (tty)
		tty_flip_buffer_push(tty);

	spin_lock(&up->port[1].lock);

	tty = NULL;
	if (isr & ISR_TXRDYB)
	    transmit_chars(&up->port[1]);
	if (isr & ISR_RXRDYB)
	    tty = receive_chars(&up->port[1]);

	spin_unlock_irqrestore(&up->port[1].lock, flags);

	if (tty)
		tty_flip_buffer_push(tty);

	return IRQ_HANDLED;
}

/* port->lock is not held.  */
static unsigned int sc26xx_tx_empty(struct uart_port *port)
{
	return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
}

/* port->lock held by caller.  */
static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
	struct uart_sc26xx_port *up;
	int line = port->line;

	port -= line;
	up = container_of(port, struct uart_sc26xx_port, port[0]);

	if (up->dtr_mask[line]) {
		if (mctrl & TIOCM_DTR)
			WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
		else
			WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
	}
	if (up->rts_mask[line]) {
		if (mctrl & TIOCM_RTS)
			WRITE_SC(port, OPR_SET, up->rts_mask[line]);
		else
			WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
	}
}

/* port->lock is held by caller and interrupts are disabled.  */
static unsigned int sc26xx_get_mctrl(struct uart_port *port)
{
	struct uart_sc26xx_port *up;
	int line = port->line;
	unsigned int mctrl = TIOCM_DSR | TIOCM_CTS | TIOCM_CAR;
	u8 ipr;

	port -= line;
	up = container_of(port, struct uart_sc26xx_port, port[0]);
	ipr = READ_SC(port, IPR) ^ 0xff;

	if (up->dsr_mask[line]) {
		mctrl &= ~TIOCM_DSR;
		mctrl |= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
	}
	if (up->cts_mask[line]) {
		mctrl &= ~TIOCM_CTS;
		mctrl |= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
	}
	if (up->dcd_mask[line]) {
		mctrl &= ~TIOCM_CAR;
		mctrl |= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
	}
	if (up->ri_mask[line]) {
		mctrl &= ~TIOCM_RNG;
		mctrl |= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
	}
	return mctrl;
}

/* port->lock held by caller.  */
static void sc26xx_stop_tx(struct uart_port *port)
{
	return;
}

/* port->lock held by caller.  */
static void sc26xx_start_tx(struct uart_port *port)
{
	struct circ_buf *xmit = &port->state->xmit;

	while (!uart_circ_empty(xmit)) {
		if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
			sc26xx_enable_irq(port, IMR_TXRDY);
			break;
		}
		WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
		port->icount.tx++;
	}
}

/* port->lock held by caller.  */
static void sc26xx_stop_rx(struct uart_port *port)
{
}

/* port->lock held by caller.  */
static void sc26xx_enable_ms(struct uart_port *port)
{
}

/* port->lock is not held.  */
static void sc26xx_break_ctl(struct uart_port *port, int break_state)
{
	if (break_state == -1)
		WRITE_SC_PORT(port, CR, CR_STRT_BRK);
	else
		WRITE_SC_PORT(port, CR, CR_STOP_BRK);
}

/* port->lock is not held.  */
static int sc26xx_startup(struct uart_port *port)
{
	sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);
	WRITE_SC(port, OPCR, 0);

	/* reset tx and rx */
	WRITE_SC_PORT(port, CR, CR_RES_RX);
	WRITE_SC_PORT(port, CR, CR_RES_TX);

	/* start rx/tx */
	WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);

	/* enable irqs */
	sc26xx_enable_irq(port, IMR_RXRDY);
	return 0;
}

/* port->lock is not held.  */
static void sc26xx_shutdown(struct uart_port *port)
{
	/* disable interrupst */
	sc26xx_disable_irq(port, IMR_TXRDY | IMR_RXRDY);

	/* stop tx/rx */
	WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);
}

/* port->lock is not held.  */
static void sc26xx_set_termios(struct uart_port *port, struct ktermios *termios,
			      struct ktermios *old)
{
	unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
	unsigned int quot = uart_get_divisor(port, baud);
	unsigned int iflag, cflag;
	unsigned long flags;
	u8 mr1, mr2, csr;

	spin_lock_irqsave(&port->lock, flags);

	while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
		udelay(2);

	WRITE_SC_PORT(port, CR, CR_DIS_TX | CR_DIS_RX);

	iflag = termios->c_iflag;
	cflag = termios->c_cflag;

	port->read_status_mask = SR_OVERRUN;
	if (iflag & INPCK)
		port->read_status_mask |= SR_PARITY | SR_FRAME;
	if (iflag & (BRKINT | PARMRK))
		port->read_status_mask |= SR_BREAK;

	port->ignore_status_mask = 0;
	if (iflag & IGNBRK)
		port->ignore_status_mask |= SR_BREAK;
	if ((cflag & CREAD) == 0)
		port->ignore_status_mask |= SR_BREAK | SR_FRAME |
					    SR_PARITY | SR_OVERRUN;

	switch (cflag & CSIZE) {
	case CS5:
		mr1 = 0x00;
		break;
	case CS6:
		mr1 = 0x01;
		break;
	case CS7:
		mr1 = 0x02;
		break;
	default:
	case CS8:
		mr1 = 0x03;
		break;
	}
	mr2 = 0x07;
	if (cflag & CSTOPB)
		mr2 = 0x0f;
	if (cflag & PARENB) {
		if (cflag & PARODD)
			mr1 |= (1 << 2);
	} else
		mr1 |= (2 << 3);

	switch (baud) {
	case 50:
		csr = 0x00;
		break;
	case 110:
		csr = 0x11;
		break;
	case 134:
		csr = 0x22;
		break;
	case 200:
		csr = 0x33;
		break;
	case 300:
		csr = 0x44;
		break;
	case 600:
		csr = 0x55;
		break;
	case 1200:
		csr = 0x66;
		break;
	case 2400:
		csr = 0x88;
		break;
	case 4800:
		csr = 0x99;
		break;
	default:
	case 9600:
		csr = 0xbb;
		break;
	case 19200:
		csr = 0xcc;
		break;
	}

	WRITE_SC_PORT(port, CR, CR_RES_MR);
	WRITE_SC_PORT(port, MRx, mr1);
	WRITE_SC_PORT(port, MRx, mr2);

	WRITE_SC(port, ACR, 0x80);
	WRITE_SC_PORT(port, CSR, csr);

	/* reset tx and rx */
	WRITE_SC_PORT(port, CR, CR_RES_RX);
	WRITE_SC_PORT(port, CR, CR_RES_TX);

	WRITE_SC_PORT(port, CR, CR_ENA_TX | CR_ENA_RX);
	while ((READ_SC_PORT(port, SR) & ((1 << 3) | (1 << 2))) != 0xc)
		udelay(2);

	/* XXX */
	uart_update_timeout(port, cflag,
			    (port->uartclk / (16 * quot)));

	spin_unlock_irqrestore(&port->lock, flags);
}

static const char *sc26xx_type(struct uart_port *port)
{
	return "SC26XX";
}

static void sc26xx_release_port(struct uart_port *port)
{
}

static int sc26xx_request_port(struct uart_port *port)
{
	return 0;
}

static void sc26xx_config_port(struct uart_port *port, int flags)
{
}

static int sc26xx_verify_port(struct uart_port *port, struct serial_struct *ser)
{
	return -EINVAL;
}

static struct uart_ops sc26xx_ops = {
	.tx_empty	= sc26xx_tx_empty,
	.set_mctrl	= sc26xx_set_mctrl,
	.get_mctrl	= sc26xx_get_mctrl,
	.stop_tx	= sc26xx_stop_tx,
	.start_tx	= sc26xx_start_tx,
	.stop_rx	= sc26xx_stop_rx,
	.enable_ms	= sc26xx_enable_ms,
	.break_ctl	= sc26xx_break_ctl,
	.startup	= sc26xx_startup,
	.shutdown	= sc26xx_shutdown,
	.set_termios	= sc26xx_set_termios,
	.type		= sc26xx_type,
	.release_port	= sc26xx_release_port,
	.request_port	= sc26xx_request_port,
	.config_port	= sc26xx_config_port,
	.verify_port	= sc26xx_verify_port,
};

static struct uart_port *sc26xx_port;

#ifdef CONFIG_SERIAL_SC26XX_CONSOLE
static void sc26xx_console_putchar(struct uart_port *port, char c)
{
	unsigned long flags;
	int limit = 1000000;

	spin_lock_irqsave(&port->lock, flags);

	while (limit-- > 0) {
		if (READ_SC_PORT(port, SR) & SR_TXRDY) {
			WRITE_SC_PORT(port, THR, c);
			break;
		}
		udelay(2);
	}

	spin_unlock_irqrestore(&port->lock, flags);
}

static void sc26xx_console_write(struct console *con, const char *s, unsigned n)
{
	struct uart_port *port = sc26xx_port;
	int i;

	for (i = 0; i < n; i++) {
		if (*s == '\n')
			sc26xx_console_putchar(port, '\r');
		sc26xx_console_putchar(port, *s++);
	}
}

static int __init sc26xx_console_setup(struct console *con, char *options)
{
	struct uart_port *port = sc26xx_port;
	int baud = 9600;
	int bits = 8;
	int parity = 'n';
	int flow = 'n';

	if (port->type != PORT_SC26XX)
		return -1;

	printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
	if (options)
		uart_parse_options(options, &baud, &parity, &bits, &flow);

	return uart_set_options(port, con, baud, parity, bits, flow);
}

static struct uart_driver sc26xx_reg;
static struct console sc26xx_console = {
	.name	=	"ttySC",
	.write	=	sc26xx_console_write,
	.device	=	uart_console_device,
	.setup  =       sc26xx_console_setup,
	.flags	=	CON_PRINTBUFFER,
	.index	=	-1,
	.data	=	&sc26xx_reg,
};
#define SC26XX_CONSOLE   &sc26xx_console
#else
#define SC26XX_CONSOLE   NULL
#endif

static struct uart_driver sc26xx_reg = {
	.owner			= THIS_MODULE,
	.driver_name		= "SC26xx",
	.dev_name		= "ttySC",
	.major			= SC26XX_MAJOR,
	.minor			= SC26XX_MINOR_START,
	.nr			= SC26XX_NR,
	.cons                   = SC26XX_CONSOLE,
};

static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
{
	unsigned int bit = (flags >> bitpos) & 15;

	return bit ? (1 << (bit - 1)) : 0;
}

static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
					int line, unsigned int data)
{
	up->dtr_mask[line] = sc26xx_flags2mask(data,  0);
	up->rts_mask[line] = sc26xx_flags2mask(data,  4);
	up->dsr_mask[line] = sc26xx_flags2mask(data,  8);
	up->cts_mask[line] = sc26xx_flags2mask(data, 12);
	up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
	up->ri_mask[line]  = sc26xx_flags2mask(data, 20);
}

static int __devinit sc26xx_probe(struct platform_device *dev)
{
	struct resource *res;
	struct uart_sc26xx_port *up;
	unsigned int *sc26xx_data = dev->dev.platform_data;
	int err;

	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!res)
		return -ENODEV;

	up = kzalloc(sizeof *up, GFP_KERNEL);
	if (unlikely(!up))
		return -ENOMEM;

	up->port[0].line = 0;
	up->port[0].ops = &sc26xx_ops;
	up->port[0].type = PORT_SC26XX;
	up->port[0].uartclk = (29491200 / 16); /* arbitrary */

	up->port[0].mapbase = res->start;
	up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
	up->port[0].iotype = UPIO_MEM;
	up->port[0].irq = platform_get_irq(dev, 0);

	up->port[0].dev = &dev->dev;

	sc26xx_init_masks(up, 0, sc26xx_data[0]);

	sc26xx_port = &up->port[0];

	up->port[1].line = 1;
	up->port[1].ops = &sc26xx_ops;
	up->port[1].type = PORT_SC26XX;
	up->port[1].uartclk = (29491200 / 16); /* arbitrary */

	up->port[1].mapbase = up->port[0].mapbase;
	up->port[1].membase = up->port[0].membase;
	up->port[1].iotype = UPIO_MEM;
	up->port[1].irq = up->port[0].irq;

	up->port[1].dev = &dev->dev;

	sc26xx_init_masks(up, 1, sc26xx_data[1]);

	err = uart_register_driver(&sc26xx_reg);
	if (err)
		goto out_free_port;

	sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;

	err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
	if (err)
		goto out_unregister_driver;

	err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
	if (err)
		goto out_remove_port0;

	err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
	if (err)
		goto out_remove_ports;

	dev_set_drvdata(&dev->dev, up);
	return 0;

out_remove_ports:
	uart_remove_one_port(&sc26xx_reg, &up->port[1]);
out_remove_port0:
	uart_remove_one_port(&sc26xx_reg, &up->port[0]);

out_unregister_driver:
	uart_unregister_driver(&sc26xx_reg);

out_free_port:
	kfree(up);
	sc26xx_port = NULL;
	return err;
}


static int __exit sc26xx_driver_remove(struct platform_device *dev)
{
	struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);

	free_irq(up->port[0].irq, up);

	uart_remove_one_port(&sc26xx_reg, &up->port[0]);
	uart_remove_one_port(&sc26xx_reg, &up->port[1]);

	uart_unregister_driver(&sc26xx_reg);

	kfree(up);
	sc26xx_port = NULL;

	dev_set_drvdata(&dev->dev, NULL);
	return 0;
}

static struct platform_driver sc26xx_driver = {
	.probe	= sc26xx_probe,
	.remove	= __devexit_p(sc26xx_driver_remove),
	.driver	= {
		.name	= "SC26xx",
		.owner	= THIS_MODULE,
	},
};

static int __init sc26xx_init(void)
{
	return platform_driver_register(&sc26xx_driver);
}

static void __exit sc26xx_exit(void)
{
	platform_driver_unregister(&sc26xx_driver);
}

module_init(sc26xx_init);
module_exit(sc26xx_exit);


MODULE_AUTHOR("Thomas Bogendörfer");
MODULE_DESCRIPTION("SC681/SC2692 serial driver");
MODULE_VERSION("1.0");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:SC26xx");
Commit	Line	Data
eea63e0e TB	1	/*
	2	* SC268xx.c: Serial driver for Philiphs SC2681/SC2692 devices.
	3	*
	4	* Copyright (C) 2006,2007 Thomas Bogendörfer (tsbogend@alpha.franken.de)
	5	*/
	6
	7	#include <linux/module.h>
	8	#include <linux/kernel.h>
	9	#include <linux/errno.h>
	10	#include <linux/tty.h>
	11	#include <linux/tty_flip.h>
	12	#include <linux/major.h>
	13	#include <linux/circ_buf.h>
	14	#include <linux/serial.h>
	15	#include <linux/sysrq.h>
	16	#include <linux/console.h>
	17	#include <linux/spinlock.h>
	18	#include <linux/slab.h>
	19	#include <linux/delay.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/irq.h>
	23
	24	#if defined(CONFIG_MAGIC_SYSRQ)
	25	#define SUPPORT_SYSRQ
	26	#endif
	27
	28	#include <linux/serial_core.h>
	29
	30	#define SC26XX_MAJOR 204
	31	#define SC26XX_MINOR_START 205
	32	#define SC26XX_NR 2
	33
	34	struct uart_sc26xx_port {
	35	struct uart_port port[2];
	36	u8 dsr_mask[2];
	37	u8 cts_mask[2];
	38	u8 dcd_mask[2];
	39	u8 ri_mask[2];
	40	u8 dtr_mask[2];
	41	u8 rts_mask[2];
	42	u8 imr;
	43	};
	44
	45	/* register common to both ports */
	46	#define RD_ISR 0x14
	47	#define RD_IPR 0x34
	48
	49	#define WR_ACR 0x10
	50	#define WR_IMR 0x14
	51	#define WR_OPCR 0x34
	52	#define WR_OPR_SET 0x38
	53	#define WR_OPR_CLR 0x3C
	54
	55	/* access common register */
	56	#define READ_SC(p, r) readb((p)->membase + RD_##r)
	57	#define WRITE_SC(p, r, v) writeb((v), (p)->membase + WR_##r)
	58
	59	/* register per port */
	60	#define RD_PORT_MRx 0x00
	61	#define RD_PORT_SR 0x04
	62	#define RD_PORT_RHR 0x0c
	63
	64	#define WR_PORT_MRx 0x00
65	#define WR_PORT_CSR 0x04
66	#define WR_PORT_CR 0x08
67	#define WR_PORT_THR 0x0c
68
69	/* SR bits */
70	#define SR_BREAK (1 << 7)
71	#define SR_FRAME (1 << 6)
72	#define SR_PARITY (1 << 5)
73	#define SR_OVERRUN (1 << 4)
74	#define SR_TXRDY (1 << 2)
75	#define SR_RXRDY (1 << 0)
76
77	#define CR_RES_MR (1 << 4)
78	#define CR_RES_RX (2 << 4)
79	#define CR_RES_TX (3 << 4)
80	#define CR_STRT_BRK (6 << 4)
81	#define CR_STOP_BRK (7 << 4)
82	#define CR_DIS_TX (1 << 3)
83	#define CR_ENA_TX (1 << 2)
84	#define CR_DIS_RX (1 << 1)
85	#define CR_ENA_RX (1 << 0)
86
87	/* ISR bits */
88	#define ISR_RXRDYB (1 << 5)
89	#define ISR_TXRDYB (1 << 4)
90	#define ISR_RXRDYA (1 << 1)
91	#define ISR_TXRDYA (1 << 0)
92
93	/* IMR bits */
94	#define IMR_RXRDY (1 << 1)
95	#define IMR_TXRDY (1 << 0)
96
97	/* access port register */
98	static inline u8 read_sc_port(struct uart_port *p, u8 reg)
99	{
100	return readb(p->membase + p->line * 0x20 + reg);
101	}
102
103	static inline void write_sc_port(struct uart_port *p, u8 reg, u8 val)
104	{
105	writeb(val, p->membase + p->line * 0x20 + reg);
106	}
107
108	#define READ_SC_PORT(p, r) read_sc_port(p, RD_PORT_##r)
109	#define WRITE_SC_PORT(p, r, v) write_sc_port(p, WR_PORT_##r, v)
110
111	static void sc26xx_enable_irq(struct uart_port *port, int mask)
112	{
113	struct uart_sc26xx_port *up;
114	int line = port->line;
115
116	port -= line;
117	up = container_of(port, struct uart_sc26xx_port, port[0]);
118
119	up->imr \|= mask << (line * 4);
120	WRITE_SC(port, IMR, up->imr);
121	}
122
123	static void sc26xx_disable_irq(struct uart_port *port, int mask)
124	{
125	struct uart_sc26xx_port *up;
126	int line = port->line;
127
128	port -= line;
129	up = container_of(port, struct uart_sc26xx_port, port[0]);
130
131	up->imr &= ~(mask << (line * 4));
132	WRITE_SC(port, IMR, up->imr);
133	}
134
135	static struct tty_struct receive_chars(struct uart_port port)
136	{
137	struct tty_struct *tty = NULL;
138	int limit = 10000;
139	unsigned char ch;
140	char flag;
141	u8 status;
142
ebd2c8f6 AC	143	if (port->state != NULL) /* Unopened serial console */
ebd2c8f6 AC	144	tty = port->state->port.tty;
eea63e0e TB	145
	146	while (limit-- > 0) {
	147	status = READ_SC_PORT(port, SR);
	148	if (!(status & SR_RXRDY))
	149	break;
	150	ch = READ_SC_PORT(port, RHR);
	151
	152	flag = TTY_NORMAL;
	153	port->icount.rx++;
	154
	155	if (unlikely(status & (SR_BREAK \| SR_FRAME \|
	156	SR_PARITY \| SR_OVERRUN))) {
	157	if (status & SR_BREAK) {
	158	status &= ~(SR_PARITY \| SR_FRAME);
	159	port->icount.brk++;
	160	if (uart_handle_break(port))
	161	continue;
	162	} else if (status & SR_PARITY)
	163	port->icount.parity++;
	164	else if (status & SR_FRAME)
	165	port->icount.frame++;
	166	if (status & SR_OVERRUN)
	167	port->icount.overrun++;
	168
	169	status &= port->read_status_mask;
	170	if (status & SR_BREAK)
	171	flag = TTY_BREAK;
	172	else if (status & SR_PARITY)
	173	flag = TTY_PARITY;
	174	else if (status & SR_FRAME)
	175	flag = TTY_FRAME;
	176	}
	177
	178	if (uart_handle_sysrq_char(port, ch))
	179	continue;
	180
	181	if (status & port->ignore_status_mask)
	182	continue;
	183
	184	tty_insert_flip_char(tty, ch, flag);
	185	}
	186	return tty;
	187	}
	188
	189	static void transmit_chars(struct uart_port *port)
	190	{
	191	struct circ_buf *xmit;
	192
ebd2c8f6	193	if (!port->state)
eea63e0e TB	194	return;
eea63e0e TB	195
ebd2c8f6	196	xmit = &port->state->xmit;
eea63e0e TB	197	if (uart_circ_empty(xmit) \|\| uart_tx_stopped(port)) {
	198	sc26xx_disable_irq(port, IMR_TXRDY);
	199	return;
	200	}
	201	while (!uart_circ_empty(xmit)) {
	202	if (!(READ_SC_PORT(port, SR) & SR_TXRDY))
	203	break;
	204
	205	WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
	206	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
	207	port->icount.tx++;
	208	}
	209	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
	210	uart_write_wakeup(port);
	211	}
	212
	213	static irqreturn_t sc26xx_interrupt(int irq, void *dev_id)
	214	{
	215	struct uart_sc26xx_port *up = dev_id;
	216	struct tty_struct *tty;
	217	unsigned long flags;
	218	u8 isr;
	219
	220	spin_lock_irqsave(&up->port[0].lock, flags);
	221
	222	tty = NULL;
	223	isr = READ_SC(&up->port[0], ISR);
	224	if (isr & ISR_TXRDYA)
	225	transmit_chars(&up->port[0]);
	226	if (isr & ISR_RXRDYA)
	227	tty = receive_chars(&up->port[0]);
	228
	229	spin_unlock(&up->port[0].lock);
	230
	231	if (tty)
	232	tty_flip_buffer_push(tty);
	233
	234	spin_lock(&up->port[1].lock);
	235
	236	tty = NULL;
	237	if (isr & ISR_TXRDYB)
	238	transmit_chars(&up->port[1]);
	239	if (isr & ISR_RXRDYB)
	240	tty = receive_chars(&up->port[1]);
	241
	242	spin_unlock_irqrestore(&up->port[1].lock, flags);
	243
	244	if (tty)
	245	tty_flip_buffer_push(tty);
	246
	247	return IRQ_HANDLED;
	248	}
	249
	250	/* port->lock is not held. */
	251	static unsigned int sc26xx_tx_empty(struct uart_port *port)
	252	{
	253	return (READ_SC_PORT(port, SR) & SR_TXRDY) ? TIOCSER_TEMT : 0;
	254	}
	255
	256	/* port->lock held by caller. */
	257	static void sc26xx_set_mctrl(struct uart_port *port, unsigned int mctrl)
	258	{
	259	struct uart_sc26xx_port *up;
	260	int line = port->line;
261
262	port -= line;
263	up = container_of(port, struct uart_sc26xx_port, port[0]);
264
265	if (up->dtr_mask[line]) {
266	if (mctrl & TIOCM_DTR)
267	WRITE_SC(port, OPR_SET, up->dtr_mask[line]);
268	else
269	WRITE_SC(port, OPR_CLR, up->dtr_mask[line]);
270	}
271	if (up->rts_mask[line]) {
272	if (mctrl & TIOCM_RTS)
273	WRITE_SC(port, OPR_SET, up->rts_mask[line]);
274	else
275	WRITE_SC(port, OPR_CLR, up->rts_mask[line]);
276	}
277	}
278
279	/* port->lock is held by caller and interrupts are disabled. */
280	static unsigned int sc26xx_get_mctrl(struct uart_port *port)
281	{
282	struct uart_sc26xx_port *up;
283	int line = port->line;
284	unsigned int mctrl = TIOCM_DSR \| TIOCM_CTS \| TIOCM_CAR;
285	u8 ipr;
286
287	port -= line;
288	up = container_of(port, struct uart_sc26xx_port, port[0]);
289	ipr = READ_SC(port, IPR) ^ 0xff;
290
291	if (up->dsr_mask[line]) {
292	mctrl &= ~TIOCM_DSR;
293	mctrl \|= ipr & up->dsr_mask[line] ? TIOCM_DSR : 0;
294	}
295	if (up->cts_mask[line]) {
296	mctrl &= ~TIOCM_CTS;
297	mctrl \|= ipr & up->cts_mask[line] ? TIOCM_CTS : 0;
298	}
299	if (up->dcd_mask[line]) {
300	mctrl &= ~TIOCM_CAR;
301	mctrl \|= ipr & up->dcd_mask[line] ? TIOCM_CAR : 0;
302	}
303	if (up->ri_mask[line]) {
304	mctrl &= ~TIOCM_RNG;
305	mctrl \|= ipr & up->ri_mask[line] ? TIOCM_RNG : 0;
306	}
307	return mctrl;
308	}
309
310	/* port->lock held by caller. */
311	static void sc26xx_stop_tx(struct uart_port *port)
312	{
313	return;
314	}
315
316	/* port->lock held by caller. */
317	static void sc26xx_start_tx(struct uart_port *port)
318	{
ebd2c8f6	319	struct circ_buf *xmit = &port->state->xmit;
eea63e0e TB	320
	321	while (!uart_circ_empty(xmit)) {
	322	if (!(READ_SC_PORT(port, SR) & SR_TXRDY)) {
	323	sc26xx_enable_irq(port, IMR_TXRDY);
	324	break;
	325	}
	326	WRITE_SC_PORT(port, THR, xmit->buf[xmit->tail]);
	327	xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
	328	port->icount.tx++;
	329	}
	330	}
	331
	332	/* port->lock held by caller. */
	333	static void sc26xx_stop_rx(struct uart_port *port)
	334	{
	335	}
	336
	337	/* port->lock held by caller. */
	338	static void sc26xx_enable_ms(struct uart_port *port)
	339	{
	340	}
	341
	342	/* port->lock is not held. */
	343	static void sc26xx_break_ctl(struct uart_port *port, int break_state)
	344	{
	345	if (break_state == -1)
	346	WRITE_SC_PORT(port, CR, CR_STRT_BRK);
	347	else
	348	WRITE_SC_PORT(port, CR, CR_STOP_BRK);
	349	}
	350
	351	/* port->lock is not held. */
	352	static int sc26xx_startup(struct uart_port *port)
	353	{
	354	sc26xx_disable_irq(port, IMR_TXRDY \| IMR_RXRDY);
	355	WRITE_SC(port, OPCR, 0);
	356
	357	/* reset tx and rx */
	358	WRITE_SC_PORT(port, CR, CR_RES_RX);
	359	WRITE_SC_PORT(port, CR, CR_RES_TX);
	360
	361	/* start rx/tx */
	362	WRITE_SC_PORT(port, CR, CR_ENA_TX \| CR_ENA_RX);
	363
	364	/* enable irqs */
	365	sc26xx_enable_irq(port, IMR_RXRDY);
	366	return 0;
	367	}
	368
	369	/* port->lock is not held. */
	370	static void sc26xx_shutdown(struct uart_port *port)
	371	{
	372	/* disable interrupst */
	373	sc26xx_disable_irq(port, IMR_TXRDY \| IMR_RXRDY);
	374
	375	/* stop tx/rx */
	376	WRITE_SC_PORT(port, CR, CR_DIS_TX \| CR_DIS_RX);
	377	}
	378
	379	/* port->lock is not held. */
	380	static void sc26xx_set_termios(struct uart_port port, struct ktermios termios,
	381	struct ktermios *old)
	382	{
	383	unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
384	unsigned int quot = uart_get_divisor(port, baud);
385	unsigned int iflag, cflag;
386	unsigned long flags;
387	u8 mr1, mr2, csr;
388
389	spin_lock_irqsave(&port->lock, flags);
390
391	while ((READ_SC_PORT(port, SR) & ((1 << 3) \| (1 << 2))) != 0xc)
392	udelay(2);
393
394	WRITE_SC_PORT(port, CR, CR_DIS_TX \| CR_DIS_RX);
395
396	iflag = termios->c_iflag;
397	cflag = termios->c_cflag;
398
399	port->read_status_mask = SR_OVERRUN;
400	if (iflag & INPCK)
401	port->read_status_mask \|= SR_PARITY \| SR_FRAME;
402	if (iflag & (BRKINT \| PARMRK))
403	port->read_status_mask \|= SR_BREAK;
404
405	port->ignore_status_mask = 0;
406	if (iflag & IGNBRK)
407	port->ignore_status_mask \|= SR_BREAK;
408	if ((cflag & CREAD) == 0)
409	port->ignore_status_mask \|= SR_BREAK \| SR_FRAME \|
410	SR_PARITY \| SR_OVERRUN;
411
412	switch (cflag & CSIZE) {
413	case CS5:
414	mr1 = 0x00;
415	break;
416	case CS6:
417	mr1 = 0x01;
418	break;
419	case CS7:
420	mr1 = 0x02;
421	break;
422	default:
423	case CS8:
424	mr1 = 0x03;
425	break;
426	}
427	mr2 = 0x07;
428	if (cflag & CSTOPB)
429	mr2 = 0x0f;
430	if (cflag & PARENB) {
431	if (cflag & PARODD)
432	mr1 \|= (1 << 2);
433	} else
434	mr1 \|= (2 << 3);
435
436	switch (baud) {
437	case 50:
438	csr = 0x00;
439	break;
440	case 110:
441	csr = 0x11;
442	break;
443	case 134:
444	csr = 0x22;
445	break;
446	case 200:
447	csr = 0x33;
448	break;
449	case 300:
450	csr = 0x44;
451	break;
452	case 600:
453	csr = 0x55;
454	break;
455	case 1200:
456	csr = 0x66;
457	break;
458	case 2400:
459	csr = 0x88;
460	break;
461	case 4800:
462	csr = 0x99;
463	break;
464	default:
465	case 9600:
466	csr = 0xbb;
467	break;
468	case 19200:
469	csr = 0xcc;
470	break;
471	}
472
473	WRITE_SC_PORT(port, CR, CR_RES_MR);
474	WRITE_SC_PORT(port, MRx, mr1);
475	WRITE_SC_PORT(port, MRx, mr2);
476
477	WRITE_SC(port, ACR, 0x80);
478	WRITE_SC_PORT(port, CSR, csr);
479
480	/* reset tx and rx */
481	WRITE_SC_PORT(port, CR, CR_RES_RX);
482	WRITE_SC_PORT(port, CR, CR_RES_TX);
483
484	WRITE_SC_PORT(port, CR, CR_ENA_TX \| CR_ENA_RX);
485	while ((READ_SC_PORT(port, SR) & ((1 << 3) \| (1 << 2))) != 0xc)
486	udelay(2);
487
488	/* XXX */
489	uart_update_timeout(port, cflag,
490	(port->uartclk / (16 * quot)));
491
492	spin_unlock_irqrestore(&port->lock, flags);
493	}
494
495	static const char sc26xx_type(struct uart_port port)
496	{
497	return "SC26XX";
498	}
499
500	static void sc26xx_release_port(struct uart_port *port)
501	{
502	}
503
504	static int sc26xx_request_port(struct uart_port *port)
505	{
506	return 0;
507	}
508
509	static void sc26xx_config_port(struct uart_port *port, int flags)
510	{
511	}
512
513	static int sc26xx_verify_port(struct uart_port port, struct serial_struct ser)
514	{
515	return -EINVAL;
516	}
517
518	static struct uart_ops sc26xx_ops = {
519	.tx_empty = sc26xx_tx_empty,
520	.set_mctrl = sc26xx_set_mctrl,
521	.get_mctrl = sc26xx_get_mctrl,
522	.stop_tx = sc26xx_stop_tx,
523	.start_tx = sc26xx_start_tx,
524	.stop_rx = sc26xx_stop_rx,
525	.enable_ms = sc26xx_enable_ms,
526	.break_ctl = sc26xx_break_ctl,
527	.startup = sc26xx_startup,
528	.shutdown = sc26xx_shutdown,
529	.set_termios = sc26xx_set_termios,
530	.type = sc26xx_type,
531	.release_port = sc26xx_release_port,
532	.request_port = sc26xx_request_port,
533	.config_port = sc26xx_config_port,
534	.verify_port = sc26xx_verify_port,
535	};
536
537	static struct uart_port *sc26xx_port;
538
539	#ifdef CONFIG_SERIAL_SC26XX_CONSOLE
540	static void sc26xx_console_putchar(struct uart_port *port, char c)
541	{
542	unsigned long flags;
543	int limit = 1000000;
544
545	spin_lock_irqsave(&port->lock, flags);
546
547	while (limit-- > 0) {
548	if (READ_SC_PORT(port, SR) & SR_TXRDY) {
549	WRITE_SC_PORT(port, THR, c);
550	break;
551	}
552	udelay(2);
553	}
554
555	spin_unlock_irqrestore(&port->lock, flags);
556	}
557
558	static void sc26xx_console_write(struct console con, const char s, unsigned n)
559	{
560	struct uart_port *port = sc26xx_port;
561	int i;
562
563	for (i = 0; i < n; i++) {
564	if (*s == '\n')
565	sc26xx_console_putchar(port, '\r');
566	sc26xx_console_putchar(port, *s++);
567	}
568	}
569
570	static int __init sc26xx_console_setup(struct console con, char options)
571	{
572	struct uart_port *port = sc26xx_port;
573	int baud = 9600;
574	int bits = 8;
575	int parity = 'n';
576	int flow = 'n';
577
578	if (port->type != PORT_SC26XX)
579	return -1;
580
581	printk(KERN_INFO "Console: ttySC%d (SC26XX)\n", con->index);
582	if (options)
583	uart_parse_options(options, &baud, &parity, &bits, &flow);
584
585	return uart_set_options(port, con, baud, parity, bits, flow);
586	}
587
588	static struct uart_driver sc26xx_reg;
589	static struct console sc26xx_console = {
590	.name = "ttySC",
591	.write = sc26xx_console_write,
592	.device = uart_console_device,
593	.setup = sc26xx_console_setup,
594	.flags = CON_PRINTBUFFER,
595	.index = -1,
596	.data = &sc26xx_reg,
597	};
598	#define SC26XX_CONSOLE &sc26xx_console
599	#else
600	#define SC26XX_CONSOLE NULL
601	#endif
602
603	static struct uart_driver sc26xx_reg = {
604	.owner = THIS_MODULE,
605	.driver_name = "SC26xx",
606	.dev_name = "ttySC",
607	.major = SC26XX_MAJOR,
608	.minor = SC26XX_MINOR_START,
609	.nr = SC26XX_NR,
610	.cons = SC26XX_CONSOLE,
611	};
612
613	static u8 sc26xx_flags2mask(unsigned int flags, unsigned int bitpos)
614	{
615	unsigned int bit = (flags >> bitpos) & 15;
616
617	return bit ? (1 << (bit - 1)) : 0;
618	}
619
620	static void __devinit sc26xx_init_masks(struct uart_sc26xx_port *up,
621	int line, unsigned int data)
622	{
623	up->dtr_mask[line] = sc26xx_flags2mask(data, 0);
624	up->rts_mask[line] = sc26xx_flags2mask(data, 4);
625	up->dsr_mask[line] = sc26xx_flags2mask(data, 8);
626	up->cts_mask[line] = sc26xx_flags2mask(data, 12);
627	up->dcd_mask[line] = sc26xx_flags2mask(data, 16);
628	up->ri_mask[line] = sc26xx_flags2mask(data, 20);
629	}
630
631	static int __devinit sc26xx_probe(struct platform_device *dev)
632	{
633	struct resource *res;
634	struct uart_sc26xx_port *up;
635	unsigned int *sc26xx_data = dev->dev.platform_data;
636	int err;
637
638	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
639	if (!res)
640	return -ENODEV;
641
642	up = kzalloc(sizeof *up, GFP_KERNEL);
643	if (unlikely(!up))
644	return -ENOMEM;
645
646	up->port[0].line = 0;
647	up->port[0].ops = &sc26xx_ops;
648	up->port[0].type = PORT_SC26XX;
649	up->port[0].uartclk = (29491200 / 16); /* arbitrary */
650
651	up->port[0].mapbase = res->start;
652	up->port[0].membase = ioremap_nocache(up->port[0].mapbase, 0x40);
653	up->port[0].iotype = UPIO_MEM;
654	up->port[0].irq = platform_get_irq(dev, 0);
655
656	up->port[0].dev = &dev->dev;
657
658	sc26xx_init_masks(up, 0, sc26xx_data[0]);
659
660	sc26xx_port = &up->port[0];
661
662	up->port[1].line = 1;
663	up->port[1].ops = &sc26xx_ops;
664	up->port[1].type = PORT_SC26XX;
665	up->port[1].uartclk = (29491200 / 16); /* arbitrary */
666
667	up->port[1].mapbase = up->port[0].mapbase;
668	up->port[1].membase = up->port[0].membase;
669	up->port[1].iotype = UPIO_MEM;
670	up->port[1].irq = up->port[0].irq;
671
672	up->port[1].dev = &dev->dev;
673
674	sc26xx_init_masks(up, 1, sc26xx_data[1]);
675
676	err = uart_register_driver(&sc26xx_reg);
677	if (err)
678	goto out_free_port;
679
680	sc26xx_reg.tty_driver->name_base = sc26xx_reg.minor;
681
682	err = uart_add_one_port(&sc26xx_reg, &up->port[0]);
683	if (err)
684	goto out_unregister_driver;
685
686	err = uart_add_one_port(&sc26xx_reg, &up->port[1]);
687	if (err)
688	goto out_remove_port0;
689
690	err = request_irq(up->port[0].irq, sc26xx_interrupt, 0, "sc26xx", up);
691	if (err)
692	goto out_remove_ports;
693
694	dev_set_drvdata(&dev->dev, up);
695	return 0;
696
697	out_remove_ports:
698	uart_remove_one_port(&sc26xx_reg, &up->port[1]);
699	out_remove_port0:
700	uart_remove_one_port(&sc26xx_reg, &up->port[0]);
701
702	out_unregister_driver:
703	uart_unregister_driver(&sc26xx_reg);
704
705	out_free_port:
706	kfree(up);
707	sc26xx_port = NULL;
708	return err;
709	}
710
711
712	static int __exit sc26xx_driver_remove(struct platform_device *dev)
713	{
714	struct uart_sc26xx_port *up = dev_get_drvdata(&dev->dev);
715
716	free_irq(up->port[0].irq, up);
717
718	uart_remove_one_port(&sc26xx_reg, &up->port[0]);
719	uart_remove_one_port(&sc26xx_reg, &up->port[1]);
720
721	uart_unregister_driver(&sc26xx_reg);
722
723	kfree(up);
724	sc26xx_port = NULL;
725
726	dev_set_drvdata(&dev->dev, NULL);
727	return 0;
728	}
729
730	static struct platform_driver sc26xx_driver = {
731	.probe = sc26xx_probe,
732	.remove = __devexit_p(sc26xx_driver_remove),
733	.driver = {
734	.name = "SC26xx",
e169c139	735	.owner = THIS_MODULE,
eea63e0e TB	736	},
	737	};
	738
	739	static int __init sc26xx_init(void)
	740	{
	741	return platform_driver_register(&sc26xx_driver);
	742	}
	743
	744	static void __exit sc26xx_exit(void)
	745	{
	746	platform_driver_unregister(&sc26xx_driver);
	747	}
	748
	749	module_init(sc26xx_init);
	750	module_exit(sc26xx_exit);
	751
	752
	753	MODULE_AUTHOR("Thomas Bogendörfer");
	754	MODULE_DESCRIPTION("SC681/SC2692 serial driver");
	755	MODULE_VERSION("1.0");
	756	MODULE_LICENSE("GPL");
e169c139	757	MODULE_ALIAS("platform:SC26xx");