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1da177e4 LT |
1 | /* |
2 | * linux/drivers/serial/pmac_zilog.c | |
3 | * | |
4 | * Driver for PowerMac Z85c30 based ESCC cell found in the | |
5 | * "macio" ASICs of various PowerMac models | |
6 | * | |
7 | * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org) | |
8 | * | |
9 | * Derived from drivers/macintosh/macserial.c by Paul Mackerras | |
10 | * and drivers/serial/sunzilog.c by David S. Miller | |
11 | * | |
12 | * Hrm... actually, I ripped most of sunzilog (Thanks David !) and | |
13 | * adapted special tweaks needed for us. I don't think it's worth | |
14 | * merging back those though. The DMA code still has to get in | |
15 | * and once done, I expect that driver to remain fairly stable in | |
16 | * the long term, unless we change the driver model again... | |
17 | * | |
18 | * This program is free software; you can redistribute it and/or modify | |
19 | * it under the terms of the GNU General Public License as published by | |
20 | * the Free Software Foundation; either version 2 of the License, or | |
21 | * (at your option) any later version. | |
22 | * | |
23 | * This program is distributed in the hope that it will be useful, | |
24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
26 | * GNU General Public License for more details. | |
27 | * | |
28 | * You should have received a copy of the GNU General Public License | |
29 | * along with this program; if not, write to the Free Software | |
30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
31 | * | |
32 | * 2004-08-06 Harald Welte <laforge@gnumonks.org> | |
33 | * - Enable BREAK interrupt | |
34 | * - Add support for sysreq | |
35 | * | |
36 | * TODO: - Add DMA support | |
37 | * - Defer port shutdown to a few seconds after close | |
38 | * - maybe put something right into uap->clk_divisor | |
39 | */ | |
40 | ||
41 | #undef DEBUG | |
42 | #undef DEBUG_HARD | |
43 | #undef USE_CTRL_O_SYSRQ | |
44 | ||
1da177e4 LT |
45 | #include <linux/module.h> |
46 | #include <linux/tty.h> | |
47 | ||
48 | #include <linux/tty_flip.h> | |
49 | #include <linux/major.h> | |
50 | #include <linux/string.h> | |
51 | #include <linux/fcntl.h> | |
52 | #include <linux/mm.h> | |
53 | #include <linux/kernel.h> | |
54 | #include <linux/delay.h> | |
55 | #include <linux/init.h> | |
56 | #include <linux/console.h> | |
1da177e4 LT |
57 | #include <linux/adb.h> |
58 | #include <linux/pmu.h> | |
59 | #include <linux/bitops.h> | |
60 | #include <linux/sysrq.h> | |
f392ecfa | 61 | #include <linux/mutex.h> |
1da177e4 LT |
62 | #include <asm/sections.h> |
63 | #include <asm/io.h> | |
64 | #include <asm/irq.h> | |
ec9cbe09 FT |
65 | |
66 | #ifdef CONFIG_PPC_PMAC | |
1da177e4 LT |
67 | #include <asm/prom.h> |
68 | #include <asm/machdep.h> | |
69 | #include <asm/pmac_feature.h> | |
70 | #include <asm/dbdma.h> | |
71 | #include <asm/macio.h> | |
ec9cbe09 FT |
72 | #else |
73 | #include <linux/platform_device.h> | |
74 | #define of_machine_is_compatible(x) (0) | |
75 | #endif | |
1da177e4 LT |
76 | |
77 | #if defined (CONFIG_SERIAL_PMACZILOG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
78 | #define SUPPORT_SYSRQ | |
79 | #endif | |
80 | ||
81 | #include <linux/serial.h> | |
82 | #include <linux/serial_core.h> | |
83 | ||
84 | #include "pmac_zilog.h" | |
85 | ||
86 | /* Not yet implemented */ | |
87 | #undef HAS_DBDMA | |
88 | ||
89 | static char version[] __initdata = "pmac_zilog: 0.6 (Benjamin Herrenschmidt <benh@kernel.crashing.org>)"; | |
90 | MODULE_AUTHOR("Benjamin Herrenschmidt <benh@kernel.crashing.org>"); | |
ec9cbe09 | 91 | MODULE_DESCRIPTION("Driver for the Mac and PowerMac serial ports."); |
1da177e4 LT |
92 | MODULE_LICENSE("GPL"); |
93 | ||
e4533b24 DW |
94 | #ifdef CONFIG_SERIAL_PMACZILOG_TTYS |
95 | #define PMACZILOG_MAJOR TTY_MAJOR | |
96 | #define PMACZILOG_MINOR 64 | |
97 | #define PMACZILOG_NAME "ttyS" | |
98 | #else | |
99 | #define PMACZILOG_MAJOR 204 | |
100 | #define PMACZILOG_MINOR 192 | |
101 | #define PMACZILOG_NAME "ttyPZ" | |
102 | #endif | |
103 | ||
1da177e4 LT |
104 | |
105 | /* | |
106 | * For the sake of early serial console, we can do a pre-probe | |
107 | * (optional) of the ports at rather early boot time. | |
108 | */ | |
109 | static struct uart_pmac_port pmz_ports[MAX_ZS_PORTS]; | |
110 | static int pmz_ports_count; | |
f392ecfa | 111 | static DEFINE_MUTEX(pmz_irq_mutex); |
1da177e4 LT |
112 | |
113 | static struct uart_driver pmz_uart_reg = { | |
114 | .owner = THIS_MODULE, | |
e4533b24 DW |
115 | .driver_name = PMACZILOG_NAME, |
116 | .dev_name = PMACZILOG_NAME, | |
117 | .major = PMACZILOG_MAJOR, | |
118 | .minor = PMACZILOG_MINOR, | |
1da177e4 LT |
119 | }; |
120 | ||
121 | ||
122 | /* | |
123 | * Load all registers to reprogram the port | |
124 | * This function must only be called when the TX is not busy. The UART | |
125 | * port lock must be held and local interrupts disabled. | |
126 | */ | |
127 | static void pmz_load_zsregs(struct uart_pmac_port *uap, u8 *regs) | |
128 | { | |
129 | int i; | |
130 | ||
131 | if (ZS_IS_ASLEEP(uap)) | |
132 | return; | |
133 | ||
134 | /* Let pending transmits finish. */ | |
135 | for (i = 0; i < 1000; i++) { | |
136 | unsigned char stat = read_zsreg(uap, R1); | |
137 | if (stat & ALL_SNT) | |
138 | break; | |
139 | udelay(100); | |
140 | } | |
141 | ||
142 | ZS_CLEARERR(uap); | |
143 | zssync(uap); | |
144 | ZS_CLEARFIFO(uap); | |
145 | zssync(uap); | |
146 | ZS_CLEARERR(uap); | |
147 | ||
148 | /* Disable all interrupts. */ | |
149 | write_zsreg(uap, R1, | |
150 | regs[R1] & ~(RxINT_MASK | TxINT_ENAB | EXT_INT_ENAB)); | |
151 | ||
152 | /* Set parity, sync config, stop bits, and clock divisor. */ | |
153 | write_zsreg(uap, R4, regs[R4]); | |
154 | ||
155 | /* Set misc. TX/RX control bits. */ | |
156 | write_zsreg(uap, R10, regs[R10]); | |
157 | ||
158 | /* Set TX/RX controls sans the enable bits. */ | |
1f7b5fff FT |
159 | write_zsreg(uap, R3, regs[R3] & ~RxENABLE); |
160 | write_zsreg(uap, R5, regs[R5] & ~TxENABLE); | |
1da177e4 LT |
161 | |
162 | /* now set R7 "prime" on ESCC */ | |
163 | write_zsreg(uap, R15, regs[R15] | EN85C30); | |
164 | write_zsreg(uap, R7, regs[R7P]); | |
165 | ||
166 | /* make sure we use R7 "non-prime" on ESCC */ | |
167 | write_zsreg(uap, R15, regs[R15] & ~EN85C30); | |
168 | ||
169 | /* Synchronous mode config. */ | |
170 | write_zsreg(uap, R6, regs[R6]); | |
171 | write_zsreg(uap, R7, regs[R7]); | |
172 | ||
173 | /* Disable baud generator. */ | |
174 | write_zsreg(uap, R14, regs[R14] & ~BRENAB); | |
175 | ||
176 | /* Clock mode control. */ | |
177 | write_zsreg(uap, R11, regs[R11]); | |
178 | ||
179 | /* Lower and upper byte of baud rate generator divisor. */ | |
180 | write_zsreg(uap, R12, regs[R12]); | |
181 | write_zsreg(uap, R13, regs[R13]); | |
182 | ||
183 | /* Now rewrite R14, with BRENAB (if set). */ | |
184 | write_zsreg(uap, R14, regs[R14]); | |
185 | ||
186 | /* Reset external status interrupts. */ | |
187 | write_zsreg(uap, R0, RES_EXT_INT); | |
188 | write_zsreg(uap, R0, RES_EXT_INT); | |
189 | ||
190 | /* Rewrite R3/R5, this time without enables masked. */ | |
191 | write_zsreg(uap, R3, regs[R3]); | |
192 | write_zsreg(uap, R5, regs[R5]); | |
193 | ||
194 | /* Rewrite R1, this time without IRQ enabled masked. */ | |
195 | write_zsreg(uap, R1, regs[R1]); | |
196 | ||
197 | /* Enable interrupts */ | |
198 | write_zsreg(uap, R9, regs[R9]); | |
199 | } | |
200 | ||
201 | /* | |
202 | * We do like sunzilog to avoid disrupting pending Tx | |
203 | * Reprogram the Zilog channel HW registers with the copies found in the | |
204 | * software state struct. If the transmitter is busy, we defer this update | |
205 | * until the next TX complete interrupt. Else, we do it right now. | |
206 | * | |
207 | * The UART port lock must be held and local interrupts disabled. | |
208 | */ | |
209 | static void pmz_maybe_update_regs(struct uart_pmac_port *uap) | |
210 | { | |
1f7b5fff | 211 | if (!ZS_REGS_HELD(uap)) { |
1da177e4 LT |
212 | if (ZS_TX_ACTIVE(uap)) { |
213 | uap->flags |= PMACZILOG_FLAG_REGS_HELD; | |
214 | } else { | |
215 | pmz_debug("pmz: maybe_update_regs: updating\n"); | |
216 | pmz_load_zsregs(uap, uap->curregs); | |
217 | } | |
218 | } | |
219 | } | |
220 | ||
7d12e780 | 221 | static struct tty_struct *pmz_receive_chars(struct uart_pmac_port *uap) |
1da177e4 LT |
222 | { |
223 | struct tty_struct *tty = NULL; | |
33f0f88f | 224 | unsigned char ch, r1, drop, error, flag; |
1da177e4 LT |
225 | int loops = 0; |
226 | ||
1da177e4 LT |
227 | /* The interrupt can be enabled when the port isn't open, typically |
228 | * that happens when using one port is open and the other closed (stale | |
229 | * interrupt) or when one port is used as a console. | |
230 | */ | |
231 | if (!ZS_IS_OPEN(uap)) { | |
232 | pmz_debug("pmz: draining input\n"); | |
233 | /* Port is closed, drain input data */ | |
234 | for (;;) { | |
235 | if ((++loops) > 1000) | |
236 | goto flood; | |
237 | (void)read_zsreg(uap, R1); | |
238 | write_zsreg(uap, R0, ERR_RES); | |
239 | (void)read_zsdata(uap); | |
240 | ch = read_zsreg(uap, R0); | |
241 | if (!(ch & Rx_CH_AV)) | |
242 | break; | |
243 | } | |
244 | return NULL; | |
245 | } | |
246 | ||
247 | /* Sanity check, make sure the old bug is no longer happening */ | |
ebd2c8f6 | 248 | if (uap->port.state == NULL || uap->port.state->port.tty == NULL) { |
1da177e4 LT |
249 | WARN_ON(1); |
250 | (void)read_zsdata(uap); | |
251 | return NULL; | |
252 | } | |
ebd2c8f6 | 253 | tty = uap->port.state->port.tty; |
1da177e4 LT |
254 | |
255 | while (1) { | |
256 | error = 0; | |
257 | drop = 0; | |
258 | ||
1da177e4 LT |
259 | r1 = read_zsreg(uap, R1); |
260 | ch = read_zsdata(uap); | |
261 | ||
262 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR)) { | |
263 | write_zsreg(uap, R0, ERR_RES); | |
264 | zssync(uap); | |
265 | } | |
266 | ||
267 | ch &= uap->parity_mask; | |
268 | if (ch == 0 && uap->flags & PMACZILOG_FLAG_BREAK) { | |
269 | uap->flags &= ~PMACZILOG_FLAG_BREAK; | |
270 | } | |
271 | ||
272 | #if defined(CONFIG_MAGIC_SYSRQ) && defined(CONFIG_SERIAL_CORE_CONSOLE) | |
273 | #ifdef USE_CTRL_O_SYSRQ | |
274 | /* Handle the SysRq ^O Hack */ | |
275 | if (ch == '\x0f') { | |
276 | uap->port.sysrq = jiffies + HZ*5; | |
277 | goto next_char; | |
278 | } | |
279 | #endif /* USE_CTRL_O_SYSRQ */ | |
280 | if (uap->port.sysrq) { | |
281 | int swallow; | |
282 | spin_unlock(&uap->port.lock); | |
7d12e780 | 283 | swallow = uart_handle_sysrq_char(&uap->port, ch); |
1da177e4 LT |
284 | spin_lock(&uap->port.lock); |
285 | if (swallow) | |
286 | goto next_char; | |
1f7b5fff | 287 | } |
1da177e4 LT |
288 | #endif /* CONFIG_MAGIC_SYSRQ && CONFIG_SERIAL_CORE_CONSOLE */ |
289 | ||
290 | /* A real serial line, record the character and status. */ | |
291 | if (drop) | |
292 | goto next_char; | |
293 | ||
33f0f88f | 294 | flag = TTY_NORMAL; |
1da177e4 LT |
295 | uap->port.icount.rx++; |
296 | ||
297 | if (r1 & (PAR_ERR | Rx_OVR | CRC_ERR | BRK_ABRT)) { | |
298 | error = 1; | |
299 | if (r1 & BRK_ABRT) { | |
300 | pmz_debug("pmz: got break !\n"); | |
301 | r1 &= ~(PAR_ERR | CRC_ERR); | |
302 | uap->port.icount.brk++; | |
303 | if (uart_handle_break(&uap->port)) | |
304 | goto next_char; | |
305 | } | |
306 | else if (r1 & PAR_ERR) | |
307 | uap->port.icount.parity++; | |
308 | else if (r1 & CRC_ERR) | |
309 | uap->port.icount.frame++; | |
310 | if (r1 & Rx_OVR) | |
311 | uap->port.icount.overrun++; | |
312 | r1 &= uap->port.read_status_mask; | |
313 | if (r1 & BRK_ABRT) | |
33f0f88f | 314 | flag = TTY_BREAK; |
1da177e4 | 315 | else if (r1 & PAR_ERR) |
33f0f88f | 316 | flag = TTY_PARITY; |
1da177e4 | 317 | else if (r1 & CRC_ERR) |
33f0f88f | 318 | flag = TTY_FRAME; |
1da177e4 LT |
319 | } |
320 | ||
321 | if (uap->port.ignore_status_mask == 0xff || | |
322 | (r1 & uap->port.ignore_status_mask) == 0) { | |
1f7b5fff | 323 | tty_insert_flip_char(tty, ch, flag); |
1da177e4 | 324 | } |
33f0f88f AC |
325 | if (r1 & Rx_OVR) |
326 | tty_insert_flip_char(tty, 0, TTY_OVERRUN); | |
1da177e4 LT |
327 | next_char: |
328 | /* We can get stuck in an infinite loop getting char 0 when the | |
329 | * line is in a wrong HW state, we break that here. | |
330 | * When that happens, I disable the receive side of the driver. | |
331 | * Note that what I've been experiencing is a real irq loop where | |
332 | * I'm getting flooded regardless of the actual port speed. | |
333 | * Something stange is going on with the HW | |
334 | */ | |
335 | if ((++loops) > 1000) | |
336 | goto flood; | |
337 | ch = read_zsreg(uap, R0); | |
338 | if (!(ch & Rx_CH_AV)) | |
339 | break; | |
340 | } | |
341 | ||
342 | return tty; | |
343 | flood: | |
344 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
345 | write_zsreg(uap, R1, uap->curregs[R1]); | |
346 | zssync(uap); | |
ec9cbe09 | 347 | pmz_error("pmz: rx irq flood !\n"); |
1da177e4 LT |
348 | return tty; |
349 | } | |
350 | ||
7d12e780 | 351 | static void pmz_status_handle(struct uart_pmac_port *uap) |
1da177e4 LT |
352 | { |
353 | unsigned char status; | |
354 | ||
355 | status = read_zsreg(uap, R0); | |
356 | write_zsreg(uap, R0, RES_EXT_INT); | |
357 | zssync(uap); | |
358 | ||
359 | if (ZS_IS_OPEN(uap) && ZS_WANTS_MODEM_STATUS(uap)) { | |
360 | if (status & SYNC_HUNT) | |
361 | uap->port.icount.dsr++; | |
362 | ||
363 | /* The Zilog just gives us an interrupt when DCD/CTS/etc. change. | |
364 | * But it does not tell us which bit has changed, we have to keep | |
365 | * track of this ourselves. | |
366 | * The CTS input is inverted for some reason. -- paulus | |
367 | */ | |
368 | if ((status ^ uap->prev_status) & DCD) | |
369 | uart_handle_dcd_change(&uap->port, | |
370 | (status & DCD)); | |
371 | if ((status ^ uap->prev_status) & CTS) | |
372 | uart_handle_cts_change(&uap->port, | |
373 | !(status & CTS)); | |
374 | ||
bdc04e31 | 375 | wake_up_interruptible(&uap->port.state->port.delta_msr_wait); |
1da177e4 LT |
376 | } |
377 | ||
378 | if (status & BRK_ABRT) | |
379 | uap->flags |= PMACZILOG_FLAG_BREAK; | |
380 | ||
381 | uap->prev_status = status; | |
382 | } | |
383 | ||
384 | static void pmz_transmit_chars(struct uart_pmac_port *uap) | |
385 | { | |
386 | struct circ_buf *xmit; | |
387 | ||
388 | if (ZS_IS_ASLEEP(uap)) | |
389 | return; | |
390 | if (ZS_IS_CONS(uap)) { | |
391 | unsigned char status = read_zsreg(uap, R0); | |
392 | ||
393 | /* TX still busy? Just wait for the next TX done interrupt. | |
394 | * | |
395 | * It can occur because of how we do serial console writes. It would | |
396 | * be nice to transmit console writes just like we normally would for | |
397 | * a TTY line. (ie. buffered and TX interrupt driven). That is not | |
398 | * easy because console writes cannot sleep. One solution might be | |
399 | * to poll on enough port->xmit space becomming free. -DaveM | |
400 | */ | |
401 | if (!(status & Tx_BUF_EMP)) | |
402 | return; | |
403 | } | |
404 | ||
405 | uap->flags &= ~PMACZILOG_FLAG_TX_ACTIVE; | |
406 | ||
407 | if (ZS_REGS_HELD(uap)) { | |
408 | pmz_load_zsregs(uap, uap->curregs); | |
409 | uap->flags &= ~PMACZILOG_FLAG_REGS_HELD; | |
410 | } | |
411 | ||
412 | if (ZS_TX_STOPPED(uap)) { | |
413 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; | |
414 | goto ack_tx_int; | |
415 | } | |
416 | ||
02ab8513 BH |
417 | /* Under some circumstances, we see interrupts reported for |
418 | * a closed channel. The interrupt mask in R1 is clear, but | |
419 | * R3 still signals the interrupts and we see them when taking | |
420 | * an interrupt for the other channel (this could be a qemu | |
421 | * bug but since the ESCC doc doesn't specify precsiely whether | |
422 | * R3 interrup status bits are masked by R1 interrupt enable | |
423 | * bits, better safe than sorry). --BenH. | |
424 | */ | |
425 | if (!ZS_IS_OPEN(uap)) | |
426 | goto ack_tx_int; | |
427 | ||
1da177e4 LT |
428 | if (uap->port.x_char) { |
429 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; | |
430 | write_zsdata(uap, uap->port.x_char); | |
431 | zssync(uap); | |
432 | uap->port.icount.tx++; | |
433 | uap->port.x_char = 0; | |
434 | return; | |
435 | } | |
436 | ||
ebd2c8f6 | 437 | if (uap->port.state == NULL) |
1da177e4 | 438 | goto ack_tx_int; |
ebd2c8f6 | 439 | xmit = &uap->port.state->xmit; |
1da177e4 LT |
440 | if (uart_circ_empty(xmit)) { |
441 | uart_write_wakeup(&uap->port); | |
442 | goto ack_tx_int; | |
443 | } | |
444 | if (uart_tx_stopped(&uap->port)) | |
445 | goto ack_tx_int; | |
446 | ||
447 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; | |
448 | write_zsdata(uap, xmit->buf[xmit->tail]); | |
449 | zssync(uap); | |
450 | ||
451 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
452 | uap->port.icount.tx++; | |
453 | ||
454 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
455 | uart_write_wakeup(&uap->port); | |
456 | ||
457 | return; | |
458 | ||
459 | ack_tx_int: | |
460 | write_zsreg(uap, R0, RES_Tx_P); | |
461 | zssync(uap); | |
462 | } | |
463 | ||
464 | /* Hrm... we register that twice, fixme later.... */ | |
7d12e780 | 465 | static irqreturn_t pmz_interrupt(int irq, void *dev_id) |
1da177e4 LT |
466 | { |
467 | struct uart_pmac_port *uap = dev_id; | |
468 | struct uart_pmac_port *uap_a; | |
469 | struct uart_pmac_port *uap_b; | |
470 | int rc = IRQ_NONE; | |
471 | struct tty_struct *tty; | |
472 | u8 r3; | |
473 | ||
474 | uap_a = pmz_get_port_A(uap); | |
475 | uap_b = uap_a->mate; | |
1f7b5fff FT |
476 | |
477 | spin_lock(&uap_a->port.lock); | |
1da177e4 LT |
478 | r3 = read_zsreg(uap_a, R3); |
479 | ||
480 | #ifdef DEBUG_HARD | |
481 | pmz_debug("irq, r3: %x\n", r3); | |
482 | #endif | |
1f7b5fff | 483 | /* Channel A */ |
1da177e4 | 484 | tty = NULL; |
1f7b5fff | 485 | if (r3 & (CHAEXT | CHATxIP | CHARxIP)) { |
1da177e4 LT |
486 | write_zsreg(uap_a, R0, RES_H_IUS); |
487 | zssync(uap_a); | |
1f7b5fff FT |
488 | if (r3 & CHAEXT) |
489 | pmz_status_handle(uap_a); | |
1da177e4 | 490 | if (r3 & CHARxIP) |
7d12e780 | 491 | tty = pmz_receive_chars(uap_a); |
1f7b5fff FT |
492 | if (r3 & CHATxIP) |
493 | pmz_transmit_chars(uap_a); | |
494 | rc = IRQ_HANDLED; | |
495 | } | |
496 | spin_unlock(&uap_a->port.lock); | |
1da177e4 LT |
497 | if (tty != NULL) |
498 | tty_flip_buffer_push(tty); | |
499 | ||
500 | if (uap_b->node == NULL) | |
501 | goto out; | |
502 | ||
1f7b5fff | 503 | spin_lock(&uap_b->port.lock); |
1da177e4 LT |
504 | tty = NULL; |
505 | if (r3 & (CHBEXT | CHBTxIP | CHBRxIP)) { | |
506 | write_zsreg(uap_b, R0, RES_H_IUS); | |
507 | zssync(uap_b); | |
1f7b5fff FT |
508 | if (r3 & CHBEXT) |
509 | pmz_status_handle(uap_b); | |
510 | if (r3 & CHBRxIP) | |
511 | tty = pmz_receive_chars(uap_b); | |
512 | if (r3 & CHBTxIP) | |
513 | pmz_transmit_chars(uap_b); | |
514 | rc = IRQ_HANDLED; | |
515 | } | |
516 | spin_unlock(&uap_b->port.lock); | |
1da177e4 LT |
517 | if (tty != NULL) |
518 | tty_flip_buffer_push(tty); | |
519 | ||
520 | out: | |
521 | #ifdef DEBUG_HARD | |
522 | pmz_debug("irq done.\n"); | |
523 | #endif | |
524 | return rc; | |
525 | } | |
526 | ||
527 | /* | |
528 | * Peek the status register, lock not held by caller | |
529 | */ | |
530 | static inline u8 pmz_peek_status(struct uart_pmac_port *uap) | |
531 | { | |
532 | unsigned long flags; | |
533 | u8 status; | |
534 | ||
535 | spin_lock_irqsave(&uap->port.lock, flags); | |
536 | status = read_zsreg(uap, R0); | |
537 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
538 | ||
539 | return status; | |
540 | } | |
541 | ||
542 | /* | |
543 | * Check if transmitter is empty | |
544 | * The port lock is not held. | |
545 | */ | |
546 | static unsigned int pmz_tx_empty(struct uart_port *port) | |
547 | { | |
548 | struct uart_pmac_port *uap = to_pmz(port); | |
549 | unsigned char status; | |
550 | ||
551 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) | |
552 | return TIOCSER_TEMT; | |
553 | ||
554 | status = pmz_peek_status(to_pmz(port)); | |
555 | if (status & Tx_BUF_EMP) | |
556 | return TIOCSER_TEMT; | |
557 | return 0; | |
558 | } | |
559 | ||
560 | /* | |
561 | * Set Modem Control (RTS & DTR) bits | |
562 | * The port lock is held and interrupts are disabled. | |
563 | * Note: Shall we really filter out RTS on external ports or | |
564 | * should that be dealt at higher level only ? | |
565 | */ | |
566 | static void pmz_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
567 | { | |
568 | struct uart_pmac_port *uap = to_pmz(port); | |
569 | unsigned char set_bits, clear_bits; | |
570 | ||
571 | /* Do nothing for irda for now... */ | |
572 | if (ZS_IS_IRDA(uap)) | |
573 | return; | |
574 | /* We get called during boot with a port not up yet */ | |
575 | if (ZS_IS_ASLEEP(uap) || | |
576 | !(ZS_IS_OPEN(uap) || ZS_IS_CONS(uap))) | |
577 | return; | |
578 | ||
579 | set_bits = clear_bits = 0; | |
580 | ||
581 | if (ZS_IS_INTMODEM(uap)) { | |
582 | if (mctrl & TIOCM_RTS) | |
583 | set_bits |= RTS; | |
584 | else | |
585 | clear_bits |= RTS; | |
586 | } | |
587 | if (mctrl & TIOCM_DTR) | |
588 | set_bits |= DTR; | |
589 | else | |
590 | clear_bits |= DTR; | |
591 | ||
592 | /* NOTE: Not subject to 'transmitter active' rule. */ | |
593 | uap->curregs[R5] |= set_bits; | |
594 | uap->curregs[R5] &= ~clear_bits; | |
595 | if (ZS_IS_ASLEEP(uap)) | |
596 | return; | |
597 | write_zsreg(uap, R5, uap->curregs[R5]); | |
598 | pmz_debug("pmz_set_mctrl: set bits: %x, clear bits: %x -> %x\n", | |
599 | set_bits, clear_bits, uap->curregs[R5]); | |
600 | zssync(uap); | |
601 | } | |
602 | ||
603 | /* | |
604 | * Get Modem Control bits (only the input ones, the core will | |
605 | * or that with a cached value of the control ones) | |
c5f4644e | 606 | * The port lock is held and interrupts are disabled. |
1da177e4 LT |
607 | */ |
608 | static unsigned int pmz_get_mctrl(struct uart_port *port) | |
609 | { | |
610 | struct uart_pmac_port *uap = to_pmz(port); | |
611 | unsigned char status; | |
612 | unsigned int ret; | |
613 | ||
614 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) | |
615 | return 0; | |
616 | ||
c5f4644e | 617 | status = read_zsreg(uap, R0); |
1da177e4 LT |
618 | |
619 | ret = 0; | |
620 | if (status & DCD) | |
621 | ret |= TIOCM_CAR; | |
622 | if (status & SYNC_HUNT) | |
623 | ret |= TIOCM_DSR; | |
624 | if (!(status & CTS)) | |
625 | ret |= TIOCM_CTS; | |
626 | ||
627 | return ret; | |
628 | } | |
629 | ||
630 | /* | |
631 | * Stop TX side. Dealt like sunzilog at next Tx interrupt, | |
b129a8cc | 632 | * though for DMA, we will have to do a bit more. |
1da177e4 LT |
633 | * The port lock is held and interrupts are disabled. |
634 | */ | |
b129a8cc | 635 | static void pmz_stop_tx(struct uart_port *port) |
1da177e4 LT |
636 | { |
637 | to_pmz(port)->flags |= PMACZILOG_FLAG_TX_STOPPED; | |
638 | } | |
639 | ||
640 | /* | |
641 | * Kick the Tx side. | |
642 | * The port lock is held and interrupts are disabled. | |
643 | */ | |
b129a8cc | 644 | static void pmz_start_tx(struct uart_port *port) |
1da177e4 LT |
645 | { |
646 | struct uart_pmac_port *uap = to_pmz(port); | |
647 | unsigned char status; | |
648 | ||
649 | pmz_debug("pmz: start_tx()\n"); | |
650 | ||
651 | uap->flags |= PMACZILOG_FLAG_TX_ACTIVE; | |
652 | uap->flags &= ~PMACZILOG_FLAG_TX_STOPPED; | |
653 | ||
654 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) | |
655 | return; | |
656 | ||
657 | status = read_zsreg(uap, R0); | |
658 | ||
659 | /* TX busy? Just wait for the TX done interrupt. */ | |
660 | if (!(status & Tx_BUF_EMP)) | |
661 | return; | |
662 | ||
663 | /* Send the first character to jump-start the TX done | |
664 | * IRQ sending engine. | |
665 | */ | |
666 | if (port->x_char) { | |
667 | write_zsdata(uap, port->x_char); | |
668 | zssync(uap); | |
669 | port->icount.tx++; | |
670 | port->x_char = 0; | |
671 | } else { | |
ebd2c8f6 | 672 | struct circ_buf *xmit = &port->state->xmit; |
1da177e4 LT |
673 | |
674 | write_zsdata(uap, xmit->buf[xmit->tail]); | |
675 | zssync(uap); | |
676 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
677 | port->icount.tx++; | |
678 | ||
679 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
680 | uart_write_wakeup(&uap->port); | |
681 | } | |
682 | pmz_debug("pmz: start_tx() done.\n"); | |
683 | } | |
684 | ||
685 | /* | |
686 | * Stop Rx side, basically disable emitting of | |
687 | * Rx interrupts on the port. We don't disable the rx | |
688 | * side of the chip proper though | |
689 | * The port lock is held. | |
690 | */ | |
691 | static void pmz_stop_rx(struct uart_port *port) | |
692 | { | |
693 | struct uart_pmac_port *uap = to_pmz(port); | |
694 | ||
695 | if (ZS_IS_ASLEEP(uap) || uap->node == NULL) | |
696 | return; | |
697 | ||
698 | pmz_debug("pmz: stop_rx()()\n"); | |
699 | ||
700 | /* Disable all RX interrupts. */ | |
701 | uap->curregs[R1] &= ~RxINT_MASK; | |
702 | pmz_maybe_update_regs(uap); | |
703 | ||
704 | pmz_debug("pmz: stop_rx() done.\n"); | |
705 | } | |
706 | ||
707 | /* | |
708 | * Enable modem status change interrupts | |
709 | * The port lock is held. | |
710 | */ | |
711 | static void pmz_enable_ms(struct uart_port *port) | |
712 | { | |
713 | struct uart_pmac_port *uap = to_pmz(port); | |
714 | unsigned char new_reg; | |
715 | ||
716 | if (ZS_IS_IRDA(uap) || uap->node == NULL) | |
717 | return; | |
718 | new_reg = uap->curregs[R15] | (DCDIE | SYNCIE | CTSIE); | |
719 | if (new_reg != uap->curregs[R15]) { | |
720 | uap->curregs[R15] = new_reg; | |
721 | ||
722 | if (ZS_IS_ASLEEP(uap)) | |
723 | return; | |
1f7b5fff | 724 | /* NOTE: Not subject to 'transmitter active' rule. */ |
1da177e4 LT |
725 | write_zsreg(uap, R15, uap->curregs[R15]); |
726 | } | |
727 | } | |
728 | ||
729 | /* | |
730 | * Control break state emission | |
731 | * The port lock is not held. | |
732 | */ | |
733 | static void pmz_break_ctl(struct uart_port *port, int break_state) | |
734 | { | |
735 | struct uart_pmac_port *uap = to_pmz(port); | |
736 | unsigned char set_bits, clear_bits, new_reg; | |
737 | unsigned long flags; | |
738 | ||
739 | if (uap->node == NULL) | |
740 | return; | |
741 | set_bits = clear_bits = 0; | |
742 | ||
743 | if (break_state) | |
744 | set_bits |= SND_BRK; | |
745 | else | |
746 | clear_bits |= SND_BRK; | |
747 | ||
748 | spin_lock_irqsave(&port->lock, flags); | |
749 | ||
750 | new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; | |
751 | if (new_reg != uap->curregs[R5]) { | |
752 | uap->curregs[R5] = new_reg; | |
753 | ||
1f7b5fff | 754 | /* NOTE: Not subject to 'transmitter active' rule. */ |
c61fae96 JL |
755 | if (ZS_IS_ASLEEP(uap)) { |
756 | spin_unlock_irqrestore(&port->lock, flags); | |
1da177e4 | 757 | return; |
c61fae96 | 758 | } |
1da177e4 LT |
759 | write_zsreg(uap, R5, uap->curregs[R5]); |
760 | } | |
761 | ||
762 | spin_unlock_irqrestore(&port->lock, flags); | |
763 | } | |
764 | ||
ec9cbe09 FT |
765 | #ifdef CONFIG_PPC_PMAC |
766 | ||
1da177e4 LT |
767 | /* |
768 | * Turn power on or off to the SCC and associated stuff | |
769 | * (port drivers, modem, IR port, etc.) | |
770 | * Returns the number of milliseconds we should wait before | |
771 | * trying to use the port. | |
772 | */ | |
773 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) | |
774 | { | |
775 | int delay = 0; | |
776 | int rc; | |
777 | ||
778 | if (state) { | |
779 | rc = pmac_call_feature( | |
780 | PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 1); | |
781 | pmz_debug("port power on result: %d\n", rc); | |
782 | if (ZS_IS_INTMODEM(uap)) { | |
783 | rc = pmac_call_feature( | |
784 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 1); | |
785 | delay = 2500; /* wait for 2.5s before using */ | |
786 | pmz_debug("modem power result: %d\n", rc); | |
787 | } | |
788 | } else { | |
789 | /* TODO: Make that depend on a timer, don't power down | |
790 | * immediately | |
791 | */ | |
792 | if (ZS_IS_INTMODEM(uap)) { | |
793 | rc = pmac_call_feature( | |
794 | PMAC_FTR_MODEM_ENABLE, uap->node, 0, 0); | |
795 | pmz_debug("port power off result: %d\n", rc); | |
796 | } | |
797 | pmac_call_feature(PMAC_FTR_SCC_ENABLE, uap->node, uap->port_type, 0); | |
798 | } | |
799 | return delay; | |
800 | } | |
801 | ||
ec9cbe09 FT |
802 | #else |
803 | ||
804 | static int pmz_set_scc_power(struct uart_pmac_port *uap, int state) | |
805 | { | |
806 | return 0; | |
807 | } | |
808 | ||
809 | #endif /* !CONFIG_PPC_PMAC */ | |
810 | ||
1da177e4 LT |
811 | /* |
812 | * FixZeroBug....Works around a bug in the SCC receving channel. | |
813 | * Inspired from Darwin code, 15 Sept. 2000 -DanM | |
814 | * | |
815 | * The following sequence prevents a problem that is seen with O'Hare ASICs | |
816 | * (most versions -- also with some Heathrow and Hydra ASICs) where a zero | |
817 | * at the input to the receiver becomes 'stuck' and locks up the receiver. | |
818 | * This problem can occur as a result of a zero bit at the receiver input | |
819 | * coincident with any of the following events: | |
820 | * | |
821 | * The SCC is initialized (hardware or software). | |
822 | * A framing error is detected. | |
823 | * The clocking option changes from synchronous or X1 asynchronous | |
824 | * clocking to X16, X32, or X64 asynchronous clocking. | |
825 | * The decoding mode is changed among NRZ, NRZI, FM0, or FM1. | |
826 | * | |
827 | * This workaround attempts to recover from the lockup condition by placing | |
828 | * the SCC in synchronous loopback mode with a fast clock before programming | |
829 | * any of the asynchronous modes. | |
830 | */ | |
831 | static void pmz_fix_zero_bug_scc(struct uart_pmac_port *uap) | |
832 | { | |
833 | write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); | |
834 | zssync(uap); | |
835 | udelay(10); | |
836 | write_zsreg(uap, 9, (ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB) | NV); | |
837 | zssync(uap); | |
838 | ||
839 | write_zsreg(uap, 4, X1CLK | MONSYNC); | |
840 | write_zsreg(uap, 3, Rx8); | |
841 | write_zsreg(uap, 5, Tx8 | RTS); | |
842 | write_zsreg(uap, 9, NV); /* Didn't we already do this? */ | |
843 | write_zsreg(uap, 11, RCBR | TCBR); | |
844 | write_zsreg(uap, 12, 0); | |
845 | write_zsreg(uap, 13, 0); | |
846 | write_zsreg(uap, 14, (LOOPBAK | BRSRC)); | |
847 | write_zsreg(uap, 14, (LOOPBAK | BRSRC | BRENAB)); | |
848 | write_zsreg(uap, 3, Rx8 | RxENABLE); | |
849 | write_zsreg(uap, 0, RES_EXT_INT); | |
850 | write_zsreg(uap, 0, RES_EXT_INT); | |
851 | write_zsreg(uap, 0, RES_EXT_INT); /* to kill some time */ | |
852 | ||
853 | /* The channel should be OK now, but it is probably receiving | |
854 | * loopback garbage. | |
855 | * Switch to asynchronous mode, disable the receiver, | |
856 | * and discard everything in the receive buffer. | |
857 | */ | |
858 | write_zsreg(uap, 9, NV); | |
859 | write_zsreg(uap, 4, X16CLK | SB_MASK); | |
860 | write_zsreg(uap, 3, Rx8); | |
861 | ||
862 | while (read_zsreg(uap, 0) & Rx_CH_AV) { | |
863 | (void)read_zsreg(uap, 8); | |
864 | write_zsreg(uap, 0, RES_EXT_INT); | |
865 | write_zsreg(uap, 0, ERR_RES); | |
866 | } | |
867 | } | |
868 | ||
869 | /* | |
870 | * Real startup routine, powers up the hardware and sets up | |
871 | * the SCC. Returns a delay in ms where you need to wait before | |
872 | * actually using the port, this is typically the internal modem | |
873 | * powerup delay. This routine expect the lock to be taken. | |
874 | */ | |
875 | static int __pmz_startup(struct uart_pmac_port *uap) | |
876 | { | |
877 | int pwr_delay = 0; | |
878 | ||
879 | memset(&uap->curregs, 0, sizeof(uap->curregs)); | |
880 | ||
881 | /* Power up the SCC & underlying hardware (modem/irda) */ | |
882 | pwr_delay = pmz_set_scc_power(uap, 1); | |
883 | ||
884 | /* Nice buggy HW ... */ | |
885 | pmz_fix_zero_bug_scc(uap); | |
886 | ||
887 | /* Reset the channel */ | |
888 | uap->curregs[R9] = 0; | |
889 | write_zsreg(uap, 9, ZS_IS_CHANNEL_A(uap) ? CHRA : CHRB); | |
890 | zssync(uap); | |
891 | udelay(10); | |
892 | write_zsreg(uap, 9, 0); | |
893 | zssync(uap); | |
894 | ||
895 | /* Clear the interrupt registers */ | |
896 | write_zsreg(uap, R1, 0); | |
897 | write_zsreg(uap, R0, ERR_RES); | |
898 | write_zsreg(uap, R0, ERR_RES); | |
899 | write_zsreg(uap, R0, RES_H_IUS); | |
900 | write_zsreg(uap, R0, RES_H_IUS); | |
901 | ||
902 | /* Setup some valid baud rate */ | |
903 | uap->curregs[R4] = X16CLK | SB1; | |
904 | uap->curregs[R3] = Rx8; | |
905 | uap->curregs[R5] = Tx8 | RTS; | |
906 | if (!ZS_IS_IRDA(uap)) | |
907 | uap->curregs[R5] |= DTR; | |
908 | uap->curregs[R12] = 0; | |
909 | uap->curregs[R13] = 0; | |
910 | uap->curregs[R14] = BRENAB; | |
911 | ||
912 | /* Clear handshaking, enable BREAK interrupts */ | |
913 | uap->curregs[R15] = BRKIE; | |
914 | ||
915 | /* Master interrupt enable */ | |
916 | uap->curregs[R9] |= NV | MIE; | |
917 | ||
918 | pmz_load_zsregs(uap, uap->curregs); | |
919 | ||
920 | /* Enable receiver and transmitter. */ | |
921 | write_zsreg(uap, R3, uap->curregs[R3] |= RxENABLE); | |
922 | write_zsreg(uap, R5, uap->curregs[R5] |= TxENABLE); | |
923 | ||
924 | /* Remember status for DCD/CTS changes */ | |
925 | uap->prev_status = read_zsreg(uap, R0); | |
926 | ||
1da177e4 LT |
927 | return pwr_delay; |
928 | } | |
929 | ||
930 | static void pmz_irda_reset(struct uart_pmac_port *uap) | |
931 | { | |
932 | uap->curregs[R5] |= DTR; | |
933 | write_zsreg(uap, R5, uap->curregs[R5]); | |
934 | zssync(uap); | |
935 | mdelay(110); | |
936 | uap->curregs[R5] &= ~DTR; | |
937 | write_zsreg(uap, R5, uap->curregs[R5]); | |
938 | zssync(uap); | |
939 | mdelay(10); | |
940 | } | |
941 | ||
942 | /* | |
943 | * This is the "normal" startup routine, using the above one | |
944 | * wrapped with the lock and doing a schedule delay | |
945 | */ | |
946 | static int pmz_startup(struct uart_port *port) | |
947 | { | |
948 | struct uart_pmac_port *uap = to_pmz(port); | |
949 | unsigned long flags; | |
950 | int pwr_delay = 0; | |
951 | ||
952 | pmz_debug("pmz: startup()\n"); | |
953 | ||
954 | if (ZS_IS_ASLEEP(uap)) | |
955 | return -EAGAIN; | |
956 | if (uap->node == NULL) | |
957 | return -ENODEV; | |
958 | ||
f392ecfa | 959 | mutex_lock(&pmz_irq_mutex); |
1da177e4 LT |
960 | |
961 | uap->flags |= PMACZILOG_FLAG_IS_OPEN; | |
962 | ||
963 | /* A console is never powered down. Else, power up and | |
964 | * initialize the chip | |
965 | */ | |
966 | if (!ZS_IS_CONS(uap)) { | |
967 | spin_lock_irqsave(&port->lock, flags); | |
968 | pwr_delay = __pmz_startup(uap); | |
969 | spin_unlock_irqrestore(&port->lock, flags); | |
970 | } | |
971 | ||
972 | pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; | |
ec9cbe09 FT |
973 | if (request_irq(uap->port.irq, pmz_interrupt, IRQF_SHARED, |
974 | "SCC", uap)) { | |
975 | pmz_error("Unable to register zs interrupt handler.\n"); | |
1da177e4 | 976 | pmz_set_scc_power(uap, 0); |
f392ecfa | 977 | mutex_unlock(&pmz_irq_mutex); |
1da177e4 LT |
978 | return -ENXIO; |
979 | } | |
980 | ||
f392ecfa | 981 | mutex_unlock(&pmz_irq_mutex); |
1da177e4 LT |
982 | |
983 | /* Right now, we deal with delay by blocking here, I'll be | |
984 | * smarter later on | |
985 | */ | |
986 | if (pwr_delay != 0) { | |
987 | pmz_debug("pmz: delaying %d ms\n", pwr_delay); | |
988 | msleep(pwr_delay); | |
989 | } | |
990 | ||
991 | /* IrDA reset is done now */ | |
992 | if (ZS_IS_IRDA(uap)) | |
993 | pmz_irda_reset(uap); | |
994 | ||
995 | /* Enable interrupts emission from the chip */ | |
996 | spin_lock_irqsave(&port->lock, flags); | |
997 | uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; | |
998 | if (!ZS_IS_EXTCLK(uap)) | |
999 | uap->curregs[R1] |= EXT_INT_ENAB; | |
1000 | write_zsreg(uap, R1, uap->curregs[R1]); | |
1f7b5fff | 1001 | spin_unlock_irqrestore(&port->lock, flags); |
1da177e4 LT |
1002 | |
1003 | pmz_debug("pmz: startup() done.\n"); | |
1004 | ||
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static void pmz_shutdown(struct uart_port *port) | |
1009 | { | |
1010 | struct uart_pmac_port *uap = to_pmz(port); | |
1011 | unsigned long flags; | |
1012 | ||
1013 | pmz_debug("pmz: shutdown()\n"); | |
1014 | ||
1015 | if (uap->node == NULL) | |
1016 | return; | |
1017 | ||
f392ecfa | 1018 | mutex_lock(&pmz_irq_mutex); |
1da177e4 LT |
1019 | |
1020 | /* Release interrupt handler */ | |
1f7b5fff | 1021 | free_irq(uap->port.irq, uap); |
1da177e4 LT |
1022 | |
1023 | spin_lock_irqsave(&port->lock, flags); | |
1024 | ||
1025 | uap->flags &= ~PMACZILOG_FLAG_IS_OPEN; | |
1026 | ||
1027 | if (!ZS_IS_OPEN(uap->mate)) | |
1028 | pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; | |
1029 | ||
1030 | /* Disable interrupts */ | |
1031 | if (!ZS_IS_ASLEEP(uap)) { | |
1032 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
1033 | write_zsreg(uap, R1, uap->curregs[R1]); | |
1034 | zssync(uap); | |
1035 | } | |
1036 | ||
1037 | if (ZS_IS_CONS(uap) || ZS_IS_ASLEEP(uap)) { | |
1038 | spin_unlock_irqrestore(&port->lock, flags); | |
f392ecfa | 1039 | mutex_unlock(&pmz_irq_mutex); |
1da177e4 LT |
1040 | return; |
1041 | } | |
1042 | ||
1043 | /* Disable receiver and transmitter. */ | |
1044 | uap->curregs[R3] &= ~RxENABLE; | |
1045 | uap->curregs[R5] &= ~TxENABLE; | |
1046 | ||
1047 | /* Disable all interrupts and BRK assertion. */ | |
1048 | uap->curregs[R5] &= ~SND_BRK; | |
1049 | pmz_maybe_update_regs(uap); | |
1050 | ||
1051 | /* Shut the chip down */ | |
1052 | pmz_set_scc_power(uap, 0); | |
1053 | ||
1054 | spin_unlock_irqrestore(&port->lock, flags); | |
1055 | ||
f392ecfa | 1056 | mutex_unlock(&pmz_irq_mutex); |
1da177e4 LT |
1057 | |
1058 | pmz_debug("pmz: shutdown() done.\n"); | |
1059 | } | |
1060 | ||
1061 | /* Shared by TTY driver and serial console setup. The port lock is held | |
1062 | * and local interrupts are disabled. | |
1063 | */ | |
1064 | static void pmz_convert_to_zs(struct uart_pmac_port *uap, unsigned int cflag, | |
1065 | unsigned int iflag, unsigned long baud) | |
1066 | { | |
1067 | int brg; | |
1068 | ||
1da177e4 LT |
1069 | /* Switch to external clocking for IrDA high clock rates. That |
1070 | * code could be re-used for Midi interfaces with different | |
1071 | * multipliers | |
1072 | */ | |
1073 | if (baud >= 115200 && ZS_IS_IRDA(uap)) { | |
1074 | uap->curregs[R4] = X1CLK; | |
1075 | uap->curregs[R11] = RCTRxCP | TCTRxCP; | |
1076 | uap->curregs[R14] = 0; /* BRG off */ | |
1077 | uap->curregs[R12] = 0; | |
1078 | uap->curregs[R13] = 0; | |
1079 | uap->flags |= PMACZILOG_FLAG_IS_EXTCLK; | |
1080 | } else { | |
1081 | switch (baud) { | |
1082 | case ZS_CLOCK/16: /* 230400 */ | |
1083 | uap->curregs[R4] = X16CLK; | |
1084 | uap->curregs[R11] = 0; | |
1085 | uap->curregs[R14] = 0; | |
1086 | break; | |
1087 | case ZS_CLOCK/32: /* 115200 */ | |
1088 | uap->curregs[R4] = X32CLK; | |
1089 | uap->curregs[R11] = 0; | |
1090 | uap->curregs[R14] = 0; | |
1091 | break; | |
1092 | default: | |
1093 | uap->curregs[R4] = X16CLK; | |
1094 | uap->curregs[R11] = TCBR | RCBR; | |
1095 | brg = BPS_TO_BRG(baud, ZS_CLOCK / 16); | |
1096 | uap->curregs[R12] = (brg & 255); | |
1097 | uap->curregs[R13] = ((brg >> 8) & 255); | |
1098 | uap->curregs[R14] = BRENAB; | |
1099 | } | |
1100 | uap->flags &= ~PMACZILOG_FLAG_IS_EXTCLK; | |
1101 | } | |
1102 | ||
1103 | /* Character size, stop bits, and parity. */ | |
1104 | uap->curregs[3] &= ~RxN_MASK; | |
1105 | uap->curregs[5] &= ~TxN_MASK; | |
1106 | ||
1107 | switch (cflag & CSIZE) { | |
1108 | case CS5: | |
1109 | uap->curregs[3] |= Rx5; | |
1110 | uap->curregs[5] |= Tx5; | |
1111 | uap->parity_mask = 0x1f; | |
1112 | break; | |
1113 | case CS6: | |
1114 | uap->curregs[3] |= Rx6; | |
1115 | uap->curregs[5] |= Tx6; | |
1116 | uap->parity_mask = 0x3f; | |
1117 | break; | |
1118 | case CS7: | |
1119 | uap->curregs[3] |= Rx7; | |
1120 | uap->curregs[5] |= Tx7; | |
1121 | uap->parity_mask = 0x7f; | |
1122 | break; | |
1123 | case CS8: | |
1124 | default: | |
1125 | uap->curregs[3] |= Rx8; | |
1126 | uap->curregs[5] |= Tx8; | |
1127 | uap->parity_mask = 0xff; | |
1128 | break; | |
1129 | }; | |
1130 | uap->curregs[4] &= ~(SB_MASK); | |
1131 | if (cflag & CSTOPB) | |
1132 | uap->curregs[4] |= SB2; | |
1133 | else | |
1134 | uap->curregs[4] |= SB1; | |
1135 | if (cflag & PARENB) | |
1136 | uap->curregs[4] |= PAR_ENAB; | |
1137 | else | |
1138 | uap->curregs[4] &= ~PAR_ENAB; | |
1139 | if (!(cflag & PARODD)) | |
1140 | uap->curregs[4] |= PAR_EVEN; | |
1141 | else | |
1142 | uap->curregs[4] &= ~PAR_EVEN; | |
1143 | ||
1144 | uap->port.read_status_mask = Rx_OVR; | |
1145 | if (iflag & INPCK) | |
1146 | uap->port.read_status_mask |= CRC_ERR | PAR_ERR; | |
1147 | if (iflag & (BRKINT | PARMRK)) | |
1148 | uap->port.read_status_mask |= BRK_ABRT; | |
1149 | ||
1150 | uap->port.ignore_status_mask = 0; | |
1151 | if (iflag & IGNPAR) | |
1152 | uap->port.ignore_status_mask |= CRC_ERR | PAR_ERR; | |
1153 | if (iflag & IGNBRK) { | |
1154 | uap->port.ignore_status_mask |= BRK_ABRT; | |
1155 | if (iflag & IGNPAR) | |
1156 | uap->port.ignore_status_mask |= Rx_OVR; | |
1157 | } | |
1158 | ||
1159 | if ((cflag & CREAD) == 0) | |
1160 | uap->port.ignore_status_mask = 0xff; | |
1161 | } | |
1162 | ||
1163 | ||
1164 | /* | |
1165 | * Set the irda codec on the imac to the specified baud rate. | |
1166 | */ | |
1167 | static void pmz_irda_setup(struct uart_pmac_port *uap, unsigned long *baud) | |
1168 | { | |
1169 | u8 cmdbyte; | |
1170 | int t, version; | |
1171 | ||
1172 | switch (*baud) { | |
1173 | /* SIR modes */ | |
1174 | case 2400: | |
1175 | cmdbyte = 0x53; | |
1176 | break; | |
1177 | case 4800: | |
1178 | cmdbyte = 0x52; | |
1179 | break; | |
1180 | case 9600: | |
1181 | cmdbyte = 0x51; | |
1182 | break; | |
1183 | case 19200: | |
1184 | cmdbyte = 0x50; | |
1185 | break; | |
1186 | case 38400: | |
1187 | cmdbyte = 0x4f; | |
1188 | break; | |
1189 | case 57600: | |
1190 | cmdbyte = 0x4e; | |
1191 | break; | |
1192 | case 115200: | |
1193 | cmdbyte = 0x4d; | |
1194 | break; | |
1195 | /* The FIR modes aren't really supported at this point, how | |
1196 | * do we select the speed ? via the FCR on KeyLargo ? | |
1197 | */ | |
1198 | case 1152000: | |
1199 | cmdbyte = 0; | |
1200 | break; | |
1201 | case 4000000: | |
1202 | cmdbyte = 0; | |
1203 | break; | |
1204 | default: /* 9600 */ | |
1205 | cmdbyte = 0x51; | |
1206 | *baud = 9600; | |
1207 | break; | |
1208 | } | |
1209 | ||
1210 | /* Wait for transmitter to drain */ | |
1211 | t = 10000; | |
1212 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0 | |
1213 | || (read_zsreg(uap, R1) & ALL_SNT) == 0) { | |
1214 | if (--t <= 0) { | |
ec9cbe09 | 1215 | pmz_error("transmitter didn't drain\n"); |
1da177e4 LT |
1216 | return; |
1217 | } | |
1218 | udelay(10); | |
1219 | } | |
1220 | ||
1221 | /* Drain the receiver too */ | |
1222 | t = 100; | |
1223 | (void)read_zsdata(uap); | |
1224 | (void)read_zsdata(uap); | |
1225 | (void)read_zsdata(uap); | |
1226 | mdelay(10); | |
1227 | while (read_zsreg(uap, R0) & Rx_CH_AV) { | |
1228 | read_zsdata(uap); | |
1229 | mdelay(10); | |
1230 | if (--t <= 0) { | |
ec9cbe09 | 1231 | pmz_error("receiver didn't drain\n"); |
1da177e4 LT |
1232 | return; |
1233 | } | |
1234 | } | |
1235 | ||
1236 | /* Switch to command mode */ | |
1237 | uap->curregs[R5] |= DTR; | |
1238 | write_zsreg(uap, R5, uap->curregs[R5]); | |
1239 | zssync(uap); | |
1f7b5fff | 1240 | mdelay(1); |
1da177e4 LT |
1241 | |
1242 | /* Switch SCC to 19200 */ | |
1243 | pmz_convert_to_zs(uap, CS8, 0, 19200); | |
1244 | pmz_load_zsregs(uap, uap->curregs); | |
1f7b5fff | 1245 | mdelay(1); |
1da177e4 LT |
1246 | |
1247 | /* Write get_version command byte */ | |
1248 | write_zsdata(uap, 1); | |
1249 | t = 5000; | |
1250 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { | |
1251 | if (--t <= 0) { | |
ec9cbe09 | 1252 | pmz_error("irda_setup timed out on get_version byte\n"); |
1da177e4 LT |
1253 | goto out; |
1254 | } | |
1255 | udelay(10); | |
1256 | } | |
1257 | version = read_zsdata(uap); | |
1258 | ||
1259 | if (version < 4) { | |
ec9cbe09 | 1260 | pmz_info("IrDA: dongle version %d not supported\n", version); |
1da177e4 LT |
1261 | goto out; |
1262 | } | |
1263 | ||
1264 | /* Send speed mode */ | |
1265 | write_zsdata(uap, cmdbyte); | |
1266 | t = 5000; | |
1267 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) { | |
1268 | if (--t <= 0) { | |
ec9cbe09 | 1269 | pmz_error("irda_setup timed out on speed mode byte\n"); |
1da177e4 LT |
1270 | goto out; |
1271 | } | |
1272 | udelay(10); | |
1273 | } | |
1274 | t = read_zsdata(uap); | |
1275 | if (t != cmdbyte) | |
ec9cbe09 | 1276 | pmz_error("irda_setup speed mode byte = %x (%x)\n", t, cmdbyte); |
1da177e4 | 1277 | |
ec9cbe09 | 1278 | pmz_info("IrDA setup for %ld bps, dongle version: %d\n", |
1da177e4 LT |
1279 | *baud, version); |
1280 | ||
1281 | (void)read_zsdata(uap); | |
1282 | (void)read_zsdata(uap); | |
1283 | (void)read_zsdata(uap); | |
1284 | ||
1285 | out: | |
1286 | /* Switch back to data mode */ | |
1287 | uap->curregs[R5] &= ~DTR; | |
1288 | write_zsreg(uap, R5, uap->curregs[R5]); | |
1289 | zssync(uap); | |
1290 | ||
1291 | (void)read_zsdata(uap); | |
1292 | (void)read_zsdata(uap); | |
1293 | (void)read_zsdata(uap); | |
1294 | } | |
1295 | ||
1296 | ||
606d099c AC |
1297 | static void __pmz_set_termios(struct uart_port *port, struct ktermios *termios, |
1298 | struct ktermios *old) | |
1da177e4 LT |
1299 | { |
1300 | struct uart_pmac_port *uap = to_pmz(port); | |
1301 | unsigned long baud; | |
1302 | ||
1303 | pmz_debug("pmz: set_termios()\n"); | |
1304 | ||
1305 | if (ZS_IS_ASLEEP(uap)) | |
1306 | return; | |
1307 | ||
606d099c | 1308 | memcpy(&uap->termios_cache, termios, sizeof(struct ktermios)); |
1da177e4 LT |
1309 | |
1310 | /* XXX Check which revs of machines actually allow 1 and 4Mb speeds | |
1311 | * on the IR dongle. Note that the IRTTY driver currently doesn't know | |
1312 | * about the FIR mode and high speed modes. So these are unused. For | |
1313 | * implementing proper support for these, we should probably add some | |
1314 | * DMA as well, at least on the Rx side, which isn't a simple thing | |
1315 | * at this point. | |
1316 | */ | |
1317 | if (ZS_IS_IRDA(uap)) { | |
1318 | /* Calc baud rate */ | |
1319 | baud = uart_get_baud_rate(port, termios, old, 1200, 4000000); | |
1320 | pmz_debug("pmz: switch IRDA to %ld bauds\n", baud); | |
1321 | /* Cet the irda codec to the right rate */ | |
1322 | pmz_irda_setup(uap, &baud); | |
1323 | /* Set final baud rate */ | |
1324 | pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); | |
1325 | pmz_load_zsregs(uap, uap->curregs); | |
1326 | zssync(uap); | |
1327 | } else { | |
1328 | baud = uart_get_baud_rate(port, termios, old, 1200, 230400); | |
1329 | pmz_convert_to_zs(uap, termios->c_cflag, termios->c_iflag, baud); | |
1330 | /* Make sure modem status interrupts are correctly configured */ | |
1331 | if (UART_ENABLE_MS(&uap->port, termios->c_cflag)) { | |
1332 | uap->curregs[R15] |= DCDIE | SYNCIE | CTSIE; | |
1333 | uap->flags |= PMACZILOG_FLAG_MODEM_STATUS; | |
1334 | } else { | |
1335 | uap->curregs[R15] &= ~(DCDIE | SYNCIE | CTSIE); | |
1336 | uap->flags &= ~PMACZILOG_FLAG_MODEM_STATUS; | |
1337 | } | |
1338 | ||
1339 | /* Load registers to the chip */ | |
1340 | pmz_maybe_update_regs(uap); | |
1341 | } | |
1342 | uart_update_timeout(port, termios->c_cflag, baud); | |
1343 | ||
1344 | pmz_debug("pmz: set_termios() done.\n"); | |
1345 | } | |
1346 | ||
1347 | /* The port lock is not held. */ | |
606d099c AC |
1348 | static void pmz_set_termios(struct uart_port *port, struct ktermios *termios, |
1349 | struct ktermios *old) | |
1da177e4 LT |
1350 | { |
1351 | struct uart_pmac_port *uap = to_pmz(port); | |
1352 | unsigned long flags; | |
1353 | ||
1354 | spin_lock_irqsave(&port->lock, flags); | |
1355 | ||
1356 | /* Disable IRQs on the port */ | |
1357 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
1358 | write_zsreg(uap, R1, uap->curregs[R1]); | |
1359 | ||
1360 | /* Setup new port configuration */ | |
1361 | __pmz_set_termios(port, termios, old); | |
1362 | ||
1363 | /* Re-enable IRQs on the port */ | |
1364 | if (ZS_IS_OPEN(uap)) { | |
1365 | uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; | |
1366 | if (!ZS_IS_EXTCLK(uap)) | |
1367 | uap->curregs[R1] |= EXT_INT_ENAB; | |
1368 | write_zsreg(uap, R1, uap->curregs[R1]); | |
1369 | } | |
1370 | spin_unlock_irqrestore(&port->lock, flags); | |
1371 | } | |
1372 | ||
1373 | static const char *pmz_type(struct uart_port *port) | |
1374 | { | |
1375 | struct uart_pmac_port *uap = to_pmz(port); | |
1376 | ||
1377 | if (ZS_IS_IRDA(uap)) | |
1378 | return "Z85c30 ESCC - Infrared port"; | |
1379 | else if (ZS_IS_INTMODEM(uap)) | |
1380 | return "Z85c30 ESCC - Internal modem"; | |
1381 | return "Z85c30 ESCC - Serial port"; | |
1382 | } | |
1383 | ||
1384 | /* We do not request/release mappings of the registers here, this | |
1385 | * happens at early serial probe time. | |
1386 | */ | |
1387 | static void pmz_release_port(struct uart_port *port) | |
1388 | { | |
1389 | } | |
1390 | ||
1391 | static int pmz_request_port(struct uart_port *port) | |
1392 | { | |
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | /* These do not need to do anything interesting either. */ | |
1397 | static void pmz_config_port(struct uart_port *port, int flags) | |
1398 | { | |
1399 | } | |
1400 | ||
1401 | /* We do not support letting the user mess with the divisor, IRQ, etc. */ | |
1402 | static int pmz_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1403 | { | |
1404 | return -EINVAL; | |
1405 | } | |
1406 | ||
8c653186 CA |
1407 | #ifdef CONFIG_CONSOLE_POLL |
1408 | ||
1409 | static int pmz_poll_get_char(struct uart_port *port) | |
1410 | { | |
1411 | struct uart_pmac_port *uap = (struct uart_pmac_port *)port; | |
1412 | ||
1413 | while ((read_zsreg(uap, R0) & Rx_CH_AV) == 0) | |
1414 | udelay(5); | |
1415 | return read_zsdata(uap); | |
1416 | } | |
1417 | ||
1418 | static void pmz_poll_put_char(struct uart_port *port, unsigned char c) | |
1419 | { | |
1420 | struct uart_pmac_port *uap = (struct uart_pmac_port *)port; | |
1421 | ||
1422 | /* Wait for the transmit buffer to empty. */ | |
1423 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) | |
1424 | udelay(5); | |
1425 | write_zsdata(uap, c); | |
1426 | } | |
1427 | ||
ec9cbe09 | 1428 | #endif /* CONFIG_CONSOLE_POLL */ |
8c653186 | 1429 | |
1da177e4 LT |
1430 | static struct uart_ops pmz_pops = { |
1431 | .tx_empty = pmz_tx_empty, | |
1432 | .set_mctrl = pmz_set_mctrl, | |
1433 | .get_mctrl = pmz_get_mctrl, | |
1434 | .stop_tx = pmz_stop_tx, | |
1435 | .start_tx = pmz_start_tx, | |
1436 | .stop_rx = pmz_stop_rx, | |
1437 | .enable_ms = pmz_enable_ms, | |
1438 | .break_ctl = pmz_break_ctl, | |
1439 | .startup = pmz_startup, | |
1440 | .shutdown = pmz_shutdown, | |
1441 | .set_termios = pmz_set_termios, | |
1442 | .type = pmz_type, | |
1443 | .release_port = pmz_release_port, | |
1444 | .request_port = pmz_request_port, | |
1445 | .config_port = pmz_config_port, | |
1446 | .verify_port = pmz_verify_port, | |
8c653186 CA |
1447 | #ifdef CONFIG_CONSOLE_POLL |
1448 | .poll_get_char = pmz_poll_get_char, | |
1449 | .poll_put_char = pmz_poll_put_char, | |
1450 | #endif | |
1da177e4 LT |
1451 | }; |
1452 | ||
ec9cbe09 FT |
1453 | #ifdef CONFIG_PPC_PMAC |
1454 | ||
1da177e4 LT |
1455 | /* |
1456 | * Setup one port structure after probing, HW is down at this point, | |
1457 | * Unlike sunzilog, we don't need to pre-init the spinlock as we don't | |
1458 | * register our console before uart_add_one_port() is called | |
1459 | */ | |
1460 | static int __init pmz_init_port(struct uart_pmac_port *uap) | |
1461 | { | |
1462 | struct device_node *np = uap->node; | |
018a3d1d JK |
1463 | const char *conn; |
1464 | const struct slot_names_prop { | |
1da177e4 LT |
1465 | int count; |
1466 | char name[1]; | |
1467 | } *slots; | |
1468 | int len; | |
cc5d0189 | 1469 | struct resource r_ports, r_rxdma, r_txdma; |
1da177e4 LT |
1470 | |
1471 | /* | |
1472 | * Request & map chip registers | |
1473 | */ | |
cc5d0189 BH |
1474 | if (of_address_to_resource(np, 0, &r_ports)) |
1475 | return -ENODEV; | |
1476 | uap->port.mapbase = r_ports.start; | |
1da177e4 | 1477 | uap->port.membase = ioremap(uap->port.mapbase, 0x1000); |
1f7b5fff | 1478 | |
1da177e4 LT |
1479 | uap->control_reg = uap->port.membase; |
1480 | uap->data_reg = uap->control_reg + 0x10; | |
1481 | ||
1482 | /* | |
1483 | * Request & map DBDMA registers | |
1484 | */ | |
1485 | #ifdef HAS_DBDMA | |
cc5d0189 BH |
1486 | if (of_address_to_resource(np, 1, &r_txdma) == 0 && |
1487 | of_address_to_resource(np, 2, &r_rxdma) == 0) | |
1da177e4 | 1488 | uap->flags |= PMACZILOG_FLAG_HAS_DMA; |
cc5d0189 BH |
1489 | #else |
1490 | memset(&r_txdma, 0, sizeof(struct resource)); | |
1491 | memset(&r_rxdma, 0, sizeof(struct resource)); | |
1da177e4 LT |
1492 | #endif |
1493 | if (ZS_HAS_DMA(uap)) { | |
cc5d0189 | 1494 | uap->tx_dma_regs = ioremap(r_txdma.start, 0x100); |
1da177e4 LT |
1495 | if (uap->tx_dma_regs == NULL) { |
1496 | uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; | |
1497 | goto no_dma; | |
1498 | } | |
cc5d0189 | 1499 | uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100); |
1da177e4 LT |
1500 | if (uap->rx_dma_regs == NULL) { |
1501 | iounmap(uap->tx_dma_regs); | |
1502 | uap->tx_dma_regs = NULL; | |
1503 | uap->flags &= ~PMACZILOG_FLAG_HAS_DMA; | |
1504 | goto no_dma; | |
1505 | } | |
0ebfff14 BH |
1506 | uap->tx_dma_irq = irq_of_parse_and_map(np, 1); |
1507 | uap->rx_dma_irq = irq_of_parse_and_map(np, 2); | |
1da177e4 LT |
1508 | } |
1509 | no_dma: | |
1510 | ||
1511 | /* | |
1512 | * Detect port type | |
1513 | */ | |
55b61fec | 1514 | if (of_device_is_compatible(np, "cobalt")) |
1da177e4 | 1515 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; |
40cd3a45 | 1516 | conn = of_get_property(np, "AAPL,connector", &len); |
1da177e4 LT |
1517 | if (conn && (strcmp(conn, "infrared") == 0)) |
1518 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; | |
1519 | uap->port_type = PMAC_SCC_ASYNC; | |
1520 | /* 1999 Powerbook G3 has slot-names property instead */ | |
40cd3a45 | 1521 | slots = of_get_property(np, "slot-names", &len); |
1da177e4 LT |
1522 | if (slots && slots->count > 0) { |
1523 | if (strcmp(slots->name, "IrDA") == 0) | |
1524 | uap->flags |= PMACZILOG_FLAG_IS_IRDA; | |
1525 | else if (strcmp(slots->name, "Modem") == 0) | |
1526 | uap->flags |= PMACZILOG_FLAG_IS_INTMODEM; | |
1527 | } | |
1528 | if (ZS_IS_IRDA(uap)) | |
1529 | uap->port_type = PMAC_SCC_IRDA; | |
1530 | if (ZS_IS_INTMODEM(uap)) { | |
30686ba6 SR |
1531 | struct device_node* i2c_modem = |
1532 | of_find_node_by_name(NULL, "i2c-modem"); | |
1da177e4 | 1533 | if (i2c_modem) { |
018a3d1d | 1534 | const char* mid = |
40cd3a45 | 1535 | of_get_property(i2c_modem, "modem-id", NULL); |
1da177e4 LT |
1536 | if (mid) switch(*mid) { |
1537 | case 0x04 : | |
1538 | case 0x05 : | |
1539 | case 0x07 : | |
1540 | case 0x08 : | |
1541 | case 0x0b : | |
1542 | case 0x0c : | |
1543 | uap->port_type = PMAC_SCC_I2S1; | |
1544 | } | |
1545 | printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n", | |
1546 | mid ? (*mid) : 0); | |
30686ba6 | 1547 | of_node_put(i2c_modem); |
1da177e4 LT |
1548 | } else { |
1549 | printk(KERN_INFO "pmac_zilog: serial modem detected\n"); | |
1550 | } | |
1551 | } | |
1552 | ||
1553 | /* | |
1554 | * Init remaining bits of "port" structure | |
1555 | */ | |
9b4a1617 | 1556 | uap->port.iotype = UPIO_MEM; |
0ebfff14 | 1557 | uap->port.irq = irq_of_parse_and_map(np, 0); |
1da177e4 LT |
1558 | uap->port.uartclk = ZS_CLOCK; |
1559 | uap->port.fifosize = 1; | |
1560 | uap->port.ops = &pmz_pops; | |
1561 | uap->port.type = PORT_PMAC_ZILOG; | |
1562 | uap->port.flags = 0; | |
1563 | ||
f08b7e9f BH |
1564 | /* |
1565 | * Fixup for the port on Gatwick for which the device-tree has | |
1566 | * missing interrupts. Normally, the macio_dev would contain | |
1567 | * fixed up interrupt info, but we use the device-tree directly | |
1568 | * here due to early probing so we need the fixup too. | |
1569 | */ | |
1570 | if (uap->port.irq == NO_IRQ && | |
1571 | np->parent && np->parent->parent && | |
1572 | of_device_is_compatible(np->parent->parent, "gatwick")) { | |
1573 | /* IRQs on gatwick are offset by 64 */ | |
1574 | uap->port.irq = irq_create_mapping(NULL, 64 + 15); | |
1575 | uap->tx_dma_irq = irq_create_mapping(NULL, 64 + 4); | |
1576 | uap->rx_dma_irq = irq_create_mapping(NULL, 64 + 5); | |
1577 | } | |
1578 | ||
1da177e4 LT |
1579 | /* Setup some valid baud rate information in the register |
1580 | * shadows so we don't write crap there before baud rate is | |
1581 | * first initialized. | |
1582 | */ | |
1583 | pmz_convert_to_zs(uap, CS8, 0, 9600); | |
1584 | ||
1585 | return 0; | |
1586 | } | |
1587 | ||
1588 | /* | |
1589 | * Get rid of a port on module removal | |
1590 | */ | |
1591 | static void pmz_dispose_port(struct uart_pmac_port *uap) | |
1592 | { | |
1593 | struct device_node *np; | |
1594 | ||
1595 | np = uap->node; | |
1596 | iounmap(uap->rx_dma_regs); | |
1597 | iounmap(uap->tx_dma_regs); | |
1598 | iounmap(uap->control_reg); | |
1599 | uap->node = NULL; | |
1600 | of_node_put(np); | |
1601 | memset(uap, 0, sizeof(struct uart_pmac_port)); | |
1602 | } | |
1603 | ||
1604 | /* | |
1f7b5fff | 1605 | * Called upon match with an escc node in the device-tree. |
1da177e4 | 1606 | */ |
5e655772 | 1607 | static int pmz_attach(struct macio_dev *mdev, const struct of_device_id *match) |
1da177e4 LT |
1608 | { |
1609 | int i; | |
1610 | ||
1611 | /* Iterate the pmz_ports array to find a matching entry | |
1612 | */ | |
1613 | for (i = 0; i < MAX_ZS_PORTS; i++) | |
61c7a080 | 1614 | if (pmz_ports[i].node == mdev->ofdev.dev.of_node) { |
1da177e4 LT |
1615 | struct uart_pmac_port *uap = &pmz_ports[i]; |
1616 | ||
1617 | uap->dev = mdev; | |
1618 | dev_set_drvdata(&mdev->ofdev.dev, uap); | |
1619 | if (macio_request_resources(uap->dev, "pmac_zilog")) | |
1620 | printk(KERN_WARNING "%s: Failed to request resource" | |
1621 | ", port still active\n", | |
1622 | uap->node->name); | |
1623 | else | |
1624 | uap->flags |= PMACZILOG_FLAG_RSRC_REQUESTED; | |
1625 | return 0; | |
1626 | } | |
1627 | return -ENODEV; | |
1628 | } | |
1629 | ||
1630 | /* | |
1631 | * That one should not be called, macio isn't really a hotswap device, | |
1632 | * we don't expect one of those serial ports to go away... | |
1633 | */ | |
1634 | static int pmz_detach(struct macio_dev *mdev) | |
1635 | { | |
1636 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); | |
1637 | ||
1638 | if (!uap) | |
1639 | return -ENODEV; | |
1640 | ||
1641 | if (uap->flags & PMACZILOG_FLAG_RSRC_REQUESTED) { | |
1642 | macio_release_resources(uap->dev); | |
1643 | uap->flags &= ~PMACZILOG_FLAG_RSRC_REQUESTED; | |
1644 | } | |
1645 | dev_set_drvdata(&mdev->ofdev.dev, NULL); | |
1646 | uap->dev = NULL; | |
1647 | ||
1648 | return 0; | |
1649 | } | |
1650 | ||
1651 | ||
0370affe | 1652 | static int pmz_suspend(struct macio_dev *mdev, pm_message_t pm_state) |
1da177e4 LT |
1653 | { |
1654 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); | |
1655 | struct uart_state *state; | |
1656 | unsigned long flags; | |
1657 | ||
1658 | if (uap == NULL) { | |
1659 | printk("HRM... pmz_suspend with NULL uap\n"); | |
1660 | return 0; | |
1661 | } | |
1662 | ||
ca078bae | 1663 | if (pm_state.event == mdev->ofdev.dev.power.power_state.event) |
1da177e4 LT |
1664 | return 0; |
1665 | ||
aa015429 | 1666 | pmz_debug("suspend, switching to state %d\n", pm_state.event); |
1da177e4 LT |
1667 | |
1668 | state = pmz_uart_reg.state + uap->port.line; | |
1669 | ||
f392ecfa | 1670 | mutex_lock(&pmz_irq_mutex); |
a2bceae0 | 1671 | mutex_lock(&state->port.mutex); |
1da177e4 LT |
1672 | |
1673 | spin_lock_irqsave(&uap->port.lock, flags); | |
1674 | ||
1675 | if (ZS_IS_OPEN(uap) || ZS_IS_CONS(uap)) { | |
1676 | /* Disable receiver and transmitter. */ | |
1677 | uap->curregs[R3] &= ~RxENABLE; | |
1678 | uap->curregs[R5] &= ~TxENABLE; | |
1679 | ||
1680 | /* Disable all interrupts and BRK assertion. */ | |
1681 | uap->curregs[R1] &= ~(EXT_INT_ENAB | TxINT_ENAB | RxINT_MASK); | |
1682 | uap->curregs[R5] &= ~SND_BRK; | |
1683 | pmz_load_zsregs(uap, uap->curregs); | |
1684 | uap->flags |= PMACZILOG_FLAG_IS_ASLEEP; | |
1685 | mb(); | |
1686 | } | |
1687 | ||
1688 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1689 | ||
1690 | if (ZS_IS_OPEN(uap) || ZS_IS_OPEN(uap->mate)) | |
1691 | if (ZS_IS_ASLEEP(uap->mate) && ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { | |
1692 | pmz_get_port_A(uap)->flags &= ~PMACZILOG_FLAG_IS_IRQ_ON; | |
1693 | disable_irq(uap->port.irq); | |
1694 | } | |
1695 | ||
1696 | if (ZS_IS_CONS(uap)) | |
1697 | uap->port.cons->flags &= ~CON_ENABLED; | |
1698 | ||
1699 | /* Shut the chip down */ | |
1700 | pmz_set_scc_power(uap, 0); | |
1701 | ||
a2bceae0 | 1702 | mutex_unlock(&state->port.mutex); |
f392ecfa | 1703 | mutex_unlock(&pmz_irq_mutex); |
1da177e4 LT |
1704 | |
1705 | pmz_debug("suspend, switching complete\n"); | |
1706 | ||
1707 | mdev->ofdev.dev.power.power_state = pm_state; | |
1708 | ||
1709 | return 0; | |
1710 | } | |
1711 | ||
1712 | ||
1713 | static int pmz_resume(struct macio_dev *mdev) | |
1714 | { | |
1715 | struct uart_pmac_port *uap = dev_get_drvdata(&mdev->ofdev.dev); | |
1716 | struct uart_state *state; | |
1717 | unsigned long flags; | |
1718 | int pwr_delay = 0; | |
1719 | ||
1720 | if (uap == NULL) | |
1721 | return 0; | |
1722 | ||
ca078bae | 1723 | if (mdev->ofdev.dev.power.power_state.event == PM_EVENT_ON) |
1da177e4 LT |
1724 | return 0; |
1725 | ||
1726 | pmz_debug("resume, switching to state 0\n"); | |
1727 | ||
1728 | state = pmz_uart_reg.state + uap->port.line; | |
1729 | ||
f392ecfa | 1730 | mutex_lock(&pmz_irq_mutex); |
a2bceae0 | 1731 | mutex_lock(&state->port.mutex); |
1da177e4 LT |
1732 | |
1733 | spin_lock_irqsave(&uap->port.lock, flags); | |
1734 | if (!ZS_IS_OPEN(uap) && !ZS_IS_CONS(uap)) { | |
1735 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1736 | goto bail; | |
1737 | } | |
1738 | pwr_delay = __pmz_startup(uap); | |
1739 | ||
1740 | /* Take care of config that may have changed while asleep */ | |
1741 | __pmz_set_termios(&uap->port, &uap->termios_cache, NULL); | |
1742 | ||
1743 | if (ZS_IS_OPEN(uap)) { | |
1744 | /* Enable interrupts */ | |
1745 | uap->curregs[R1] |= INT_ALL_Rx | TxINT_ENAB; | |
1746 | if (!ZS_IS_EXTCLK(uap)) | |
1747 | uap->curregs[R1] |= EXT_INT_ENAB; | |
1748 | write_zsreg(uap, R1, uap->curregs[R1]); | |
1749 | } | |
1750 | ||
1751 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
1752 | ||
1753 | if (ZS_IS_CONS(uap)) | |
1754 | uap->port.cons->flags |= CON_ENABLED; | |
1755 | ||
1756 | /* Re-enable IRQ on the controller */ | |
1757 | if (ZS_IS_OPEN(uap) && !ZS_IS_IRQ_ON(pmz_get_port_A(uap))) { | |
1758 | pmz_get_port_A(uap)->flags |= PMACZILOG_FLAG_IS_IRQ_ON; | |
1759 | enable_irq(uap->port.irq); | |
1760 | } | |
1761 | ||
1762 | bail: | |
a2bceae0 | 1763 | mutex_unlock(&state->port.mutex); |
f392ecfa | 1764 | mutex_unlock(&pmz_irq_mutex); |
1da177e4 LT |
1765 | |
1766 | /* Right now, we deal with delay by blocking here, I'll be | |
1767 | * smarter later on | |
1768 | */ | |
1769 | if (pwr_delay != 0) { | |
1770 | pmz_debug("pmz: delaying %d ms\n", pwr_delay); | |
1771 | msleep(pwr_delay); | |
1772 | } | |
1773 | ||
1774 | pmz_debug("resume, switching complete\n"); | |
1775 | ||
ca078bae | 1776 | mdev->ofdev.dev.power.power_state.event = PM_EVENT_ON; |
1da177e4 LT |
1777 | |
1778 | return 0; | |
1779 | } | |
1780 | ||
1781 | /* | |
1782 | * Probe all ports in the system and build the ports array, we register | |
1783 | * with the serial layer at this point, the macio-type probing is only | |
1784 | * used later to "attach" to the sysfs tree so we get power management | |
1785 | * events | |
1786 | */ | |
1787 | static int __init pmz_probe(void) | |
1788 | { | |
1789 | struct device_node *node_p, *node_a, *node_b, *np; | |
1790 | int count = 0; | |
1791 | int rc; | |
1792 | ||
1793 | /* | |
1794 | * Find all escc chips in the system | |
1795 | */ | |
1796 | node_p = of_find_node_by_name(NULL, "escc"); | |
1797 | while (node_p) { | |
1798 | /* | |
1799 | * First get channel A/B node pointers | |
1800 | * | |
1801 | * TODO: Add routines with proper locking to do that... | |
1802 | */ | |
1803 | node_a = node_b = NULL; | |
1804 | for (np = NULL; (np = of_get_next_child(node_p, np)) != NULL;) { | |
1805 | if (strncmp(np->name, "ch-a", 4) == 0) | |
1806 | node_a = of_node_get(np); | |
1807 | else if (strncmp(np->name, "ch-b", 4) == 0) | |
1808 | node_b = of_node_get(np); | |
1809 | } | |
1810 | if (!node_a && !node_b) { | |
1811 | of_node_put(node_a); | |
1812 | of_node_put(node_b); | |
1813 | printk(KERN_ERR "pmac_zilog: missing node %c for escc %s\n", | |
1814 | (!node_a) ? 'a' : 'b', node_p->full_name); | |
1815 | goto next; | |
1816 | } | |
1817 | ||
1818 | /* | |
1819 | * Fill basic fields in the port structures | |
1820 | */ | |
1821 | pmz_ports[count].mate = &pmz_ports[count+1]; | |
1822 | pmz_ports[count+1].mate = &pmz_ports[count]; | |
1823 | pmz_ports[count].flags = PMACZILOG_FLAG_IS_CHANNEL_A; | |
1824 | pmz_ports[count].node = node_a; | |
1825 | pmz_ports[count+1].node = node_b; | |
1826 | pmz_ports[count].port.line = count; | |
1f7b5fff | 1827 | pmz_ports[count+1].port.line = count+1; |
1da177e4 LT |
1828 | |
1829 | /* | |
1830 | * Setup the ports for real | |
1831 | */ | |
1832 | rc = pmz_init_port(&pmz_ports[count]); | |
1833 | if (rc == 0 && node_b != NULL) | |
1834 | rc = pmz_init_port(&pmz_ports[count+1]); | |
1835 | if (rc != 0) { | |
1836 | of_node_put(node_a); | |
1837 | of_node_put(node_b); | |
1838 | memset(&pmz_ports[count], 0, sizeof(struct uart_pmac_port)); | |
1839 | memset(&pmz_ports[count+1], 0, sizeof(struct uart_pmac_port)); | |
1840 | goto next; | |
1841 | } | |
1842 | count += 2; | |
1843 | next: | |
1844 | node_p = of_find_node_by_name(node_p, "escc"); | |
1845 | } | |
1846 | pmz_ports_count = count; | |
1847 | ||
1848 | return 0; | |
1849 | } | |
1850 | ||
ec9cbe09 FT |
1851 | #else |
1852 | ||
1853 | extern struct platform_device scc_a_pdev, scc_b_pdev; | |
1854 | ||
1855 | static int __init pmz_init_port(struct uart_pmac_port *uap) | |
1856 | { | |
1857 | struct resource *r_ports; | |
1858 | int irq; | |
1859 | ||
1860 | r_ports = platform_get_resource(uap->node, IORESOURCE_MEM, 0); | |
1861 | irq = platform_get_irq(uap->node, 0); | |
1862 | if (!r_ports || !irq) | |
1863 | return -ENODEV; | |
1864 | ||
1865 | uap->port.mapbase = r_ports->start; | |
1866 | uap->port.membase = (unsigned char __iomem *) r_ports->start; | |
1867 | uap->port.iotype = UPIO_MEM; | |
1868 | uap->port.irq = irq; | |
1869 | uap->port.uartclk = ZS_CLOCK; | |
1870 | uap->port.fifosize = 1; | |
1871 | uap->port.ops = &pmz_pops; | |
1872 | uap->port.type = PORT_PMAC_ZILOG; | |
1873 | uap->port.flags = 0; | |
1874 | ||
1875 | uap->control_reg = uap->port.membase; | |
1876 | uap->data_reg = uap->control_reg + 4; | |
1877 | uap->port_type = 0; | |
1878 | ||
1879 | pmz_convert_to_zs(uap, CS8, 0, 9600); | |
1880 | ||
1881 | return 0; | |
1882 | } | |
1883 | ||
1884 | static int __init pmz_probe(void) | |
1885 | { | |
1886 | int err; | |
1887 | ||
1888 | pmz_ports_count = 0; | |
1889 | ||
1890 | pmz_ports[0].mate = &pmz_ports[1]; | |
1891 | pmz_ports[0].port.line = 0; | |
1892 | pmz_ports[0].flags = PMACZILOG_FLAG_IS_CHANNEL_A; | |
1893 | pmz_ports[0].node = &scc_a_pdev; | |
1894 | err = pmz_init_port(&pmz_ports[0]); | |
1895 | if (err) | |
1896 | return err; | |
1897 | pmz_ports_count++; | |
1898 | ||
1899 | pmz_ports[1].mate = &pmz_ports[0]; | |
1900 | pmz_ports[1].port.line = 1; | |
1901 | pmz_ports[1].flags = 0; | |
1902 | pmz_ports[1].node = &scc_b_pdev; | |
1903 | err = pmz_init_port(&pmz_ports[1]); | |
1904 | if (err) | |
1905 | return err; | |
1906 | pmz_ports_count++; | |
1907 | ||
1908 | return 0; | |
1909 | } | |
1910 | ||
1911 | static void pmz_dispose_port(struct uart_pmac_port *uap) | |
1912 | { | |
1913 | memset(uap, 0, sizeof(struct uart_pmac_port)); | |
1914 | } | |
1915 | ||
1916 | static int __init pmz_attach(struct platform_device *pdev) | |
1917 | { | |
1918 | int i; | |
1919 | ||
1920 | for (i = 0; i < pmz_ports_count; i++) | |
1921 | if (pmz_ports[i].node == pdev) | |
1922 | return 0; | |
1923 | return -ENODEV; | |
1924 | } | |
1925 | ||
1926 | static int __exit pmz_detach(struct platform_device *pdev) | |
1927 | { | |
1928 | return 0; | |
1929 | } | |
1930 | ||
1931 | #endif /* !CONFIG_PPC_PMAC */ | |
1932 | ||
1da177e4 LT |
1933 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE |
1934 | ||
1935 | static void pmz_console_write(struct console *con, const char *s, unsigned int count); | |
1936 | static int __init pmz_console_setup(struct console *co, char *options); | |
1937 | ||
1938 | static struct console pmz_console = { | |
e4533b24 | 1939 | .name = PMACZILOG_NAME, |
1da177e4 LT |
1940 | .write = pmz_console_write, |
1941 | .device = uart_console_device, | |
1942 | .setup = pmz_console_setup, | |
1943 | .flags = CON_PRINTBUFFER, | |
1944 | .index = -1, | |
1945 | .data = &pmz_uart_reg, | |
1946 | }; | |
1947 | ||
1948 | #define PMACZILOG_CONSOLE &pmz_console | |
1949 | #else /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ | |
1950 | #define PMACZILOG_CONSOLE (NULL) | |
1951 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ | |
1952 | ||
1953 | /* | |
1954 | * Register the driver, console driver and ports with the serial | |
1955 | * core | |
1956 | */ | |
1957 | static int __init pmz_register(void) | |
1958 | { | |
1959 | int i, rc; | |
1960 | ||
1961 | pmz_uart_reg.nr = pmz_ports_count; | |
1962 | pmz_uart_reg.cons = PMACZILOG_CONSOLE; | |
1da177e4 LT |
1963 | |
1964 | /* | |
1965 | * Register this driver with the serial core | |
1966 | */ | |
1967 | rc = uart_register_driver(&pmz_uart_reg); | |
1968 | if (rc) | |
1969 | return rc; | |
1970 | ||
1971 | /* | |
1972 | * Register each port with the serial core | |
1973 | */ | |
1974 | for (i = 0; i < pmz_ports_count; i++) { | |
1975 | struct uart_pmac_port *uport = &pmz_ports[i]; | |
1976 | /* NULL node may happen on wallstreet */ | |
1977 | if (uport->node != NULL) | |
1978 | rc = uart_add_one_port(&pmz_uart_reg, &uport->port); | |
1979 | if (rc) | |
1980 | goto err_out; | |
1981 | } | |
1982 | ||
1983 | return 0; | |
1984 | err_out: | |
1985 | while (i-- > 0) { | |
1986 | struct uart_pmac_port *uport = &pmz_ports[i]; | |
1987 | uart_remove_one_port(&pmz_uart_reg, &uport->port); | |
1988 | } | |
1989 | uart_unregister_driver(&pmz_uart_reg); | |
1990 | return rc; | |
1991 | } | |
1992 | ||
ec9cbe09 FT |
1993 | #ifdef CONFIG_PPC_PMAC |
1994 | ||
5e655772 | 1995 | static struct of_device_id pmz_match[] = |
1da177e4 LT |
1996 | { |
1997 | { | |
1f7b5fff | 1998 | .name = "ch-a", |
1da177e4 LT |
1999 | }, |
2000 | { | |
1f7b5fff | 2001 | .name = "ch-b", |
1da177e4 LT |
2002 | }, |
2003 | {}, | |
2004 | }; | |
5e655772 | 2005 | MODULE_DEVICE_TABLE (of, pmz_match); |
1da177e4 | 2006 | |
1f7b5fff | 2007 | static struct macio_driver pmz_driver = { |
c2cdf6ab BH |
2008 | .driver = { |
2009 | .name = "pmac_zilog", | |
2010 | .owner = THIS_MODULE, | |
2011 | .of_match_table = pmz_match, | |
2012 | }, | |
1da177e4 LT |
2013 | .probe = pmz_attach, |
2014 | .remove = pmz_detach, | |
2015 | .suspend = pmz_suspend, | |
1f7b5fff | 2016 | .resume = pmz_resume, |
1da177e4 LT |
2017 | }; |
2018 | ||
ec9cbe09 FT |
2019 | #else |
2020 | ||
2021 | static struct platform_driver pmz_driver = { | |
2022 | .remove = __exit_p(pmz_detach), | |
2023 | .driver = { | |
2024 | .name = "scc", | |
2025 | .owner = THIS_MODULE, | |
2026 | }, | |
2027 | }; | |
2028 | ||
2029 | #endif /* !CONFIG_PPC_PMAC */ | |
2030 | ||
1da177e4 LT |
2031 | static int __init init_pmz(void) |
2032 | { | |
2033 | int rc, i; | |
2034 | printk(KERN_INFO "%s\n", version); | |
2035 | ||
2036 | /* | |
2037 | * First, we need to do a direct OF-based probe pass. We | |
2038 | * do that because we want serial console up before the | |
2039 | * macio stuffs calls us back, and since that makes it | |
2040 | * easier to pass the proper number of channels to | |
2041 | * uart_register_driver() | |
2042 | */ | |
2043 | if (pmz_ports_count == 0) | |
2044 | pmz_probe(); | |
2045 | ||
2046 | /* | |
2047 | * Bail early if no port found | |
2048 | */ | |
2049 | if (pmz_ports_count == 0) | |
2050 | return -ENODEV; | |
2051 | ||
2052 | /* | |
2053 | * Now we register with the serial layer | |
2054 | */ | |
2055 | rc = pmz_register(); | |
2056 | if (rc) { | |
2057 | printk(KERN_ERR | |
2058 | "pmac_zilog: Error registering serial device, disabling pmac_zilog.\n" | |
2059 | "pmac_zilog: Did another serial driver already claim the minors?\n"); | |
2060 | /* effectively "pmz_unprobe()" */ | |
2061 | for (i=0; i < pmz_ports_count; i++) | |
2062 | pmz_dispose_port(&pmz_ports[i]); | |
2063 | return rc; | |
2064 | } | |
1f7b5fff | 2065 | |
1da177e4 LT |
2066 | /* |
2067 | * Then we register the macio driver itself | |
2068 | */ | |
ec9cbe09 | 2069 | #ifdef CONFIG_PPC_PMAC |
1da177e4 | 2070 | return macio_register_driver(&pmz_driver); |
ec9cbe09 FT |
2071 | #else |
2072 | return platform_driver_probe(&pmz_driver, pmz_attach); | |
2073 | #endif | |
1da177e4 LT |
2074 | } |
2075 | ||
2076 | static void __exit exit_pmz(void) | |
2077 | { | |
2078 | int i; | |
2079 | ||
ec9cbe09 | 2080 | #ifdef CONFIG_PPC_PMAC |
1da177e4 LT |
2081 | /* Get rid of macio-driver (detach from macio) */ |
2082 | macio_unregister_driver(&pmz_driver); | |
ec9cbe09 FT |
2083 | #else |
2084 | platform_driver_unregister(&pmz_driver); | |
2085 | #endif | |
1da177e4 LT |
2086 | |
2087 | for (i = 0; i < pmz_ports_count; i++) { | |
2088 | struct uart_pmac_port *uport = &pmz_ports[i]; | |
2089 | if (uport->node != NULL) { | |
2090 | uart_remove_one_port(&pmz_uart_reg, &uport->port); | |
2091 | pmz_dispose_port(uport); | |
2092 | } | |
2093 | } | |
2094 | /* Unregister UART driver */ | |
2095 | uart_unregister_driver(&pmz_uart_reg); | |
2096 | } | |
2097 | ||
2098 | #ifdef CONFIG_SERIAL_PMACZILOG_CONSOLE | |
2099 | ||
d358788f RK |
2100 | static void pmz_console_putchar(struct uart_port *port, int ch) |
2101 | { | |
2102 | struct uart_pmac_port *uap = (struct uart_pmac_port *)port; | |
2103 | ||
2104 | /* Wait for the transmit buffer to empty. */ | |
2105 | while ((read_zsreg(uap, R0) & Tx_BUF_EMP) == 0) | |
2106 | udelay(5); | |
2107 | write_zsdata(uap, ch); | |
2108 | } | |
2109 | ||
1da177e4 LT |
2110 | /* |
2111 | * Print a string to the serial port trying not to disturb | |
2112 | * any possible real use of the port... | |
2113 | */ | |
2114 | static void pmz_console_write(struct console *con, const char *s, unsigned int count) | |
2115 | { | |
2116 | struct uart_pmac_port *uap = &pmz_ports[con->index]; | |
2117 | unsigned long flags; | |
1da177e4 LT |
2118 | |
2119 | if (ZS_IS_ASLEEP(uap)) | |
2120 | return; | |
2121 | spin_lock_irqsave(&uap->port.lock, flags); | |
2122 | ||
2123 | /* Turn of interrupts and enable the transmitter. */ | |
2124 | write_zsreg(uap, R1, uap->curregs[1] & ~TxINT_ENAB); | |
2125 | write_zsreg(uap, R5, uap->curregs[5] | TxENABLE | RTS | DTR); | |
2126 | ||
d358788f | 2127 | uart_console_write(&uap->port, s, count, pmz_console_putchar); |
1da177e4 LT |
2128 | |
2129 | /* Restore the values in the registers. */ | |
2130 | write_zsreg(uap, R1, uap->curregs[1]); | |
2131 | /* Don't disable the transmitter. */ | |
2132 | ||
2133 | spin_unlock_irqrestore(&uap->port.lock, flags); | |
2134 | } | |
2135 | ||
2136 | /* | |
2137 | * Setup the serial console | |
2138 | */ | |
2139 | static int __init pmz_console_setup(struct console *co, char *options) | |
2140 | { | |
2141 | struct uart_pmac_port *uap; | |
2142 | struct uart_port *port; | |
2143 | int baud = 38400; | |
2144 | int bits = 8; | |
2145 | int parity = 'n'; | |
2146 | int flow = 'n'; | |
2147 | unsigned long pwr_delay; | |
2148 | ||
2149 | /* | |
2150 | * XServe's default to 57600 bps | |
2151 | */ | |
71a157e8 GL |
2152 | if (of_machine_is_compatible("RackMac1,1") |
2153 | || of_machine_is_compatible("RackMac1,2") | |
2154 | || of_machine_is_compatible("MacRISC4")) | |
1f7b5fff | 2155 | baud = 57600; |
1da177e4 LT |
2156 | |
2157 | /* | |
2158 | * Check whether an invalid uart number has been specified, and | |
2159 | * if so, search for the first available port that does have | |
2160 | * console support. | |
2161 | */ | |
2162 | if (co->index >= pmz_ports_count) | |
2163 | co->index = 0; | |
2164 | uap = &pmz_ports[co->index]; | |
2165 | if (uap->node == NULL) | |
2166 | return -ENODEV; | |
2167 | port = &uap->port; | |
2168 | ||
2169 | /* | |
2170 | * Mark port as beeing a console | |
2171 | */ | |
2172 | uap->flags |= PMACZILOG_FLAG_IS_CONS; | |
2173 | ||
2174 | /* | |
2175 | * Temporary fix for uart layer who didn't setup the spinlock yet | |
2176 | */ | |
2177 | spin_lock_init(&port->lock); | |
2178 | ||
2179 | /* | |
2180 | * Enable the hardware | |
2181 | */ | |
2182 | pwr_delay = __pmz_startup(uap); | |
2183 | if (pwr_delay) | |
2184 | mdelay(pwr_delay); | |
2185 | ||
2186 | if (options) | |
2187 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
2188 | ||
2189 | return uart_set_options(port, co, baud, parity, bits, flow); | |
2190 | } | |
2191 | ||
2192 | static int __init pmz_console_init(void) | |
2193 | { | |
2194 | /* Probe ports */ | |
2195 | pmz_probe(); | |
2196 | ||
2197 | /* TODO: Autoprobe console based on OF */ | |
2198 | /* pmz_console.index = i; */ | |
2199 | register_console(&pmz_console); | |
2200 | ||
2201 | return 0; | |
2202 | ||
2203 | } | |
2204 | console_initcall(pmz_console_init); | |
2205 | #endif /* CONFIG_SERIAL_PMACZILOG_CONSOLE */ | |
2206 | ||
2207 | module_init(init_pmz); | |
2208 | module_exit(exit_pmz); |