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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * drivers/serial/mpsc.c | |
3 | * | |
4 | * Generic driver for the MPSC (UART mode) on Marvell parts (e.g., GT64240, | |
5 | * GT64260, MV64340, MV64360, GT96100, ... ). | |
6 | * | |
7 | * Author: Mark A. Greer <mgreer@mvista.com> | |
8 | * | |
9 | * Based on an old MPSC driver that was in the linuxppc tree. It appears to | |
10 | * have been created by Chris Zankel (formerly of MontaVista) but there | |
11 | * is no proper Copyright so I'm not sure. Apparently, parts were also | |
12 | * taken from PPCBoot (now U-Boot). Also based on drivers/serial/8250.c | |
13 | * by Russell King. | |
14 | * | |
15 | * 2004 (c) MontaVista, Software, Inc. This file is licensed under | |
16 | * the terms of the GNU General Public License version 2. This program | |
17 | * is licensed "as is" without any warranty of any kind, whether express | |
18 | * or implied. | |
19 | */ | |
20 | /* | |
21 | * The MPSC interface is much like a typical network controller's interface. | |
22 | * That is, you set up separate rings of descriptors for transmitting and | |
23 | * receiving data. There is also a pool of buffers with (one buffer per | |
24 | * descriptor) that incoming data are dma'd into or outgoing data are dma'd | |
25 | * out of. | |
26 | * | |
27 | * The MPSC requires two other controllers to be able to work. The Baud Rate | |
28 | * Generator (BRG) provides a clock at programmable frequencies which determines | |
29 | * the baud rate. The Serial DMA Controller (SDMA) takes incoming data from the | |
30 | * MPSC and DMA's it into memory or DMA's outgoing data and passes it to the | |
31 | * MPSC. It is actually the SDMA interrupt that the driver uses to keep the | |
32 | * transmit and receive "engines" going (i.e., indicate data has been | |
33 | * transmitted or received). | |
34 | * | |
35 | * NOTES: | |
36 | * | |
37 | * 1) Some chips have an erratum where several regs cannot be | |
38 | * read. To work around that, we keep a local copy of those regs in | |
39 | * 'mpsc_port_info'. | |
40 | * | |
41 | * 2) Some chips have an erratum where the ctlr will hang when the SDMA ctlr | |
42 | * accesses system mem with coherency enabled. For that reason, the driver | |
43 | * assumes that coherency for that ctlr has been disabled. This means | |
44 | * that when in a cache coherent system, the driver has to manually manage | |
45 | * the data cache on the areas that it touches because the dma_* macro are | |
46 | * basically no-ops. | |
47 | * | |
48 | * 3) There is an erratum (on PPC) where you can't use the instruction to do | |
49 | * a DMA_TO_DEVICE/cache clean so DMA_BIDIRECTIONAL/flushes are used in places | |
50 | * where a DMA_TO_DEVICE/clean would have [otherwise] sufficed. | |
51 | * | |
52 | * 4) AFAICT, hardware flow control isn't supported by the controller --MAG. | |
53 | */ | |
54 | ||
55 | #include "mpsc.h" | |
56 | ||
57 | /* | |
58 | * Define how this driver is known to the outside (we've been assigned a | |
59 | * range on the "Low-density serial ports" major). | |
60 | */ | |
61 | #define MPSC_MAJOR 204 | |
62 | #define MPSC_MINOR_START 44 | |
63 | #define MPSC_DRIVER_NAME "MPSC" | |
64 | #define MPSC_DEVFS_NAME "ttymm/" | |
65 | #define MPSC_DEV_NAME "ttyMM" | |
66 | #define MPSC_VERSION "1.00" | |
67 | ||
68 | static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS]; | |
69 | static struct mpsc_shared_regs mpsc_shared_regs; | |
70 | ||
71 | /* | |
72 | ****************************************************************************** | |
73 | * | |
74 | * Baud Rate Generator Routines (BRG) | |
75 | * | |
76 | ****************************************************************************** | |
77 | */ | |
78 | static void | |
79 | mpsc_brg_init(struct mpsc_port_info *pi, u32 clk_src) | |
80 | { | |
81 | u32 v; | |
82 | ||
83 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
84 | v = (v & ~(0xf << 18)) | ((clk_src & 0xf) << 18); | |
85 | ||
86 | if (pi->brg_can_tune) | |
87 | v &= ~(1 << 25); | |
88 | ||
89 | if (pi->mirror_regs) | |
90 | pi->BRG_BCR_m = v; | |
91 | writel(v, pi->brg_base + BRG_BCR); | |
92 | ||
93 | writel(readl(pi->brg_base + BRG_BTR) & 0xffff0000, | |
94 | pi->brg_base + BRG_BTR); | |
95 | return; | |
96 | } | |
97 | ||
98 | static void | |
99 | mpsc_brg_enable(struct mpsc_port_info *pi) | |
100 | { | |
101 | u32 v; | |
102 | ||
103 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
104 | v |= (1 << 16); | |
105 | ||
106 | if (pi->mirror_regs) | |
107 | pi->BRG_BCR_m = v; | |
108 | writel(v, pi->brg_base + BRG_BCR); | |
109 | return; | |
110 | } | |
111 | ||
112 | static void | |
113 | mpsc_brg_disable(struct mpsc_port_info *pi) | |
114 | { | |
115 | u32 v; | |
116 | ||
117 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
118 | v &= ~(1 << 16); | |
119 | ||
120 | if (pi->mirror_regs) | |
121 | pi->BRG_BCR_m = v; | |
122 | writel(v, pi->brg_base + BRG_BCR); | |
123 | return; | |
124 | } | |
125 | ||
126 | static inline void | |
127 | mpsc_set_baudrate(struct mpsc_port_info *pi, u32 baud) | |
128 | { | |
129 | /* | |
130 | * To set the baud, we adjust the CDV field in the BRG_BCR reg. | |
131 | * From manual: Baud = clk / ((CDV+1)*2) ==> CDV = (clk / (baud*2)) - 1. | |
132 | * However, the input clock is divided by 16 in the MPSC b/c of how | |
133 | * 'MPSC_MMCRH' was set up so we have to divide the 'clk' used in our | |
134 | * calculation by 16 to account for that. So the real calculation | |
135 | * that accounts for the way the mpsc is set up is: | |
136 | * CDV = (clk / (baud*2*16)) - 1 ==> CDV = (clk / (baud << 5)) - 1. | |
137 | */ | |
138 | u32 cdv = (pi->port.uartclk / (baud << 5)) - 1; | |
139 | u32 v; | |
140 | ||
141 | mpsc_brg_disable(pi); | |
142 | v = (pi->mirror_regs) ? pi->BRG_BCR_m : readl(pi->brg_base + BRG_BCR); | |
143 | v = (v & 0xffff0000) | (cdv & 0xffff); | |
144 | ||
145 | if (pi->mirror_regs) | |
146 | pi->BRG_BCR_m = v; | |
147 | writel(v, pi->brg_base + BRG_BCR); | |
148 | mpsc_brg_enable(pi); | |
149 | ||
150 | return; | |
151 | } | |
152 | ||
153 | /* | |
154 | ****************************************************************************** | |
155 | * | |
156 | * Serial DMA Routines (SDMA) | |
157 | * | |
158 | ****************************************************************************** | |
159 | */ | |
160 | ||
161 | static void | |
162 | mpsc_sdma_burstsize(struct mpsc_port_info *pi, u32 burst_size) | |
163 | { | |
164 | u32 v; | |
165 | ||
166 | pr_debug("mpsc_sdma_burstsize[%d]: burst_size: %d\n", | |
167 | pi->port.line, burst_size); | |
168 | ||
169 | burst_size >>= 3; /* Divide by 8 b/c reg values are 8-byte chunks */ | |
170 | ||
171 | if (burst_size < 2) | |
172 | v = 0x0; /* 1 64-bit word */ | |
173 | else if (burst_size < 4) | |
174 | v = 0x1; /* 2 64-bit words */ | |
175 | else if (burst_size < 8) | |
176 | v = 0x2; /* 4 64-bit words */ | |
177 | else | |
178 | v = 0x3; /* 8 64-bit words */ | |
179 | ||
180 | writel((readl(pi->sdma_base + SDMA_SDC) & (0x3 << 12)) | (v << 12), | |
181 | pi->sdma_base + SDMA_SDC); | |
182 | return; | |
183 | } | |
184 | ||
185 | static void | |
186 | mpsc_sdma_init(struct mpsc_port_info *pi, u32 burst_size) | |
187 | { | |
188 | pr_debug("mpsc_sdma_init[%d]: burst_size: %d\n", pi->port.line, | |
189 | burst_size); | |
190 | ||
191 | writel((readl(pi->sdma_base + SDMA_SDC) & 0x3ff) | 0x03f, | |
192 | pi->sdma_base + SDMA_SDC); | |
193 | mpsc_sdma_burstsize(pi, burst_size); | |
194 | return; | |
195 | } | |
196 | ||
197 | static inline u32 | |
198 | mpsc_sdma_intr_mask(struct mpsc_port_info *pi, u32 mask) | |
199 | { | |
200 | u32 old, v; | |
201 | ||
202 | pr_debug("mpsc_sdma_intr_mask[%d]: mask: 0x%x\n", pi->port.line, mask); | |
203 | ||
204 | old = v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : | |
205 | readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
206 | ||
207 | mask &= 0xf; | |
208 | if (pi->port.line) | |
209 | mask <<= 8; | |
210 | v &= ~mask; | |
211 | ||
212 | if (pi->mirror_regs) | |
213 | pi->shared_regs->SDMA_INTR_MASK_m = v; | |
214 | writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
215 | ||
216 | if (pi->port.line) | |
217 | old >>= 8; | |
218 | return old & 0xf; | |
219 | } | |
220 | ||
221 | static inline void | |
222 | mpsc_sdma_intr_unmask(struct mpsc_port_info *pi, u32 mask) | |
223 | { | |
224 | u32 v; | |
225 | ||
226 | pr_debug("mpsc_sdma_intr_unmask[%d]: mask: 0x%x\n", pi->port.line,mask); | |
227 | ||
228 | v = (pi->mirror_regs) ? pi->shared_regs->SDMA_INTR_MASK_m : | |
229 | readl(pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
230 | ||
231 | mask &= 0xf; | |
232 | if (pi->port.line) | |
233 | mask <<= 8; | |
234 | v |= mask; | |
235 | ||
236 | if (pi->mirror_regs) | |
237 | pi->shared_regs->SDMA_INTR_MASK_m = v; | |
238 | writel(v, pi->shared_regs->sdma_intr_base + SDMA_INTR_MASK); | |
239 | return; | |
240 | } | |
241 | ||
242 | static inline void | |
243 | mpsc_sdma_intr_ack(struct mpsc_port_info *pi) | |
244 | { | |
245 | pr_debug("mpsc_sdma_intr_ack[%d]: Acknowledging IRQ\n", pi->port.line); | |
246 | ||
247 | if (pi->mirror_regs) | |
248 | pi->shared_regs->SDMA_INTR_CAUSE_m = 0; | |
249 | writel(0, pi->shared_regs->sdma_intr_base + SDMA_INTR_CAUSE); | |
250 | return; | |
251 | } | |
252 | ||
253 | static inline void | |
254 | mpsc_sdma_set_rx_ring(struct mpsc_port_info *pi, struct mpsc_rx_desc *rxre_p) | |
255 | { | |
256 | pr_debug("mpsc_sdma_set_rx_ring[%d]: rxre_p: 0x%x\n", | |
257 | pi->port.line, (u32) rxre_p); | |
258 | ||
259 | writel((u32)rxre_p, pi->sdma_base + SDMA_SCRDP); | |
260 | return; | |
261 | } | |
262 | ||
263 | static inline void | |
264 | mpsc_sdma_set_tx_ring(struct mpsc_port_info *pi, struct mpsc_tx_desc *txre_p) | |
265 | { | |
266 | writel((u32)txre_p, pi->sdma_base + SDMA_SFTDP); | |
267 | writel((u32)txre_p, pi->sdma_base + SDMA_SCTDP); | |
268 | return; | |
269 | } | |
270 | ||
271 | static inline void | |
272 | mpsc_sdma_cmd(struct mpsc_port_info *pi, u32 val) | |
273 | { | |
274 | u32 v; | |
275 | ||
276 | v = readl(pi->sdma_base + SDMA_SDCM); | |
277 | if (val) | |
278 | v |= val; | |
279 | else | |
280 | v = 0; | |
281 | wmb(); | |
282 | writel(v, pi->sdma_base + SDMA_SDCM); | |
283 | wmb(); | |
284 | return; | |
285 | } | |
286 | ||
287 | static inline uint | |
288 | mpsc_sdma_tx_active(struct mpsc_port_info *pi) | |
289 | { | |
290 | return readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_TXD; | |
291 | } | |
292 | ||
293 | static inline void | |
294 | mpsc_sdma_start_tx(struct mpsc_port_info *pi) | |
295 | { | |
296 | struct mpsc_tx_desc *txre, *txre_p; | |
297 | ||
298 | /* If tx isn't running & there's a desc ready to go, start it */ | |
299 | if (!mpsc_sdma_tx_active(pi)) { | |
300 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
301 | (pi->txr_tail * MPSC_TXRE_SIZE)); | |
302 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); | |
303 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
304 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
305 | invalidate_dcache_range((ulong)txre, | |
306 | (ulong)txre + MPSC_TXRE_SIZE); | |
307 | #endif | |
308 | ||
309 | if (be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O) { | |
310 | txre_p = (struct mpsc_tx_desc *)(pi->txr_p + | |
311 | (pi->txr_tail * | |
312 | MPSC_TXRE_SIZE)); | |
313 | ||
314 | mpsc_sdma_set_tx_ring(pi, txre_p); | |
315 | mpsc_sdma_cmd(pi, SDMA_SDCM_STD | SDMA_SDCM_TXD); | |
316 | } | |
317 | } | |
318 | ||
319 | return; | |
320 | } | |
321 | ||
322 | static inline void | |
323 | mpsc_sdma_stop(struct mpsc_port_info *pi) | |
324 | { | |
325 | pr_debug("mpsc_sdma_stop[%d]: Stopping SDMA\n", pi->port.line); | |
326 | ||
327 | /* Abort any SDMA transfers */ | |
328 | mpsc_sdma_cmd(pi, 0); | |
329 | mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT); | |
330 | ||
331 | /* Clear the SDMA current and first TX and RX pointers */ | |
2c6e7599 AV |
332 | mpsc_sdma_set_tx_ring(pi, NULL); |
333 | mpsc_sdma_set_rx_ring(pi, NULL); | |
1da177e4 LT |
334 | |
335 | /* Disable interrupts */ | |
336 | mpsc_sdma_intr_mask(pi, 0xf); | |
337 | mpsc_sdma_intr_ack(pi); | |
338 | ||
339 | return; | |
340 | } | |
341 | ||
342 | /* | |
343 | ****************************************************************************** | |
344 | * | |
345 | * Multi-Protocol Serial Controller Routines (MPSC) | |
346 | * | |
347 | ****************************************************************************** | |
348 | */ | |
349 | ||
350 | static void | |
351 | mpsc_hw_init(struct mpsc_port_info *pi) | |
352 | { | |
353 | u32 v; | |
354 | ||
355 | pr_debug("mpsc_hw_init[%d]: Initializing hardware\n", pi->port.line); | |
356 | ||
357 | /* Set up clock routing */ | |
358 | if (pi->mirror_regs) { | |
359 | v = pi->shared_regs->MPSC_MRR_m; | |
360 | v &= ~0x1c7; | |
361 | pi->shared_regs->MPSC_MRR_m = v; | |
362 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); | |
363 | ||
364 | v = pi->shared_regs->MPSC_RCRR_m; | |
365 | v = (v & ~0xf0f) | 0x100; | |
366 | pi->shared_regs->MPSC_RCRR_m = v; | |
367 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); | |
368 | ||
369 | v = pi->shared_regs->MPSC_TCRR_m; | |
370 | v = (v & ~0xf0f) | 0x100; | |
371 | pi->shared_regs->MPSC_TCRR_m = v; | |
372 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); | |
373 | } | |
374 | else { | |
375 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_MRR); | |
376 | v &= ~0x1c7; | |
377 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_MRR); | |
378 | ||
379 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_RCRR); | |
380 | v = (v & ~0xf0f) | 0x100; | |
381 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_RCRR); | |
382 | ||
383 | v = readl(pi->shared_regs->mpsc_routing_base + MPSC_TCRR); | |
384 | v = (v & ~0xf0f) | 0x100; | |
385 | writel(v, pi->shared_regs->mpsc_routing_base + MPSC_TCRR); | |
386 | } | |
387 | ||
388 | /* Put MPSC in UART mode & enabel Tx/Rx egines */ | |
389 | writel(0x000004c4, pi->mpsc_base + MPSC_MMCRL); | |
390 | ||
391 | /* No preamble, 16x divider, low-latency, */ | |
392 | writel(0x04400400, pi->mpsc_base + MPSC_MMCRH); | |
393 | ||
394 | if (pi->mirror_regs) { | |
395 | pi->MPSC_CHR_1_m = 0; | |
396 | pi->MPSC_CHR_2_m = 0; | |
397 | } | |
398 | writel(0, pi->mpsc_base + MPSC_CHR_1); | |
399 | writel(0, pi->mpsc_base + MPSC_CHR_2); | |
400 | writel(pi->mpsc_max_idle, pi->mpsc_base + MPSC_CHR_3); | |
401 | writel(0, pi->mpsc_base + MPSC_CHR_4); | |
402 | writel(0, pi->mpsc_base + MPSC_CHR_5); | |
403 | writel(0, pi->mpsc_base + MPSC_CHR_6); | |
404 | writel(0, pi->mpsc_base + MPSC_CHR_7); | |
405 | writel(0, pi->mpsc_base + MPSC_CHR_8); | |
406 | writel(0, pi->mpsc_base + MPSC_CHR_9); | |
407 | writel(0, pi->mpsc_base + MPSC_CHR_10); | |
408 | ||
409 | return; | |
410 | } | |
411 | ||
412 | static inline void | |
413 | mpsc_enter_hunt(struct mpsc_port_info *pi) | |
414 | { | |
415 | pr_debug("mpsc_enter_hunt[%d]: Hunting...\n", pi->port.line); | |
416 | ||
417 | if (pi->mirror_regs) { | |
418 | writel(pi->MPSC_CHR_2_m | MPSC_CHR_2_EH, | |
419 | pi->mpsc_base + MPSC_CHR_2); | |
420 | /* Erratum prevents reading CHR_2 so just delay for a while */ | |
421 | udelay(100); | |
422 | } | |
423 | else { | |
424 | writel(readl(pi->mpsc_base + MPSC_CHR_2) | MPSC_CHR_2_EH, | |
425 | pi->mpsc_base + MPSC_CHR_2); | |
426 | ||
427 | while (readl(pi->mpsc_base + MPSC_CHR_2) & MPSC_CHR_2_EH) | |
428 | udelay(10); | |
429 | } | |
430 | ||
431 | return; | |
432 | } | |
433 | ||
434 | static inline void | |
435 | mpsc_freeze(struct mpsc_port_info *pi) | |
436 | { | |
437 | u32 v; | |
438 | ||
439 | pr_debug("mpsc_freeze[%d]: Freezing\n", pi->port.line); | |
440 | ||
441 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
442 | readl(pi->mpsc_base + MPSC_MPCR); | |
443 | v |= MPSC_MPCR_FRZ; | |
444 | ||
445 | if (pi->mirror_regs) | |
446 | pi->MPSC_MPCR_m = v; | |
447 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
448 | return; | |
449 | } | |
450 | ||
451 | static inline void | |
452 | mpsc_unfreeze(struct mpsc_port_info *pi) | |
453 | { | |
454 | u32 v; | |
455 | ||
456 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
457 | readl(pi->mpsc_base + MPSC_MPCR); | |
458 | v &= ~MPSC_MPCR_FRZ; | |
459 | ||
460 | if (pi->mirror_regs) | |
461 | pi->MPSC_MPCR_m = v; | |
462 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
463 | ||
464 | pr_debug("mpsc_unfreeze[%d]: Unfrozen\n", pi->port.line); | |
465 | return; | |
466 | } | |
467 | ||
468 | static inline void | |
469 | mpsc_set_char_length(struct mpsc_port_info *pi, u32 len) | |
470 | { | |
471 | u32 v; | |
472 | ||
473 | pr_debug("mpsc_set_char_length[%d]: char len: %d\n", pi->port.line,len); | |
474 | ||
475 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
476 | readl(pi->mpsc_base + MPSC_MPCR); | |
477 | v = (v & ~(0x3 << 12)) | ((len & 0x3) << 12); | |
478 | ||
479 | if (pi->mirror_regs) | |
480 | pi->MPSC_MPCR_m = v; | |
481 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
482 | return; | |
483 | } | |
484 | ||
485 | static inline void | |
486 | mpsc_set_stop_bit_length(struct mpsc_port_info *pi, u32 len) | |
487 | { | |
488 | u32 v; | |
489 | ||
490 | pr_debug("mpsc_set_stop_bit_length[%d]: stop bits: %d\n", | |
491 | pi->port.line, len); | |
492 | ||
493 | v = (pi->mirror_regs) ? pi->MPSC_MPCR_m : | |
494 | readl(pi->mpsc_base + MPSC_MPCR); | |
495 | ||
496 | v = (v & ~(1 << 14)) | ((len & 0x1) << 14); | |
497 | ||
498 | if (pi->mirror_regs) | |
499 | pi->MPSC_MPCR_m = v; | |
500 | writel(v, pi->mpsc_base + MPSC_MPCR); | |
501 | return; | |
502 | } | |
503 | ||
504 | static inline void | |
505 | mpsc_set_parity(struct mpsc_port_info *pi, u32 p) | |
506 | { | |
507 | u32 v; | |
508 | ||
509 | pr_debug("mpsc_set_parity[%d]: parity bits: 0x%x\n", pi->port.line, p); | |
510 | ||
511 | v = (pi->mirror_regs) ? pi->MPSC_CHR_2_m : | |
512 | readl(pi->mpsc_base + MPSC_CHR_2); | |
513 | ||
514 | p &= 0x3; | |
515 | v = (v & ~0xc000c) | (p << 18) | (p << 2); | |
516 | ||
517 | if (pi->mirror_regs) | |
518 | pi->MPSC_CHR_2_m = v; | |
519 | writel(v, pi->mpsc_base + MPSC_CHR_2); | |
520 | return; | |
521 | } | |
522 | ||
523 | /* | |
524 | ****************************************************************************** | |
525 | * | |
526 | * Driver Init Routines | |
527 | * | |
528 | ****************************************************************************** | |
529 | */ | |
530 | ||
531 | static void | |
532 | mpsc_init_hw(struct mpsc_port_info *pi) | |
533 | { | |
534 | pr_debug("mpsc_init_hw[%d]: Initializing\n", pi->port.line); | |
535 | ||
536 | mpsc_brg_init(pi, pi->brg_clk_src); | |
537 | mpsc_brg_enable(pi); | |
538 | mpsc_sdma_init(pi, dma_get_cache_alignment()); /* burst a cacheline */ | |
539 | mpsc_sdma_stop(pi); | |
540 | mpsc_hw_init(pi); | |
541 | ||
542 | return; | |
543 | } | |
544 | ||
545 | static int | |
546 | mpsc_alloc_ring_mem(struct mpsc_port_info *pi) | |
547 | { | |
548 | int rc = 0; | |
549 | static void mpsc_free_ring_mem(struct mpsc_port_info *pi); | |
550 | ||
551 | pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n", | |
552 | pi->port.line); | |
553 | ||
554 | if (!pi->dma_region) { | |
555 | if (!dma_supported(pi->port.dev, 0xffffffff)) { | |
556 | printk(KERN_ERR "MPSC: Inadequate DMA support\n"); | |
557 | rc = -ENXIO; | |
558 | } | |
559 | else if ((pi->dma_region = dma_alloc_noncoherent(pi->port.dev, | |
560 | MPSC_DMA_ALLOC_SIZE, &pi->dma_region_p, GFP_KERNEL)) | |
561 | == NULL) { | |
562 | ||
563 | printk(KERN_ERR "MPSC: Can't alloc Desc region\n"); | |
564 | rc = -ENOMEM; | |
565 | } | |
566 | } | |
567 | ||
568 | return rc; | |
569 | } | |
570 | ||
571 | static void | |
572 | mpsc_free_ring_mem(struct mpsc_port_info *pi) | |
573 | { | |
574 | pr_debug("mpsc_free_ring_mem[%d]: Freeing ring mem\n", pi->port.line); | |
575 | ||
576 | if (pi->dma_region) { | |
577 | dma_free_noncoherent(pi->port.dev, MPSC_DMA_ALLOC_SIZE, | |
578 | pi->dma_region, pi->dma_region_p); | |
579 | pi->dma_region = NULL; | |
580 | pi->dma_region_p = (dma_addr_t) NULL; | |
581 | } | |
582 | ||
583 | return; | |
584 | } | |
585 | ||
586 | static void | |
587 | mpsc_init_rings(struct mpsc_port_info *pi) | |
588 | { | |
589 | struct mpsc_rx_desc *rxre; | |
590 | struct mpsc_tx_desc *txre; | |
591 | dma_addr_t dp, dp_p; | |
592 | u8 *bp, *bp_p; | |
593 | int i; | |
594 | ||
595 | pr_debug("mpsc_init_rings[%d]: Initializing rings\n", pi->port.line); | |
596 | ||
597 | BUG_ON(pi->dma_region == NULL); | |
598 | ||
599 | memset(pi->dma_region, 0, MPSC_DMA_ALLOC_SIZE); | |
600 | ||
601 | /* | |
602 | * Descriptors & buffers are multiples of cacheline size and must be | |
603 | * cacheline aligned. | |
604 | */ | |
605 | dp = ALIGN((u32) pi->dma_region, dma_get_cache_alignment()); | |
606 | dp_p = ALIGN((u32) pi->dma_region_p, dma_get_cache_alignment()); | |
607 | ||
608 | /* | |
609 | * Partition dma region into rx ring descriptor, rx buffers, | |
610 | * tx ring descriptors, and tx buffers. | |
611 | */ | |
612 | pi->rxr = dp; | |
613 | pi->rxr_p = dp_p; | |
614 | dp += MPSC_RXR_SIZE; | |
615 | dp_p += MPSC_RXR_SIZE; | |
616 | ||
617 | pi->rxb = (u8 *) dp; | |
618 | pi->rxb_p = (u8 *) dp_p; | |
619 | dp += MPSC_RXB_SIZE; | |
620 | dp_p += MPSC_RXB_SIZE; | |
621 | ||
622 | pi->rxr_posn = 0; | |
623 | ||
624 | pi->txr = dp; | |
625 | pi->txr_p = dp_p; | |
626 | dp += MPSC_TXR_SIZE; | |
627 | dp_p += MPSC_TXR_SIZE; | |
628 | ||
629 | pi->txb = (u8 *) dp; | |
630 | pi->txb_p = (u8 *) dp_p; | |
631 | ||
632 | pi->txr_head = 0; | |
633 | pi->txr_tail = 0; | |
634 | ||
635 | /* Init rx ring descriptors */ | |
636 | dp = pi->rxr; | |
637 | dp_p = pi->rxr_p; | |
638 | bp = pi->rxb; | |
639 | bp_p = pi->rxb_p; | |
640 | ||
641 | for (i = 0; i < MPSC_RXR_ENTRIES; i++) { | |
642 | rxre = (struct mpsc_rx_desc *)dp; | |
643 | ||
644 | rxre->bufsize = cpu_to_be16(MPSC_RXBE_SIZE); | |
645 | rxre->bytecnt = cpu_to_be16(0); | |
646 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | | |
647 | SDMA_DESC_CMDSTAT_EI | | |
648 | SDMA_DESC_CMDSTAT_F | | |
649 | SDMA_DESC_CMDSTAT_L); | |
650 | rxre->link = cpu_to_be32(dp_p + MPSC_RXRE_SIZE); | |
651 | rxre->buf_ptr = cpu_to_be32(bp_p); | |
652 | ||
653 | dp += MPSC_RXRE_SIZE; | |
654 | dp_p += MPSC_RXRE_SIZE; | |
655 | bp += MPSC_RXBE_SIZE; | |
656 | bp_p += MPSC_RXBE_SIZE; | |
657 | } | |
658 | rxre->link = cpu_to_be32(pi->rxr_p); /* Wrap last back to first */ | |
659 | ||
660 | /* Init tx ring descriptors */ | |
661 | dp = pi->txr; | |
662 | dp_p = pi->txr_p; | |
663 | bp = pi->txb; | |
664 | bp_p = pi->txb_p; | |
665 | ||
666 | for (i = 0; i < MPSC_TXR_ENTRIES; i++) { | |
667 | txre = (struct mpsc_tx_desc *)dp; | |
668 | ||
669 | txre->link = cpu_to_be32(dp_p + MPSC_TXRE_SIZE); | |
670 | txre->buf_ptr = cpu_to_be32(bp_p); | |
671 | ||
672 | dp += MPSC_TXRE_SIZE; | |
673 | dp_p += MPSC_TXRE_SIZE; | |
674 | bp += MPSC_TXBE_SIZE; | |
675 | bp_p += MPSC_TXBE_SIZE; | |
676 | } | |
677 | txre->link = cpu_to_be32(pi->txr_p); /* Wrap last back to first */ | |
678 | ||
679 | dma_cache_sync((void *) pi->dma_region, MPSC_DMA_ALLOC_SIZE, | |
680 | DMA_BIDIRECTIONAL); | |
681 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
682 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
683 | flush_dcache_range((ulong)pi->dma_region, | |
684 | (ulong)pi->dma_region + MPSC_DMA_ALLOC_SIZE); | |
685 | #endif | |
686 | ||
687 | return; | |
688 | } | |
689 | ||
690 | static void | |
691 | mpsc_uninit_rings(struct mpsc_port_info *pi) | |
692 | { | |
693 | pr_debug("mpsc_uninit_rings[%d]: Uninitializing rings\n",pi->port.line); | |
694 | ||
695 | BUG_ON(pi->dma_region == NULL); | |
696 | ||
697 | pi->rxr = 0; | |
698 | pi->rxr_p = 0; | |
699 | pi->rxb = NULL; | |
700 | pi->rxb_p = NULL; | |
701 | pi->rxr_posn = 0; | |
702 | ||
703 | pi->txr = 0; | |
704 | pi->txr_p = 0; | |
705 | pi->txb = NULL; | |
706 | pi->txb_p = NULL; | |
707 | pi->txr_head = 0; | |
708 | pi->txr_tail = 0; | |
709 | ||
710 | return; | |
711 | } | |
712 | ||
713 | static int | |
714 | mpsc_make_ready(struct mpsc_port_info *pi) | |
715 | { | |
716 | int rc; | |
717 | ||
718 | pr_debug("mpsc_make_ready[%d]: Making cltr ready\n", pi->port.line); | |
719 | ||
720 | if (!pi->ready) { | |
721 | mpsc_init_hw(pi); | |
722 | if ((rc = mpsc_alloc_ring_mem(pi))) | |
723 | return rc; | |
724 | mpsc_init_rings(pi); | |
725 | pi->ready = 1; | |
726 | } | |
727 | ||
728 | return 0; | |
729 | } | |
730 | ||
731 | /* | |
732 | ****************************************************************************** | |
733 | * | |
734 | * Interrupt Handling Routines | |
735 | * | |
736 | ****************************************************************************** | |
737 | */ | |
738 | ||
739 | static inline int | |
740 | mpsc_rx_intr(struct mpsc_port_info *pi, struct pt_regs *regs) | |
741 | { | |
742 | struct mpsc_rx_desc *rxre; | |
743 | struct tty_struct *tty = pi->port.info->tty; | |
744 | u32 cmdstat, bytes_in, i; | |
745 | int rc = 0; | |
746 | u8 *bp; | |
747 | char flag = TTY_NORMAL; | |
748 | static void mpsc_start_rx(struct mpsc_port_info *pi); | |
749 | ||
750 | pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line); | |
751 | ||
752 | rxre = (struct mpsc_rx_desc *)(pi->rxr + (pi->rxr_posn*MPSC_RXRE_SIZE)); | |
753 | ||
754 | dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); | |
755 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
756 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
757 | invalidate_dcache_range((ulong)rxre, | |
758 | (ulong)rxre + MPSC_RXRE_SIZE); | |
759 | #endif | |
760 | ||
761 | /* | |
762 | * Loop through Rx descriptors handling ones that have been completed. | |
763 | */ | |
764 | while (!((cmdstat = be32_to_cpu(rxre->cmdstat)) & SDMA_DESC_CMDSTAT_O)){ | |
765 | bytes_in = be16_to_cpu(rxre->bytecnt); | |
766 | ||
767 | /* Following use of tty struct directly is deprecated */ | |
768 | if (unlikely((tty->flip.count + bytes_in) >= TTY_FLIPBUF_SIZE)){ | |
769 | if (tty->low_latency) | |
770 | tty_flip_buffer_push(tty); | |
771 | /* | |
772 | * If this failed then we will throw awa the bytes | |
773 | * but mst do so to clear interrupts. | |
774 | */ | |
775 | } | |
776 | ||
777 | bp = pi->rxb + (pi->rxr_posn * MPSC_RXBE_SIZE); | |
778 | dma_cache_sync((void *) bp, MPSC_RXBE_SIZE, DMA_FROM_DEVICE); | |
779 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
780 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
781 | invalidate_dcache_range((ulong)bp, | |
782 | (ulong)bp + MPSC_RXBE_SIZE); | |
783 | #endif | |
784 | ||
785 | /* | |
786 | * Other than for parity error, the manual provides little | |
787 | * info on what data will be in a frame flagged by any of | |
788 | * these errors. For parity error, it is the last byte in | |
789 | * the buffer that had the error. As for the rest, I guess | |
790 | * we'll assume there is no data in the buffer. | |
791 | * If there is...it gets lost. | |
792 | */ | |
793 | if (unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | | |
794 | SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) { | |
795 | ||
796 | pi->port.icount.rx++; | |
797 | ||
798 | if (cmdstat & SDMA_DESC_CMDSTAT_BR) { /* Break */ | |
799 | pi->port.icount.brk++; | |
800 | ||
801 | if (uart_handle_break(&pi->port)) | |
802 | goto next_frame; | |
803 | } | |
804 | else if (cmdstat & SDMA_DESC_CMDSTAT_FR)/* Framing */ | |
805 | pi->port.icount.frame++; | |
806 | else if (cmdstat & SDMA_DESC_CMDSTAT_OR) /* Overrun */ | |
807 | pi->port.icount.overrun++; | |
808 | ||
809 | cmdstat &= pi->port.read_status_mask; | |
810 | ||
811 | if (cmdstat & SDMA_DESC_CMDSTAT_BR) | |
812 | flag = TTY_BREAK; | |
813 | else if (cmdstat & SDMA_DESC_CMDSTAT_FR) | |
814 | flag = TTY_FRAME; | |
815 | else if (cmdstat & SDMA_DESC_CMDSTAT_OR) | |
816 | flag = TTY_OVERRUN; | |
817 | else if (cmdstat & SDMA_DESC_CMDSTAT_PE) | |
818 | flag = TTY_PARITY; | |
819 | } | |
820 | ||
821 | if (uart_handle_sysrq_char(&pi->port, *bp, regs)) { | |
822 | bp++; | |
823 | bytes_in--; | |
824 | goto next_frame; | |
825 | } | |
826 | ||
827 | if ((unlikely(cmdstat & (SDMA_DESC_CMDSTAT_BR | | |
828 | SDMA_DESC_CMDSTAT_FR | SDMA_DESC_CMDSTAT_OR))) && | |
829 | !(cmdstat & pi->port.ignore_status_mask)) | |
830 | ||
831 | tty_insert_flip_char(tty, *bp, flag); | |
832 | else { | |
833 | for (i=0; i<bytes_in; i++) | |
834 | tty_insert_flip_char(tty, *bp++, TTY_NORMAL); | |
835 | ||
836 | pi->port.icount.rx += bytes_in; | |
837 | } | |
838 | ||
839 | next_frame: | |
840 | rxre->bytecnt = cpu_to_be16(0); | |
841 | wmb(); | |
842 | rxre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | | |
843 | SDMA_DESC_CMDSTAT_EI | | |
844 | SDMA_DESC_CMDSTAT_F | | |
845 | SDMA_DESC_CMDSTAT_L); | |
846 | wmb(); | |
847 | dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_BIDIRECTIONAL); | |
848 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
849 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
850 | flush_dcache_range((ulong)rxre, | |
851 | (ulong)rxre + MPSC_RXRE_SIZE); | |
852 | #endif | |
853 | ||
854 | /* Advance to next descriptor */ | |
855 | pi->rxr_posn = (pi->rxr_posn + 1) & (MPSC_RXR_ENTRIES - 1); | |
856 | rxre = (struct mpsc_rx_desc *)(pi->rxr + | |
857 | (pi->rxr_posn * MPSC_RXRE_SIZE)); | |
858 | dma_cache_sync((void *)rxre, MPSC_RXRE_SIZE, DMA_FROM_DEVICE); | |
859 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
860 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
861 | invalidate_dcache_range((ulong)rxre, | |
862 | (ulong)rxre + MPSC_RXRE_SIZE); | |
863 | #endif | |
864 | ||
865 | rc = 1; | |
866 | } | |
867 | ||
868 | /* Restart rx engine, if its stopped */ | |
869 | if ((readl(pi->sdma_base + SDMA_SDCM) & SDMA_SDCM_ERD) == 0) | |
870 | mpsc_start_rx(pi); | |
871 | ||
872 | tty_flip_buffer_push(tty); | |
873 | return rc; | |
874 | } | |
875 | ||
876 | static inline void | |
877 | mpsc_setup_tx_desc(struct mpsc_port_info *pi, u32 count, u32 intr) | |
878 | { | |
879 | struct mpsc_tx_desc *txre; | |
880 | ||
881 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
882 | (pi->txr_head * MPSC_TXRE_SIZE)); | |
883 | ||
884 | txre->bytecnt = cpu_to_be16(count); | |
885 | txre->shadow = txre->bytecnt; | |
886 | wmb(); /* ensure cmdstat is last field updated */ | |
887 | txre->cmdstat = cpu_to_be32(SDMA_DESC_CMDSTAT_O | SDMA_DESC_CMDSTAT_F | | |
888 | SDMA_DESC_CMDSTAT_L | ((intr) ? | |
889 | SDMA_DESC_CMDSTAT_EI | |
890 | : 0)); | |
891 | wmb(); | |
892 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_BIDIRECTIONAL); | |
893 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
894 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
895 | flush_dcache_range((ulong)txre, | |
896 | (ulong)txre + MPSC_TXRE_SIZE); | |
897 | #endif | |
898 | ||
899 | return; | |
900 | } | |
901 | ||
902 | static inline void | |
903 | mpsc_copy_tx_data(struct mpsc_port_info *pi) | |
904 | { | |
905 | struct circ_buf *xmit = &pi->port.info->xmit; | |
906 | u8 *bp; | |
907 | u32 i; | |
908 | ||
909 | /* Make sure the desc ring isn't full */ | |
910 | while (CIRC_CNT(pi->txr_head, pi->txr_tail, MPSC_TXR_ENTRIES) < | |
911 | (MPSC_TXR_ENTRIES - 1)) { | |
912 | if (pi->port.x_char) { | |
913 | /* | |
914 | * Ideally, we should use the TCS field in | |
915 | * CHR_1 to put the x_char out immediately but | |
916 | * errata prevents us from being able to read | |
917 | * CHR_2 to know that its safe to write to | |
918 | * CHR_1. Instead, just put it in-band with | |
919 | * all the other Tx data. | |
920 | */ | |
921 | bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); | |
922 | *bp = pi->port.x_char; | |
923 | pi->port.x_char = 0; | |
924 | i = 1; | |
925 | } | |
926 | else if (!uart_circ_empty(xmit) && !uart_tx_stopped(&pi->port)){ | |
927 | i = min((u32) MPSC_TXBE_SIZE, | |
928 | (u32) uart_circ_chars_pending(xmit)); | |
929 | i = min(i, (u32) CIRC_CNT_TO_END(xmit->head, xmit->tail, | |
930 | UART_XMIT_SIZE)); | |
931 | bp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); | |
932 | memcpy(bp, &xmit->buf[xmit->tail], i); | |
933 | xmit->tail = (xmit->tail + i) & (UART_XMIT_SIZE - 1); | |
934 | ||
935 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
936 | uart_write_wakeup(&pi->port); | |
937 | } | |
938 | else /* All tx data copied into ring bufs */ | |
939 | return; | |
940 | ||
941 | dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); | |
942 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
943 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
944 | flush_dcache_range((ulong)bp, | |
945 | (ulong)bp + MPSC_TXBE_SIZE); | |
946 | #endif | |
947 | mpsc_setup_tx_desc(pi, i, 1); | |
948 | ||
949 | /* Advance to next descriptor */ | |
950 | pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); | |
951 | } | |
952 | ||
953 | return; | |
954 | } | |
955 | ||
956 | static inline int | |
957 | mpsc_tx_intr(struct mpsc_port_info *pi) | |
958 | { | |
959 | struct mpsc_tx_desc *txre; | |
960 | int rc = 0; | |
961 | ||
962 | if (!mpsc_sdma_tx_active(pi)) { | |
963 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
964 | (pi->txr_tail * MPSC_TXRE_SIZE)); | |
965 | ||
966 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, DMA_FROM_DEVICE); | |
967 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
968 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
969 | invalidate_dcache_range((ulong)txre, | |
970 | (ulong)txre + MPSC_TXRE_SIZE); | |
971 | #endif | |
972 | ||
973 | while (!(be32_to_cpu(txre->cmdstat) & SDMA_DESC_CMDSTAT_O)) { | |
974 | rc = 1; | |
975 | pi->port.icount.tx += be16_to_cpu(txre->bytecnt); | |
976 | pi->txr_tail = (pi->txr_tail+1) & (MPSC_TXR_ENTRIES-1); | |
977 | ||
978 | /* If no more data to tx, fall out of loop */ | |
979 | if (pi->txr_head == pi->txr_tail) | |
980 | break; | |
981 | ||
982 | txre = (struct mpsc_tx_desc *)(pi->txr + | |
983 | (pi->txr_tail * MPSC_TXRE_SIZE)); | |
984 | dma_cache_sync((void *) txre, MPSC_TXRE_SIZE, | |
985 | DMA_FROM_DEVICE); | |
986 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
987 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
988 | invalidate_dcache_range((ulong)txre, | |
989 | (ulong)txre + MPSC_TXRE_SIZE); | |
990 | #endif | |
991 | } | |
992 | ||
993 | mpsc_copy_tx_data(pi); | |
994 | mpsc_sdma_start_tx(pi); /* start next desc if ready */ | |
995 | } | |
996 | ||
997 | return rc; | |
998 | } | |
999 | ||
1000 | /* | |
1001 | * This is the driver's interrupt handler. To avoid a race, we first clear | |
1002 | * the interrupt, then handle any completed Rx/Tx descriptors. When done | |
1003 | * handling those descriptors, we restart the Rx/Tx engines if they're stopped. | |
1004 | */ | |
1005 | static irqreturn_t | |
1006 | mpsc_sdma_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1007 | { | |
1008 | struct mpsc_port_info *pi = dev_id; | |
1009 | ulong iflags; | |
1010 | int rc = IRQ_NONE; | |
1011 | ||
1012 | pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Received\n",pi->port.line); | |
1013 | ||
1014 | spin_lock_irqsave(&pi->port.lock, iflags); | |
1015 | mpsc_sdma_intr_ack(pi); | |
1016 | if (mpsc_rx_intr(pi, regs)) | |
1017 | rc = IRQ_HANDLED; | |
1018 | if (mpsc_tx_intr(pi)) | |
1019 | rc = IRQ_HANDLED; | |
1020 | spin_unlock_irqrestore(&pi->port.lock, iflags); | |
1021 | ||
1022 | pr_debug("mpsc_sdma_intr[%d]: SDMA Interrupt Handled\n", pi->port.line); | |
1023 | return rc; | |
1024 | } | |
1025 | ||
1026 | /* | |
1027 | ****************************************************************************** | |
1028 | * | |
1029 | * serial_core.c Interface routines | |
1030 | * | |
1031 | ****************************************************************************** | |
1032 | */ | |
1033 | static uint | |
1034 | mpsc_tx_empty(struct uart_port *port) | |
1035 | { | |
1036 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1037 | ulong iflags; | |
1038 | uint rc; | |
1039 | ||
1040 | spin_lock_irqsave(&pi->port.lock, iflags); | |
1041 | rc = mpsc_sdma_tx_active(pi) ? 0 : TIOCSER_TEMT; | |
1042 | spin_unlock_irqrestore(&pi->port.lock, iflags); | |
1043 | ||
1044 | return rc; | |
1045 | } | |
1046 | ||
1047 | static void | |
1048 | mpsc_set_mctrl(struct uart_port *port, uint mctrl) | |
1049 | { | |
1050 | /* Have no way to set modem control lines AFAICT */ | |
1051 | return; | |
1052 | } | |
1053 | ||
1054 | static uint | |
1055 | mpsc_get_mctrl(struct uart_port *port) | |
1056 | { | |
1057 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1058 | u32 mflags, status; | |
1059 | ulong iflags; | |
1060 | ||
1061 | spin_lock_irqsave(&pi->port.lock, iflags); | |
1062 | status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m : | |
1063 | readl(pi->mpsc_base + MPSC_CHR_10); | |
1064 | spin_unlock_irqrestore(&pi->port.lock, iflags); | |
1065 | ||
1066 | mflags = 0; | |
1067 | if (status & 0x1) | |
1068 | mflags |= TIOCM_CTS; | |
1069 | if (status & 0x2) | |
1070 | mflags |= TIOCM_CAR; | |
1071 | ||
1072 | return mflags | TIOCM_DSR; /* No way to tell if DSR asserted */ | |
1073 | } | |
1074 | ||
1075 | static void | |
1076 | mpsc_stop_tx(struct uart_port *port, uint tty_start) | |
1077 | { | |
1078 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1079 | ||
1080 | pr_debug("mpsc_stop_tx[%d]: tty_start: %d\n", port->line, tty_start); | |
1081 | ||
1082 | mpsc_freeze(pi); | |
1083 | return; | |
1084 | } | |
1085 | ||
1086 | static void | |
1087 | mpsc_start_tx(struct uart_port *port, uint tty_start) | |
1088 | { | |
1089 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1090 | ||
1091 | mpsc_unfreeze(pi); | |
1092 | mpsc_copy_tx_data(pi); | |
1093 | mpsc_sdma_start_tx(pi); | |
1094 | ||
1095 | pr_debug("mpsc_start_tx[%d]: tty_start: %d\n", port->line, tty_start); | |
1096 | return; | |
1097 | } | |
1098 | ||
1099 | static void | |
1100 | mpsc_start_rx(struct mpsc_port_info *pi) | |
1101 | { | |
1102 | pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line); | |
1103 | ||
1104 | if (pi->rcv_data) { | |
1105 | mpsc_enter_hunt(pi); | |
1106 | mpsc_sdma_cmd(pi, SDMA_SDCM_ERD); | |
1107 | } | |
1108 | return; | |
1109 | } | |
1110 | ||
1111 | static void | |
1112 | mpsc_stop_rx(struct uart_port *port) | |
1113 | { | |
1114 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1115 | ||
1116 | pr_debug("mpsc_stop_rx[%d]: Stopping...\n", port->line); | |
1117 | ||
1118 | mpsc_sdma_cmd(pi, SDMA_SDCM_AR); | |
1119 | return; | |
1120 | } | |
1121 | ||
1122 | static void | |
1123 | mpsc_enable_ms(struct uart_port *port) | |
1124 | { | |
1125 | return; /* Not supported */ | |
1126 | } | |
1127 | ||
1128 | static void | |
1129 | mpsc_break_ctl(struct uart_port *port, int ctl) | |
1130 | { | |
1131 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1132 | ulong flags; | |
1133 | u32 v; | |
1134 | ||
1135 | v = ctl ? 0x00ff0000 : 0; | |
1136 | ||
1137 | spin_lock_irqsave(&pi->port.lock, flags); | |
1138 | if (pi->mirror_regs) | |
1139 | pi->MPSC_CHR_1_m = v; | |
1140 | writel(v, pi->mpsc_base + MPSC_CHR_1); | |
1141 | spin_unlock_irqrestore(&pi->port.lock, flags); | |
1142 | ||
1143 | return; | |
1144 | } | |
1145 | ||
1146 | static int | |
1147 | mpsc_startup(struct uart_port *port) | |
1148 | { | |
1149 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1150 | u32 flag = 0; | |
1151 | int rc; | |
1152 | ||
1153 | pr_debug("mpsc_startup[%d]: Starting up MPSC, irq: %d\n", | |
1154 | port->line, pi->port.irq); | |
1155 | ||
1156 | if ((rc = mpsc_make_ready(pi)) == 0) { | |
1157 | /* Setup IRQ handler */ | |
1158 | mpsc_sdma_intr_ack(pi); | |
1159 | ||
1160 | /* If irq's are shared, need to set flag */ | |
1161 | if (mpsc_ports[0].port.irq == mpsc_ports[1].port.irq) | |
1162 | flag = SA_SHIRQ; | |
1163 | ||
1164 | if (request_irq(pi->port.irq, mpsc_sdma_intr, flag, | |
1165 | "mpsc/sdma", pi)) | |
1166 | printk(KERN_ERR "MPSC: Can't get SDMA IRQ %d\n", | |
1167 | pi->port.irq); | |
1168 | ||
1169 | mpsc_sdma_intr_unmask(pi, 0xf); | |
1170 | mpsc_sdma_set_rx_ring(pi, (struct mpsc_rx_desc *)(pi->rxr_p + | |
1171 | (pi->rxr_posn * MPSC_RXRE_SIZE))); | |
1172 | } | |
1173 | ||
1174 | return rc; | |
1175 | } | |
1176 | ||
1177 | static void | |
1178 | mpsc_shutdown(struct uart_port *port) | |
1179 | { | |
1180 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1181 | static void mpsc_release_port(struct uart_port *port); | |
1182 | ||
1183 | pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line); | |
1184 | ||
1185 | mpsc_sdma_stop(pi); | |
1186 | free_irq(pi->port.irq, pi); | |
1187 | return; | |
1188 | } | |
1189 | ||
1190 | static void | |
1191 | mpsc_set_termios(struct uart_port *port, struct termios *termios, | |
1192 | struct termios *old) | |
1193 | { | |
1194 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1195 | u32 baud; | |
1196 | ulong flags; | |
1197 | u32 chr_bits, stop_bits, par; | |
1198 | ||
1199 | pi->c_iflag = termios->c_iflag; | |
1200 | pi->c_cflag = termios->c_cflag; | |
1201 | ||
1202 | switch (termios->c_cflag & CSIZE) { | |
1203 | case CS5: | |
1204 | chr_bits = MPSC_MPCR_CL_5; | |
1205 | break; | |
1206 | case CS6: | |
1207 | chr_bits = MPSC_MPCR_CL_6; | |
1208 | break; | |
1209 | case CS7: | |
1210 | chr_bits = MPSC_MPCR_CL_7; | |
1211 | break; | |
1212 | case CS8: | |
1213 | default: | |
1214 | chr_bits = MPSC_MPCR_CL_8; | |
1215 | break; | |
1216 | } | |
1217 | ||
1218 | if (termios->c_cflag & CSTOPB) | |
1219 | stop_bits = MPSC_MPCR_SBL_2; | |
1220 | else | |
1221 | stop_bits = MPSC_MPCR_SBL_1; | |
1222 | ||
1223 | par = MPSC_CHR_2_PAR_EVEN; | |
1224 | if (termios->c_cflag & PARENB) | |
1225 | if (termios->c_cflag & PARODD) | |
1226 | par = MPSC_CHR_2_PAR_ODD; | |
1227 | #ifdef CMSPAR | |
1228 | if (termios->c_cflag & CMSPAR) { | |
1229 | if (termios->c_cflag & PARODD) | |
1230 | par = MPSC_CHR_2_PAR_MARK; | |
1231 | else | |
1232 | par = MPSC_CHR_2_PAR_SPACE; | |
1233 | } | |
1234 | #endif | |
1235 | ||
1236 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk); | |
1237 | ||
1238 | spin_lock_irqsave(&pi->port.lock, flags); | |
1239 | ||
1240 | uart_update_timeout(port, termios->c_cflag, baud); | |
1241 | ||
1242 | mpsc_set_char_length(pi, chr_bits); | |
1243 | mpsc_set_stop_bit_length(pi, stop_bits); | |
1244 | mpsc_set_parity(pi, par); | |
1245 | mpsc_set_baudrate(pi, baud); | |
1246 | ||
1247 | /* Characters/events to read */ | |
1248 | pi->rcv_data = 1; | |
1249 | pi->port.read_status_mask = SDMA_DESC_CMDSTAT_OR; | |
1250 | ||
1251 | if (termios->c_iflag & INPCK) | |
1252 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_PE | | |
1253 | SDMA_DESC_CMDSTAT_FR; | |
1254 | ||
1255 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
1256 | pi->port.read_status_mask |= SDMA_DESC_CMDSTAT_BR; | |
1257 | ||
1258 | /* Characters/events to ignore */ | |
1259 | pi->port.ignore_status_mask = 0; | |
1260 | ||
1261 | if (termios->c_iflag & IGNPAR) | |
1262 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_PE | | |
1263 | SDMA_DESC_CMDSTAT_FR; | |
1264 | ||
1265 | if (termios->c_iflag & IGNBRK) { | |
1266 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_BR; | |
1267 | ||
1268 | if (termios->c_iflag & IGNPAR) | |
1269 | pi->port.ignore_status_mask |= SDMA_DESC_CMDSTAT_OR; | |
1270 | } | |
1271 | ||
1272 | /* Ignore all chars if CREAD not set */ | |
1273 | if (!(termios->c_cflag & CREAD)) | |
1274 | pi->rcv_data = 0; | |
1275 | else | |
1276 | mpsc_start_rx(pi); | |
1277 | ||
1278 | spin_unlock_irqrestore(&pi->port.lock, flags); | |
1279 | return; | |
1280 | } | |
1281 | ||
1282 | static const char * | |
1283 | mpsc_type(struct uart_port *port) | |
1284 | { | |
1285 | pr_debug("mpsc_type[%d]: port type: %s\n", port->line,MPSC_DRIVER_NAME); | |
1286 | return MPSC_DRIVER_NAME; | |
1287 | } | |
1288 | ||
1289 | static int | |
1290 | mpsc_request_port(struct uart_port *port) | |
1291 | { | |
1292 | /* Should make chip/platform specific call */ | |
1293 | return 0; | |
1294 | } | |
1295 | ||
1296 | static void | |
1297 | mpsc_release_port(struct uart_port *port) | |
1298 | { | |
1299 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1300 | ||
1301 | if (pi->ready) { | |
1302 | mpsc_uninit_rings(pi); | |
1303 | mpsc_free_ring_mem(pi); | |
1304 | pi->ready = 0; | |
1305 | } | |
1306 | ||
1307 | return; | |
1308 | } | |
1309 | ||
1310 | static void | |
1311 | mpsc_config_port(struct uart_port *port, int flags) | |
1312 | { | |
1313 | return; | |
1314 | } | |
1315 | ||
1316 | static int | |
1317 | mpsc_verify_port(struct uart_port *port, struct serial_struct *ser) | |
1318 | { | |
1319 | struct mpsc_port_info *pi = (struct mpsc_port_info *)port; | |
1320 | int rc = 0; | |
1321 | ||
1322 | pr_debug("mpsc_verify_port[%d]: Verifying port data\n", pi->port.line); | |
1323 | ||
1324 | if (ser->type != PORT_UNKNOWN && ser->type != PORT_MPSC) | |
1325 | rc = -EINVAL; | |
1326 | else if (pi->port.irq != ser->irq) | |
1327 | rc = -EINVAL; | |
1328 | else if (ser->io_type != SERIAL_IO_MEM) | |
1329 | rc = -EINVAL; | |
1330 | else if (pi->port.uartclk / 16 != ser->baud_base) /* Not sure */ | |
1331 | rc = -EINVAL; | |
1332 | else if ((void *)pi->port.mapbase != ser->iomem_base) | |
1333 | rc = -EINVAL; | |
1334 | else if (pi->port.iobase != ser->port) | |
1335 | rc = -EINVAL; | |
1336 | else if (ser->hub6 != 0) | |
1337 | rc = -EINVAL; | |
1338 | ||
1339 | return rc; | |
1340 | } | |
1341 | ||
1342 | static struct uart_ops mpsc_pops = { | |
1343 | .tx_empty = mpsc_tx_empty, | |
1344 | .set_mctrl = mpsc_set_mctrl, | |
1345 | .get_mctrl = mpsc_get_mctrl, | |
1346 | .stop_tx = mpsc_stop_tx, | |
1347 | .start_tx = mpsc_start_tx, | |
1348 | .stop_rx = mpsc_stop_rx, | |
1349 | .enable_ms = mpsc_enable_ms, | |
1350 | .break_ctl = mpsc_break_ctl, | |
1351 | .startup = mpsc_startup, | |
1352 | .shutdown = mpsc_shutdown, | |
1353 | .set_termios = mpsc_set_termios, | |
1354 | .type = mpsc_type, | |
1355 | .release_port = mpsc_release_port, | |
1356 | .request_port = mpsc_request_port, | |
1357 | .config_port = mpsc_config_port, | |
1358 | .verify_port = mpsc_verify_port, | |
1359 | }; | |
1360 | ||
1361 | /* | |
1362 | ****************************************************************************** | |
1363 | * | |
1364 | * Console Interface Routines | |
1365 | * | |
1366 | ****************************************************************************** | |
1367 | */ | |
1368 | ||
1369 | #ifdef CONFIG_SERIAL_MPSC_CONSOLE | |
1370 | static void | |
1371 | mpsc_console_write(struct console *co, const char *s, uint count) | |
1372 | { | |
1373 | struct mpsc_port_info *pi = &mpsc_ports[co->index]; | |
1374 | u8 *bp, *dp, add_cr = 0; | |
1375 | int i; | |
1376 | ||
1377 | while (mpsc_sdma_tx_active(pi)) | |
1378 | udelay(100); | |
1379 | ||
1380 | while (count > 0) { | |
1381 | bp = dp = pi->txb + (pi->txr_head * MPSC_TXBE_SIZE); | |
1382 | ||
1383 | for (i = 0; i < MPSC_TXBE_SIZE; i++) { | |
1384 | if (count == 0) | |
1385 | break; | |
1386 | ||
1387 | if (add_cr) { | |
1388 | *(dp++) = '\r'; | |
1389 | add_cr = 0; | |
1390 | } | |
1391 | else { | |
1392 | *(dp++) = *s; | |
1393 | ||
1394 | if (*(s++) == '\n') { /* add '\r' after '\n' */ | |
1395 | add_cr = 1; | |
1396 | count++; | |
1397 | } | |
1398 | } | |
1399 | ||
1400 | count--; | |
1401 | } | |
1402 | ||
1403 | dma_cache_sync((void *) bp, MPSC_TXBE_SIZE, DMA_BIDIRECTIONAL); | |
1404 | #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE) | |
1405 | if (pi->cache_mgmt) /* GT642[46]0 Res #COMM-2 */ | |
1406 | flush_dcache_range((ulong)bp, | |
1407 | (ulong)bp + MPSC_TXBE_SIZE); | |
1408 | #endif | |
1409 | mpsc_setup_tx_desc(pi, i, 0); | |
1410 | pi->txr_head = (pi->txr_head + 1) & (MPSC_TXR_ENTRIES - 1); | |
1411 | mpsc_sdma_start_tx(pi); | |
1412 | ||
1413 | while (mpsc_sdma_tx_active(pi)) | |
1414 | udelay(100); | |
1415 | ||
1416 | pi->txr_tail = (pi->txr_tail + 1) & (MPSC_TXR_ENTRIES - 1); | |
1417 | } | |
1418 | ||
1419 | return; | |
1420 | } | |
1421 | ||
1422 | static int __init | |
1423 | mpsc_console_setup(struct console *co, char *options) | |
1424 | { | |
1425 | struct mpsc_port_info *pi; | |
1426 | int baud, bits, parity, flow; | |
1427 | ||
1428 | pr_debug("mpsc_console_setup[%d]: options: %s\n", co->index, options); | |
1429 | ||
1430 | if (co->index >= MPSC_NUM_CTLRS) | |
1431 | co->index = 0; | |
1432 | ||
1433 | pi = &mpsc_ports[co->index]; | |
1434 | ||
1435 | baud = pi->default_baud; | |
1436 | bits = pi->default_bits; | |
1437 | parity = pi->default_parity; | |
1438 | flow = pi->default_flow; | |
1439 | ||
1440 | if (!pi->port.ops) | |
1441 | return -ENODEV; | |
1442 | ||
1443 | spin_lock_init(&pi->port.lock); /* Temporary fix--copied from 8250.c */ | |
1444 | ||
1445 | if (options) | |
1446 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1447 | ||
1448 | return uart_set_options(&pi->port, co, baud, parity, bits, flow); | |
1449 | } | |
1450 | ||
1451 | extern struct uart_driver mpsc_reg; | |
1452 | static struct console mpsc_console = { | |
1453 | .name = MPSC_DEV_NAME, | |
1454 | .write = mpsc_console_write, | |
1455 | .device = uart_console_device, | |
1456 | .setup = mpsc_console_setup, | |
1457 | .flags = CON_PRINTBUFFER, | |
1458 | .index = -1, | |
1459 | .data = &mpsc_reg, | |
1460 | }; | |
1461 | ||
1462 | static int __init | |
1463 | mpsc_late_console_init(void) | |
1464 | { | |
1465 | pr_debug("mpsc_late_console_init: Enter\n"); | |
1466 | ||
1467 | if (!(mpsc_console.flags & CON_ENABLED)) | |
1468 | register_console(&mpsc_console); | |
1469 | return 0; | |
1470 | } | |
1471 | ||
1472 | late_initcall(mpsc_late_console_init); | |
1473 | ||
1474 | #define MPSC_CONSOLE &mpsc_console | |
1475 | #else | |
1476 | #define MPSC_CONSOLE NULL | |
1477 | #endif | |
1478 | /* | |
1479 | ****************************************************************************** | |
1480 | * | |
1481 | * Dummy Platform Driver to extract & map shared register regions | |
1482 | * | |
1483 | ****************************************************************************** | |
1484 | */ | |
1485 | static void | |
1486 | mpsc_resource_err(char *s) | |
1487 | { | |
1488 | printk(KERN_WARNING "MPSC: Platform device resource error in %s\n", s); | |
1489 | return; | |
1490 | } | |
1491 | ||
1492 | static int | |
1493 | mpsc_shared_map_regs(struct platform_device *pd) | |
1494 | { | |
1495 | struct resource *r; | |
1496 | ||
1497 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, | |
1498 | MPSC_ROUTING_BASE_ORDER)) && request_mem_region(r->start, | |
1499 | MPSC_ROUTING_REG_BLOCK_SIZE, "mpsc_routing_regs")) { | |
1500 | ||
1501 | mpsc_shared_regs.mpsc_routing_base = ioremap(r->start, | |
1502 | MPSC_ROUTING_REG_BLOCK_SIZE); | |
1503 | mpsc_shared_regs.mpsc_routing_base_p = r->start; | |
1504 | } | |
1505 | else { | |
1506 | mpsc_resource_err("MPSC routing base"); | |
1507 | return -ENOMEM; | |
1508 | } | |
1509 | ||
1510 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, | |
1511 | MPSC_SDMA_INTR_BASE_ORDER)) && request_mem_region(r->start, | |
1512 | MPSC_SDMA_INTR_REG_BLOCK_SIZE, "sdma_intr_regs")) { | |
1513 | ||
1514 | mpsc_shared_regs.sdma_intr_base = ioremap(r->start, | |
1515 | MPSC_SDMA_INTR_REG_BLOCK_SIZE); | |
1516 | mpsc_shared_regs.sdma_intr_base_p = r->start; | |
1517 | } | |
1518 | else { | |
1519 | iounmap(mpsc_shared_regs.mpsc_routing_base); | |
1520 | release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, | |
1521 | MPSC_ROUTING_REG_BLOCK_SIZE); | |
1522 | mpsc_resource_err("SDMA intr base"); | |
1523 | return -ENOMEM; | |
1524 | } | |
1525 | ||
1526 | return 0; | |
1527 | } | |
1528 | ||
1529 | static void | |
1530 | mpsc_shared_unmap_regs(void) | |
1531 | { | |
1532 | if (!mpsc_shared_regs.mpsc_routing_base) { | |
1533 | iounmap(mpsc_shared_regs.mpsc_routing_base); | |
1534 | release_mem_region(mpsc_shared_regs.mpsc_routing_base_p, | |
1535 | MPSC_ROUTING_REG_BLOCK_SIZE); | |
1536 | } | |
1537 | if (!mpsc_shared_regs.sdma_intr_base) { | |
1538 | iounmap(mpsc_shared_regs.sdma_intr_base); | |
1539 | release_mem_region(mpsc_shared_regs.sdma_intr_base_p, | |
1540 | MPSC_SDMA_INTR_REG_BLOCK_SIZE); | |
1541 | } | |
1542 | ||
2c6e7599 AV |
1543 | mpsc_shared_regs.mpsc_routing_base = NULL; |
1544 | mpsc_shared_regs.sdma_intr_base = NULL; | |
1da177e4 LT |
1545 | |
1546 | mpsc_shared_regs.mpsc_routing_base_p = 0; | |
1547 | mpsc_shared_regs.sdma_intr_base_p = 0; | |
1548 | ||
1549 | return; | |
1550 | } | |
1551 | ||
1552 | static int | |
1553 | mpsc_shared_drv_probe(struct device *dev) | |
1554 | { | |
1555 | struct platform_device *pd = to_platform_device(dev); | |
1556 | struct mpsc_shared_pdata *pdata; | |
1557 | int rc = -ENODEV; | |
1558 | ||
1559 | if (pd->id == 0) { | |
1560 | if (!(rc = mpsc_shared_map_regs(pd))) { | |
1561 | pdata = (struct mpsc_shared_pdata *)dev->platform_data; | |
1562 | ||
1563 | mpsc_shared_regs.MPSC_MRR_m = pdata->mrr_val; | |
1564 | mpsc_shared_regs.MPSC_RCRR_m= pdata->rcrr_val; | |
1565 | mpsc_shared_regs.MPSC_TCRR_m= pdata->tcrr_val; | |
1566 | mpsc_shared_regs.SDMA_INTR_CAUSE_m = | |
1567 | pdata->intr_cause_val; | |
1568 | mpsc_shared_regs.SDMA_INTR_MASK_m = | |
1569 | pdata->intr_mask_val; | |
1570 | ||
1571 | rc = 0; | |
1572 | } | |
1573 | } | |
1574 | ||
1575 | return rc; | |
1576 | } | |
1577 | ||
1578 | static int | |
1579 | mpsc_shared_drv_remove(struct device *dev) | |
1580 | { | |
1581 | struct platform_device *pd = to_platform_device(dev); | |
1582 | int rc = -ENODEV; | |
1583 | ||
1584 | if (pd->id == 0) { | |
1585 | mpsc_shared_unmap_regs(); | |
1586 | mpsc_shared_regs.MPSC_MRR_m = 0; | |
1587 | mpsc_shared_regs.MPSC_RCRR_m = 0; | |
1588 | mpsc_shared_regs.MPSC_TCRR_m = 0; | |
1589 | mpsc_shared_regs.SDMA_INTR_CAUSE_m = 0; | |
1590 | mpsc_shared_regs.SDMA_INTR_MASK_m = 0; | |
1591 | rc = 0; | |
1592 | } | |
1593 | ||
1594 | return rc; | |
1595 | } | |
1596 | ||
1597 | static struct device_driver mpsc_shared_driver = { | |
1598 | .name = MPSC_SHARED_NAME, | |
1599 | .bus = &platform_bus_type, | |
1600 | .probe = mpsc_shared_drv_probe, | |
1601 | .remove = mpsc_shared_drv_remove, | |
1602 | }; | |
1603 | ||
1604 | /* | |
1605 | ****************************************************************************** | |
1606 | * | |
1607 | * Driver Interface Routines | |
1608 | * | |
1609 | ****************************************************************************** | |
1610 | */ | |
1611 | static struct uart_driver mpsc_reg = { | |
1612 | .owner = THIS_MODULE, | |
1613 | .driver_name = MPSC_DRIVER_NAME, | |
1614 | .devfs_name = MPSC_DEVFS_NAME, | |
1615 | .dev_name = MPSC_DEV_NAME, | |
1616 | .major = MPSC_MAJOR, | |
1617 | .minor = MPSC_MINOR_START, | |
1618 | .nr = MPSC_NUM_CTLRS, | |
1619 | .cons = MPSC_CONSOLE, | |
1620 | }; | |
1621 | ||
1622 | static int | |
1623 | mpsc_drv_map_regs(struct mpsc_port_info *pi, struct platform_device *pd) | |
1624 | { | |
1625 | struct resource *r; | |
1626 | ||
1627 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, MPSC_BASE_ORDER)) && | |
1628 | request_mem_region(r->start, MPSC_REG_BLOCK_SIZE, "mpsc_regs")){ | |
1629 | ||
1630 | pi->mpsc_base = ioremap(r->start, MPSC_REG_BLOCK_SIZE); | |
1631 | pi->mpsc_base_p = r->start; | |
1632 | } | |
1633 | else { | |
1634 | mpsc_resource_err("MPSC base"); | |
1635 | return -ENOMEM; | |
1636 | } | |
1637 | ||
1638 | if ((r = platform_get_resource(pd, IORESOURCE_MEM, | |
1639 | MPSC_SDMA_BASE_ORDER)) && request_mem_region(r->start, | |
1640 | MPSC_SDMA_REG_BLOCK_SIZE, "sdma_regs")) { | |
1641 | ||
1642 | pi->sdma_base = ioremap(r->start,MPSC_SDMA_REG_BLOCK_SIZE); | |
1643 | pi->sdma_base_p = r->start; | |
1644 | } | |
1645 | else { | |
1646 | mpsc_resource_err("SDMA base"); | |
1647 | return -ENOMEM; | |
1648 | } | |
1649 | ||
1650 | if ((r = platform_get_resource(pd,IORESOURCE_MEM,MPSC_BRG_BASE_ORDER)) | |
1651 | && request_mem_region(r->start, MPSC_BRG_REG_BLOCK_SIZE, | |
1652 | "brg_regs")) { | |
1653 | ||
1654 | pi->brg_base = ioremap(r->start, MPSC_BRG_REG_BLOCK_SIZE); | |
1655 | pi->brg_base_p = r->start; | |
1656 | } | |
1657 | else { | |
1658 | mpsc_resource_err("BRG base"); | |
1659 | return -ENOMEM; | |
1660 | } | |
1661 | ||
1662 | return 0; | |
1663 | } | |
1664 | ||
1665 | static void | |
1666 | mpsc_drv_unmap_regs(struct mpsc_port_info *pi) | |
1667 | { | |
1668 | if (!pi->mpsc_base) { | |
1669 | iounmap(pi->mpsc_base); | |
1670 | release_mem_region(pi->mpsc_base_p, MPSC_REG_BLOCK_SIZE); | |
1671 | } | |
1672 | if (!pi->sdma_base) { | |
1673 | iounmap(pi->sdma_base); | |
1674 | release_mem_region(pi->sdma_base_p, MPSC_SDMA_REG_BLOCK_SIZE); | |
1675 | } | |
1676 | if (!pi->brg_base) { | |
1677 | iounmap(pi->brg_base); | |
1678 | release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE); | |
1679 | } | |
1680 | ||
2c6e7599 AV |
1681 | pi->mpsc_base = NULL; |
1682 | pi->sdma_base = NULL; | |
1683 | pi->brg_base = NULL; | |
1da177e4 LT |
1684 | |
1685 | pi->mpsc_base_p = 0; | |
1686 | pi->sdma_base_p = 0; | |
1687 | pi->brg_base_p = 0; | |
1688 | ||
1689 | return; | |
1690 | } | |
1691 | ||
1692 | static void | |
1693 | mpsc_drv_get_platform_data(struct mpsc_port_info *pi, | |
1694 | struct platform_device *pd, int num) | |
1695 | { | |
1696 | struct mpsc_pdata *pdata; | |
1697 | ||
1698 | pdata = (struct mpsc_pdata *)pd->dev.platform_data; | |
1699 | ||
1700 | pi->port.uartclk = pdata->brg_clk_freq; | |
1701 | pi->port.iotype = UPIO_MEM; | |
1702 | pi->port.line = num; | |
1703 | pi->port.type = PORT_MPSC; | |
1704 | pi->port.fifosize = MPSC_TXBE_SIZE; | |
1705 | pi->port.membase = pi->mpsc_base; | |
1706 | pi->port.mapbase = (ulong)pi->mpsc_base; | |
1707 | pi->port.ops = &mpsc_pops; | |
1708 | ||
1709 | pi->mirror_regs = pdata->mirror_regs; | |
1710 | pi->cache_mgmt = pdata->cache_mgmt; | |
1711 | pi->brg_can_tune = pdata->brg_can_tune; | |
1712 | pi->brg_clk_src = pdata->brg_clk_src; | |
1713 | pi->mpsc_max_idle = pdata->max_idle; | |
1714 | pi->default_baud = pdata->default_baud; | |
1715 | pi->default_bits = pdata->default_bits; | |
1716 | pi->default_parity = pdata->default_parity; | |
1717 | pi->default_flow = pdata->default_flow; | |
1718 | ||
1719 | /* Initial values of mirrored regs */ | |
1720 | pi->MPSC_CHR_1_m = pdata->chr_1_val; | |
1721 | pi->MPSC_CHR_2_m = pdata->chr_2_val; | |
1722 | pi->MPSC_CHR_10_m = pdata->chr_10_val; | |
1723 | pi->MPSC_MPCR_m = pdata->mpcr_val; | |
1724 | pi->BRG_BCR_m = pdata->bcr_val; | |
1725 | ||
1726 | pi->shared_regs = &mpsc_shared_regs; | |
1727 | ||
1728 | pi->port.irq = platform_get_irq(pd, 0); | |
1729 | ||
1730 | return; | |
1731 | } | |
1732 | ||
1733 | static int | |
1734 | mpsc_drv_probe(struct device *dev) | |
1735 | { | |
1736 | struct platform_device *pd = to_platform_device(dev); | |
1737 | struct mpsc_port_info *pi; | |
1738 | int rc = -ENODEV; | |
1739 | ||
1740 | pr_debug("mpsc_drv_probe: Adding MPSC %d\n", pd->id); | |
1741 | ||
1742 | if (pd->id < MPSC_NUM_CTLRS) { | |
1743 | pi = &mpsc_ports[pd->id]; | |
1744 | ||
1745 | if (!(rc = mpsc_drv_map_regs(pi, pd))) { | |
1746 | mpsc_drv_get_platform_data(pi, pd, pd->id); | |
1747 | ||
1748 | if (!(rc = mpsc_make_ready(pi))) | |
1749 | if (!(rc = uart_add_one_port(&mpsc_reg, | |
1750 | &pi->port))) | |
1751 | rc = 0; | |
1752 | else { | |
1753 | mpsc_release_port( | |
1754 | (struct uart_port *)pi); | |
1755 | mpsc_drv_unmap_regs(pi); | |
1756 | } | |
1757 | else | |
1758 | mpsc_drv_unmap_regs(pi); | |
1759 | } | |
1760 | } | |
1761 | ||
1762 | return rc; | |
1763 | } | |
1764 | ||
1765 | static int | |
1766 | mpsc_drv_remove(struct device *dev) | |
1767 | { | |
1768 | struct platform_device *pd = to_platform_device(dev); | |
1769 | ||
1770 | pr_debug("mpsc_drv_exit: Removing MPSC %d\n", pd->id); | |
1771 | ||
1772 | if (pd->id < MPSC_NUM_CTLRS) { | |
1773 | uart_remove_one_port(&mpsc_reg, &mpsc_ports[pd->id].port); | |
1774 | mpsc_release_port((struct uart_port *)&mpsc_ports[pd->id].port); | |
1775 | mpsc_drv_unmap_regs(&mpsc_ports[pd->id]); | |
1776 | return 0; | |
1777 | } | |
1778 | else | |
1779 | return -ENODEV; | |
1780 | } | |
1781 | ||
1782 | static struct device_driver mpsc_driver = { | |
1783 | .name = MPSC_CTLR_NAME, | |
1784 | .bus = &platform_bus_type, | |
1785 | .probe = mpsc_drv_probe, | |
1786 | .remove = mpsc_drv_remove, | |
1787 | }; | |
1788 | ||
1789 | static int __init | |
1790 | mpsc_drv_init(void) | |
1791 | { | |
1792 | int rc; | |
1793 | ||
1794 | printk(KERN_INFO "Serial: MPSC driver $Revision: 1.00 $\n"); | |
1795 | ||
1796 | memset(mpsc_ports, 0, sizeof(mpsc_ports)); | |
1797 | memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); | |
1798 | ||
1799 | if (!(rc = uart_register_driver(&mpsc_reg))) { | |
1800 | if (!(rc = driver_register(&mpsc_shared_driver))) { | |
1801 | if ((rc = driver_register(&mpsc_driver))) { | |
1802 | driver_unregister(&mpsc_shared_driver); | |
1803 | uart_unregister_driver(&mpsc_reg); | |
1804 | } | |
1805 | } | |
1806 | else | |
1807 | uart_unregister_driver(&mpsc_reg); | |
1808 | } | |
1809 | ||
1810 | return rc; | |
1811 | ||
1812 | } | |
1813 | ||
1814 | static void __exit | |
1815 | mpsc_drv_exit(void) | |
1816 | { | |
1817 | driver_unregister(&mpsc_driver); | |
1818 | driver_unregister(&mpsc_shared_driver); | |
1819 | uart_unregister_driver(&mpsc_reg); | |
1820 | memset(mpsc_ports, 0, sizeof(mpsc_ports)); | |
1821 | memset(&mpsc_shared_regs, 0, sizeof(mpsc_shared_regs)); | |
1822 | return; | |
1823 | } | |
1824 | ||
1825 | module_init(mpsc_drv_init); | |
1826 | module_exit(mpsc_drv_exit); | |
1827 | ||
1828 | MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>"); | |
1829 | MODULE_DESCRIPTION("Generic Marvell MPSC serial/UART driver $Revision: 1.00 $"); | |
1830 | MODULE_VERSION(MPSC_VERSION); | |
1831 | MODULE_LICENSE("GPL"); | |
1832 | MODULE_ALIAS_CHARDEV_MAJOR(MPSC_MAJOR); |