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serial: bfin_sport_uart: protect changes to uart_port
[net-next-2.6.git] / drivers / serial / bfin_sport_uart.c
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2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW
9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
13 * http://www.analog.com/UploadedFiles/Application_Notes/399447663EE191.pdf
14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW
17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW
24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
5a0e3ad6 31#include <linux/slab.h>
2f351741
BW
32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36
37#include <asm/delay.h>
38#include <asm/portmux.h>
39
40#include "bfin_sport_uart.h"
41
2f351741
BW
42struct sport_uart_port {
43 struct uart_port port;
2f351741 44 int err_irq;
ccf68e59 45 unsigned short csize;
46 unsigned short rxmask;
47 unsigned short txmask1;
48 unsigned short txmask2;
49 unsigned char stopb;
50/* unsigned char parib; */
1f7d1c85
SZ
51#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
52 int cts_pin;
53 int rts_pin;
54#endif
2f351741
BW
55};
56
57static void sport_uart_tx_chars(struct sport_uart_port *up);
58static void sport_stop_tx(struct uart_port *port);
59
60static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
61{
ccf68e59 62 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
63 up->txmask1, up->txmask2);
64
65 /* Place Start and Stop bits */
4328e3e5 66 __asm__ __volatile__ (
ccf68e59 67 "%[val] <<= 1;"
68 "%[val] = %[val] & %[mask1];"
69 "%[val] = %[val] | %[mask2];"
70 : [val]"+d"(value)
71 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
72 : "ASTAT"
4328e3e5 73 );
6ef53066 74 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW
75
76 SPORT_PUT_TX(up, value);
77}
78
ccf68e59 79static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 80{
ccf68e59 81 unsigned int value;
82 unsigned char extract;
4328e3e5 83 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 84
ccf68e59 85 if ((up->csize + up->stopb) > 7)
86 value = SPORT_GET_RX32(up);
87 else
88 value = SPORT_GET_RX(up);
89
90 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
91 up->csize, up->rxmask);
2f351741 92
ccf68e59 93 /* Extract data */
4328e3e5
MF
94 __asm__ __volatile__ (
95 "%[extr] = 0;"
ccf68e59 96 "%[mask1] = %[rxmask];"
97 "%[mask2] = 0x0200(Z);"
4328e3e5
MF
98 "%[shift] = 0;"
99 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
100 ".Lloop_s:"
101 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
102 "%[tmp] <<= %[shift];"
103 "%[extr] = %[extr] | %[tmp];"
104 "%[mask1] = %[mask1] - %[mask2];"
105 ".Lloop_e:"
106 "%[shift] += 1;"
ccf68e59 107 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
108 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
109 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF
110 : "ASTAT", "LB0", "LC0", "LT0"
111 );
2f351741
BW
112
113 pr_debug(" extract:%x\n", extract);
114 return extract;
115}
116
ccf68e59 117static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 118{
ccf68e59 119 int tclkdiv, rclkdiv;
120 unsigned int sclk = get_sclk();
2f351741 121
ccf68e59 122 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
123 SPORT_PUT_TCR1(up, (ITFS | TLSBIT | ITCLK));
124 SPORT_PUT_TCR2(up, size + 1);
6ef53066 125 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW
126
127 /* Set RCR1 and RCR2 */
128 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 129 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 130 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 131
ccf68e59 132 tclkdiv = sclk / (2 * baud_rate) - 1;
133 rclkdiv = sclk / (2 * baud_rate * 2) - 1;
2f351741 134 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW
135 SPORT_PUT_RCLKDIV(up, rclkdiv);
136 SSYNC();
ccf68e59 137 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
138 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW
139
140 return 0;
141}
142
143static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
144{
145 struct sport_uart_port *up = dev_id;
ebd2c8f6 146 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW
147 unsigned int ch;
148
ccf68e59 149 spin_lock(&up->port.lock);
150
151 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW
152 ch = rx_one_byte(up);
153 up->port.icount.rx++;
154
ccf68e59 155 if (!uart_handle_sysrq_char(&up->port, ch))
2f351741 156 tty_insert_flip_char(tty, ch, TTY_NORMAL);
ccf68e59 157 }
2f351741
BW
158 tty_flip_buffer_push(tty);
159
ccf68e59 160 spin_unlock(&up->port.lock);
161
2f351741
BW
162 return IRQ_HANDLED;
163}
164
165static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
166{
ccf68e59 167 struct sport_uart_port *up = dev_id;
168
169 spin_lock(&up->port.lock);
170 sport_uart_tx_chars(up);
171 spin_unlock(&up->port.lock);
2f351741
BW
172
173 return IRQ_HANDLED;
174}
175
176static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
177{
178 struct sport_uart_port *up = dev_id;
ebd2c8f6 179 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW
180 unsigned int stat = SPORT_GET_STAT(up);
181
ccf68e59 182 spin_lock(&up->port.lock);
183
2f351741
BW
184 /* Overflow in RX FIFO */
185 if (stat & ROVF) {
186 up->port.icount.overrun++;
187 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
188 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
189 }
190 /* These should not happen */
191 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 192 pr_err("SPORT Error:%s %s %s\n",
193 (stat & TOVF) ? "TX overflow" : "",
194 (stat & TUVF) ? "TX underflow" : "",
195 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW
196 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
197 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
198 }
199 SSYNC();
200
ccf68e59 201 spin_unlock(&up->port.lock);
2f351741
BW
202 return IRQ_HANDLED;
203}
204
1f7d1c85
SZ
205#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
206static unsigned int sport_get_mctrl(struct uart_port *port)
207{
208 struct sport_uart_port *up = (struct sport_uart_port *)port;
209 if (up->cts_pin < 0)
210 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
211
212 /* CTS PIN is negative assertive. */
213 if (SPORT_UART_GET_CTS(up))
214 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
215 else
216 return TIOCM_DSR | TIOCM_CAR;
217}
218
219static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
220{
221 struct sport_uart_port *up = (struct sport_uart_port *)port;
222 if (up->rts_pin < 0)
223 return;
224
225 /* RTS PIN is negative assertive. */
226 if (mctrl & TIOCM_RTS)
227 SPORT_UART_ENABLE_RTS(up);
228 else
229 SPORT_UART_DISABLE_RTS(up);
230}
231
232/*
233 * Handle any change of modem status signal.
234 */
235static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
236{
237 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
238 unsigned int status;
239
240 status = sport_get_mctrl(&up->port);
241 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
242
243 return IRQ_HANDLED;
244}
245#else
246static unsigned int sport_get_mctrl(struct uart_port *port)
247{
248 pr_debug("%s enter\n", __func__);
249 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
250}
251
252static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
253{
254 pr_debug("%s enter\n", __func__);
255}
256#endif
257
2f351741
BW
258/* Reqeust IRQ, Setup clock */
259static int sport_startup(struct uart_port *port)
260{
261 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 262 int ret;
2f351741 263
6ef53066 264 pr_debug("%s enter\n", __func__);
ccf68e59 265 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
266 "SPORT_UART_RX", up);
267 if (ret) {
268 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
269 return ret;
2f351741
BW
270 }
271
ccf68e59 272 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
273 "SPORT_UART_TX", up);
274 if (ret) {
275 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW
276 goto fail1;
277 }
278
ccf68e59 279 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
280 "SPORT_UART_STATUS", up);
281 if (ret) {
282 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW
283 goto fail2;
284 }
285
1f7d1c85
SZ
286#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
287 if (up->cts_pin >= 0) {
288 if (request_irq(gpio_to_irq(up->cts_pin),
289 sport_mctrl_cts_int,
290 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
291 IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
292 up->cts_pin = -1;
293 dev_info(port->dev, "Unable to attach BlackFin UART \
294 over SPORT CTS interrupt. So, disable it.\n");
295 }
296 }
297 if (up->rts_pin >= 0)
298 gpio_direction_output(up->rts_pin, 0);
299#endif
300
2f351741 301 return 0;
ccf68e59 302 fail2:
303 free_irq(up->port.irq+1, up);
304 fail1:
305 free_irq(up->port.irq, up);
2f351741 306
ccf68e59 307 return ret;
2f351741
BW
308}
309
310static void sport_uart_tx_chars(struct sport_uart_port *up)
311{
ebd2c8f6 312 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW
313
314 if (SPORT_GET_STAT(up) & TXF)
315 return;
316
317 if (up->port.x_char) {
318 tx_one_byte(up, up->port.x_char);
319 up->port.icount.tx++;
320 up->port.x_char = 0;
321 return;
322 }
323
324 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
3f3a978b
SZ
325 /* The waiting loop to stop SPORT TX from TX interrupt is
326 * too long. This may block SPORT RX interrupts and cause
327 * RX FIFO overflow. So, do stop sport TX only after the last
328 * char in TX FIFO is moved into the shift register.
329 */
330 if (SPORT_GET_STAT(up) & TXHRE)
331 sport_stop_tx(&up->port);
2f351741
BW
332 return;
333 }
334
335 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
336 tx_one_byte(up, xmit->buf[xmit->tail]);
337 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
338 up->port.icount.tx++;
339 }
340
341 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
342 uart_write_wakeup(&up->port);
343}
344
345static unsigned int sport_tx_empty(struct uart_port *port)
346{
347 struct sport_uart_port *up = (struct sport_uart_port *)port;
348 unsigned int stat;
349
350 stat = SPORT_GET_STAT(up);
6ef53066 351 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW
352 if (stat & TXHRE) {
353 return TIOCSER_TEMT;
354 } else
355 return 0;
356}
357
2f351741
BW
358static void sport_stop_tx(struct uart_port *port)
359{
360 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 361
6ef53066 362 pr_debug("%s enter\n", __func__);
2f351741 363
2f351741 364 /* Although the hold register is empty, last byte is still in shift
ccf68e59 365 * register and not sent out yet. So, put a dummy data into TX FIFO.
366 * Then, sport tx stops when last byte is shift out and the dummy
367 * data is moved into the shift register.
368 */
369 SPORT_PUT_TX(up, 0xffff);
370 while (!(SPORT_GET_STAT(up) & TXHRE))
371 cpu_relax();
2f351741
BW
372
373 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
374 SSYNC();
375
376 return;
377}
378
379static void sport_start_tx(struct uart_port *port)
380{
381 struct sport_uart_port *up = (struct sport_uart_port *)port;
382
6ef53066 383 pr_debug("%s enter\n", __func__);
ccf68e59 384
2f351741
BW
385 /* Write data into SPORT FIFO before enable SPROT to transmit */
386 sport_uart_tx_chars(up);
387
388 /* Enable transmit, then an interrupt will generated */
389 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
390 SSYNC();
6ef53066 391 pr_debug("%s exit\n", __func__);
2f351741
BW
392}
393
394static void sport_stop_rx(struct uart_port *port)
395{
396 struct sport_uart_port *up = (struct sport_uart_port *)port;
397
6ef53066 398 pr_debug("%s enter\n", __func__);
2f351741
BW
399 /* Disable sport to stop rx */
400 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
401 SSYNC();
402}
403
404static void sport_enable_ms(struct uart_port *port)
405{
6ef53066 406 pr_debug("%s enter\n", __func__);
2f351741
BW
407}
408
409static void sport_break_ctl(struct uart_port *port, int break_state)
410{
6ef53066 411 pr_debug("%s enter\n", __func__);
2f351741
BW
412}
413
414static void sport_shutdown(struct uart_port *port)
415{
416 struct sport_uart_port *up = (struct sport_uart_port *)port;
417
ccf68e59 418 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW
419
420 /* Disable sport */
421 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
422 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
423 SSYNC();
424
ccf68e59 425 free_irq(up->port.irq, up);
426 free_irq(up->port.irq+1, up);
2f351741 427 free_irq(up->err_irq, up);
1f7d1c85
SZ
428#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
429 if (up->cts_pin >= 0)
430 free_irq(gpio_to_irq(up->cts_pin), up);
431#endif
2f351741
BW
432}
433
2f351741
BW
434static const char *sport_type(struct uart_port *port)
435{
436 struct sport_uart_port *up = (struct sport_uart_port *)port;
437
6ef53066 438 pr_debug("%s enter\n", __func__);
ccf68e59 439 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW
440}
441
442static void sport_release_port(struct uart_port *port)
443{
6ef53066 444 pr_debug("%s enter\n", __func__);
2f351741
BW
445}
446
447static int sport_request_port(struct uart_port *port)
448{
6ef53066 449 pr_debug("%s enter\n", __func__);
2f351741
BW
450 return 0;
451}
452
453static void sport_config_port(struct uart_port *port, int flags)
454{
455 struct sport_uart_port *up = (struct sport_uart_port *)port;
456
6ef53066 457 pr_debug("%s enter\n", __func__);
2f351741
BW
458 up->port.type = PORT_BFIN_SPORT;
459}
460
461static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
462{
6ef53066 463 pr_debug("%s enter\n", __func__);
2f351741
BW
464 return 0;
465}
466
ccf68e59 467static void sport_set_termios(struct uart_port *port,
468 struct ktermios *termios, struct ktermios *old)
469{
470 struct sport_uart_port *up = (struct sport_uart_port *)port;
471 unsigned long flags;
472 int i;
473
474 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
475
476 switch (termios->c_cflag & CSIZE) {
477 case CS8:
478 up->csize = 8;
479 break;
480 case CS7:
481 up->csize = 7;
482 break;
483 case CS6:
484 up->csize = 6;
485 break;
486 case CS5:
487 up->csize = 5;
488 break;
489 default:
490 pr_warning("requested word length not supported\n");
491 }
492
493 if (termios->c_cflag & CSTOPB) {
494 up->stopb = 1;
495 }
496 if (termios->c_cflag & PARENB) {
497 pr_warning("PAREN bits is not supported yet\n");
498 /* up->parib = 1; */
499 }
500
9498dc95
SZ
501 spin_lock_irqsave(&up->port.lock, flags);
502
ccf68e59 503 port->read_status_mask = OE;
504 if (termios->c_iflag & INPCK)
505 port->read_status_mask |= (FE | PE);
506 if (termios->c_iflag & (BRKINT | PARMRK))
507 port->read_status_mask |= BI;
508
509 /*
510 * Characters to ignore
511 */
512 port->ignore_status_mask = 0;
513 if (termios->c_iflag & IGNPAR)
514 port->ignore_status_mask |= FE | PE;
515 if (termios->c_iflag & IGNBRK) {
516 port->ignore_status_mask |= BI;
517 /*
518 * If we're ignoring parity and break indicators,
519 * ignore overruns too (for real raw support).
520 */
521 if (termios->c_iflag & IGNPAR)
522 port->ignore_status_mask |= OE;
523 }
524
525 /* RX extract mask */
526 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
527 /* TX masks, 8 bit data and 1 bit stop for example:
528 * mask1 = b#0111111110
529 * mask2 = b#1000000000
530 */
531 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
532 up->txmask1 |= (1<<i);
533 up->txmask2 = (1<<i);
534 if (up->stopb) {
535 ++i;
536 up->txmask2 |= (1<<i);
537 }
538 up->txmask1 <<= 1;
539 up->txmask2 <<= 1;
540 /* uart baud rate */
541 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
542
ccf68e59 543 /* Disable UART */
544 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
545 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
546
547 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
548
549 /* driver TX line high after config, one dummy data is
550 * necessary to stop sport after shift one byte
551 */
552 SPORT_PUT_TX(up, 0xffff);
553 SPORT_PUT_TX(up, 0xffff);
554 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
555 SSYNC();
556 while (!(SPORT_GET_STAT(up) & TXHRE))
557 cpu_relax();
558 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
559 SSYNC();
560
561 /* Port speed changed, update the per-port timeout. */
562 uart_update_timeout(port, termios->c_cflag, port->uartclk);
563
564 /* Enable sport rx */
565 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
566 SSYNC();
567
568 spin_unlock_irqrestore(&up->port.lock, flags);
569}
570
2f351741
BW
571struct uart_ops sport_uart_ops = {
572 .tx_empty = sport_tx_empty,
573 .set_mctrl = sport_set_mctrl,
574 .get_mctrl = sport_get_mctrl,
575 .stop_tx = sport_stop_tx,
576 .start_tx = sport_start_tx,
577 .stop_rx = sport_stop_rx,
578 .enable_ms = sport_enable_ms,
579 .break_ctl = sport_break_ctl,
580 .startup = sport_startup,
581 .shutdown = sport_shutdown,
582 .set_termios = sport_set_termios,
583 .type = sport_type,
584 .release_port = sport_release_port,
585 .request_port = sport_request_port,
586 .config_port = sport_config_port,
587 .verify_port = sport_verify_port,
588};
589
ccf68e59 590#define BFIN_SPORT_UART_MAX_PORTS 4
591
592static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
593
594#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
b59588aa
SZ
595#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
596
ccf68e59 597static int __init
598sport_uart_console_setup(struct console *co, char *options)
599{
600 struct sport_uart_port *up;
601 int baud = 57600;
602 int bits = 8;
603 int parity = 'n';
1f7d1c85
SZ
604# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
605 int flow = 'r';
606# else
ccf68e59 607 int flow = 'n';
1f7d1c85 608# endif
ccf68e59 609
610 /* Check whether an invalid uart number has been specified */
611 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
612 return -ENODEV;
613
614 up = bfin_sport_uart_ports[co->index];
615 if (!up)
616 return -ENODEV;
617
618 if (options)
619 uart_parse_options(options, &baud, &parity, &bits, &flow);
620
621 return uart_set_options(&up->port, co, baud, parity, bits, flow);
622}
623
624static void sport_uart_console_putchar(struct uart_port *port, int ch)
625{
626 struct sport_uart_port *up = (struct sport_uart_port *)port;
627
628 while (SPORT_GET_STAT(up) & TXF)
629 barrier();
630
631 tx_one_byte(up, ch);
632}
633
634/*
635 * Interrupts are disabled on entering
636 */
637static void
638sport_uart_console_write(struct console *co, const char *s, unsigned int count)
639{
640 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
641 unsigned long flags;
642
643 spin_lock_irqsave(&up->port.lock, flags);
644
645 if (SPORT_GET_TCR1(up) & TSPEN)
646 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
647 else {
648 /* dummy data to start sport */
649 while (SPORT_GET_STAT(up) & TXF)
650 barrier();
651 SPORT_PUT_TX(up, 0xffff);
652 /* Enable transmit, then an interrupt will generated */
653 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
654 SSYNC();
655
656 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
657
658 /* Although the hold register is empty, last byte is still in shift
659 * register and not sent out yet. So, put a dummy data into TX FIFO.
660 * Then, sport tx stops when last byte is shift out and the dummy
661 * data is moved into the shift register.
662 */
663 while (SPORT_GET_STAT(up) & TXF)
664 barrier();
665 SPORT_PUT_TX(up, 0xffff);
666 while (!(SPORT_GET_STAT(up) & TXHRE))
667 barrier();
668
669 /* Stop sport tx transfer */
670 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
671 SSYNC();
2f351741 672 }
ccf68e59 673
674 spin_unlock_irqrestore(&up->port.lock, flags);
675}
676
677static struct uart_driver sport_uart_reg;
678
679static struct console sport_uart_console = {
680 .name = DEVICE_NAME,
681 .write = sport_uart_console_write,
682 .device = uart_console_device,
683 .setup = sport_uart_console_setup,
684 .flags = CON_PRINTBUFFER,
685 .index = -1,
686 .data = &sport_uart_reg,
2f351741
BW
687};
688
ccf68e59 689#define SPORT_UART_CONSOLE (&sport_uart_console)
690#else
691#define SPORT_UART_CONSOLE NULL
692#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
693
694
2f351741
BW
695static struct uart_driver sport_uart_reg = {
696 .owner = THIS_MODULE,
ccf68e59 697 .driver_name = DRV_NAME,
698 .dev_name = DEVICE_NAME,
2f351741
BW
699 .major = 204,
700 .minor = 84,
ccf68e59 701 .nr = BFIN_SPORT_UART_MAX_PORTS,
702 .cons = SPORT_UART_CONSOLE,
2f351741
BW
703};
704
ccf68e59 705#ifdef CONFIG_PM
706static int sport_uart_suspend(struct device *dev)
2f351741 707{
ccf68e59 708 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 709
ccf68e59 710 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW
711 if (sport)
712 uart_suspend_port(&sport_uart_reg, &sport->port);
713
714 return 0;
715}
716
ccf68e59 717static int sport_uart_resume(struct device *dev)
2f351741 718{
ccf68e59 719 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 720
ccf68e59 721 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW
722 if (sport)
723 uart_resume_port(&sport_uart_reg, &sport->port);
724
725 return 0;
726}
727
ccf68e59 728static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
729 .suspend = sport_uart_suspend,
730 .resume = sport_uart_resume,
731};
732#endif
733
734static int __devinit sport_uart_probe(struct platform_device *pdev)
2f351741 735{
ccf68e59 736 struct resource *res;
737 struct sport_uart_port *sport;
738 int ret = 0;
2f351741 739
ccf68e59 740 dev_dbg(&pdev->dev, "%s enter\n", __func__);
741
742 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
743 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
744 return -ENOENT;
745 }
746
747 if (bfin_sport_uart_ports[pdev->id] == NULL) {
748 bfin_sport_uart_ports[pdev->id] =
749 kmalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
750 sport = bfin_sport_uart_ports[pdev->id];
751 if (!sport) {
752 dev_err(&pdev->dev,
753 "Fail to kmalloc sport_uart_port\n");
754 return -ENOMEM;
755 }
756
757 ret = peripheral_request_list(
758 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
759 if (ret) {
760 dev_err(&pdev->dev,
761 "Fail to request SPORT peripherals\n");
762 goto out_error_free_mem;
763 }
764
765 spin_lock_init(&sport->port.lock);
766 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
767 sport->port.ops = &sport_uart_ops;
768 sport->port.line = pdev->id;
769 sport->port.iotype = UPIO_MEM;
770 sport->port.flags = UPF_BOOT_AUTOCONF;
771
772 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
773 if (res == NULL) {
774 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
775 ret = -ENOENT;
776 goto out_error_free_peripherals;
777 }
778
779 sport->port.membase = ioremap(res->start,
780 res->end - res->start);
781 if (!sport->port.membase) {
782 dev_err(&pdev->dev, "Cannot map sport IO\n");
783 ret = -ENXIO;
784 goto out_error_free_peripherals;
785 }
e8126b32 786 sport->port.mapbase = res->start;
ccf68e59 787
788 sport->port.irq = platform_get_irq(pdev, 0);
789 if (sport->port.irq < 0) {
790 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
791 ret = -ENOENT;
792 goto out_error_unmap;
793 }
794
795 sport->err_irq = platform_get_irq(pdev, 1);
796 if (sport->err_irq < 0) {
797 dev_err(&pdev->dev, "No sport status IRQ specified\n");
798 ret = -ENOENT;
799 goto out_error_unmap;
800 }
1f7d1c85
SZ
801#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
802 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
803 if (res == NULL)
804 sport->cts_pin = -1;
805 else
806 sport->cts_pin = res->start;
807
808 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
809 if (res == NULL)
810 sport->rts_pin = -1;
811 else
812 sport->rts_pin = res->start;
813
814 if (sport->rts_pin >= 0)
815 gpio_request(sport->rts_pin, DRV_NAME);
816#endif
ccf68e59 817 }
818
819#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
820 if (!is_early_platform_device(pdev)) {
821#endif
822 sport = bfin_sport_uart_ports[pdev->id];
823 sport->port.dev = &pdev->dev;
824 dev_set_drvdata(&pdev->dev, sport);
825 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
826#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
827 }
828#endif
829 if (!ret)
830 return 0;
831
832 if (sport) {
833out_error_unmap:
834 iounmap(sport->port.membase);
835out_error_free_peripherals:
836 peripheral_free_list(
837 (unsigned short *)pdev->dev.platform_data);
838out_error_free_mem:
839 kfree(sport);
840 bfin_sport_uart_ports[pdev->id] = NULL;
841 }
842
843 return ret;
2f351741
BW
844}
845
ccf68e59 846static int __devexit sport_uart_remove(struct platform_device *pdev)
2f351741 847{
ccf68e59 848 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 849
ccf68e59 850 dev_dbg(&pdev->dev, "%s enter\n", __func__);
851 dev_set_drvdata(&pdev->dev, NULL);
2f351741 852
ccf68e59 853 if (sport) {
2f351741 854 uart_remove_one_port(&sport_uart_reg, &sport->port);
1f7d1c85
SZ
855#ifdef CONFIG_SERIAL_BFIN_CTSRTS
856 if (sport->rts_pin >= 0)
857 gpio_free(sport->rts_pin);
858#endif
ccf68e59 859 iounmap(sport->port.membase);
860 peripheral_free_list(
861 (unsigned short *)pdev->dev.platform_data);
862 kfree(sport);
863 bfin_sport_uart_ports[pdev->id] = NULL;
864 }
2f351741
BW
865
866 return 0;
867}
868
869static struct platform_driver sport_uart_driver = {
870 .probe = sport_uart_probe,
ccf68e59 871 .remove = __devexit_p(sport_uart_remove),
2f351741
BW
872 .driver = {
873 .name = DRV_NAME,
ccf68e59 874#ifdef CONFIG_PM
875 .pm = &bfin_sport_uart_dev_pm_ops,
876#endif
2f351741
BW
877 },
878};
879
ccf68e59 880#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
881static __initdata struct early_platform_driver early_sport_uart_driver = {
b59588aa 882 .class_str = CLASS_BFIN_SPORT_CONSOLE,
ccf68e59 883 .pdrv = &sport_uart_driver,
884 .requested_id = EARLY_PLATFORM_ID_UNSET,
885};
886
887static int __init sport_uart_rs_console_init(void)
888{
889 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
890
b59588aa
SZ
891 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
892 BFIN_SPORT_UART_MAX_PORTS, 0);
ccf68e59 893
894 register_console(&sport_uart_console);
895
896 return 0;
897}
898console_initcall(sport_uart_rs_console_init);
899#endif
900
2f351741
BW
901static int __init sport_uart_init(void)
902{
903 int ret;
904
e8126b32 905 pr_info("Blackfin uart over sport driver\n");
ccf68e59 906
2f351741 907 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 908 if (ret) {
909 pr_err("failed to register %s:%d\n",
2f351741
BW
910 sport_uart_reg.driver_name, ret);
911 return ret;
912 }
913
914 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 915 if (ret) {
916 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW
917 uart_unregister_driver(&sport_uart_reg);
918 }
919
2f351741
BW
920 return ret;
921}
ccf68e59 922module_init(sport_uart_init);
2f351741
BW
923
924static void __exit sport_uart_exit(void)
925{
2f351741
BW
926 platform_driver_unregister(&sport_uart_driver);
927 uart_unregister_driver(&sport_uart_reg);
928}
2f351741
BW
929module_exit(sport_uart_exit);
930
ccf68e59 931MODULE_AUTHOR("Sonic Zhang, Roy Huang");
932MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 933MODULE_LICENSE("GPL");