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Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[net-next-2.6.git] / drivers / serial / bfin_sport_uart.c
CommitLineData
2f351741 1/*
ccf68e59 2 * Blackfin On-Chip Sport Emulated UART Driver
2f351741 3 *
ccf68e59 4 * Copyright 2006-2009 Analog Devices Inc.
2f351741 5 *
ccf68e59 6 * Enter bugs at http://blackfin.uclinux.org/
2f351741 7 *
ccf68e59 8 * Licensed under the GPL-2 or later.
2f351741
BW		 9 */
10
11/*
12 * This driver and the hardware supported are in term of EE-191 of ADI.
631dd1a8 13 * http://www.analog.com/static/imported-files/application_notes/EE191.pdf
2f351741
BW		 14 * This application note describe how to implement a UART on a Sharc DSP,
15 * but this driver is implemented on Blackfin Processor.
ccf68e59 16 * Transmit Frame Sync is not used by this driver to transfer data out.
2f351741
BW		 17 */
18
ccf68e59 19/* #define DEBUG */
2f351741 20
ccf68e59 21#define DRV_NAME "bfin-sport-uart"
22#define DEVICE_NAME "ttySS"
23#define pr_fmt(fmt) DRV_NAME ": " fmt
2f351741
BW		 24
25#include <linux/module.h>
26#include <linux/ioport.h>
ccf68e59 27#include <linux/io.h>
2f351741
BW		 28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
5a0e3ad6 31#include <linux/slab.h>
2f351741
BW		 32#include <linux/platform_device.h>
33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_core.h>
36
2ce1efc9 37#include <asm/bfin_sport.h>
2f351741
BW		 38#include <asm/delay.h>
39#include <asm/portmux.h>
40
41#include "bfin_sport_uart.h"
42
2f351741
BW		 43struct sport_uart_port {
44 struct uart_port port;
2f351741 45 int err_irq;
ccf68e59 46 unsigned short csize;
47 unsigned short rxmask;
48 unsigned short txmask1;
49 unsigned short txmask2;
50 unsigned char stopb;
51/* unsigned char parib; */
1f7d1c85
SZ		 52#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
53 int cts_pin;
54 int rts_pin;
55#endif
2f351741
BW		 56};
57
9356c461 58static int sport_uart_tx_chars(struct sport_uart_port *up);
2f351741
BW		 59static void sport_stop_tx(struct uart_port *port);
60
61static inline void tx_one_byte(struct sport_uart_port *up, unsigned int value)
62{
ccf68e59 63 pr_debug("%s value:%x, mask1=0x%x, mask2=0x%x\n", __func__, value,
64 up->txmask1, up->txmask2);
65
66 /* Place Start and Stop bits */
4328e3e5 67 __asm__ __volatile__ (
ccf68e59 68 "%[val] <<= 1;"
69 "%[val] = %[val] & %[mask1];"
70 "%[val] = %[val] | %[mask2];"
71 : [val]"+d"(value)
72 : [mask1]"d"(up->txmask1), [mask2]"d"(up->txmask2)
73 : "ASTAT"
4328e3e5 74 );
6ef53066 75 pr_debug("%s value:%x\n", __func__, value);
2f351741
BW		 76
77 SPORT_PUT_TX(up, value);
78}
79
ccf68e59 80static inline unsigned char rx_one_byte(struct sport_uart_port *up)
2f351741 81{
ccf68e59 82 unsigned int value;
83 unsigned char extract;
4328e3e5 84 u32 tmp_mask1, tmp_mask2, tmp_shift, tmp;
2f351741 85
ccf68e59 86 if ((up->csize + up->stopb) > 7)
87 value = SPORT_GET_RX32(up);
88 else
89 value = SPORT_GET_RX(up);
90
91 pr_debug("%s value:%x, cs=%d, mask=0x%x\n", __func__, value,
92 up->csize, up->rxmask);
2f351741 93
ccf68e59 94 /* Extract data */
4328e3e5
MF		 95 __asm__ __volatile__ (
96 "%[extr] = 0;"
ccf68e59 97 "%[mask1] = %[rxmask];"
98 "%[mask2] = 0x0200(Z);"
4328e3e5
MF		 99 "%[shift] = 0;"
100 "LSETUP(.Lloop_s, .Lloop_e) LC0 = %[lc];"
101 ".Lloop_s:"
102 "%[tmp] = extract(%[val], %[mask1].L)(Z);"
103 "%[tmp] <<= %[shift];"
104 "%[extr] = %[extr] | %[tmp];"
105 "%[mask1] = %[mask1] - %[mask2];"
106 ".Lloop_e:"
107 "%[shift] += 1;"
ccf68e59 108 : [extr]"=&d"(extract), [shift]"=&d"(tmp_shift), [tmp]"=&d"(tmp),
109 [mask1]"=&d"(tmp_mask1), [mask2]"=&d"(tmp_mask2)
110 : [val]"d"(value), [rxmask]"d"(up->rxmask), [lc]"a"(up->csize)
4328e3e5
MF		 111 : "ASTAT", "LB0", "LC0", "LT0"
112 );
2f351741
BW		 113
114 pr_debug(" extract:%x\n", extract);
115 return extract;
116}
117
ccf68e59 118static int sport_uart_setup(struct sport_uart_port *up, int size, int baud_rate)
2f351741 119{
ccf68e59 120 int tclkdiv, rclkdiv;
121 unsigned int sclk = get_sclk();
2f351741 122
ccf68e59 123 /* Set TCR1 and TCR2, TFSR is not enabled for uart */
33674691 124 SPORT_PUT_TCR1(up, (LATFS | ITFS | TFSR | TLSBIT | ITCLK));
ccf68e59 125 SPORT_PUT_TCR2(up, size + 1);
6ef53066 126 pr_debug("%s TCR1:%x, TCR2:%x\n", __func__, SPORT_GET_TCR1(up), SPORT_GET_TCR2(up));
2f351741
BW		 127
128 /* Set RCR1 and RCR2 */
129 SPORT_PUT_RCR1(up, (RCKFE | LARFS | LRFS | RFSR | IRCLK));
ccf68e59 130 SPORT_PUT_RCR2(up, (size + 1) * 2 - 1);
6ef53066 131 pr_debug("%s RCR1:%x, RCR2:%x\n", __func__, SPORT_GET_RCR1(up), SPORT_GET_RCR2(up));
2f351741 132
ccf68e59 133 tclkdiv = sclk / (2 * baud_rate) - 1;
0dd25df1
SZ		 134 /* The actual uart baud rate of devices vary between +/-2%. The sport
135 * RX sample rate should be faster than the double of the worst case,
136 * otherwise, wrong data are received. So, set sport RX clock to be
137 * 3% faster.
138 */
139 rclkdiv = sclk / (2 * baud_rate * 2 * 97 / 100) - 1;
2f351741 140 SPORT_PUT_TCLKDIV(up, tclkdiv);
2f351741
BW		 141 SPORT_PUT_RCLKDIV(up, rclkdiv);
142 SSYNC();
ccf68e59 143 pr_debug("%s sclk:%d, baud_rate:%d, tclkdiv:%d, rclkdiv:%d\n",
144 __func__, sclk, baud_rate, tclkdiv, rclkdiv);
2f351741
BW		 145
146 return 0;
147}
148
149static irqreturn_t sport_uart_rx_irq(int irq, void *dev_id)
150{
151 struct sport_uart_port *up = dev_id;
ebd2c8f6 152 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 153 unsigned int ch;
154
ccf68e59 155 spin_lock(&up->port.lock);
156
157 while (SPORT_GET_STAT(up) & RXNE) {
2f351741
BW		 158 ch = rx_one_byte(up);
159 up->port.icount.rx++;
160
ccf68e59 161 if (!uart_handle_sysrq_char(&up->port, ch))
2f351741 162 tty_insert_flip_char(tty, ch, TTY_NORMAL);
ccf68e59 163 }
2f351741
BW		 164 tty_flip_buffer_push(tty);
165
ccf68e59 166 spin_unlock(&up->port.lock);
167
2f351741
BW		 168 return IRQ_HANDLED;
169}
170
171static irqreturn_t sport_uart_tx_irq(int irq, void *dev_id)
172{
ccf68e59 173 struct sport_uart_port *up = dev_id;
174
175 spin_lock(&up->port.lock);
176 sport_uart_tx_chars(up);
177 spin_unlock(&up->port.lock);
2f351741
BW		 178
179 return IRQ_HANDLED;
180}
181
182static irqreturn_t sport_uart_err_irq(int irq, void *dev_id)
183{
184 struct sport_uart_port *up = dev_id;
ebd2c8f6 185 struct tty_struct *tty = up->port.state->port.tty;
2f351741
BW		 186 unsigned int stat = SPORT_GET_STAT(up);
187
ccf68e59 188 spin_lock(&up->port.lock);
189
2f351741
BW		 190 /* Overflow in RX FIFO */
191 if (stat & ROVF) {
192 up->port.icount.overrun++;
193 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
194 SPORT_PUT_STAT(up, ROVF); /* Clear ROVF bit */
195 }
196 /* These should not happen */
197 if (stat & (TOVF | TUVF | RUVF)) {
ccf68e59 198 pr_err("SPORT Error:%s %s %s\n",
199 (stat & TOVF) ? "TX overflow" : "",
200 (stat & TUVF) ? "TX underflow" : "",
201 (stat & RUVF) ? "RX underflow" : "");
2f351741
BW		 202 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
203 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
204 }
205 SSYNC();
206
ccf68e59 207 spin_unlock(&up->port.lock);
2f351741
BW		 208 return IRQ_HANDLED;
209}
210
1f7d1c85
SZ		 211#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
212static unsigned int sport_get_mctrl(struct uart_port *port)
213{
214 struct sport_uart_port *up = (struct sport_uart_port *)port;
215 if (up->cts_pin < 0)
216 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
217
218 /* CTS PIN is negative assertive. */
219 if (SPORT_UART_GET_CTS(up))
220 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
221 else
222 return TIOCM_DSR | TIOCM_CAR;
223}
224
225static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
226{
227 struct sport_uart_port *up = (struct sport_uart_port *)port;
228 if (up->rts_pin < 0)
229 return;
230
231 /* RTS PIN is negative assertive. */
232 if (mctrl & TIOCM_RTS)
233 SPORT_UART_ENABLE_RTS(up);
234 else
235 SPORT_UART_DISABLE_RTS(up);
236}
237
238/*
239 * Handle any change of modem status signal.
240 */
241static irqreturn_t sport_mctrl_cts_int(int irq, void *dev_id)
242{
243 struct sport_uart_port *up = (struct sport_uart_port *)dev_id;
244 unsigned int status;
245
246 status = sport_get_mctrl(&up->port);
247 uart_handle_cts_change(&up->port, status & TIOCM_CTS);
248
249 return IRQ_HANDLED;
250}
251#else
252static unsigned int sport_get_mctrl(struct uart_port *port)
253{
254 pr_debug("%s enter\n", __func__);
255 return TIOCM_CTS | TIOCM_CD | TIOCM_DSR;
256}
257
258static void sport_set_mctrl(struct uart_port *port, unsigned int mctrl)
259{
260 pr_debug("%s enter\n", __func__);
261}
262#endif
263
2f351741
BW		 264/* Reqeust IRQ, Setup clock */
265static int sport_startup(struct uart_port *port)
266{
267 struct sport_uart_port *up = (struct sport_uart_port *)port;
ccf68e59 268 int ret;
2f351741 269
6ef53066 270 pr_debug("%s enter\n", __func__);
ccf68e59 271 ret = request_irq(up->port.irq, sport_uart_rx_irq, 0,
272 "SPORT_UART_RX", up);
273 if (ret) {
274 dev_err(port->dev, "unable to request SPORT RX interrupt\n");
275 return ret;
2f351741
BW		 276 }
277
ccf68e59 278 ret = request_irq(up->port.irq+1, sport_uart_tx_irq, 0,
279 "SPORT_UART_TX", up);
280 if (ret) {
281 dev_err(port->dev, "unable to request SPORT TX interrupt\n");
2f351741
BW		 282 goto fail1;
283 }
284
ccf68e59 285 ret = request_irq(up->err_irq, sport_uart_err_irq, 0,
286 "SPORT_UART_STATUS", up);
287 if (ret) {
288 dev_err(port->dev, "unable to request SPORT status interrupt\n");
2f351741
BW		 289 goto fail2;
290 }
291
1f7d1c85
SZ		 292#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
293 if (up->cts_pin >= 0) {
294 if (request_irq(gpio_to_irq(up->cts_pin),
295 sport_mctrl_cts_int,
296 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
297 IRQF_DISABLED, "BFIN_SPORT_UART_CTS", up)) {
298 up->cts_pin = -1;
299 dev_info(port->dev, "Unable to attach BlackFin UART \
300 over SPORT CTS interrupt. So, disable it.\n");
301 }
302 }
303 if (up->rts_pin >= 0)
304 gpio_direction_output(up->rts_pin, 0);
305#endif
306
2f351741 307 return 0;
ccf68e59 308 fail2:
309 free_irq(up->port.irq+1, up);
310 fail1:
311 free_irq(up->port.irq, up);
2f351741 312
ccf68e59 313 return ret;
2f351741
BW		 314}
315
9356c461
SZ		 316/*
317 * sport_uart_tx_chars
318 *
319 * ret 1 means need to enable sport.
320 * ret 0 means do nothing.
321 */
322static int sport_uart_tx_chars(struct sport_uart_port *up)
2f351741 323{
ebd2c8f6 324 struct circ_buf *xmit = &up->port.state->xmit;
2f351741
BW		 325
326 if (SPORT_GET_STAT(up) & TXF)
9356c461 327 return 0;
2f351741
BW		 328
329 if (up->port.x_char) {
330 tx_one_byte(up, up->port.x_char);
331 up->port.icount.tx++;
332 up->port.x_char = 0;
9356c461 333 return 1;
2f351741
BW		 334 }
335
336 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
3f3a978b
SZ		 337 /* The waiting loop to stop SPORT TX from TX interrupt is
338 * too long. This may block SPORT RX interrupts and cause
339 * RX FIFO overflow. So, do stop sport TX only after the last
340 * char in TX FIFO is moved into the shift register.
341 */
342 if (SPORT_GET_STAT(up) & TXHRE)
343 sport_stop_tx(&up->port);
9356c461 344 return 0;
2f351741
BW		 345 }
346
347 while(!(SPORT_GET_STAT(up) & TXF) && !uart_circ_empty(xmit)) {
348 tx_one_byte(up, xmit->buf[xmit->tail]);
349 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE -1);
350 up->port.icount.tx++;
351 }
352
353 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
354 uart_write_wakeup(&up->port);
9356c461
SZ		 355
356 return 1;
2f351741
BW		 357}
358
359static unsigned int sport_tx_empty(struct uart_port *port)
360{
361 struct sport_uart_port *up = (struct sport_uart_port *)port;
362 unsigned int stat;
363
364 stat = SPORT_GET_STAT(up);
6ef53066 365 pr_debug("%s stat:%04x\n", __func__, stat);
2f351741
BW		 366 if (stat & TXHRE) {
367 return TIOCSER_TEMT;
368 } else
369 return 0;
370}
371
2f351741
BW		 372static void sport_stop_tx(struct uart_port *port)
373{
374 struct sport_uart_port *up = (struct sport_uart_port *)port;
2f351741 375
6ef53066 376 pr_debug("%s enter\n", __func__);
2f351741 377
9356c461
SZ		 378 if (!(SPORT_GET_TCR1(up) & TSPEN))
379 return;
380
2f351741 381 /* Although the hold register is empty, last byte is still in shift
ccf68e59 382 * register and not sent out yet. So, put a dummy data into TX FIFO.
383 * Then, sport tx stops when last byte is shift out and the dummy
384 * data is moved into the shift register.
385 */
386 SPORT_PUT_TX(up, 0xffff);
387 while (!(SPORT_GET_STAT(up) & TXHRE))
388 cpu_relax();
2f351741
BW		 389
390 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
391 SSYNC();
392
393 return;
394}
395
396static void sport_start_tx(struct uart_port *port)
397{
398 struct sport_uart_port *up = (struct sport_uart_port *)port;
399
6ef53066 400 pr_debug("%s enter\n", __func__);
ccf68e59 401
2f351741 402 /* Write data into SPORT FIFO before enable SPROT to transmit */
9356c461
SZ		 403 if (sport_uart_tx_chars(up)) {
404 /* Enable transmit, then an interrupt will generated */
405 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
406 SSYNC();
407 }
2f351741 408
6ef53066 409 pr_debug("%s exit\n", __func__);
2f351741
BW		 410}
411
412static void sport_stop_rx(struct uart_port *port)
413{
414 struct sport_uart_port *up = (struct sport_uart_port *)port;
415
6ef53066 416 pr_debug("%s enter\n", __func__);
2f351741
BW		 417 /* Disable sport to stop rx */
418 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
419 SSYNC();
420}
421
422static void sport_enable_ms(struct uart_port *port)
423{
6ef53066 424 pr_debug("%s enter\n", __func__);
2f351741
BW		 425}
426
427static void sport_break_ctl(struct uart_port *port, int break_state)
428{
6ef53066 429 pr_debug("%s enter\n", __func__);
2f351741
BW		 430}
431
432static void sport_shutdown(struct uart_port *port)
433{
434 struct sport_uart_port *up = (struct sport_uart_port *)port;
435
ccf68e59 436 dev_dbg(port->dev, "%s enter\n", __func__);
2f351741
BW		 437
438 /* Disable sport */
439 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
440 SPORT_PUT_RCR1(up, (SPORT_GET_RCR1(up) & ~RSPEN));
441 SSYNC();
442
ccf68e59 443 free_irq(up->port.irq, up);
444 free_irq(up->port.irq+1, up);
2f351741 445 free_irq(up->err_irq, up);
1f7d1c85
SZ		 446#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
447 if (up->cts_pin >= 0)
448 free_irq(gpio_to_irq(up->cts_pin), up);
449#endif
2f351741
BW		 450}
451
2f351741
BW		 452static const char *sport_type(struct uart_port *port)
453{
454 struct sport_uart_port *up = (struct sport_uart_port *)port;
455
6ef53066 456 pr_debug("%s enter\n", __func__);
ccf68e59 457 return up->port.type == PORT_BFIN_SPORT ? "BFIN-SPORT-UART" : NULL;
2f351741
BW		 458}
459
460static void sport_release_port(struct uart_port *port)
461{
6ef53066 462 pr_debug("%s enter\n", __func__);
2f351741
BW		 463}
464
465static int sport_request_port(struct uart_port *port)
466{
6ef53066 467 pr_debug("%s enter\n", __func__);
2f351741
BW		 468 return 0;
469}
470
471static void sport_config_port(struct uart_port *port, int flags)
472{
473 struct sport_uart_port *up = (struct sport_uart_port *)port;
474
6ef53066 475 pr_debug("%s enter\n", __func__);
2f351741
BW		 476 up->port.type = PORT_BFIN_SPORT;
477}
478
479static int sport_verify_port(struct uart_port *port, struct serial_struct *ser)
480{
6ef53066 481 pr_debug("%s enter\n", __func__);
2f351741
BW		 482 return 0;
483}
484
ccf68e59 485static void sport_set_termios(struct uart_port *port,
486 struct ktermios *termios, struct ktermios *old)
487{
488 struct sport_uart_port *up = (struct sport_uart_port *)port;
489 unsigned long flags;
490 int i;
491
492 pr_debug("%s enter, c_cflag:%08x\n", __func__, termios->c_cflag);
493
494 switch (termios->c_cflag & CSIZE) {
495 case CS8:
496 up->csize = 8;
497 break;
498 case CS7:
499 up->csize = 7;
500 break;
501 case CS6:
502 up->csize = 6;
503 break;
504 case CS5:
505 up->csize = 5;
506 break;
507 default:
508 pr_warning("requested word length not supported\n");
509 }
510
511 if (termios->c_cflag & CSTOPB) {
512 up->stopb = 1;
513 }
514 if (termios->c_cflag & PARENB) {
515 pr_warning("PAREN bits is not supported yet\n");
516 /* up->parib = 1; */
517 }
518
9498dc95
SZ		 519 spin_lock_irqsave(&up->port.lock, flags);
520
60bd940f 521 port->read_status_mask = 0;
ccf68e59 522
523 /*
524 * Characters to ignore
525 */
526 port->ignore_status_mask = 0;
ccf68e59 527
528 /* RX extract mask */
529 up->rxmask = 0x01 | (((up->csize + up->stopb) * 2 - 1) << 0x8);
530 /* TX masks, 8 bit data and 1 bit stop for example:
531 * mask1 = b#0111111110
532 * mask2 = b#1000000000
533 */
534 for (i = 0, up->txmask1 = 0; i < up->csize; i++)
535 up->txmask1 |= (1<<i);
536 up->txmask2 = (1<<i);
537 if (up->stopb) {
538 ++i;
539 up->txmask2 |= (1<<i);
540 }
541 up->txmask1 <<= 1;
542 up->txmask2 <<= 1;
543 /* uart baud rate */
544 port->uartclk = uart_get_baud_rate(port, termios, old, 0, get_sclk()/16);
545
ccf68e59 546 /* Disable UART */
547 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
548 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) & ~RSPEN);
549
550 sport_uart_setup(up, up->csize + up->stopb, port->uartclk);
551
552 /* driver TX line high after config, one dummy data is
553 * necessary to stop sport after shift one byte
554 */
555 SPORT_PUT_TX(up, 0xffff);
556 SPORT_PUT_TX(up, 0xffff);
557 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
558 SSYNC();
559 while (!(SPORT_GET_STAT(up) & TXHRE))
560 cpu_relax();
561 SPORT_PUT_TCR1(up, SPORT_GET_TCR1(up) & ~TSPEN);
562 SSYNC();
563
564 /* Port speed changed, update the per-port timeout. */
565 uart_update_timeout(port, termios->c_cflag, port->uartclk);
566
567 /* Enable sport rx */
568 SPORT_PUT_RCR1(up, SPORT_GET_RCR1(up) | RSPEN);
569 SSYNC();
570
571 spin_unlock_irqrestore(&up->port.lock, flags);
572}
573
2f351741
BW		 574struct uart_ops sport_uart_ops = {
575 .tx_empty = sport_tx_empty,
576 .set_mctrl = sport_set_mctrl,
577 .get_mctrl = sport_get_mctrl,
578 .stop_tx = sport_stop_tx,
579 .start_tx = sport_start_tx,
580 .stop_rx = sport_stop_rx,
581 .enable_ms = sport_enable_ms,
582 .break_ctl = sport_break_ctl,
583 .startup = sport_startup,
584 .shutdown = sport_shutdown,
585 .set_termios = sport_set_termios,
586 .type = sport_type,
587 .release_port = sport_release_port,
588 .request_port = sport_request_port,
589 .config_port = sport_config_port,
590 .verify_port = sport_verify_port,
591};
592
ccf68e59 593#define BFIN_SPORT_UART_MAX_PORTS 4
594
595static struct sport_uart_port *bfin_sport_uart_ports[BFIN_SPORT_UART_MAX_PORTS];
596
597#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
b59588aa
SZ		 598#define CLASS_BFIN_SPORT_CONSOLE "bfin-sport-console"
599
ccf68e59 600static int __init
601sport_uart_console_setup(struct console *co, char *options)
602{
603 struct sport_uart_port *up;
604 int baud = 57600;
605 int bits = 8;
606 int parity = 'n';
1f7d1c85
SZ		 607# ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
608 int flow = 'r';
609# else
ccf68e59 610 int flow = 'n';
1f7d1c85 611# endif
ccf68e59 612
613 /* Check whether an invalid uart number has been specified */
614 if (co->index < 0 || co->index >= BFIN_SPORT_UART_MAX_PORTS)
615 return -ENODEV;
616
617 up = bfin_sport_uart_ports[co->index];
618 if (!up)
619 return -ENODEV;
620
621 if (options)
622 uart_parse_options(options, &baud, &parity, &bits, &flow);
623
624 return uart_set_options(&up->port, co, baud, parity, bits, flow);
625}
626
627static void sport_uart_console_putchar(struct uart_port *port, int ch)
628{
629 struct sport_uart_port *up = (struct sport_uart_port *)port;
630
631 while (SPORT_GET_STAT(up) & TXF)
632 barrier();
633
634 tx_one_byte(up, ch);
635}
636
637/*
638 * Interrupts are disabled on entering
639 */
640static void
641sport_uart_console_write(struct console *co, const char *s, unsigned int count)
642{
643 struct sport_uart_port *up = bfin_sport_uart_ports[co->index];
644 unsigned long flags;
645
646 spin_lock_irqsave(&up->port.lock, flags);
647
648 if (SPORT_GET_TCR1(up) & TSPEN)
649 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
650 else {
651 /* dummy data to start sport */
652 while (SPORT_GET_STAT(up) & TXF)
653 barrier();
654 SPORT_PUT_TX(up, 0xffff);
655 /* Enable transmit, then an interrupt will generated */
656 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) | TSPEN));
657 SSYNC();
658
659 uart_console_write(&up->port, s, count, sport_uart_console_putchar);
660
661 /* Although the hold register is empty, last byte is still in shift
662 * register and not sent out yet. So, put a dummy data into TX FIFO.
663 * Then, sport tx stops when last byte is shift out and the dummy
664 * data is moved into the shift register.
665 */
666 while (SPORT_GET_STAT(up) & TXF)
667 barrier();
668 SPORT_PUT_TX(up, 0xffff);
669 while (!(SPORT_GET_STAT(up) & TXHRE))
670 barrier();
671
672 /* Stop sport tx transfer */
673 SPORT_PUT_TCR1(up, (SPORT_GET_TCR1(up) & ~TSPEN));
674 SSYNC();
2f351741 675 }
ccf68e59 676
677 spin_unlock_irqrestore(&up->port.lock, flags);
678}
679
680static struct uart_driver sport_uart_reg;
681
682static struct console sport_uart_console = {
683 .name = DEVICE_NAME,
684 .write = sport_uart_console_write,
685 .device = uart_console_device,
686 .setup = sport_uart_console_setup,
687 .flags = CON_PRINTBUFFER,
688 .index = -1,
689 .data = &sport_uart_reg,
2f351741
BW		 690};
691
ccf68e59 692#define SPORT_UART_CONSOLE (&sport_uart_console)
693#else
694#define SPORT_UART_CONSOLE NULL
695#endif /* CONFIG_SERIAL_BFIN_SPORT_CONSOLE */
696
697
2f351741
BW		 698static struct uart_driver sport_uart_reg = {
699 .owner = THIS_MODULE,
ccf68e59 700 .driver_name = DRV_NAME,
701 .dev_name = DEVICE_NAME,
2f351741
BW		 702 .major = 204,
703 .minor = 84,
ccf68e59 704 .nr = BFIN_SPORT_UART_MAX_PORTS,
705 .cons = SPORT_UART_CONSOLE,
2f351741
BW		 706};
707
ccf68e59 708#ifdef CONFIG_PM
709static int sport_uart_suspend(struct device *dev)
2f351741 710{
ccf68e59 711 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 712
ccf68e59 713 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 714 if (sport)
715 uart_suspend_port(&sport_uart_reg, &sport->port);
716
717 return 0;
718}
719
ccf68e59 720static int sport_uart_resume(struct device *dev)
2f351741 721{
ccf68e59 722 struct sport_uart_port *sport = dev_get_drvdata(dev);
2f351741 723
ccf68e59 724 dev_dbg(dev, "%s enter\n", __func__);
2f351741
BW		 725 if (sport)
726 uart_resume_port(&sport_uart_reg, &sport->port);
727
728 return 0;
729}
730
ccf68e59 731static struct dev_pm_ops bfin_sport_uart_dev_pm_ops = {
732 .suspend = sport_uart_suspend,
733 .resume = sport_uart_resume,
734};
735#endif
736
737static int __devinit sport_uart_probe(struct platform_device *pdev)
2f351741 738{
ccf68e59 739 struct resource *res;
740 struct sport_uart_port *sport;
741 int ret = 0;
2f351741 742
ccf68e59 743 dev_dbg(&pdev->dev, "%s enter\n", __func__);
744
745 if (pdev->id < 0 || pdev->id >= BFIN_SPORT_UART_MAX_PORTS) {
746 dev_err(&pdev->dev, "Wrong sport uart platform device id.\n");
747 return -ENOENT;
748 }
749
750 if (bfin_sport_uart_ports[pdev->id] == NULL) {
751 bfin_sport_uart_ports[pdev->id] =
f4d10ca8 752 kzalloc(sizeof(struct sport_uart_port), GFP_KERNEL);
ccf68e59 753 sport = bfin_sport_uart_ports[pdev->id];
754 if (!sport) {
755 dev_err(&pdev->dev,
f4d10ca8 756 "Fail to malloc sport_uart_port\n");
ccf68e59 757 return -ENOMEM;
758 }
759
760 ret = peripheral_request_list(
761 (unsigned short *)pdev->dev.platform_data, DRV_NAME);
762 if (ret) {
763 dev_err(&pdev->dev,
764 "Fail to request SPORT peripherals\n");
765 goto out_error_free_mem;
766 }
767
768 spin_lock_init(&sport->port.lock);
769 sport->port.fifosize = SPORT_TX_FIFO_SIZE,
770 sport->port.ops = &sport_uart_ops;
771 sport->port.line = pdev->id;
772 sport->port.iotype = UPIO_MEM;
773 sport->port.flags = UPF_BOOT_AUTOCONF;
774
775 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
776 if (res == NULL) {
777 dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
778 ret = -ENOENT;
779 goto out_error_free_peripherals;
780 }
781
e114474c 782 sport->port.membase = ioremap(res->start, resource_size(res));
ccf68e59 783 if (!sport->port.membase) {
784 dev_err(&pdev->dev, "Cannot map sport IO\n");
785 ret = -ENXIO;
786 goto out_error_free_peripherals;
787 }
e8126b32 788 sport->port.mapbase = res->start;
ccf68e59 789
790 sport->port.irq = platform_get_irq(pdev, 0);
791 if (sport->port.irq < 0) {
792 dev_err(&pdev->dev, "No sport RX/TX IRQ specified\n");
793 ret = -ENOENT;
794 goto out_error_unmap;
795 }
796
797 sport->err_irq = platform_get_irq(pdev, 1);
798 if (sport->err_irq < 0) {
799 dev_err(&pdev->dev, "No sport status IRQ specified\n");
800 ret = -ENOENT;
801 goto out_error_unmap;
802 }
1f7d1c85
SZ		 803#ifdef CONFIG_SERIAL_BFIN_SPORT_CTSRTS
804 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
805 if (res == NULL)
806 sport->cts_pin = -1;
807 else
808 sport->cts_pin = res->start;
809
810 res = platform_get_resource(pdev, IORESOURCE_IO, 1);
811 if (res == NULL)
812 sport->rts_pin = -1;
813 else
814 sport->rts_pin = res->start;
815
816 if (sport->rts_pin >= 0)
817 gpio_request(sport->rts_pin, DRV_NAME);
818#endif
ccf68e59 819 }
820
821#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
822 if (!is_early_platform_device(pdev)) {
823#endif
824 sport = bfin_sport_uart_ports[pdev->id];
825 sport->port.dev = &pdev->dev;
826 dev_set_drvdata(&pdev->dev, sport);
827 ret = uart_add_one_port(&sport_uart_reg, &sport->port);
828#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
829 }
830#endif
831 if (!ret)
832 return 0;
833
834 if (sport) {
835out_error_unmap:
836 iounmap(sport->port.membase);
837out_error_free_peripherals:
838 peripheral_free_list(
839 (unsigned short *)pdev->dev.platform_data);
840out_error_free_mem:
841 kfree(sport);
842 bfin_sport_uart_ports[pdev->id] = NULL;
843 }
844
845 return ret;
2f351741
BW		 846}
847
ccf68e59 848static int __devexit sport_uart_remove(struct platform_device *pdev)
2f351741 849{
ccf68e59 850 struct sport_uart_port *sport = platform_get_drvdata(pdev);
2f351741 851
ccf68e59 852 dev_dbg(&pdev->dev, "%s enter\n", __func__);
853 dev_set_drvdata(&pdev->dev, NULL);
2f351741 854
ccf68e59 855 if (sport) {
2f351741 856 uart_remove_one_port(&sport_uart_reg, &sport->port);
1f7d1c85
SZ		 857#ifdef CONFIG_SERIAL_BFIN_CTSRTS
858 if (sport->rts_pin >= 0)
859 gpio_free(sport->rts_pin);
860#endif
ccf68e59 861 iounmap(sport->port.membase);
862 peripheral_free_list(
863 (unsigned short *)pdev->dev.platform_data);
864 kfree(sport);
865 bfin_sport_uart_ports[pdev->id] = NULL;
866 }
2f351741
BW		 867
868 return 0;
869}
870
871static struct platform_driver sport_uart_driver = {
872 .probe = sport_uart_probe,
ccf68e59 873 .remove = __devexit_p(sport_uart_remove),
2f351741
BW		 874 .driver = {
875 .name = DRV_NAME,
ccf68e59 876#ifdef CONFIG_PM
877 .pm = &bfin_sport_uart_dev_pm_ops,
878#endif
2f351741
BW		 879 },
880};
881
ccf68e59 882#ifdef CONFIG_SERIAL_BFIN_SPORT_CONSOLE
883static __initdata struct early_platform_driver early_sport_uart_driver = {
b59588aa 884 .class_str = CLASS_BFIN_SPORT_CONSOLE,
ccf68e59 885 .pdrv = &sport_uart_driver,
886 .requested_id = EARLY_PLATFORM_ID_UNSET,
887};
888
889static int __init sport_uart_rs_console_init(void)
890{
891 early_platform_driver_register(&early_sport_uart_driver, DRV_NAME);
892
b59588aa
SZ		 893 early_platform_driver_probe(CLASS_BFIN_SPORT_CONSOLE,
894 BFIN_SPORT_UART_MAX_PORTS, 0);
ccf68e59 895
896 register_console(&sport_uart_console);
897
898 return 0;
899}
900console_initcall(sport_uart_rs_console_init);
901#endif
902
2f351741
BW		 903static int __init sport_uart_init(void)
904{
905 int ret;
906
e8126b32 907 pr_info("Blackfin uart over sport driver\n");
ccf68e59 908
2f351741 909 ret = uart_register_driver(&sport_uart_reg);
ccf68e59 910 if (ret) {
911 pr_err("failed to register %s:%d\n",
2f351741
BW		 912 sport_uart_reg.driver_name, ret);
913 return ret;
914 }
915
916 ret = platform_driver_register(&sport_uart_driver);
ccf68e59 917 if (ret) {
918 pr_err("failed to register sport uart driver:%d\n", ret);
2f351741
BW		 919 uart_unregister_driver(&sport_uart_reg);
920 }
921
2f351741
BW		 922 return ret;
923}
ccf68e59 924module_init(sport_uart_init);
2f351741
BW		 925
926static void __exit sport_uart_exit(void)
927{
2f351741
BW		 928 platform_driver_unregister(&sport_uart_driver);
929 uart_unregister_driver(&sport_uart_reg);
930}
2f351741
BW		 931module_exit(sport_uart_exit);
932
ccf68e59 933MODULE_AUTHOR("Sonic Zhang, Roy Huang");
934MODULE_DESCRIPTION("Blackfin serial over SPORT driver");
2f351741 935MODULE_LICENSE("GPL");
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