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[Blackfin] arch: kill section mismatch warnings
[net-next-2.6.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561
BW		 1/*
2 * File: drivers/serial/bfin_5xx.c
3 * Based on: Based on drivers/serial/sa1100.c
4 * Author: Aubrey Li <aubrey.li@analog.com>
5 *
6 * Created:
7 * Description: Driver for blackfin 5xx serial ports
8 *
194de561
BW		 9 * Modified:
10 * Copyright 2006 Analog Devices Inc.
11 *
12 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, see the file COPYING, or write
26 * to the Free Software Foundation, Inc.,
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */
29
30#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
39#include <linux/platform_device.h>
40#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43
474f1a66
SZ		 44#ifdef CONFIG_KGDB_UART
45#include <linux/kgdb.h>
46#include <asm/irq_regs.h>
47#endif
48
194de561
BW		 49#include <asm/gpio.h>
50#include <asm/mach/bfin_serial_5xx.h>
51
52#ifdef CONFIG_SERIAL_BFIN_DMA
53#include <linux/dma-mapping.h>
54#include <asm/io.h>
55#include <asm/irq.h>
56#include <asm/cacheflush.h>
57#endif
58
59/* UART name and device definitions */
60#define BFIN_SERIAL_NAME "ttyBF"
61#define BFIN_SERIAL_MAJOR 204
62#define BFIN_SERIAL_MINOR 64
63
64/*
65 * Setup for console. Argument comes from the menuconfig
66 */
67#define DMA_RX_XCOUNT 512
68#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
69
70#define DMA_RX_FLUSH_JIFFIES 5
71
72#ifdef CONFIG_SERIAL_BFIN_DMA
73static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
74#else
75static void bfin_serial_do_work(struct work_struct *work);
76static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
77static void local_put_char(struct bfin_serial_port *uart, char ch);
78#endif
79
80static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
81
82/*
83 * interrupts are disabled on entry
84 */
85static void bfin_serial_stop_tx(struct uart_port *port)
86{
87 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
88
f4d640c9
RH		 89 while (!(UART_GET_LSR(uart) & TEMT))
90 continue;
f4d640c9 91
194de561
BW		 92#ifdef CONFIG_SERIAL_BFIN_DMA
93 disable_dma(uart->tx_dma_channel);
f4d640c9
RH		 94#else
95#ifdef CONFIG_BF54x
96 /* Waiting for Transmission Finished */
97 while (!(UART_GET_LSR(uart) & TFI))
98 continue;
99 /* Clear TFI bit */
100 UART_PUT_LSR(uart, TFI);
101 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 102#else
103 unsigned short ier;
104
105 ier = UART_GET_IER(uart);
106 ier &= ~ETBEI;
107 UART_PUT_IER(uart, ier);
108#endif
f4d640c9 109#endif
194de561
BW		 110}
111
112/*
113 * port is locked and interrupts are disabled
114 */
115static void bfin_serial_start_tx(struct uart_port *port)
116{
117 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
118
119#ifdef CONFIG_SERIAL_BFIN_DMA
120 bfin_serial_dma_tx_chars(uart);
f4d640c9
RH		 121#else
122#ifdef CONFIG_BF54x
123 UART_SET_IER(uart, ETBEI);
194de561
BW		 124#else
125 unsigned short ier;
126 ier = UART_GET_IER(uart);
127 ier |= ETBEI;
128 UART_PUT_IER(uart, ier);
194de561 129#endif
a359cca7 130 bfin_serial_tx_chars(uart);
f4d640c9 131#endif
194de561
BW		 132}
133
134/*
135 * Interrupts are enabled
136 */
137static void bfin_serial_stop_rx(struct uart_port *port)
138{
139 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
a359cca7
SZ		 140#ifdef CONFIG_KGDB_UART
141 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
142#endif
f4d640c9
RH		 143#ifdef CONFIG_BF54x
144 UART_CLEAR_IER(uart, ERBFI);
145#else
194de561
BW		 146 unsigned short ier;
147
148 ier = UART_GET_IER(uart);
149 ier &= ~ERBFI;
150 UART_PUT_IER(uart, ier);
f4d640c9 151#endif
a359cca7
SZ		 152#ifdef CONFIG_KGDB_UART
153 }
154#endif
194de561
BW		 155}
156
157/*
158 * Set the modem control timer to fire immediately.
159 */
160static void bfin_serial_enable_ms(struct uart_port *port)
161{
162}
163
474f1a66
SZ		 164#ifdef CONFIG_KGDB_UART
165static int kgdb_entry_state;
166
167void kgdb_put_debug_char(int chr)
168{
169 struct bfin_serial_port *uart;
170
171 if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
172 uart = &bfin_serial_ports[0];
173 else
174 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
175
176 while (!(UART_GET_LSR(uart) & THRE)) {
d5148ffa 177 SSYNC();
474f1a66 178 }
a359cca7
SZ		 179
180#ifndef CONFIG_BF54x
474f1a66 181 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 182 SSYNC();
a359cca7 183#endif
474f1a66 184 UART_PUT_CHAR(uart, (unsigned char)chr);
d5148ffa 185 SSYNC();
474f1a66
SZ		 186}
187
188int kgdb_get_debug_char(void)
189{
190 struct bfin_serial_port *uart;
191 unsigned char chr;
192
193 if (CONFIG_KGDB_UART_PORT<0 || CONFIG_KGDB_UART_PORT>=NR_PORTS)
194 uart = &bfin_serial_ports[0];
195 else
196 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
197
198 while(!(UART_GET_LSR(uart) & DR)) {
d5148ffa 199 SSYNC();
474f1a66 200 }
a359cca7 201#ifndef CONFIG_BF54x
474f1a66 202 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 203 SSYNC();
a359cca7 204#endif
474f1a66 205 chr = UART_GET_CHAR(uart);
d5148ffa 206 SSYNC();
474f1a66
SZ		 207
208 return chr;
209}
210#endif
211
194de561
BW		 212#ifdef CONFIG_SERIAL_BFIN_PIO
213static void local_put_char(struct bfin_serial_port *uart, char ch)
214{
215 unsigned short status;
216 int flags = 0;
217
218 spin_lock_irqsave(&uart->port.lock, flags);
219
220 do {
221 status = UART_GET_LSR(uart);
222 } while (!(status & THRE));
223
224 UART_PUT_CHAR(uart, ch);
225 SSYNC();
226
227 spin_unlock_irqrestore(&uart->port.lock, flags);
228}
229
230static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
231{
2ac5ee47 232 struct tty_struct *tty = uart->port.info->tty;
194de561 233 unsigned int status, ch, flg;
bbf275f0 234 static int in_break = 0;
474f1a66
SZ		 235#ifdef CONFIG_KGDB_UART
236 struct pt_regs *regs = get_irq_regs();
237#endif
194de561
BW		 238
239 status = UART_GET_LSR(uart);
240 ch = UART_GET_CHAR(uart);
241 uart->port.icount.rx++;
242
474f1a66
SZ		 243#ifdef CONFIG_KGDB_UART
244 if (uart->port.line == CONFIG_KGDB_UART_PORT) {
245 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
246 kgdb_breakkey_pressed(regs);
247 return;
248 } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
249 kgdb_entry_state = 1;
250 } else if (kgdb_entry_state == 1 && ch == 'q') {
251 kgdb_entry_state = 0;
252 kgdb_breakkey_pressed(regs);
253 return;
254 } else if (ch == 0x3) {/* Ctrl + C */
255 kgdb_entry_state = 0;
256 kgdb_breakkey_pressed(regs);
257 return;
258 } else {
259 kgdb_entry_state = 0;
260 }
261 }
262#endif
bbf275f0
MF		 263
264 if (ANOMALY_05000230) {
265 /* The BF533 family of processors have a nice misbehavior where
266 * they continuously generate characters for a "single" break.
267 * We have to basically ignore this flood until the "next" valid
268 * character comes across. All other Blackfin families operate
269 * properly though.
270 * Note: While Anomaly 05000230 does not directly address this,
271 * the changes that went in for it also fixed this issue.
272 */
273 if (in_break) {
274 if (ch != 0) {
275 in_break = 0;
276 ch = UART_GET_CHAR(uart);
277 if (bfin_revid() < 5)
278 return;
279 } else
2ac5ee47 280 return;
bbf275f0 281 }
194de561 282 }
194de561
BW		 283
284 if (status & BI) {
bbf275f0
MF		 285 if (ANOMALY_05000230)
286 in_break = 1;
194de561
BW		 287 uart->port.icount.brk++;
288 if (uart_handle_break(&uart->port))
289 goto ignore_char;
9808901b 290 status &= ~(PE | FE);
2ac5ee47
MF		 291 }
292 if (status & PE)
194de561 293 uart->port.icount.parity++;
2ac5ee47 294 if (status & OE)
194de561 295 uart->port.icount.overrun++;
2ac5ee47 296 if (status & FE)
194de561 297 uart->port.icount.frame++;
2ac5ee47
MF		 298
299 status &= uart->port.read_status_mask;
300
301 if (status & BI)
302 flg = TTY_BREAK;
303 else if (status & PE)
304 flg = TTY_PARITY;
305 else if (status & FE)
306 flg = TTY_FRAME;
307 else
194de561
BW		 308 flg = TTY_NORMAL;
309
310 if (uart_handle_sysrq_char(&uart->port, ch))
311 goto ignore_char;
194de561 312
2ac5ee47
MF		 313 uart_insert_char(&uart->port, status, OE, ch, flg);
314
315 ignore_char:
316 tty_flip_buffer_push(tty);
194de561
BW		 317}
318
319static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
320{
321 struct circ_buf *xmit = &uart->port.info->xmit;
322
323 if (uart->port.x_char) {
324 UART_PUT_CHAR(uart, uart->port.x_char);
325 uart->port.icount.tx++;
326 uart->port.x_char = 0;
327 return;
328 }
329 /*
330 * Check the modem control lines before
331 * transmitting anything.
332 */
333 bfin_serial_mctrl_check(uart);
334
335 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
336 bfin_serial_stop_tx(&uart->port);
337 return;
338 }
339
340 local_put_char(uart, xmit->buf[xmit->tail]);
341 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
342 uart->port.icount.tx++;
343
344 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
345 uart_write_wakeup(&uart->port);
346
347 if (uart_circ_empty(xmit))
348 bfin_serial_stop_tx(&uart->port);
349}
350
5c4e472b
AL		 351static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
352{
353 struct bfin_serial_port *uart = dev_id;
354
f4d640c9
RH		 355#ifdef CONFIG_BF54x
356 unsigned short status;
357 spin_lock(&uart->port.lock);
358 status = UART_GET_LSR(uart);
359 while ((UART_GET_IER(uart) & ERBFI) && (status & DR)) {
360 bfin_serial_rx_chars(uart);
361 status = UART_GET_LSR(uart);
362 }
363 spin_unlock(&uart->port.lock);
364#else
5c4e472b
AL		 365 spin_lock(&uart->port.lock);
366 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_RX_READY)
367 bfin_serial_rx_chars(uart);
368 spin_unlock(&uart->port.lock);
f4d640c9 369#endif
5c4e472b
AL		 370 return IRQ_HANDLED;
371}
372
373static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 374{
375 struct bfin_serial_port *uart = dev_id;
194de561 376
f4d640c9
RH		 377#ifdef CONFIG_BF54x
378 unsigned short status;
379 spin_lock(&uart->port.lock);
380 status = UART_GET_LSR(uart);
381 while ((UART_GET_IER(uart) & ETBEI) && (status & THRE)) {
382 bfin_serial_tx_chars(uart);
383 status = UART_GET_LSR(uart);
384 }
385 spin_unlock(&uart->port.lock);
386#else
194de561 387 spin_lock(&uart->port.lock);
5c4e472b
AL		 388 while ((UART_GET_IIR(uart) & IIR_STATUS) == IIR_TX_READY)
389 bfin_serial_tx_chars(uart);
194de561 390 spin_unlock(&uart->port.lock);
f4d640c9 391#endif
194de561
BW		 392 return IRQ_HANDLED;
393}
394
5c4e472b 395
194de561
BW		 396static void bfin_serial_do_work(struct work_struct *work)
397{
398 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
399
400 bfin_serial_mctrl_check(uart);
401}
194de561
BW		 402#endif
403
404#ifdef CONFIG_SERIAL_BFIN_DMA
405static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
406{
407 struct circ_buf *xmit = &uart->port.info->xmit;
408 unsigned short ier;
409 int flags = 0;
410
411 if (!uart->tx_done)
412 return;
413
414 uart->tx_done = 0;
415
416 if (uart->port.x_char) {
417 UART_PUT_CHAR(uart, uart->port.x_char);
418 uart->port.icount.tx++;
419 uart->port.x_char = 0;
420 uart->tx_done = 1;
421 return;
422 }
423 /*
424 * Check the modem control lines before
425 * transmitting anything.
426 */
427 bfin_serial_mctrl_check(uart);
428
429 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
430 bfin_serial_stop_tx(&uart->port);
431 uart->tx_done = 1;
432 return;
433 }
434
435 spin_lock_irqsave(&uart->port.lock, flags);
436 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
437 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
438 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
439 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
440 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
441 set_dma_config(uart->tx_dma_channel,
442 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
443 INTR_ON_BUF,
444 DIMENSION_LINEAR,
2047e40d
MH		 445 DATA_SIZE_8,
446 DMA_SYNC_RESTART));
194de561
BW		 447 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
448 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
449 set_dma_x_modify(uart->tx_dma_channel, 1);
450 enable_dma(uart->tx_dma_channel);
f4d640c9
RH		 451#ifdef CONFIG_BF54x
452 UART_SET_IER(uart, ETBEI);
453#else
194de561
BW		 454 ier = UART_GET_IER(uart);
455 ier |= ETBEI;
456 UART_PUT_IER(uart, ier);
f4d640c9 457#endif
194de561
BW		 458 spin_unlock_irqrestore(&uart->port.lock, flags);
459}
460
2ac5ee47 461static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561
BW		 462{
463 struct tty_struct *tty = uart->port.info->tty;
464 int i, flg, status;
465
466 status = UART_GET_LSR(uart);
467 uart->port.icount.rx += CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, UART_XMIT_SIZE);;
468
469 if (status & BI) {
470 uart->port.icount.brk++;
471 if (uart_handle_break(&uart->port))
472 goto dma_ignore_char;
9808901b 473 status &= ~(PE | FE);
2ac5ee47
MF		 474 }
475 if (status & PE)
194de561 476 uart->port.icount.parity++;
2ac5ee47 477 if (status & OE)
194de561 478 uart->port.icount.overrun++;
2ac5ee47 479 if (status & FE)
194de561 480 uart->port.icount.frame++;
2ac5ee47
MF		 481
482 status &= uart->port.read_status_mask;
483
484 if (status & BI)
485 flg = TTY_BREAK;
486 else if (status & PE)
487 flg = TTY_PARITY;
488 else if (status & FE)
489 flg = TTY_FRAME;
490 else
194de561
BW		 491 flg = TTY_NORMAL;
492
493 for (i = uart->rx_dma_buf.head; i < uart->rx_dma_buf.tail; i++) {
494 if (uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
495 goto dma_ignore_char;
2ac5ee47 496 uart_insert_char(&uart->port, status, OE, uart->rx_dma_buf.buf[i], flg);
194de561 497 }
2ac5ee47
MF		 498
499 dma_ignore_char:
194de561
BW		 500 tty_flip_buffer_push(tty);
501}
502
503void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
504{
505 int x_pos, pos;
506 int flags = 0;
507
508 bfin_serial_dma_tx_chars(uart);
509
510 spin_lock_irqsave(&uart->port.lock, flags);
511 x_pos = DMA_RX_XCOUNT - get_dma_curr_xcount(uart->rx_dma_channel);
512 if (x_pos == DMA_RX_XCOUNT)
513 x_pos = 0;
514
515 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
516
517 if (pos>uart->rx_dma_buf.tail) {
518 uart->rx_dma_buf.tail = pos;
519 bfin_serial_dma_rx_chars(uart);
520 uart->rx_dma_buf.head = uart->rx_dma_buf.tail;
521 }
522 spin_unlock_irqrestore(&uart->port.lock, flags);
523 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
524 add_timer(&(uart->rx_dma_timer));
525}
526
527static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
528{
529 struct bfin_serial_port *uart = dev_id;
530 struct circ_buf *xmit = &uart->port.info->xmit;
531 unsigned short ier;
532
533 spin_lock(&uart->port.lock);
534 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
535 clear_dma_irqstat(uart->tx_dma_channel);
536 disable_dma(uart->tx_dma_channel);
f4d640c9
RH		 537#ifdef CONFIG_BF54x
538 UART_CLEAR_IER(uart, ETBEI);
539#else
194de561
BW		 540 ier = UART_GET_IER(uart);
541 ier &= ~ETBEI;
542 UART_PUT_IER(uart, ier);
f4d640c9 543#endif
194de561
BW		 544 xmit->tail = (xmit->tail+uart->tx_count) &(UART_XMIT_SIZE -1);
545 uart->port.icount.tx+=uart->tx_count;
546
547 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
548 uart_write_wakeup(&uart->port);
549
550 if (uart_circ_empty(xmit))
551 bfin_serial_stop_tx(&uart->port);
552 uart->tx_done = 1;
553 }
554
555 spin_unlock(&uart->port.lock);
556 return IRQ_HANDLED;
557}
558
559static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
560{
561 struct bfin_serial_port *uart = dev_id;
562 unsigned short irqstat;
563
564 uart->rx_dma_nrows++;
565 if (uart->rx_dma_nrows == DMA_RX_YCOUNT) {
566 uart->rx_dma_nrows = 0;
567 uart->rx_dma_buf.tail = DMA_RX_XCOUNT*DMA_RX_YCOUNT;
568 bfin_serial_dma_rx_chars(uart);
569 uart->rx_dma_buf.head = uart->rx_dma_buf.tail = 0;
570 }
571 spin_lock(&uart->port.lock);
572 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
573 clear_dma_irqstat(uart->rx_dma_channel);
574
575 spin_unlock(&uart->port.lock);
576 return IRQ_HANDLED;
577}
578#endif
579
580/*
581 * Return TIOCSER_TEMT when transmitter is not busy.
582 */
583static unsigned int bfin_serial_tx_empty(struct uart_port *port)
584{
585 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
586 unsigned short lsr;
587
588 lsr = UART_GET_LSR(uart);
589 if (lsr & TEMT)
590 return TIOCSER_TEMT;
591 else
592 return 0;
593}
594
595static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
596{
597#ifdef CONFIG_SERIAL_BFIN_CTSRTS
598 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
599 if (uart->cts_pin < 0)
600 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
601
602 if (gpio_get_value(uart->cts_pin))
603 return TIOCM_DSR | TIOCM_CAR;
604 else
605#endif
606 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
607}
608
609static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
610{
611#ifdef CONFIG_SERIAL_BFIN_CTSRTS
612 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
613 if (uart->rts_pin < 0)
614 return;
615
616 if (mctrl & TIOCM_RTS)
617 gpio_set_value(uart->rts_pin, 0);
618 else
619 gpio_set_value(uart->rts_pin, 1);
620#endif
621}
622
623/*
624 * Handle any change of modem status signal since we were last called.
625 */
626static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
627{
628#ifdef CONFIG_SERIAL_BFIN_CTSRTS
629 unsigned int status;
630# ifdef CONFIG_SERIAL_BFIN_DMA
631 struct uart_info *info = uart->port.info;
632 struct tty_struct *tty = info->tty;
633
634 status = bfin_serial_get_mctrl(&uart->port);
635 if (!(status & TIOCM_CTS)) {
636 tty->hw_stopped = 1;
637 } else {
638 tty->hw_stopped = 0;
639 }
640# else
641 status = bfin_serial_get_mctrl(&uart->port);
642 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
643 if (!(status & TIOCM_CTS))
644 schedule_work(&uart->cts_workqueue);
645# endif
646#endif
647}
648
649/*
650 * Interrupts are always disabled.
651 */
652static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
653{
cf686762
MF		 654 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
655 u16 lcr = UART_GET_LCR(uart);
656 if (break_state)
657 lcr |= SB;
658 else
659 lcr &= ~SB;
660 UART_PUT_LCR(uart, lcr);
661 SSYNC();
194de561
BW		 662}
663
664static int bfin_serial_startup(struct uart_port *port)
665{
666 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
667
668#ifdef CONFIG_SERIAL_BFIN_DMA
669 dma_addr_t dma_handle;
670
671 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
672 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
673 return -EBUSY;
674 }
675
676 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
677 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
678 free_dma(uart->rx_dma_channel);
679 return -EBUSY;
680 }
681
682 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
683 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
684
685 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
686 uart->rx_dma_buf.head = 0;
687 uart->rx_dma_buf.tail = 0;
688 uart->rx_dma_nrows = 0;
689
690 set_dma_config(uart->rx_dma_channel,
691 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
692 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 693 DATA_SIZE_8,
694 DMA_SYNC_RESTART));
194de561
BW		 695 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
696 set_dma_x_modify(uart->rx_dma_channel, 1);
697 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
698 set_dma_y_modify(uart->rx_dma_channel, 1);
699 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
700 enable_dma(uart->rx_dma_channel);
701
702 uart->rx_dma_timer.data = (unsigned long)(uart);
703 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
704 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
705 add_timer(&(uart->rx_dma_timer));
706#else
a359cca7
SZ		 707 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
708 "BFIN_UART_RX", uart)) {
474f1a66 709# ifdef CONFIG_KGDB_UART
a359cca7 710 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
474f1a66 711# endif
194de561
BW		 712 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
713 return -EBUSY;
a359cca7
SZ		 714# ifdef CONFIG_KGDB_UART
715 }
716# endif
194de561
BW		 717 }
718
a359cca7 719
194de561 720 if (request_irq
5c4e472b 721 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW		 722 "BFIN_UART_TX", uart)) {
723 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
724 free_irq(uart->port.irq, uart);
725 return -EBUSY;
726 }
727#endif
f4d640c9
RH		 728#ifdef CONFIG_BF54x
729 UART_SET_IER(uart, ERBFI);
730#else
194de561 731 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
f4d640c9 732#endif
194de561
BW		 733 return 0;
734}
735
736static void bfin_serial_shutdown(struct uart_port *port)
737{
738 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
739
740#ifdef CONFIG_SERIAL_BFIN_DMA
741 disable_dma(uart->tx_dma_channel);
742 free_dma(uart->tx_dma_channel);
743 disable_dma(uart->rx_dma_channel);
744 free_dma(uart->rx_dma_channel);
745 del_timer(&(uart->rx_dma_timer));
746#else
474f1a66
SZ		 747#ifdef CONFIG_KGDB_UART
748 if (uart->port.line != CONFIG_KGDB_UART_PORT)
749#endif
194de561
BW		 750 free_irq(uart->port.irq, uart);
751 free_irq(uart->port.irq+1, uart);
752#endif
753}
754
755static void
756bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
757 struct ktermios *old)
758{
759 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
760 unsigned long flags;
761 unsigned int baud, quot;
762 unsigned short val, ier, lsr, lcr = 0;
763
764 switch (termios->c_cflag & CSIZE) {
765 case CS8:
766 lcr = WLS(8);
767 break;
768 case CS7:
769 lcr = WLS(7);
770 break;
771 case CS6:
772 lcr = WLS(6);
773 break;
774 case CS5:
775 lcr = WLS(5);
776 break;
777 default:
778 printk(KERN_ERR "%s: word lengh not supported\n",
779 __FUNCTION__);
780 }
781
782 if (termios->c_cflag & CSTOPB)
783 lcr |= STB;
19aa6382 784 if (termios->c_cflag & PARENB)
194de561 785 lcr |= PEN;
19aa6382
MF		 786 if (!(termios->c_cflag & PARODD))
787 lcr |= EPS;
788 if (termios->c_cflag & CMSPAR)
789 lcr |= STP;
194de561 790
2ac5ee47
MF		 791 port->read_status_mask = OE;
792 if (termios->c_iflag & INPCK)
793 port->read_status_mask |= (FE | PE);
794 if (termios->c_iflag & (BRKINT | PARMRK))
795 port->read_status_mask |= BI;
194de561 796
2ac5ee47
MF		 797 /*
798 * Characters to ignore
799 */
800 port->ignore_status_mask = 0;
801 if (termios->c_iflag & IGNPAR)
802 port->ignore_status_mask |= FE | PE;
803 if (termios->c_iflag & IGNBRK) {
804 port->ignore_status_mask |= BI;
805 /*
806 * If we're ignoring parity and break indicators,
807 * ignore overruns too (for real raw support).
808 */
809 if (termios->c_iflag & IGNPAR)
810 port->ignore_status_mask |= OE;
811 }
194de561
BW		 812
813 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
814 quot = uart_get_divisor(port, baud);
815 spin_lock_irqsave(&uart->port.lock, flags);
816
817 do {
818 lsr = UART_GET_LSR(uart);
819 } while (!(lsr & TEMT));
820
821 /* Disable UART */
822 ier = UART_GET_IER(uart);
f4d640c9
RH		 823#ifdef CONFIG_BF54x
824 UART_CLEAR_IER(uart, 0xF);
825#else
194de561 826 UART_PUT_IER(uart, 0);
f4d640c9 827#endif
194de561 828
f4d640c9 829#ifndef CONFIG_BF54x
194de561
BW		 830 /* Set DLAB in LCR to Access DLL and DLH */
831 val = UART_GET_LCR(uart);
832 val |= DLAB;
833 UART_PUT_LCR(uart, val);
834 SSYNC();
f4d640c9 835#endif
194de561
BW		 836
837 UART_PUT_DLL(uart, quot & 0xFF);
838 SSYNC();
839 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
840 SSYNC();
841
f4d640c9 842#ifndef CONFIG_BF54x
194de561
BW		 843 /* Clear DLAB in LCR to Access THR RBR IER */
844 val = UART_GET_LCR(uart);
845 val &= ~DLAB;
846 UART_PUT_LCR(uart, val);
847 SSYNC();
f4d640c9 848#endif
194de561
BW		 849
850 UART_PUT_LCR(uart, lcr);
851
852 /* Enable UART */
f4d640c9
RH		 853#ifdef CONFIG_BF54x
854 UART_SET_IER(uart, ier);
855#else
194de561 856 UART_PUT_IER(uart, ier);
f4d640c9 857#endif
194de561
BW		 858
859 val = UART_GET_GCTL(uart);
860 val |= UCEN;
861 UART_PUT_GCTL(uart, val);
862
863 spin_unlock_irqrestore(&uart->port.lock, flags);
864}
865
866static const char *bfin_serial_type(struct uart_port *port)
867{
868 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
869
870 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
871}
872
873/*
874 * Release the memory region(s) being used by 'port'.
875 */
876static void bfin_serial_release_port(struct uart_port *port)
877{
878}
879
880/*
881 * Request the memory region(s) being used by 'port'.
882 */
883static int bfin_serial_request_port(struct uart_port *port)
884{
885 return 0;
886}
887
888/*
889 * Configure/autoconfigure the port.
890 */
891static void bfin_serial_config_port(struct uart_port *port, int flags)
892{
893 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
894
895 if (flags & UART_CONFIG_TYPE &&
896 bfin_serial_request_port(&uart->port) == 0)
897 uart->port.type = PORT_BFIN;
898}
899
900/*
901 * Verify the new serial_struct (for TIOCSSERIAL).
902 * The only change we allow are to the flags and type, and
903 * even then only between PORT_BFIN and PORT_UNKNOWN
904 */
905static int
906bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
907{
908 return 0;
909}
910
911static struct uart_ops bfin_serial_pops = {
912 .tx_empty = bfin_serial_tx_empty,
913 .set_mctrl = bfin_serial_set_mctrl,
914 .get_mctrl = bfin_serial_get_mctrl,
915 .stop_tx = bfin_serial_stop_tx,
916 .start_tx = bfin_serial_start_tx,
917 .stop_rx = bfin_serial_stop_rx,
918 .enable_ms = bfin_serial_enable_ms,
919 .break_ctl = bfin_serial_break_ctl,
920 .startup = bfin_serial_startup,
921 .shutdown = bfin_serial_shutdown,
922 .set_termios = bfin_serial_set_termios,
923 .type = bfin_serial_type,
924 .release_port = bfin_serial_release_port,
925 .request_port = bfin_serial_request_port,
926 .config_port = bfin_serial_config_port,
927 .verify_port = bfin_serial_verify_port,
928};
929
930static void __init bfin_serial_init_ports(void)
931{
932 static int first = 1;
933 int i;
934
935 if (!first)
936 return;
937 first = 0;
938
939 for (i = 0; i < nr_ports; i++) {
940 bfin_serial_ports[i].port.uartclk = get_sclk();
941 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
942 bfin_serial_ports[i].port.line = i;
943 bfin_serial_ports[i].port.iotype = UPIO_MEM;
944 bfin_serial_ports[i].port.membase =
945 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
946 bfin_serial_ports[i].port.mapbase =
947 bfin_serial_resource[i].uart_base_addr;
948 bfin_serial_ports[i].port.irq =
949 bfin_serial_resource[i].uart_irq;
950 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
951#ifdef CONFIG_SERIAL_BFIN_DMA
952 bfin_serial_ports[i].tx_done = 1;
953 bfin_serial_ports[i].tx_count = 0;
954 bfin_serial_ports[i].tx_dma_channel =
955 bfin_serial_resource[i].uart_tx_dma_channel;
956 bfin_serial_ports[i].rx_dma_channel =
957 bfin_serial_resource[i].uart_rx_dma_channel;
958 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
959#else
960 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
961#endif
962#ifdef CONFIG_SERIAL_BFIN_CTSRTS
963 bfin_serial_ports[i].cts_pin =
964 bfin_serial_resource[i].uart_cts_pin;
965 bfin_serial_ports[i].rts_pin =
966 bfin_serial_resource[i].uart_rts_pin;
967#endif
968 bfin_serial_hw_init(&bfin_serial_ports[i]);
194de561 969 }
f4d640c9 970
194de561
BW		 971}
972
973#ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 974/*
975 * If the port was already initialised (eg, by a boot loader),
976 * try to determine the current setup.
977 */
978static void __init
979bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
980 int *parity, int *bits)
981{
982 unsigned short status;
983
984 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
985 if (status == (ERBFI | ETBEI)) {
986 /* ok, the port was enabled */
987 unsigned short lcr, val;
988 unsigned short dlh, dll;
989
990 lcr = UART_GET_LCR(uart);
991
992 *parity = 'n';
993 if (lcr & PEN) {
994 if (lcr & EPS)
995 *parity = 'e';
996 else
997 *parity = 'o';
998 }
999 switch (lcr & 0x03) {
1000 case 0: *bits = 5; break;
1001 case 1: *bits = 6; break;
1002 case 2: *bits = 7; break;
1003 case 3: *bits = 8; break;
1004 }
f4d640c9 1005#ifndef CONFIG_BF54x
194de561
BW		 1006 /* Set DLAB in LCR to Access DLL and DLH */
1007 val = UART_GET_LCR(uart);
1008 val |= DLAB;
1009 UART_PUT_LCR(uart, val);
f4d640c9 1010#endif
194de561
BW		 1011
1012 dll = UART_GET_DLL(uart);
1013 dlh = UART_GET_DLH(uart);
1014
f4d640c9 1015#ifndef CONFIG_BF54x
194de561
BW		 1016 /* Clear DLAB in LCR to Access THR RBR IER */
1017 val = UART_GET_LCR(uart);
1018 val &= ~DLAB;
1019 UART_PUT_LCR(uart, val);
f4d640c9 1020#endif
194de561
BW		 1021
1022 *baud = get_sclk() / (16*(dll | dlh << 8));
1023 }
1024 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits);
1025}
0ae53640
RG		 1026#endif
1027
1028#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1029static struct uart_driver bfin_serial_reg;
194de561
BW		 1030
1031static int __init
1032bfin_serial_console_setup(struct console *co, char *options)
1033{
1034 struct bfin_serial_port *uart;
0ae53640 1035# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 1036 int baud = 57600;
1037 int bits = 8;
1038 int parity = 'n';
0ae53640 1039# ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561 1040 int flow = 'r';
0ae53640 1041# else
194de561 1042 int flow = 'n';
0ae53640
RG		 1043# endif
1044# endif
194de561
BW		 1045
1046 /*
1047 * Check whether an invalid uart number has been specified, and
1048 * if so, search for the first available port that does have
1049 * console support.
1050 */
1051 if (co->index == -1 || co->index >= nr_ports)
1052 co->index = 0;
1053 uart = &bfin_serial_ports[co->index];
1054
0ae53640 1055# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 1056 if (options)
1057 uart_parse_options(options, &baud, &parity, &bits, &flow);
1058 else
1059 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1060
1061 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG		 1062# else
1063 return 0;
1064# endif
1065}
1066#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1067 defined (CONFIG_EARLY_PRINTK) */
1068
1069#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1070static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1071{
1072 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1073 while (!(UART_GET_LSR(uart) & THRE))
1074 barrier();
1075 UART_PUT_CHAR(uart, ch);
1076 SSYNC();
1077}
1078
1079/*
1080 * Interrupts are disabled on entering
1081 */
1082static void
1083bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1084{
1085 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1086 int flags = 0;
1087
1088 spin_lock_irqsave(&uart->port.lock, flags);
1089 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1090 spin_unlock_irqrestore(&uart->port.lock, flags);
1091
194de561
BW		 1092}
1093
194de561
BW		 1094static struct console bfin_serial_console = {
1095 .name = BFIN_SERIAL_NAME,
1096 .write = bfin_serial_console_write,
1097 .device = uart_console_device,
1098 .setup = bfin_serial_console_setup,
1099 .flags = CON_PRINTBUFFER,
1100 .index = -1,
1101 .data = &bfin_serial_reg,
1102};
1103
1104static int __init bfin_serial_rs_console_init(void)
1105{
1106 bfin_serial_init_ports();
1107 register_console(&bfin_serial_console);
474f1a66
SZ		 1108#ifdef CONFIG_KGDB_UART
1109 kgdb_entry_state = 0;
1110 init_kgdb_uart();
1111#endif
194de561
BW		 1112 return 0;
1113}
1114console_initcall(bfin_serial_rs_console_init);
1115
1116#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1117#else
1118#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1119#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1120
1121
1122#ifdef CONFIG_EARLY_PRINTK
1123static __init void early_serial_putc(struct uart_port *port, int ch)
1124{
1125 unsigned timeout = 0xffff;
1126 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1127
1128 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1129 cpu_relax();
1130 UART_PUT_CHAR(uart, ch);
1131}
1132
1133static __init void early_serial_write(struct console *con, const char *s,
1134 unsigned int n)
1135{
1136 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1137 unsigned int i;
1138
1139 for (i = 0; i < n; i++, s++) {
1140 if (*s == '\n')
1141 early_serial_putc(&uart->port, '\r');
1142 early_serial_putc(&uart->port, *s);
1143 }
1144}
1145
1146static struct __init console bfin_early_serial_console = {
1147 .name = "early_BFuart",
1148 .write = early_serial_write,
1149 .device = uart_console_device,
1150 .flags = CON_PRINTBUFFER,
1151 .setup = bfin_serial_console_setup,
1152 .index = -1,
1153 .data = &bfin_serial_reg,
1154};
1155
1156struct console __init *bfin_earlyserial_init(unsigned int port,
1157 unsigned int cflag)
1158{
1159 struct bfin_serial_port *uart;
1160 struct ktermios t;
1161
1162 if (port == -1 || port >= nr_ports)
1163 port = 0;
1164 bfin_serial_init_ports();
1165 bfin_early_serial_console.index = port;
0ae53640
RG		 1166 uart = &bfin_serial_ports[port];
1167 t.c_cflag = cflag;
1168 t.c_iflag = 0;
1169 t.c_oflag = 0;
1170 t.c_lflag = ICANON;
1171 t.c_line = port;
1172 bfin_serial_set_termios(&uart->port, &t, &t);
1173 return &bfin_early_serial_console;
1174}
1175
1176#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
194de561
BW		 1177
1178static struct uart_driver bfin_serial_reg = {
1179 .owner = THIS_MODULE,
1180 .driver_name = "bfin-uart",
1181 .dev_name = BFIN_SERIAL_NAME,
1182 .major = BFIN_SERIAL_MAJOR,
1183 .minor = BFIN_SERIAL_MINOR,
1184 .nr = NR_PORTS,
1185 .cons = BFIN_SERIAL_CONSOLE,
1186};
1187
1188static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1189{
1190 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1191
1192 if (uart)
1193 uart_suspend_port(&bfin_serial_reg, &uart->port);
1194
1195 return 0;
1196}
1197
1198static int bfin_serial_resume(struct platform_device *dev)
1199{
1200 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1201
1202 if (uart)
1203 uart_resume_port(&bfin_serial_reg, &uart->port);
1204
1205 return 0;
1206}
1207
1208static int bfin_serial_probe(struct platform_device *dev)
1209{
1210 struct resource *res = dev->resource;
1211 int i;
1212
1213 for (i = 0; i < dev->num_resources; i++, res++)
1214 if (res->flags & IORESOURCE_MEM)
1215 break;
1216
1217 if (i < dev->num_resources) {
1218 for (i = 0; i < nr_ports; i++, res++) {
1219 if (bfin_serial_ports[i].port.mapbase != res->start)
1220 continue;
1221 bfin_serial_ports[i].port.dev = &dev->dev;
1222 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1223 platform_set_drvdata(dev, &bfin_serial_ports[i]);
1224 }
1225 }
1226
1227 return 0;
1228}
1229
1230static int bfin_serial_remove(struct platform_device *pdev)
1231{
1232 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1233
1234
1235#ifdef CONFIG_SERIAL_BFIN_CTSRTS
1236 gpio_free(uart->cts_pin);
1237 gpio_free(uart->rts_pin);
1238#endif
1239
1240 platform_set_drvdata(pdev, NULL);
1241
1242 if (uart)
1243 uart_remove_one_port(&bfin_serial_reg, &uart->port);
1244
1245 return 0;
1246}
1247
1248static struct platform_driver bfin_serial_driver = {
1249 .probe = bfin_serial_probe,
1250 .remove = bfin_serial_remove,
1251 .suspend = bfin_serial_suspend,
1252 .resume = bfin_serial_resume,
1253 .driver = {
1254 .name = "bfin-uart",
1255 },
1256};
1257
1258static int __init bfin_serial_init(void)
1259{
1260 int ret;
474f1a66
SZ		 1261#ifdef CONFIG_KGDB_UART
1262 struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
a359cca7 1263 struct ktermios t;
474f1a66 1264#endif
194de561
BW		 1265
1266 pr_info("Serial: Blackfin serial driver\n");
1267
1268 bfin_serial_init_ports();
1269
1270 ret = uart_register_driver(&bfin_serial_reg);
1271 if (ret == 0) {
1272 ret = platform_driver_register(&bfin_serial_driver);
1273 if (ret) {
1274 pr_debug("uart register failed\n");
1275 uart_unregister_driver(&bfin_serial_reg);
1276 }
1277 }
474f1a66
SZ		 1278#ifdef CONFIG_KGDB_UART
1279 if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
a359cca7 1280 request_irq(uart->port.irq, bfin_serial_rx_int,
474f1a66
SZ		 1281 IRQF_DISABLED, "BFIN_UART_RX", uart);
1282 pr_info("Request irq for kgdb uart port\n");
a359cca7
SZ		 1283#ifdef CONFIG_BF54x
1284 UART_SET_IER(uart, ERBFI);
1285#else
474f1a66 1286 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
a359cca7 1287#endif
d5148ffa 1288 SSYNC();
474f1a66
SZ		 1289 t.c_cflag = CS8|B57600;
1290 t.c_iflag = 0;
1291 t.c_oflag = 0;
1292 t.c_lflag = ICANON;
1293 t.c_line = CONFIG_KGDB_UART_PORT;
1294 bfin_serial_set_termios(&uart->port, &t, &t);
1295 }
1296#endif
194de561
BW		 1297 return ret;
1298}
1299
1300static void __exit bfin_serial_exit(void)
1301{
1302 platform_driver_unregister(&bfin_serial_driver);
1303 uart_unregister_driver(&bfin_serial_reg);
1304}
1305
1306module_init(bfin_serial_init);
1307module_exit(bfin_serial_exit);
1308
1309MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1310MODULE_DESCRIPTION("Blackfin generic serial port driver");
1311MODULE_LICENSE("GPL");
1312MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
Clone of davem's net-next-2.6 tree