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Commit | Line | Data |
---|---|---|
194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
d273e201 | 4 | * Copyright 2006-2008 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
52e15f0e SZ |
25 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
26 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
474f1a66 SZ |
27 | #include <linux/kgdb.h> |
28 | #include <asm/irq_regs.h> | |
29 | #endif | |
30 | ||
194de561 | 31 | #include <asm/gpio.h> |
639f6571 | 32 | #include <mach/bfin_serial_5xx.h> |
194de561 BW |
33 | |
34 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #endif | |
40 | ||
41 | /* UART name and device definitions */ | |
42 | #define BFIN_SERIAL_NAME "ttyBF" | |
43 | #define BFIN_SERIAL_MAJOR 204 | |
44 | #define BFIN_SERIAL_MINOR 64 | |
45 | ||
c9607ecc MF |
46 | static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
47 | static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource); | |
48 | ||
52e15f0e SZ |
49 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
50 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
51 | ||
52 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
53 | # error KGDB only support UART in PIO mode. | |
54 | # endif | |
55 | ||
56 | static int kgdboc_port_line; | |
57 | static int kgdboc_break_enabled; | |
58 | #endif | |
194de561 BW |
59 | /* |
60 | * Setup for console. Argument comes from the menuconfig | |
61 | */ | |
62 | #define DMA_RX_XCOUNT 512 | |
63 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
64 | ||
0aef4564 | 65 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
f30ac0ce | 66 | #define CTS_CHECK_JIFFIES (HZ / 50) |
194de561 BW |
67 | |
68 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
69 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
70 | #else | |
194de561 | 71 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
72 | #endif |
73 | ||
74 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart); | |
75 | ||
80d5c474 GY |
76 | static void bfin_serial_reset_irda(struct uart_port *port); |
77 | ||
194de561 BW |
78 | /* |
79 | * interrupts are disabled on entry | |
80 | */ | |
81 | static void bfin_serial_stop_tx(struct uart_port *port) | |
82 | { | |
83 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
0711d857 | 84 | struct circ_buf *xmit = &uart->port.info->xmit; |
194de561 | 85 | |
f4d640c9 | 86 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 87 | cpu_relax(); |
f4d640c9 | 88 | |
194de561 BW |
89 | #ifdef CONFIG_SERIAL_BFIN_DMA |
90 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
91 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
92 | uart->port.icount.tx += uart->tx_count; | |
93 | uart->tx_count = 0; | |
94 | uart->tx_done = 1; | |
f4d640c9 RH |
95 | #else |
96 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
97 | /* Clear TFI bit */ |
98 | UART_PUT_LSR(uart, TFI); | |
194de561 | 99 | #endif |
89bf6dc5 | 100 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 101 | #endif |
194de561 BW |
102 | } |
103 | ||
104 | /* | |
105 | * port is locked and interrupts are disabled | |
106 | */ | |
107 | static void bfin_serial_start_tx(struct uart_port *port) | |
108 | { | |
109 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80d5c474 GY |
110 | struct tty_struct *tty = uart->port.info->port.tty; |
111 | ||
112 | /* | |
113 | * To avoid losting RX interrupt, we reset IR function | |
114 | * before sending data. | |
115 | */ | |
116 | if (tty->termios->c_line == N_IRDA) | |
117 | bfin_serial_reset_irda(port); | |
194de561 BW |
118 | |
119 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
120 | if (uart->tx_done) |
121 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 122 | #else |
f4d640c9 | 123 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 124 | bfin_serial_tx_chars(uart); |
f4d640c9 | 125 | #endif |
194de561 BW |
126 | } |
127 | ||
128 | /* | |
129 | * Interrupts are enabled | |
130 | */ | |
131 | static void bfin_serial_stop_rx(struct uart_port *port) | |
132 | { | |
133 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 134 | |
f4d640c9 | 135 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
136 | } |
137 | ||
138 | /* | |
139 | * Set the modem control timer to fire immediately. | |
140 | */ | |
141 | static void bfin_serial_enable_ms(struct uart_port *port) | |
142 | { | |
143 | } | |
144 | ||
474f1a66 | 145 | |
50e2e15a | 146 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
147 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
148 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
149 | #else | |
150 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
151 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
152 | #endif | |
153 | ||
194de561 | 154 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
155 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
156 | { | |
52e15f0e | 157 | struct tty_struct *tty = NULL; |
194de561 | 158 | unsigned int status, ch, flg; |
8851c71e | 159 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 160 | |
759eb040 | 161 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
162 | UART_CLEAR_LSR(uart); |
163 | ||
164 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
165 | uart->port.icount.rx++; |
166 | ||
52e15f0e SZ |
167 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
168 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
169 | if (kgdb_connected && kgdboc_port_line == uart->port.line) | |
170 | if (ch == 0x3) {/* Ctrl + C */ | |
171 | kgdb_breakpoint(); | |
474f1a66 | 172 | return; |
474f1a66 | 173 | } |
52e15f0e SZ |
174 | |
175 | if (!uart->port.info || !uart->port.info->tty) | |
176 | return; | |
474f1a66 | 177 | #endif |
52e15f0e | 178 | tty = uart->port.info->tty; |
bbf275f0 | 179 | |
50e2e15a | 180 | if (ANOMALY_05000363) { |
8851c71e MF |
181 | /* The BF533 (and BF561) family of processors have a nice anomaly |
182 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 183 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
184 | * character comes across. Due to the nature of the flood, it is |
185 | * not possible to reliably catch bytes that are sent too quickly | |
186 | * after this break. So application code talking to the Blackfin | |
187 | * which sends a break signal must allow at least 1.5 character | |
188 | * times after the end of the break for things to stabilize. This | |
189 | * timeout was picked as it must absolutely be larger than 1 | |
190 | * character time +/- some percent. So 1.5 sounds good. All other | |
191 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 192 | */ |
8851c71e MF |
193 | if (anomaly_start.tv_sec) { |
194 | struct timeval curr; | |
195 | suseconds_t usecs; | |
196 | ||
197 | if ((~ch & (~ch + 1)) & 0xff) | |
198 | goto known_good_char; | |
199 | ||
200 | do_gettimeofday(&curr); | |
201 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
202 | goto known_good_char; | |
203 | ||
204 | usecs = 0; | |
205 | if (curr.tv_sec != anomaly_start.tv_sec) | |
206 | usecs += USEC_PER_SEC; | |
207 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
208 | ||
209 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
210 | goto known_good_char; | |
211 | ||
212 | if (ch) | |
213 | anomaly_start.tv_sec = 0; | |
214 | else | |
215 | anomaly_start = curr; | |
216 | ||
217 | return; | |
218 | ||
219 | known_good_char: | |
220 | anomaly_start.tv_sec = 0; | |
bbf275f0 | 221 | } |
194de561 | 222 | } |
194de561 BW |
223 | |
224 | if (status & BI) { | |
50e2e15a | 225 | if (ANOMALY_05000363) |
8851c71e MF |
226 | if (bfin_revid() < 5) |
227 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
228 | uart->port.icount.brk++; |
229 | if (uart_handle_break(&uart->port)) | |
230 | goto ignore_char; | |
9808901b | 231 | status &= ~(PE | FE); |
2ac5ee47 MF |
232 | } |
233 | if (status & PE) | |
194de561 | 234 | uart->port.icount.parity++; |
2ac5ee47 | 235 | if (status & OE) |
194de561 | 236 | uart->port.icount.overrun++; |
2ac5ee47 | 237 | if (status & FE) |
194de561 | 238 | uart->port.icount.frame++; |
2ac5ee47 MF |
239 | |
240 | status &= uart->port.read_status_mask; | |
241 | ||
242 | if (status & BI) | |
243 | flg = TTY_BREAK; | |
244 | else if (status & PE) | |
245 | flg = TTY_PARITY; | |
246 | else if (status & FE) | |
247 | flg = TTY_FRAME; | |
248 | else | |
194de561 BW |
249 | flg = TTY_NORMAL; |
250 | ||
251 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
252 | goto ignore_char; | |
194de561 | 253 | |
2ac5ee47 MF |
254 | uart_insert_char(&uart->port, status, OE, ch, flg); |
255 | ||
256 | ignore_char: | |
257 | tty_flip_buffer_push(tty); | |
194de561 BW |
258 | } |
259 | ||
260 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
261 | { | |
262 | struct circ_buf *xmit = &uart->port.info->xmit; | |
263 | ||
194de561 BW |
264 | /* |
265 | * Check the modem control lines before | |
266 | * transmitting anything. | |
267 | */ | |
268 | bfin_serial_mctrl_check(uart); | |
269 | ||
270 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { | |
5ffdeea2 SZ |
271 | #ifdef CONFIG_BF54x |
272 | /* Clear TFI bit */ | |
273 | UART_PUT_LSR(uart, TFI); | |
274 | #endif | |
275 | UART_CLEAR_IER(uart, ETBEI); | |
194de561 BW |
276 | return; |
277 | } | |
278 | ||
f30ac0ce SZ |
279 | if (uart->port.x_char) { |
280 | UART_PUT_CHAR(uart, uart->port.x_char); | |
281 | uart->port.icount.tx++; | |
282 | uart->port.x_char = 0; | |
283 | } | |
284 | ||
759eb040 SZ |
285 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
286 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
287 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
288 | uart->port.icount.tx++; | |
289 | SSYNC(); | |
290 | } | |
194de561 BW |
291 | |
292 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
293 | uart_write_wakeup(&uart->port); | |
194de561 BW |
294 | } |
295 | ||
5c4e472b AL |
296 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
297 | { | |
298 | struct bfin_serial_port *uart = dev_id; | |
299 | ||
f4d640c9 | 300 | spin_lock(&uart->port.lock); |
0bcfd70e | 301 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 302 | bfin_serial_rx_chars(uart); |
f4d640c9 | 303 | spin_unlock(&uart->port.lock); |
759eb040 | 304 | |
5c4e472b AL |
305 | return IRQ_HANDLED; |
306 | } | |
307 | ||
308 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
309 | { |
310 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 311 | |
f4d640c9 | 312 | spin_lock(&uart->port.lock); |
0bcfd70e | 313 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 314 | bfin_serial_tx_chars(uart); |
f4d640c9 | 315 | spin_unlock(&uart->port.lock); |
759eb040 | 316 | |
194de561 BW |
317 | return IRQ_HANDLED; |
318 | } | |
4cb4f22b | 319 | #endif |
194de561 | 320 | |
194de561 BW |
321 | #ifdef CONFIG_SERIAL_BFIN_DMA |
322 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
323 | { | |
324 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 325 | |
194de561 BW |
326 | uart->tx_done = 0; |
327 | ||
f30ac0ce SZ |
328 | /* |
329 | * Check the modem control lines before | |
330 | * transmitting anything. | |
331 | */ | |
332 | bfin_serial_mctrl_check(uart); | |
333 | ||
1b73351c | 334 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 335 | uart->tx_count = 0; |
1b73351c SZ |
336 | uart->tx_done = 1; |
337 | return; | |
338 | } | |
339 | ||
194de561 BW |
340 | if (uart->port.x_char) { |
341 | UART_PUT_CHAR(uart, uart->port.x_char); | |
342 | uart->port.icount.tx++; | |
343 | uart->port.x_char = 0; | |
194de561 | 344 | } |
1b73351c | 345 | |
194de561 BW |
346 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
347 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
348 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
349 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
350 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
351 | set_dma_config(uart->tx_dma_channel, | |
352 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
353 | INTR_ON_BUF, | |
354 | DIMENSION_LINEAR, | |
2047e40d MH |
355 | DATA_SIZE_8, |
356 | DMA_SYNC_RESTART)); | |
194de561 BW |
357 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
358 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
359 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
360 | enable_dma(uart->tx_dma_channel); | |
99ee7b5f | 361 | |
f4d640c9 | 362 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
363 | } |
364 | ||
2ac5ee47 | 365 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 366 | { |
a88487c7 | 367 | struct tty_struct *tty = uart->port.info->port.tty; |
194de561 BW |
368 | int i, flg, status; |
369 | ||
370 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
371 | UART_CLEAR_LSR(uart); |
372 | ||
56f5de8f SZ |
373 | uart->port.icount.rx += |
374 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
375 | UART_XMIT_SIZE); | |
194de561 BW |
376 | |
377 | if (status & BI) { | |
378 | uart->port.icount.brk++; | |
379 | if (uart_handle_break(&uart->port)) | |
380 | goto dma_ignore_char; | |
9808901b | 381 | status &= ~(PE | FE); |
2ac5ee47 MF |
382 | } |
383 | if (status & PE) | |
194de561 | 384 | uart->port.icount.parity++; |
2ac5ee47 | 385 | if (status & OE) |
194de561 | 386 | uart->port.icount.overrun++; |
2ac5ee47 | 387 | if (status & FE) |
194de561 | 388 | uart->port.icount.frame++; |
2ac5ee47 MF |
389 | |
390 | status &= uart->port.read_status_mask; | |
391 | ||
392 | if (status & BI) | |
393 | flg = TTY_BREAK; | |
394 | else if (status & PE) | |
395 | flg = TTY_PARITY; | |
396 | else if (status & FE) | |
397 | flg = TTY_FRAME; | |
398 | else | |
194de561 BW |
399 | flg = TTY_NORMAL; |
400 | ||
56f5de8f SZ |
401 | for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) { |
402 | if (i >= UART_XMIT_SIZE) | |
403 | i = 0; | |
404 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) | |
405 | uart_insert_char(&uart->port, status, OE, | |
406 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 407 | } |
2ac5ee47 MF |
408 | |
409 | dma_ignore_char: | |
194de561 BW |
410 | tty_flip_buffer_push(tty); |
411 | } | |
412 | ||
413 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
414 | { | |
415 | int x_pos, pos; | |
194de561 | 416 | |
56f5de8f SZ |
417 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
418 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
419 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
420 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT) | |
421 | uart->rx_dma_nrows = 0; | |
422 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
423 | if (x_pos == DMA_RX_XCOUNT) |
424 | x_pos = 0; | |
425 | ||
426 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
56f5de8f SZ |
427 | if (pos != uart->rx_dma_buf.tail) { |
428 | uart->rx_dma_buf.head = pos; | |
194de561 | 429 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 430 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 431 | } |
0aef4564 | 432 | |
0a278423 | 433 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
434 | } |
435 | ||
436 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
437 | { | |
438 | struct bfin_serial_port *uart = dev_id; | |
439 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 BW |
440 | |
441 | spin_lock(&uart->port.lock); | |
442 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 443 | disable_dma(uart->tx_dma_channel); |
0711d857 | 444 | clear_dma_irqstat(uart->tx_dma_channel); |
f4d640c9 | 445 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
446 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
447 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 448 | |
56f5de8f SZ |
449 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
450 | uart_write_wakeup(&uart->port); | |
451 | ||
1b73351c | 452 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
453 | } |
454 | ||
455 | spin_unlock(&uart->port.lock); | |
456 | return IRQ_HANDLED; | |
457 | } | |
458 | ||
459 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
460 | { | |
461 | struct bfin_serial_port *uart = dev_id; | |
462 | unsigned short irqstat; | |
0711d857 | 463 | |
194de561 BW |
464 | spin_lock(&uart->port.lock); |
465 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
466 | clear_dma_irqstat(uart->rx_dma_channel); | |
194de561 | 467 | spin_unlock(&uart->port.lock); |
0aef4564 | 468 | |
0a278423 | 469 | mod_timer(&(uart->rx_dma_timer), jiffies); |
0aef4564 | 470 | |
194de561 BW |
471 | return IRQ_HANDLED; |
472 | } | |
473 | #endif | |
474 | ||
475 | /* | |
476 | * Return TIOCSER_TEMT when transmitter is not busy. | |
477 | */ | |
478 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
479 | { | |
480 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
481 | unsigned short lsr; | |
482 | ||
483 | lsr = UART_GET_LSR(uart); | |
484 | if (lsr & TEMT) | |
485 | return TIOCSER_TEMT; | |
486 | else | |
487 | return 0; | |
488 | } | |
489 | ||
490 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
491 | { | |
492 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
493 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
494 | if (uart->cts_pin < 0) | |
495 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
496 | ||
1feaa51d | 497 | if (UART_GET_CTS(uart)) |
194de561 BW |
498 | return TIOCM_DSR | TIOCM_CAR; |
499 | else | |
500 | #endif | |
501 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
502 | } | |
503 | ||
504 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
505 | { | |
506 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
507 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
508 | if (uart->rts_pin < 0) | |
509 | return; | |
510 | ||
511 | if (mctrl & TIOCM_RTS) | |
1feaa51d | 512 | UART_CLEAR_RTS(uart); |
194de561 | 513 | else |
1feaa51d | 514 | UART_SET_RTS(uart); |
194de561 BW |
515 | #endif |
516 | } | |
517 | ||
518 | /* | |
519 | * Handle any change of modem status signal since we were last called. | |
520 | */ | |
521 | static void bfin_serial_mctrl_check(struct bfin_serial_port *uart) | |
522 | { | |
523 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
524 | unsigned int status; | |
194de561 | 525 | struct uart_info *info = uart->port.info; |
a88487c7 | 526 | struct tty_struct *tty = info->port.tty; |
194de561 BW |
527 | |
528 | status = bfin_serial_get_mctrl(&uart->port); | |
4cb4f22b | 529 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); |
194de561 BW |
530 | if (!(status & TIOCM_CTS)) { |
531 | tty->hw_stopped = 1; | |
f30ac0ce SZ |
532 | uart->cts_timer.data = (unsigned long)(uart); |
533 | uart->cts_timer.function = (void *)bfin_serial_mctrl_check; | |
534 | uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES; | |
535 | add_timer(&(uart->cts_timer)); | |
194de561 BW |
536 | } else { |
537 | tty->hw_stopped = 0; | |
538 | } | |
194de561 BW |
539 | #endif |
540 | } | |
541 | ||
542 | /* | |
543 | * Interrupts are always disabled. | |
544 | */ | |
545 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) | |
546 | { | |
cf686762 MF |
547 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
548 | u16 lcr = UART_GET_LCR(uart); | |
549 | if (break_state) | |
550 | lcr |= SB; | |
551 | else | |
552 | lcr &= ~SB; | |
553 | UART_PUT_LCR(uart, lcr); | |
554 | SSYNC(); | |
194de561 BW |
555 | } |
556 | ||
557 | static int bfin_serial_startup(struct uart_port *port) | |
558 | { | |
559 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
560 | ||
561 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
562 | dma_addr_t dma_handle; | |
563 | ||
564 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
565 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
566 | return -EBUSY; | |
567 | } | |
568 | ||
569 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
570 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
571 | free_dma(uart->rx_dma_channel); | |
572 | return -EBUSY; | |
573 | } | |
574 | ||
575 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
576 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
577 | ||
578 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
579 | uart->rx_dma_buf.head = 0; | |
580 | uart->rx_dma_buf.tail = 0; | |
581 | uart->rx_dma_nrows = 0; | |
582 | ||
583 | set_dma_config(uart->rx_dma_channel, | |
584 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
585 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
586 | DATA_SIZE_8, |
587 | DMA_SYNC_RESTART)); | |
194de561 BW |
588 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
589 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
590 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
591 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
592 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
593 | enable_dma(uart->rx_dma_channel); | |
594 | ||
595 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
596 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
597 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
598 | add_timer(&(uart->rx_dma_timer)); | |
599 | #else | |
52e15f0e SZ |
600 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
601 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
602 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
603 | kgdboc_break_enabled = 0; | |
604 | else { | |
605 | # endif | |
a359cca7 SZ |
606 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
607 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
608 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
609 | return -EBUSY; | |
610 | } | |
611 | ||
612 | if (request_irq | |
5c4e472b | 613 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
614 | "BFIN_UART_TX", uart)) { |
615 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
616 | free_irq(uart->port.irq, uart); | |
617 | return -EBUSY; | |
618 | } | |
ab2375f2 SZ |
619 | |
620 | # ifdef CONFIG_BF54x | |
621 | { | |
622 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; | |
623 | ||
624 | switch (uart->port.irq) { | |
625 | case IRQ_UART3_RX: | |
626 | uart_dma_ch_rx = CH_UART3_RX; | |
627 | uart_dma_ch_tx = CH_UART3_TX; | |
628 | break; | |
629 | case IRQ_UART2_RX: | |
630 | uart_dma_ch_rx = CH_UART2_RX; | |
631 | uart_dma_ch_tx = CH_UART2_TX; | |
632 | break; | |
633 | default: | |
634 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
635 | break; | |
636 | }; | |
637 | ||
638 | if (uart_dma_ch_rx && | |
639 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
640 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
641 | free_irq(uart->port.irq, uart); | |
642 | free_irq(uart->port.irq + 1, uart); | |
643 | return -EBUSY; | |
644 | } | |
645 | if (uart_dma_ch_tx && | |
646 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
647 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
648 | free_dma(uart_dma_ch_rx); | |
649 | free_irq(uart->port.irq, uart); | |
650 | free_irq(uart->port.irq + 1, uart); | |
651 | return -EBUSY; | |
652 | } | |
653 | } | |
654 | # endif | |
52e15f0e SZ |
655 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
656 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
657 | } | |
658 | # endif | |
194de561 | 659 | #endif |
f4d640c9 | 660 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
661 | return 0; |
662 | } | |
663 | ||
664 | static void bfin_serial_shutdown(struct uart_port *port) | |
665 | { | |
666 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
667 | ||
668 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
669 | disable_dma(uart->tx_dma_channel); | |
670 | free_dma(uart->tx_dma_channel); | |
671 | disable_dma(uart->rx_dma_channel); | |
672 | free_dma(uart->rx_dma_channel); | |
673 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 674 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 675 | #else |
ab2375f2 SZ |
676 | #ifdef CONFIG_BF54x |
677 | switch (uart->port.irq) { | |
678 | case IRQ_UART3_RX: | |
679 | free_dma(CH_UART3_RX); | |
680 | free_dma(CH_UART3_TX); | |
681 | break; | |
682 | case IRQ_UART2_RX: | |
683 | free_dma(CH_UART2_RX); | |
684 | free_dma(CH_UART2_TX); | |
685 | break; | |
686 | default: | |
687 | break; | |
688 | }; | |
474f1a66 | 689 | #endif |
194de561 BW |
690 | free_irq(uart->port.irq, uart); |
691 | free_irq(uart->port.irq+1, uart); | |
692 | #endif | |
693 | } | |
694 | ||
695 | static void | |
696 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
697 | struct ktermios *old) | |
698 | { | |
699 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
700 | unsigned long flags; | |
701 | unsigned int baud, quot; | |
0c44a86d | 702 | unsigned short val, ier, lcr = 0; |
194de561 BW |
703 | |
704 | switch (termios->c_cflag & CSIZE) { | |
705 | case CS8: | |
706 | lcr = WLS(8); | |
707 | break; | |
708 | case CS7: | |
709 | lcr = WLS(7); | |
710 | break; | |
711 | case CS6: | |
712 | lcr = WLS(6); | |
713 | break; | |
714 | case CS5: | |
715 | lcr = WLS(5); | |
716 | break; | |
717 | default: | |
718 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 719 | __func__); |
194de561 BW |
720 | } |
721 | ||
722 | if (termios->c_cflag & CSTOPB) | |
723 | lcr |= STB; | |
19aa6382 | 724 | if (termios->c_cflag & PARENB) |
194de561 | 725 | lcr |= PEN; |
19aa6382 MF |
726 | if (!(termios->c_cflag & PARODD)) |
727 | lcr |= EPS; | |
728 | if (termios->c_cflag & CMSPAR) | |
729 | lcr |= STP; | |
194de561 | 730 | |
2ac5ee47 MF |
731 | port->read_status_mask = OE; |
732 | if (termios->c_iflag & INPCK) | |
733 | port->read_status_mask |= (FE | PE); | |
734 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
735 | port->read_status_mask |= BI; | |
194de561 | 736 | |
2ac5ee47 MF |
737 | /* |
738 | * Characters to ignore | |
739 | */ | |
740 | port->ignore_status_mask = 0; | |
741 | if (termios->c_iflag & IGNPAR) | |
742 | port->ignore_status_mask |= FE | PE; | |
743 | if (termios->c_iflag & IGNBRK) { | |
744 | port->ignore_status_mask |= BI; | |
745 | /* | |
746 | * If we're ignoring parity and break indicators, | |
747 | * ignore overruns too (for real raw support). | |
748 | */ | |
749 | if (termios->c_iflag & IGNPAR) | |
750 | port->ignore_status_mask |= OE; | |
751 | } | |
194de561 BW |
752 | |
753 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
754 | quot = uart_get_divisor(port, baud); | |
755 | spin_lock_irqsave(&uart->port.lock, flags); | |
756 | ||
8851c71e MF |
757 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
758 | ||
194de561 BW |
759 | /* Disable UART */ |
760 | ier = UART_GET_IER(uart); | |
1feaa51d | 761 | UART_DISABLE_INTS(uart); |
194de561 BW |
762 | |
763 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 764 | UART_SET_DLAB(uart); |
194de561 BW |
765 | |
766 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
767 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
768 | SSYNC(); | |
769 | ||
770 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 771 | UART_CLEAR_DLAB(uart); |
194de561 BW |
772 | |
773 | UART_PUT_LCR(uart, lcr); | |
774 | ||
775 | /* Enable UART */ | |
1feaa51d | 776 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
777 | |
778 | val = UART_GET_GCTL(uart); | |
779 | val |= UCEN; | |
780 | UART_PUT_GCTL(uart, val); | |
781 | ||
b3ef5aba GY |
782 | /* Port speed changed, update the per-port timeout. */ |
783 | uart_update_timeout(port, termios->c_cflag, baud); | |
784 | ||
194de561 BW |
785 | spin_unlock_irqrestore(&uart->port.lock, flags); |
786 | } | |
787 | ||
788 | static const char *bfin_serial_type(struct uart_port *port) | |
789 | { | |
790 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
791 | ||
792 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
793 | } | |
794 | ||
795 | /* | |
796 | * Release the memory region(s) being used by 'port'. | |
797 | */ | |
798 | static void bfin_serial_release_port(struct uart_port *port) | |
799 | { | |
800 | } | |
801 | ||
802 | /* | |
803 | * Request the memory region(s) being used by 'port'. | |
804 | */ | |
805 | static int bfin_serial_request_port(struct uart_port *port) | |
806 | { | |
807 | return 0; | |
808 | } | |
809 | ||
810 | /* | |
811 | * Configure/autoconfigure the port. | |
812 | */ | |
813 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
814 | { | |
815 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
816 | ||
817 | if (flags & UART_CONFIG_TYPE && | |
818 | bfin_serial_request_port(&uart->port) == 0) | |
819 | uart->port.type = PORT_BFIN; | |
820 | } | |
821 | ||
822 | /* | |
823 | * Verify the new serial_struct (for TIOCSSERIAL). | |
824 | * The only change we allow are to the flags and type, and | |
825 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
826 | */ | |
827 | static int | |
828 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
829 | { | |
830 | return 0; | |
831 | } | |
832 | ||
7d01b475 GY |
833 | /* |
834 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
835 | * In other cases, disable IrDA function. | |
836 | */ | |
3b8458a9 | 837 | static void bfin_serial_set_ldisc(struct uart_port *port) |
7d01b475 | 838 | { |
3b8458a9 | 839 | int line = port->line; |
7d01b475 GY |
840 | unsigned short val; |
841 | ||
a88487c7 | 842 | if (line >= port->info->port.tty->driver->num) |
7d01b475 GY |
843 | return; |
844 | ||
b1cbefe5 | 845 | switch (port->info->port.tty->termios->c_line) { |
7d01b475 GY |
846 | case N_IRDA: |
847 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
848 | val |= (IREN | RPOLC); | |
849 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
850 | break; | |
851 | default: | |
852 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
853 | val &= ~(IREN | RPOLC); | |
854 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
855 | } | |
856 | } | |
857 | ||
52e15f0e SZ |
858 | #ifdef CONFIG_CONSOLE_POLL |
859 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) | |
860 | { | |
861 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
862 | ||
863 | while (!(UART_GET_LSR(uart) & THRE)) | |
864 | cpu_relax(); | |
865 | ||
866 | UART_CLEAR_DLAB(uart); | |
867 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
868 | } | |
869 | ||
870 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
871 | { | |
872 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
873 | unsigned char chr; | |
874 | ||
875 | while (!(UART_GET_LSR(uart) & DR)) | |
876 | cpu_relax(); | |
877 | ||
878 | UART_CLEAR_DLAB(uart); | |
879 | chr = UART_GET_CHAR(uart); | |
880 | ||
881 | return chr; | |
882 | } | |
883 | #endif | |
884 | ||
885 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
886 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
887 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
888 | { | |
889 | if (kgdboc_break_enabled) { | |
890 | kgdboc_break_enabled = 0; | |
891 | bfin_serial_shutdown(port); | |
892 | } | |
893 | } | |
894 | ||
895 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
896 | { | |
897 | kgdboc_port_line = port->line; | |
898 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
899 | return 0; | |
900 | } | |
901 | #endif | |
902 | ||
80d5c474 GY |
903 | static void bfin_serial_reset_irda(struct uart_port *port) |
904 | { | |
905 | int line = port->line; | |
906 | unsigned short val; | |
907 | ||
908 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
909 | val &= ~(IREN | RPOLC); | |
910 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
911 | SSYNC(); | |
912 | val |= (IREN | RPOLC); | |
913 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
914 | SSYNC(); | |
915 | } | |
916 | ||
194de561 BW |
917 | static struct uart_ops bfin_serial_pops = { |
918 | .tx_empty = bfin_serial_tx_empty, | |
919 | .set_mctrl = bfin_serial_set_mctrl, | |
920 | .get_mctrl = bfin_serial_get_mctrl, | |
921 | .stop_tx = bfin_serial_stop_tx, | |
922 | .start_tx = bfin_serial_start_tx, | |
923 | .stop_rx = bfin_serial_stop_rx, | |
924 | .enable_ms = bfin_serial_enable_ms, | |
925 | .break_ctl = bfin_serial_break_ctl, | |
926 | .startup = bfin_serial_startup, | |
927 | .shutdown = bfin_serial_shutdown, | |
928 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 929 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
930 | .type = bfin_serial_type, |
931 | .release_port = bfin_serial_release_port, | |
932 | .request_port = bfin_serial_request_port, | |
933 | .config_port = bfin_serial_config_port, | |
934 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
935 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
936 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
937 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
938 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
939 | #endif | |
940 | #ifdef CONFIG_CONSOLE_POLL | |
941 | .poll_put_char = bfin_serial_poll_put_char, | |
942 | .poll_get_char = bfin_serial_poll_get_char, | |
943 | #endif | |
194de561 BW |
944 | }; |
945 | ||
946 | static void __init bfin_serial_init_ports(void) | |
947 | { | |
948 | static int first = 1; | |
949 | int i; | |
950 | ||
951 | if (!first) | |
952 | return; | |
953 | first = 0; | |
954 | ||
c9607ecc | 955 | for (i = 0; i < nr_active_ports; i++) { |
194de561 | 956 | bfin_serial_ports[i].port.uartclk = get_sclk(); |
b3ef5aba | 957 | bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; |
194de561 BW |
958 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; |
959 | bfin_serial_ports[i].port.line = i; | |
960 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
961 | bfin_serial_ports[i].port.membase = | |
962 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
963 | bfin_serial_ports[i].port.mapbase = | |
964 | bfin_serial_resource[i].uart_base_addr; | |
965 | bfin_serial_ports[i].port.irq = | |
966 | bfin_serial_resource[i].uart_irq; | |
967 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; | |
968 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
969 | bfin_serial_ports[i].tx_done = 1; | |
970 | bfin_serial_ports[i].tx_count = 0; | |
971 | bfin_serial_ports[i].tx_dma_channel = | |
972 | bfin_serial_resource[i].uart_tx_dma_channel; | |
973 | bfin_serial_ports[i].rx_dma_channel = | |
974 | bfin_serial_resource[i].uart_rx_dma_channel; | |
975 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 BW |
976 | #endif |
977 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
f30ac0ce | 978 | init_timer(&(bfin_serial_ports[i].cts_timer)); |
194de561 BW |
979 | bfin_serial_ports[i].cts_pin = |
980 | bfin_serial_resource[i].uart_cts_pin; | |
981 | bfin_serial_ports[i].rts_pin = | |
982 | bfin_serial_resource[i].uart_rts_pin; | |
983 | #endif | |
984 | bfin_serial_hw_init(&bfin_serial_ports[i]); | |
194de561 | 985 | } |
f4d640c9 | 986 | |
194de561 BW |
987 | } |
988 | ||
b6efa1ea | 989 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
990 | /* |
991 | * If the port was already initialised (eg, by a boot loader), | |
992 | * try to determine the current setup. | |
993 | */ | |
994 | static void __init | |
995 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
996 | int *parity, int *bits) | |
997 | { | |
998 | unsigned short status; | |
999 | ||
1000 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1001 | if (status == (ERBFI | ETBEI)) { | |
1002 | /* ok, the port was enabled */ | |
45828b81 | 1003 | u16 lcr, dlh, dll; |
194de561 BW |
1004 | |
1005 | lcr = UART_GET_LCR(uart); | |
1006 | ||
1007 | *parity = 'n'; | |
1008 | if (lcr & PEN) { | |
1009 | if (lcr & EPS) | |
1010 | *parity = 'e'; | |
1011 | else | |
1012 | *parity = 'o'; | |
1013 | } | |
1014 | switch (lcr & 0x03) { | |
1015 | case 0: *bits = 5; break; | |
1016 | case 1: *bits = 6; break; | |
1017 | case 2: *bits = 7; break; | |
1018 | case 3: *bits = 8; break; | |
1019 | } | |
1020 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1021 | UART_SET_DLAB(uart); |
194de561 BW |
1022 | |
1023 | dll = UART_GET_DLL(uart); | |
1024 | dlh = UART_GET_DLH(uart); | |
1025 | ||
1026 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1027 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1028 | |
1029 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1030 | } | |
71cc2c21 | 1031 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1032 | } |
0ae53640 | 1033 | |
0ae53640 | 1034 | static struct uart_driver bfin_serial_reg; |
194de561 BW |
1035 | |
1036 | static int __init | |
1037 | bfin_serial_console_setup(struct console *co, char *options) | |
1038 | { | |
1039 | struct bfin_serial_port *uart; | |
1040 | int baud = 57600; | |
1041 | int bits = 8; | |
1042 | int parity = 'n'; | |
b6efa1ea | 1043 | # ifdef CONFIG_SERIAL_BFIN_CTSRTS |
194de561 | 1044 | int flow = 'r'; |
b6efa1ea | 1045 | # else |
194de561 | 1046 | int flow = 'n'; |
0ae53640 | 1047 | # endif |
194de561 BW |
1048 | |
1049 | /* | |
1050 | * Check whether an invalid uart number has been specified, and | |
1051 | * if so, search for the first available port that does have | |
1052 | * console support. | |
1053 | */ | |
c9607ecc | 1054 | if (co->index == -1 || co->index >= nr_active_ports) |
194de561 BW |
1055 | co->index = 0; |
1056 | uart = &bfin_serial_ports[co->index]; | |
1057 | ||
1058 | if (options) | |
1059 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1060 | else | |
1061 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1062 | ||
1063 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1064 | } |
1065 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1066 | defined (CONFIG_EARLY_PRINTK) */ | |
1067 | ||
1068 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1069 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1070 | { | |
1071 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1072 | while (!(UART_GET_LSR(uart) & THRE)) | |
1073 | barrier(); | |
1074 | UART_PUT_CHAR(uart, ch); | |
1075 | SSYNC(); | |
1076 | } | |
1077 | ||
1078 | /* | |
1079 | * Interrupts are disabled on entering | |
1080 | */ | |
1081 | static void | |
1082 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1083 | { | |
1084 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
1085 | int flags = 0; | |
1086 | ||
1087 | spin_lock_irqsave(&uart->port.lock, flags); | |
1088 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1089 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1090 | ||
194de561 BW |
1091 | } |
1092 | ||
194de561 BW |
1093 | static struct console bfin_serial_console = { |
1094 | .name = BFIN_SERIAL_NAME, | |
1095 | .write = bfin_serial_console_write, | |
1096 | .device = uart_console_device, | |
1097 | .setup = bfin_serial_console_setup, | |
1098 | .flags = CON_PRINTBUFFER, | |
1099 | .index = -1, | |
1100 | .data = &bfin_serial_reg, | |
1101 | }; | |
1102 | ||
1103 | static int __init bfin_serial_rs_console_init(void) | |
1104 | { | |
1105 | bfin_serial_init_ports(); | |
1106 | register_console(&bfin_serial_console); | |
52e15f0e | 1107 | |
194de561 BW |
1108 | return 0; |
1109 | } | |
1110 | console_initcall(bfin_serial_rs_console_init); | |
1111 | ||
1112 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1113 | #else | |
1114 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1115 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1116 | ||
1117 | ||
1118 | #ifdef CONFIG_EARLY_PRINTK | |
1119 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1120 | { | |
1121 | unsigned timeout = 0xffff; | |
1122 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1123 | ||
1124 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1125 | cpu_relax(); | |
1126 | UART_PUT_CHAR(uart, ch); | |
1127 | } | |
1128 | ||
1129 | static __init void early_serial_write(struct console *con, const char *s, | |
1130 | unsigned int n) | |
1131 | { | |
1132 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1133 | unsigned int i; | |
1134 | ||
1135 | for (i = 0; i < n; i++, s++) { | |
1136 | if (*s == '\n') | |
1137 | early_serial_putc(&uart->port, '\r'); | |
1138 | early_serial_putc(&uart->port, *s); | |
1139 | } | |
1140 | } | |
1141 | ||
c1113400 | 1142 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 RG |
1143 | .name = "early_BFuart", |
1144 | .write = early_serial_write, | |
1145 | .device = uart_console_device, | |
1146 | .flags = CON_PRINTBUFFER, | |
1147 | .setup = bfin_serial_console_setup, | |
1148 | .index = -1, | |
1149 | .data = &bfin_serial_reg, | |
1150 | }; | |
1151 | ||
1152 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1153 | unsigned int cflag) | |
1154 | { | |
1155 | struct bfin_serial_port *uart; | |
1156 | struct ktermios t; | |
1157 | ||
c9607ecc | 1158 | if (port == -1 || port >= nr_active_ports) |
0ae53640 RG |
1159 | port = 0; |
1160 | bfin_serial_init_ports(); | |
1161 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1162 | uart = &bfin_serial_ports[port]; |
1163 | t.c_cflag = cflag; | |
1164 | t.c_iflag = 0; | |
1165 | t.c_oflag = 0; | |
1166 | t.c_lflag = ICANON; | |
1167 | t.c_line = port; | |
1168 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1169 | return &bfin_early_serial_console; | |
1170 | } | |
1171 | ||
b6efa1ea | 1172 | #endif /* CONFIG_EARLY_PRINTK */ |
194de561 BW |
1173 | |
1174 | static struct uart_driver bfin_serial_reg = { | |
1175 | .owner = THIS_MODULE, | |
1176 | .driver_name = "bfin-uart", | |
1177 | .dev_name = BFIN_SERIAL_NAME, | |
1178 | .major = BFIN_SERIAL_MAJOR, | |
1179 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1180 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1181 | .cons = BFIN_SERIAL_CONSOLE, |
1182 | }; | |
1183 | ||
1184 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1185 | { | |
ccfbc3e1 | 1186 | int i; |
194de561 | 1187 | |
c9607ecc | 1188 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1189 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1190 | continue; | |
1191 | uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1192 | } | |
194de561 BW |
1193 | |
1194 | return 0; | |
1195 | } | |
1196 | ||
1197 | static int bfin_serial_resume(struct platform_device *dev) | |
1198 | { | |
ccfbc3e1 | 1199 | int i; |
194de561 | 1200 | |
c9607ecc | 1201 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1202 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1203 | continue; | |
1204 | uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1205 | } | |
194de561 BW |
1206 | |
1207 | return 0; | |
1208 | } | |
1209 | ||
1210 | static int bfin_serial_probe(struct platform_device *dev) | |
1211 | { | |
1212 | struct resource *res = dev->resource; | |
1213 | int i; | |
1214 | ||
1215 | for (i = 0; i < dev->num_resources; i++, res++) | |
1216 | if (res->flags & IORESOURCE_MEM) | |
1217 | break; | |
1218 | ||
1219 | if (i < dev->num_resources) { | |
c9607ecc | 1220 | for (i = 0; i < nr_active_ports; i++, res++) { |
194de561 BW |
1221 | if (bfin_serial_ports[i].port.mapbase != res->start) |
1222 | continue; | |
1223 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1224 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
194de561 BW |
1225 | } |
1226 | } | |
1227 | ||
1228 | return 0; | |
1229 | } | |
1230 | ||
ccfbc3e1 | 1231 | static int bfin_serial_remove(struct platform_device *dev) |
194de561 | 1232 | { |
ccfbc3e1 | 1233 | int i; |
194de561 | 1234 | |
c9607ecc | 1235 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1236 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1237 | continue; | |
1238 | uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1239 | bfin_serial_ports[i].port.dev = NULL; | |
194de561 | 1240 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
ccfbc3e1 SZ |
1241 | gpio_free(bfin_serial_ports[i].cts_pin); |
1242 | gpio_free(bfin_serial_ports[i].rts_pin); | |
194de561 | 1243 | #endif |
ccfbc3e1 | 1244 | } |
194de561 BW |
1245 | |
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | static struct platform_driver bfin_serial_driver = { | |
1250 | .probe = bfin_serial_probe, | |
1251 | .remove = bfin_serial_remove, | |
1252 | .suspend = bfin_serial_suspend, | |
1253 | .resume = bfin_serial_resume, | |
1254 | .driver = { | |
1255 | .name = "bfin-uart", | |
e169c139 | 1256 | .owner = THIS_MODULE, |
194de561 BW |
1257 | }, |
1258 | }; | |
1259 | ||
1260 | static int __init bfin_serial_init(void) | |
1261 | { | |
1262 | int ret; | |
1263 | ||
1264 | pr_info("Serial: Blackfin serial driver\n"); | |
1265 | ||
1266 | bfin_serial_init_ports(); | |
1267 | ||
1268 | ret = uart_register_driver(&bfin_serial_reg); | |
1269 | if (ret == 0) { | |
1270 | ret = platform_driver_register(&bfin_serial_driver); | |
1271 | if (ret) { | |
1272 | pr_debug("uart register failed\n"); | |
1273 | uart_unregister_driver(&bfin_serial_reg); | |
1274 | } | |
1275 | } | |
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | static void __exit bfin_serial_exit(void) | |
1280 | { | |
1281 | platform_driver_unregister(&bfin_serial_driver); | |
1282 | uart_unregister_driver(&bfin_serial_reg); | |
1283 | } | |
1284 | ||
52e15f0e | 1285 | |
194de561 BW |
1286 | module_init(bfin_serial_init); |
1287 | module_exit(bfin_serial_exit); | |
1288 | ||
1289 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1290 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1291 | MODULE_LICENSE("GPL"); | |
1292 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1293 | MODULE_ALIAS("platform:bfin-uart"); |