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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6
[net-next-2.6.git] / drivers / serial / bfin_5xx.c
CommitLineData
194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
d273e201 4 * Copyright 2006-2008 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW		 9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
474f1a66
SZ		 25#ifdef CONFIG_KGDB_UART
26#include <linux/kgdb.h>
27#include <asm/irq_regs.h>
28#endif
29
194de561 30#include <asm/gpio.h>
639f6571 31#include <mach/bfin_serial_5xx.h>
194de561
BW		 32
33#ifdef CONFIG_SERIAL_BFIN_DMA
34#include <linux/dma-mapping.h>
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/cacheflush.h>
38#endif
39
40/* UART name and device definitions */
41#define BFIN_SERIAL_NAME "ttyBF"
42#define BFIN_SERIAL_MAJOR 204
43#define BFIN_SERIAL_MINOR 64
44
c9607ecc
MF		 45static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
46static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource);
47
194de561
BW		 48/*
49 * Setup for console. Argument comes from the menuconfig
50 */
51#define DMA_RX_XCOUNT 512
52#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
53
0aef4564 54#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
f30ac0ce 55#define CTS_CHECK_JIFFIES (HZ / 50)
194de561
BW		 56
57#ifdef CONFIG_SERIAL_BFIN_DMA
58static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
59#else
194de561 60static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW		 61#endif
62
63static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
64
65/*
66 * interrupts are disabled on entry
67 */
68static void bfin_serial_stop_tx(struct uart_port *port)
69{
70 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
0711d857 71 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 72
f4d640c9 73 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 74 cpu_relax();
f4d640c9 75
194de561
BW		 76#ifdef CONFIG_SERIAL_BFIN_DMA
77 disable_dma(uart->tx_dma_channel);
0711d857
SZ		 78 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
79 uart->port.icount.tx += uart->tx_count;
80 uart->tx_count = 0;
81 uart->tx_done = 1;
f4d640c9
RH		 82#else
83#ifdef CONFIG_BF54x
f4d640c9
RH		 84 /* Clear TFI bit */
85 UART_PUT_LSR(uart, TFI);
194de561 86#endif
89bf6dc5 87 UART_CLEAR_IER(uart, ETBEI);
f4d640c9 88#endif
194de561
BW		 89}
90
91/*
92 * port is locked and interrupts are disabled
93 */
94static void bfin_serial_start_tx(struct uart_port *port)
95{
96 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
97
98#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ		 99 if (uart->tx_done)
100 bfin_serial_dma_tx_chars(uart);
f4d640c9 101#else
f4d640c9 102 UART_SET_IER(uart, ETBEI);
a359cca7 103 bfin_serial_tx_chars(uart);
f4d640c9 104#endif
194de561
BW		 105}
106
107/*
108 * Interrupts are enabled
109 */
110static void bfin_serial_stop_rx(struct uart_port *port)
111{
112 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
89bf6dc5
MF		 113#ifdef CONFIG_KGDB_UART
114 if (uart->port.line != CONFIG_KGDB_UART_PORT)
a359cca7 115#endif
f4d640c9 116 UART_CLEAR_IER(uart, ERBFI);
194de561
BW		 117}
118
119/*
120 * Set the modem control timer to fire immediately.
121 */
122static void bfin_serial_enable_ms(struct uart_port *port)
123{
124}
125
474f1a66
SZ		 126#ifdef CONFIG_KGDB_UART
127static int kgdb_entry_state;
128
129void kgdb_put_debug_char(int chr)
130{
131 struct bfin_serial_port *uart;
d273e201 132
2ade9729
GY		 133 if (CONFIG_KGDB_UART_PORT < 0
134 || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS)
474f1a66
SZ		 135 uart = &bfin_serial_ports[0];
136 else
137 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
d273e201 138
474f1a66 139 while (!(UART_GET_LSR(uart) & THRE)) {
d5148ffa 140 SSYNC();
474f1a66 141 }
a359cca7 142
45828b81 143 UART_CLEAR_DLAB(uart);
474f1a66 144 UART_PUT_CHAR(uart, (unsigned char)chr);
d5148ffa 145 SSYNC();
474f1a66
SZ		 146}
147
148int kgdb_get_debug_char(void)
149{
150 struct bfin_serial_port *uart;
151 unsigned char chr;
152
2ade9729
GY		 153 if (CONFIG_KGDB_UART_PORT < 0
154 || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS)
474f1a66
SZ		 155 uart = &bfin_serial_ports[0];
156 else
157 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
d273e201 158
474f1a66 159 while(!(UART_GET_LSR(uart) & DR)) {
d5148ffa 160 SSYNC();
474f1a66 161 }
45828b81 162 UART_CLEAR_DLAB(uart);
474f1a66 163 chr = UART_GET_CHAR(uart);
d5148ffa 164 SSYNC();
474f1a66
SZ		 165
166 return chr;
167}
168#endif
169
50e2e15a 170#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF		 171# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
172# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
173#else
174# define UART_GET_ANOMALY_THRESHOLD(uart) 0
175# define UART_SET_ANOMALY_THRESHOLD(uart, v)
176#endif
177
194de561 178#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW		 179static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
180{
a88487c7 181 struct tty_struct *tty = uart->port.info->port.tty;
194de561 182 unsigned int status, ch, flg;
8851c71e 183 static struct timeval anomaly_start = { .tv_sec = 0 };
194de561 184
759eb040 185 status = UART_GET_LSR(uart);
0bcfd70e
MF		 186 UART_CLEAR_LSR(uart);
187
188 ch = UART_GET_CHAR(uart);
194de561
BW		 189 uart->port.icount.rx++;
190
474f1a66
SZ		 191#ifdef CONFIG_KGDB_UART
192 if (uart->port.line == CONFIG_KGDB_UART_PORT) {
89bf6dc5 193 struct pt_regs *regs = get_irq_regs();
474f1a66
SZ		 194 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
195 kgdb_breakkey_pressed(regs);
196 return;
197 } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
198 kgdb_entry_state = 1;
199 } else if (kgdb_entry_state == 1 && ch == 'q') {
200 kgdb_entry_state = 0;
201 kgdb_breakkey_pressed(regs);
202 return;
203 } else if (ch == 0x3) {/* Ctrl + C */
204 kgdb_entry_state = 0;
205 kgdb_breakkey_pressed(regs);
206 return;
207 } else {
208 kgdb_entry_state = 0;
209 }
210 }
211#endif
bbf275f0 212
50e2e15a 213 if (ANOMALY_05000363) {
8851c71e
MF		 214 /* The BF533 (and BF561) family of processors have a nice anomaly
215 * where they continuously generate characters for a "single" break.
bbf275f0 216 * We have to basically ignore this flood until the "next" valid
8851c71e
MF		 217 * character comes across. Due to the nature of the flood, it is
218 * not possible to reliably catch bytes that are sent too quickly
219 * after this break. So application code talking to the Blackfin
220 * which sends a break signal must allow at least 1.5 character
221 * times after the end of the break for things to stabilize. This
222 * timeout was picked as it must absolutely be larger than 1
223 * character time +/- some percent. So 1.5 sounds good. All other
224 * Blackfin families operate properly. Woo.
bbf275f0 225 */
8851c71e
MF		 226 if (anomaly_start.tv_sec) {
227 struct timeval curr;
228 suseconds_t usecs;
229
230 if ((~ch & (~ch + 1)) & 0xff)
231 goto known_good_char;
232
233 do_gettimeofday(&curr);
234 if (curr.tv_sec - anomaly_start.tv_sec > 1)
235 goto known_good_char;
236
237 usecs = 0;
238 if (curr.tv_sec != anomaly_start.tv_sec)
239 usecs += USEC_PER_SEC;
240 usecs += curr.tv_usec - anomaly_start.tv_usec;
241
242 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
243 goto known_good_char;
244
245 if (ch)
246 anomaly_start.tv_sec = 0;
247 else
248 anomaly_start = curr;
249
250 return;
251
252 known_good_char:
253 anomaly_start.tv_sec = 0;
bbf275f0 254 }
194de561 255 }
194de561
BW		 256
257 if (status & BI) {
50e2e15a 258 if (ANOMALY_05000363)
8851c71e
MF		 259 if (bfin_revid() < 5)
260 do_gettimeofday(&anomaly_start);
194de561
BW		 261 uart->port.icount.brk++;
262 if (uart_handle_break(&uart->port))
263 goto ignore_char;
9808901b 264 status &= ~(PE | FE);
2ac5ee47
MF		 265 }
266 if (status & PE)
194de561 267 uart->port.icount.parity++;
2ac5ee47 268 if (status & OE)
194de561 269 uart->port.icount.overrun++;
2ac5ee47 270 if (status & FE)
194de561 271 uart->port.icount.frame++;
2ac5ee47
MF		 272
273 status &= uart->port.read_status_mask;
274
275 if (status & BI)
276 flg = TTY_BREAK;
277 else if (status & PE)
278 flg = TTY_PARITY;
279 else if (status & FE)
280 flg = TTY_FRAME;
281 else
194de561
BW		 282 flg = TTY_NORMAL;
283
284 if (uart_handle_sysrq_char(&uart->port, ch))
285 goto ignore_char;
194de561 286
2ac5ee47
MF		 287 uart_insert_char(&uart->port, status, OE, ch, flg);
288
289 ignore_char:
290 tty_flip_buffer_push(tty);
194de561
BW		 291}
292
293static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
294{
295 struct circ_buf *xmit = &uart->port.info->xmit;
296
194de561
BW		 297 /*
298 * Check the modem control lines before
299 * transmitting anything.
300 */
301 bfin_serial_mctrl_check(uart);
302
303 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
5ffdeea2
SZ		 304#ifdef CONFIG_BF54x
305 /* Clear TFI bit */
306 UART_PUT_LSR(uart, TFI);
307#endif
308 UART_CLEAR_IER(uart, ETBEI);
194de561
BW		 309 return;
310 }
311
f30ac0ce
SZ		 312 if (uart->port.x_char) {
313 UART_PUT_CHAR(uart, uart->port.x_char);
314 uart->port.icount.tx++;
315 uart->port.x_char = 0;
316 }
317
759eb040
SZ		 318 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
319 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
320 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
321 uart->port.icount.tx++;
322 SSYNC();
323 }
194de561
BW		 324
325 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
326 uart_write_wakeup(&uart->port);
194de561
BW		 327}
328
5c4e472b
AL		 329static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
330{
331 struct bfin_serial_port *uart = dev_id;
332
f4d640c9 333 spin_lock(&uart->port.lock);
0bcfd70e 334 while (UART_GET_LSR(uart) & DR)
f4d640c9 335 bfin_serial_rx_chars(uart);
f4d640c9 336 spin_unlock(&uart->port.lock);
759eb040 337
5c4e472b
AL		 338 return IRQ_HANDLED;
339}
340
341static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW		 342{
343 struct bfin_serial_port *uart = dev_id;
194de561 344
f4d640c9 345 spin_lock(&uart->port.lock);
0bcfd70e 346 if (UART_GET_LSR(uart) & THRE)
f4d640c9 347 bfin_serial_tx_chars(uart);
f4d640c9 348 spin_unlock(&uart->port.lock);
759eb040 349
194de561
BW		 350 return IRQ_HANDLED;
351}
4cb4f22b 352#endif
194de561 353
194de561
BW		 354#ifdef CONFIG_SERIAL_BFIN_DMA
355static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
356{
357 struct circ_buf *xmit = &uart->port.info->xmit;
194de561 358
194de561
BW		 359 uart->tx_done = 0;
360
f30ac0ce
SZ		 361 /*
362 * Check the modem control lines before
363 * transmitting anything.
364 */
365 bfin_serial_mctrl_check(uart);
366
1b73351c 367 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 368 uart->tx_count = 0;
1b73351c
SZ		 369 uart->tx_done = 1;
370 return;
371 }
372
194de561
BW		 373 if (uart->port.x_char) {
374 UART_PUT_CHAR(uart, uart->port.x_char);
375 uart->port.icount.tx++;
376 uart->port.x_char = 0;
194de561 377 }
1b73351c 378
194de561
BW		 379 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
380 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
381 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
382 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
383 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
384 set_dma_config(uart->tx_dma_channel,
385 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
386 INTR_ON_BUF,
387 DIMENSION_LINEAR,
2047e40d
MH		 388 DATA_SIZE_8,
389 DMA_SYNC_RESTART));
194de561
BW		 390 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
391 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
392 set_dma_x_modify(uart->tx_dma_channel, 1);
393 enable_dma(uart->tx_dma_channel);
99ee7b5f 394
f4d640c9 395 UART_SET_IER(uart, ETBEI);
194de561
BW		 396}
397
2ac5ee47 398static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561 399{
a88487c7 400 struct tty_struct *tty = uart->port.info->port.tty;
194de561
BW		 401 int i, flg, status;
402
403 status = UART_GET_LSR(uart);
0bcfd70e
MF		 404 UART_CLEAR_LSR(uart);
405
56f5de8f
SZ		 406 uart->port.icount.rx +=
407 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
408 UART_XMIT_SIZE);
194de561
BW		 409
410 if (status & BI) {
411 uart->port.icount.brk++;
412 if (uart_handle_break(&uart->port))
413 goto dma_ignore_char;
9808901b 414 status &= ~(PE | FE);
2ac5ee47
MF		 415 }
416 if (status & PE)
194de561 417 uart->port.icount.parity++;
2ac5ee47 418 if (status & OE)
194de561 419 uart->port.icount.overrun++;
2ac5ee47 420 if (status & FE)
194de561 421 uart->port.icount.frame++;
2ac5ee47
MF		 422
423 status &= uart->port.read_status_mask;
424
425 if (status & BI)
426 flg = TTY_BREAK;
427 else if (status & PE)
428 flg = TTY_PARITY;
429 else if (status & FE)
430 flg = TTY_FRAME;
431 else
194de561
BW		 432 flg = TTY_NORMAL;
433
56f5de8f
SZ		 434 for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
435 if (i >= UART_XMIT_SIZE)
436 i = 0;
437 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
438 uart_insert_char(&uart->port, status, OE,
439 uart->rx_dma_buf.buf[i], flg);
194de561 440 }
2ac5ee47
MF		 441
442 dma_ignore_char:
194de561
BW		 443 tty_flip_buffer_push(tty);
444}
445
446void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
447{
448 int x_pos, pos;
194de561 449
56f5de8f
SZ		 450 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
451 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
452 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
453 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
454 uart->rx_dma_nrows = 0;
455 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW		 456 if (x_pos == DMA_RX_XCOUNT)
457 x_pos = 0;
458
459 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
56f5de8f
SZ		 460 if (pos != uart->rx_dma_buf.tail) {
461 uart->rx_dma_buf.head = pos;
194de561 462 bfin_serial_dma_rx_chars(uart);
56f5de8f 463 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 464 }
0aef4564 465
0a278423 466 mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES);
194de561
BW		 467}
468
469static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
470{
471 struct bfin_serial_port *uart = dev_id;
472 struct circ_buf *xmit = &uart->port.info->xmit;
194de561
BW		 473
474 spin_lock(&uart->port.lock);
475 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 476 disable_dma(uart->tx_dma_channel);
0711d857 477 clear_dma_irqstat(uart->tx_dma_channel);
f4d640c9 478 UART_CLEAR_IER(uart, ETBEI);
0711d857
SZ		 479 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
480 uart->port.icount.tx += uart->tx_count;
1b73351c 481
56f5de8f
SZ		 482 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
483 uart_write_wakeup(&uart->port);
484
1b73351c 485 bfin_serial_dma_tx_chars(uart);
194de561
BW		 486 }
487
488 spin_unlock(&uart->port.lock);
489 return IRQ_HANDLED;
490}
491
492static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
493{
494 struct bfin_serial_port *uart = dev_id;
495 unsigned short irqstat;
0711d857 496
194de561
BW		 497 spin_lock(&uart->port.lock);
498 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
499 clear_dma_irqstat(uart->rx_dma_channel);
194de561 500 spin_unlock(&uart->port.lock);
0aef4564 501
0a278423 502 mod_timer(&(uart->rx_dma_timer), jiffies);
0aef4564 503
194de561
BW		 504 return IRQ_HANDLED;
505}
506#endif
507
508/*
509 * Return TIOCSER_TEMT when transmitter is not busy.
510 */
511static unsigned int bfin_serial_tx_empty(struct uart_port *port)
512{
513 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
514 unsigned short lsr;
515
516 lsr = UART_GET_LSR(uart);
517 if (lsr & TEMT)
518 return TIOCSER_TEMT;
519 else
520 return 0;
521}
522
523static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
524{
525#ifdef CONFIG_SERIAL_BFIN_CTSRTS
526 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
527 if (uart->cts_pin < 0)
528 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
529
1feaa51d 530 if (UART_GET_CTS(uart))
194de561
BW		 531 return TIOCM_DSR | TIOCM_CAR;
532 else
533#endif
534 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
535}
536
537static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
538{
539#ifdef CONFIG_SERIAL_BFIN_CTSRTS
540 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
541 if (uart->rts_pin < 0)
542 return;
543
544 if (mctrl & TIOCM_RTS)
1feaa51d 545 UART_CLEAR_RTS(uart);
194de561 546 else
1feaa51d 547 UART_SET_RTS(uart);
194de561
BW		 548#endif
549}
550
551/*
552 * Handle any change of modem status signal since we were last called.
553 */
554static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
555{
556#ifdef CONFIG_SERIAL_BFIN_CTSRTS
557 unsigned int status;
194de561 558 struct uart_info *info = uart->port.info;
a88487c7 559 struct tty_struct *tty = info->port.tty;
194de561
BW		 560
561 status = bfin_serial_get_mctrl(&uart->port);
4cb4f22b 562 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
194de561
BW		 563 if (!(status & TIOCM_CTS)) {
564 tty->hw_stopped = 1;
f30ac0ce
SZ		 565 uart->cts_timer.data = (unsigned long)(uart);
566 uart->cts_timer.function = (void *)bfin_serial_mctrl_check;
567 uart->cts_timer.expires = jiffies + CTS_CHECK_JIFFIES;
568 add_timer(&(uart->cts_timer));
194de561
BW		 569 } else {
570 tty->hw_stopped = 0;
571 }
194de561
BW		 572#endif
573}
574
575/*
576 * Interrupts are always disabled.
577 */
578static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
579{
cf686762
MF		 580 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
581 u16 lcr = UART_GET_LCR(uart);
582 if (break_state)
583 lcr |= SB;
584 else
585 lcr &= ~SB;
586 UART_PUT_LCR(uart, lcr);
587 SSYNC();
194de561
BW		 588}
589
590static int bfin_serial_startup(struct uart_port *port)
591{
592 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
593
594#ifdef CONFIG_SERIAL_BFIN_DMA
595 dma_addr_t dma_handle;
596
597 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
598 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
599 return -EBUSY;
600 }
601
602 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
603 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
604 free_dma(uart->rx_dma_channel);
605 return -EBUSY;
606 }
607
608 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
609 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
610
611 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
612 uart->rx_dma_buf.head = 0;
613 uart->rx_dma_buf.tail = 0;
614 uart->rx_dma_nrows = 0;
615
616 set_dma_config(uart->rx_dma_channel,
617 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
618 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH		 619 DATA_SIZE_8,
620 DMA_SYNC_RESTART));
194de561
BW		 621 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
622 set_dma_x_modify(uart->rx_dma_channel, 1);
623 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
624 set_dma_y_modify(uart->rx_dma_channel, 1);
625 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
626 enable_dma(uart->rx_dma_channel);
627
628 uart->rx_dma_timer.data = (unsigned long)(uart);
629 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
630 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
631 add_timer(&(uart->rx_dma_timer));
632#else
a359cca7
SZ		 633 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
634 "BFIN_UART_RX", uart)) {
474f1a66 635# ifdef CONFIG_KGDB_UART
a359cca7 636 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
474f1a66 637# endif
194de561
BW		 638 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
639 return -EBUSY;
a359cca7
SZ		 640# ifdef CONFIG_KGDB_UART
641 }
642# endif
194de561
BW		 643 }
644
645 if (request_irq
5c4e472b 646 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW		 647 "BFIN_UART_TX", uart)) {
648 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
649 free_irq(uart->port.irq, uart);
650 return -EBUSY;
651 }
ab2375f2
SZ		 652
653# ifdef CONFIG_BF54x
654 {
655 unsigned uart_dma_ch_rx, uart_dma_ch_tx;
656
657 switch (uart->port.irq) {
658 case IRQ_UART3_RX:
659 uart_dma_ch_rx = CH_UART3_RX;
660 uart_dma_ch_tx = CH_UART3_TX;
661 break;
662 case IRQ_UART2_RX:
663 uart_dma_ch_rx = CH_UART2_RX;
664 uart_dma_ch_tx = CH_UART2_TX;
665 break;
666 default:
667 uart_dma_ch_rx = uart_dma_ch_tx = 0;
668 break;
669 };
670
671 if (uart_dma_ch_rx &&
672 request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) {
673 printk(KERN_NOTICE"Fail to attach UART interrupt\n");
674 free_irq(uart->port.irq, uart);
675 free_irq(uart->port.irq + 1, uart);
676 return -EBUSY;
677 }
678 if (uart_dma_ch_tx &&
679 request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) {
680 printk(KERN_NOTICE "Fail to attach UART interrupt\n");
681 free_dma(uart_dma_ch_rx);
682 free_irq(uart->port.irq, uart);
683 free_irq(uart->port.irq + 1, uart);
684 return -EBUSY;
685 }
686 }
687# endif
194de561 688#endif
f4d640c9 689 UART_SET_IER(uart, ERBFI);
194de561
BW		 690 return 0;
691}
692
693static void bfin_serial_shutdown(struct uart_port *port)
694{
695 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
696
697#ifdef CONFIG_SERIAL_BFIN_DMA
698 disable_dma(uart->tx_dma_channel);
699 free_dma(uart->tx_dma_channel);
700 disable_dma(uart->rx_dma_channel);
701 free_dma(uart->rx_dma_channel);
702 del_timer(&(uart->rx_dma_timer));
75b780bd 703 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 704#else
ab2375f2
SZ		 705#ifdef CONFIG_BF54x
706 switch (uart->port.irq) {
707 case IRQ_UART3_RX:
708 free_dma(CH_UART3_RX);
709 free_dma(CH_UART3_TX);
710 break;
711 case IRQ_UART2_RX:
712 free_dma(CH_UART2_RX);
713 free_dma(CH_UART2_TX);
714 break;
715 default:
716 break;
717 };
718#endif
474f1a66
SZ		 719#ifdef CONFIG_KGDB_UART
720 if (uart->port.line != CONFIG_KGDB_UART_PORT)
721#endif
194de561
BW		 722 free_irq(uart->port.irq, uart);
723 free_irq(uart->port.irq+1, uart);
724#endif
725}
726
727static void
728bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
729 struct ktermios *old)
730{
731 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
732 unsigned long flags;
733 unsigned int baud, quot;
0c44a86d 734 unsigned short val, ier, lcr = 0;
194de561
BW		 735
736 switch (termios->c_cflag & CSIZE) {
737 case CS8:
738 lcr = WLS(8);
739 break;
740 case CS7:
741 lcr = WLS(7);
742 break;
743 case CS6:
744 lcr = WLS(6);
745 break;
746 case CS5:
747 lcr = WLS(5);
748 break;
749 default:
750 printk(KERN_ERR "%s: word lengh not supported\n",
71cc2c21 751 __func__);
194de561
BW		 752 }
753
754 if (termios->c_cflag & CSTOPB)
755 lcr |= STB;
19aa6382 756 if (termios->c_cflag & PARENB)
194de561 757 lcr |= PEN;
19aa6382
MF		 758 if (!(termios->c_cflag & PARODD))
759 lcr |= EPS;
760 if (termios->c_cflag & CMSPAR)
761 lcr |= STP;
194de561 762
2ac5ee47
MF		 763 port->read_status_mask = OE;
764 if (termios->c_iflag & INPCK)
765 port->read_status_mask |= (FE | PE);
766 if (termios->c_iflag & (BRKINT | PARMRK))
767 port->read_status_mask |= BI;
194de561 768
2ac5ee47
MF		 769 /*
770 * Characters to ignore
771 */
772 port->ignore_status_mask = 0;
773 if (termios->c_iflag & IGNPAR)
774 port->ignore_status_mask |= FE | PE;
775 if (termios->c_iflag & IGNBRK) {
776 port->ignore_status_mask |= BI;
777 /*
778 * If we're ignoring parity and break indicators,
779 * ignore overruns too (for real raw support).
780 */
781 if (termios->c_iflag & IGNPAR)
782 port->ignore_status_mask |= OE;
783 }
194de561
BW		 784
785 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
786 quot = uart_get_divisor(port, baud);
787 spin_lock_irqsave(&uart->port.lock, flags);
788
8851c71e
MF		 789 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
790
194de561
BW		 791 /* Disable UART */
792 ier = UART_GET_IER(uart);
1feaa51d 793 UART_DISABLE_INTS(uart);
194de561
BW		 794
795 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 796 UART_SET_DLAB(uart);
194de561
BW		 797
798 UART_PUT_DLL(uart, quot & 0xFF);
194de561
BW		 799 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
800 SSYNC();
801
802 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 803 UART_CLEAR_DLAB(uart);
194de561
BW		 804
805 UART_PUT_LCR(uart, lcr);
806
807 /* Enable UART */
1feaa51d 808 UART_ENABLE_INTS(uart, ier);
194de561
BW		 809
810 val = UART_GET_GCTL(uart);
811 val |= UCEN;
812 UART_PUT_GCTL(uart, val);
813
b3ef5aba
GY		 814 /* Port speed changed, update the per-port timeout. */
815 uart_update_timeout(port, termios->c_cflag, baud);
816
194de561
BW		 817 spin_unlock_irqrestore(&uart->port.lock, flags);
818}
819
820static const char *bfin_serial_type(struct uart_port *port)
821{
822 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
823
824 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
825}
826
827/*
828 * Release the memory region(s) being used by 'port'.
829 */
830static void bfin_serial_release_port(struct uart_port *port)
831{
832}
833
834/*
835 * Request the memory region(s) being used by 'port'.
836 */
837static int bfin_serial_request_port(struct uart_port *port)
838{
839 return 0;
840}
841
842/*
843 * Configure/autoconfigure the port.
844 */
845static void bfin_serial_config_port(struct uart_port *port, int flags)
846{
847 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
848
849 if (flags & UART_CONFIG_TYPE &&
850 bfin_serial_request_port(&uart->port) == 0)
851 uart->port.type = PORT_BFIN;
852}
853
854/*
855 * Verify the new serial_struct (for TIOCSSERIAL).
856 * The only change we allow are to the flags and type, and
857 * even then only between PORT_BFIN and PORT_UNKNOWN
858 */
859static int
860bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
861{
862 return 0;
863}
864
7d01b475
GY		 865/*
866 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
867 * In other cases, disable IrDA function.
868 */
3b8458a9 869static void bfin_serial_set_ldisc(struct uart_port *port)
7d01b475 870{
3b8458a9 871 int line = port->line;
7d01b475
GY		 872 unsigned short val;
873
a88487c7 874 if (line >= port->info->port.tty->driver->num)
7d01b475
GY		 875 return;
876
b1cbefe5 877 switch (port->info->port.tty->termios->c_line) {
7d01b475
GY		 878 case N_IRDA:
879 val = UART_GET_GCTL(&bfin_serial_ports[line]);
880 val |= (IREN | RPOLC);
881 UART_PUT_GCTL(&bfin_serial_ports[line], val);
882 break;
883 default:
884 val = UART_GET_GCTL(&bfin_serial_ports[line]);
885 val &= ~(IREN | RPOLC);
886 UART_PUT_GCTL(&bfin_serial_ports[line], val);
887 }
888}
889
194de561
BW		 890static struct uart_ops bfin_serial_pops = {
891 .tx_empty = bfin_serial_tx_empty,
892 .set_mctrl = bfin_serial_set_mctrl,
893 .get_mctrl = bfin_serial_get_mctrl,
894 .stop_tx = bfin_serial_stop_tx,
895 .start_tx = bfin_serial_start_tx,
896 .stop_rx = bfin_serial_stop_rx,
897 .enable_ms = bfin_serial_enable_ms,
898 .break_ctl = bfin_serial_break_ctl,
899 .startup = bfin_serial_startup,
900 .shutdown = bfin_serial_shutdown,
901 .set_termios = bfin_serial_set_termios,
3b8458a9 902 .set_ldisc = bfin_serial_set_ldisc,
194de561
BW		 903 .type = bfin_serial_type,
904 .release_port = bfin_serial_release_port,
905 .request_port = bfin_serial_request_port,
906 .config_port = bfin_serial_config_port,
907 .verify_port = bfin_serial_verify_port,
908};
909
910static void __init bfin_serial_init_ports(void)
911{
912 static int first = 1;
913 int i;
914
915 if (!first)
916 return;
917 first = 0;
918
c9607ecc 919 for (i = 0; i < nr_active_ports; i++) {
194de561 920 bfin_serial_ports[i].port.uartclk = get_sclk();
b3ef5aba 921 bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE;
194de561
BW		 922 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
923 bfin_serial_ports[i].port.line = i;
924 bfin_serial_ports[i].port.iotype = UPIO_MEM;
925 bfin_serial_ports[i].port.membase =
926 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
927 bfin_serial_ports[i].port.mapbase =
928 bfin_serial_resource[i].uart_base_addr;
929 bfin_serial_ports[i].port.irq =
930 bfin_serial_resource[i].uart_irq;
931 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
932#ifdef CONFIG_SERIAL_BFIN_DMA
933 bfin_serial_ports[i].tx_done = 1;
934 bfin_serial_ports[i].tx_count = 0;
935 bfin_serial_ports[i].tx_dma_channel =
936 bfin_serial_resource[i].uart_tx_dma_channel;
937 bfin_serial_ports[i].rx_dma_channel =
938 bfin_serial_resource[i].uart_rx_dma_channel;
939 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561
BW		 940#endif
941#ifdef CONFIG_SERIAL_BFIN_CTSRTS
f30ac0ce 942 init_timer(&(bfin_serial_ports[i].cts_timer));
194de561
BW		 943 bfin_serial_ports[i].cts_pin =
944 bfin_serial_resource[i].uart_cts_pin;
945 bfin_serial_ports[i].rts_pin =
946 bfin_serial_resource[i].uart_rts_pin;
947#endif
948 bfin_serial_hw_init(&bfin_serial_ports[i]);
194de561 949 }
f4d640c9 950
194de561
BW		 951}
952
953#ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 954/*
955 * If the port was already initialised (eg, by a boot loader),
956 * try to determine the current setup.
957 */
958static void __init
959bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
960 int *parity, int *bits)
961{
962 unsigned short status;
963
964 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
965 if (status == (ERBFI | ETBEI)) {
966 /* ok, the port was enabled */
45828b81 967 u16 lcr, dlh, dll;
194de561
BW		 968
969 lcr = UART_GET_LCR(uart);
970
971 *parity = 'n';
972 if (lcr & PEN) {
973 if (lcr & EPS)
974 *parity = 'e';
975 else
976 *parity = 'o';
977 }
978 switch (lcr & 0x03) {
979 case 0: *bits = 5; break;
980 case 1: *bits = 6; break;
981 case 2: *bits = 7; break;
982 case 3: *bits = 8; break;
983 }
984 /* Set DLAB in LCR to Access DLL and DLH */
45828b81 985 UART_SET_DLAB(uart);
194de561
BW		 986
987 dll = UART_GET_DLL(uart);
988 dlh = UART_GET_DLH(uart);
989
990 /* Clear DLAB in LCR to Access THR RBR IER */
45828b81 991 UART_CLEAR_DLAB(uart);
194de561
BW		 992
993 *baud = get_sclk() / (16*(dll | dlh << 8));
994 }
71cc2c21 995 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits);
194de561 996}
0ae53640
RG		 997#endif
998
999#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1000static struct uart_driver bfin_serial_reg;
194de561
BW		 1001
1002static int __init
1003bfin_serial_console_setup(struct console *co, char *options)
1004{
1005 struct bfin_serial_port *uart;
0ae53640 1006# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 1007 int baud = 57600;
1008 int bits = 8;
1009 int parity = 'n';
0ae53640 1010# ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561 1011 int flow = 'r';
0ae53640 1012# else
194de561 1013 int flow = 'n';
0ae53640
RG		 1014# endif
1015# endif
194de561
BW		 1016
1017 /*
1018 * Check whether an invalid uart number has been specified, and
1019 * if so, search for the first available port that does have
1020 * console support.
1021 */
c9607ecc 1022 if (co->index == -1 || co->index >= nr_active_ports)
194de561
BW		 1023 co->index = 0;
1024 uart = &bfin_serial_ports[co->index];
1025
0ae53640 1026# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW		 1027 if (options)
1028 uart_parse_options(options, &baud, &parity, &bits, &flow);
1029 else
1030 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1031
1032 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG		 1033# else
1034 return 0;
1035# endif
1036}
1037#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1038 defined (CONFIG_EARLY_PRINTK) */
1039
1040#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1041static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1042{
1043 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1044 while (!(UART_GET_LSR(uart) & THRE))
1045 barrier();
1046 UART_PUT_CHAR(uart, ch);
1047 SSYNC();
1048}
1049
1050/*
1051 * Interrupts are disabled on entering
1052 */
1053static void
1054bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1055{
1056 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1057 int flags = 0;
1058
1059 spin_lock_irqsave(&uart->port.lock, flags);
1060 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1061 spin_unlock_irqrestore(&uart->port.lock, flags);
1062
194de561
BW		 1063}
1064
194de561
BW		 1065static struct console bfin_serial_console = {
1066 .name = BFIN_SERIAL_NAME,
1067 .write = bfin_serial_console_write,
1068 .device = uart_console_device,
1069 .setup = bfin_serial_console_setup,
1070 .flags = CON_PRINTBUFFER,
1071 .index = -1,
1072 .data = &bfin_serial_reg,
1073};
1074
1075static int __init bfin_serial_rs_console_init(void)
1076{
1077 bfin_serial_init_ports();
1078 register_console(&bfin_serial_console);
474f1a66
SZ		 1079#ifdef CONFIG_KGDB_UART
1080 kgdb_entry_state = 0;
1081 init_kgdb_uart();
1082#endif
194de561
BW		 1083 return 0;
1084}
1085console_initcall(bfin_serial_rs_console_init);
1086
1087#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1088#else
1089#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG		 1090#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1091
1092
1093#ifdef CONFIG_EARLY_PRINTK
1094static __init void early_serial_putc(struct uart_port *port, int ch)
1095{
1096 unsigned timeout = 0xffff;
1097 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1098
1099 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1100 cpu_relax();
1101 UART_PUT_CHAR(uart, ch);
1102}
1103
1104static __init void early_serial_write(struct console *con, const char *s,
1105 unsigned int n)
1106{
1107 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1108 unsigned int i;
1109
1110 for (i = 0; i < n; i++, s++) {
1111 if (*s == '\n')
1112 early_serial_putc(&uart->port, '\r');
1113 early_serial_putc(&uart->port, *s);
1114 }
1115}
1116
c1113400 1117static struct __initdata console bfin_early_serial_console = {
0ae53640
RG		 1118 .name = "early_BFuart",
1119 .write = early_serial_write,
1120 .device = uart_console_device,
1121 .flags = CON_PRINTBUFFER,
1122 .setup = bfin_serial_console_setup,
1123 .index = -1,
1124 .data = &bfin_serial_reg,
1125};
1126
1127struct console __init *bfin_earlyserial_init(unsigned int port,
1128 unsigned int cflag)
1129{
1130 struct bfin_serial_port *uart;
1131 struct ktermios t;
1132
c9607ecc 1133 if (port == -1 || port >= nr_active_ports)
0ae53640
RG		 1134 port = 0;
1135 bfin_serial_init_ports();
1136 bfin_early_serial_console.index = port;
0ae53640
RG		 1137 uart = &bfin_serial_ports[port];
1138 t.c_cflag = cflag;
1139 t.c_iflag = 0;
1140 t.c_oflag = 0;
1141 t.c_lflag = ICANON;
1142 t.c_line = port;
1143 bfin_serial_set_termios(&uart->port, &t, &t);
1144 return &bfin_early_serial_console;
1145}
1146
1147#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
194de561
BW		 1148
1149static struct uart_driver bfin_serial_reg = {
1150 .owner = THIS_MODULE,
1151 .driver_name = "bfin-uart",
1152 .dev_name = BFIN_SERIAL_NAME,
1153 .major = BFIN_SERIAL_MAJOR,
1154 .minor = BFIN_SERIAL_MINOR,
2ade9729 1155 .nr = BFIN_UART_NR_PORTS,
194de561
BW		 1156 .cons = BFIN_SERIAL_CONSOLE,
1157};
1158
1159static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1160{
ccfbc3e1 1161 int i;
194de561 1162
c9607ecc 1163 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1164 if (bfin_serial_ports[i].port.dev != &dev->dev)
1165 continue;
1166 uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1167 }
194de561
BW		 1168
1169 return 0;
1170}
1171
1172static int bfin_serial_resume(struct platform_device *dev)
1173{
ccfbc3e1 1174 int i;
194de561 1175
c9607ecc 1176 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1177 if (bfin_serial_ports[i].port.dev != &dev->dev)
1178 continue;
1179 uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1180 }
194de561
BW		 1181
1182 return 0;
1183}
1184
1185static int bfin_serial_probe(struct platform_device *dev)
1186{
1187 struct resource *res = dev->resource;
1188 int i;
1189
1190 for (i = 0; i < dev->num_resources; i++, res++)
1191 if (res->flags & IORESOURCE_MEM)
1192 break;
1193
1194 if (i < dev->num_resources) {
c9607ecc 1195 for (i = 0; i < nr_active_ports; i++, res++) {
194de561
BW		 1196 if (bfin_serial_ports[i].port.mapbase != res->start)
1197 continue;
1198 bfin_serial_ports[i].port.dev = &dev->dev;
1199 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
194de561
BW		 1200 }
1201 }
1202
1203 return 0;
1204}
1205
ccfbc3e1 1206static int bfin_serial_remove(struct platform_device *dev)
194de561 1207{
ccfbc3e1 1208 int i;
194de561 1209
c9607ecc 1210 for (i = 0; i < nr_active_ports; i++) {
ccfbc3e1
SZ		 1211 if (bfin_serial_ports[i].port.dev != &dev->dev)
1212 continue;
1213 uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1214 bfin_serial_ports[i].port.dev = NULL;
194de561 1215#ifdef CONFIG_SERIAL_BFIN_CTSRTS
ccfbc3e1
SZ		 1216 gpio_free(bfin_serial_ports[i].cts_pin);
1217 gpio_free(bfin_serial_ports[i].rts_pin);
194de561 1218#endif
ccfbc3e1 1219 }
194de561
BW		 1220
1221 return 0;
1222}
1223
1224static struct platform_driver bfin_serial_driver = {
1225 .probe = bfin_serial_probe,
1226 .remove = bfin_serial_remove,
1227 .suspend = bfin_serial_suspend,
1228 .resume = bfin_serial_resume,
1229 .driver = {
1230 .name = "bfin-uart",
e169c139 1231 .owner = THIS_MODULE,
194de561
BW		 1232 },
1233};
1234
1235static int __init bfin_serial_init(void)
1236{
1237 int ret;
474f1a66
SZ		 1238#ifdef CONFIG_KGDB_UART
1239 struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
a359cca7 1240 struct ktermios t;
474f1a66 1241#endif
194de561
BW		 1242
1243 pr_info("Serial: Blackfin serial driver\n");
1244
1245 bfin_serial_init_ports();
1246
1247 ret = uart_register_driver(&bfin_serial_reg);
1248 if (ret == 0) {
1249 ret = platform_driver_register(&bfin_serial_driver);
1250 if (ret) {
1251 pr_debug("uart register failed\n");
1252 uart_unregister_driver(&bfin_serial_reg);
1253 }
1254 }
474f1a66
SZ		 1255#ifdef CONFIG_KGDB_UART
1256 if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
a359cca7 1257 request_irq(uart->port.irq, bfin_serial_rx_int,
474f1a66
SZ		 1258 IRQF_DISABLED, "BFIN_UART_RX", uart);
1259 pr_info("Request irq for kgdb uart port\n");
a359cca7 1260 UART_SET_IER(uart, ERBFI);
d5148ffa 1261 SSYNC();
474f1a66
SZ		 1262 t.c_cflag = CS8|B57600;
1263 t.c_iflag = 0;
1264 t.c_oflag = 0;
1265 t.c_lflag = ICANON;
1266 t.c_line = CONFIG_KGDB_UART_PORT;
1267 bfin_serial_set_termios(&uart->port, &t, &t);
1268 }
1269#endif
194de561
BW		 1270 return ret;
1271}
1272
1273static void __exit bfin_serial_exit(void)
1274{
1275 platform_driver_unregister(&bfin_serial_driver);
1276 uart_unregister_driver(&bfin_serial_reg);
1277}
1278
1279module_init(bfin_serial_init);
1280module_exit(bfin_serial_exit);
1281
1282MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1283MODULE_DESCRIPTION("Blackfin generic serial port driver");
1284MODULE_LICENSE("GPL");
1285MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1286MODULE_ALIAS("platform:bfin-uart");
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