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Commit | Line | Data |
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194de561 | 1 | /* |
1ba7a3ee | 2 | * Blackfin On-Chip Serial Driver |
194de561 | 3 | * |
d273e201 | 4 | * Copyright 2006-2008 Analog Devices Inc. |
194de561 | 5 | * |
1ba7a3ee | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
194de561 | 7 | * |
1ba7a3ee | 8 | * Licensed under the GPL-2 or later. |
194de561 BW |
9 | */ |
10 | ||
11 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |
12 | #define SUPPORT_SYSRQ | |
13 | #endif | |
14 | ||
15 | #include <linux/module.h> | |
16 | #include <linux/ioport.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/console.h> | |
19 | #include <linux/sysrq.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/tty.h> | |
22 | #include <linux/tty_flip.h> | |
23 | #include <linux/serial_core.h> | |
24 | ||
52e15f0e SZ |
25 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
26 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
474f1a66 SZ |
27 | #include <linux/kgdb.h> |
28 | #include <asm/irq_regs.h> | |
29 | #endif | |
30 | ||
194de561 | 31 | #include <asm/gpio.h> |
639f6571 | 32 | #include <mach/bfin_serial_5xx.h> |
194de561 BW |
33 | |
34 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <asm/io.h> | |
37 | #include <asm/irq.h> | |
38 | #include <asm/cacheflush.h> | |
39 | #endif | |
40 | ||
41 | /* UART name and device definitions */ | |
42 | #define BFIN_SERIAL_NAME "ttyBF" | |
43 | #define BFIN_SERIAL_MAJOR 204 | |
44 | #define BFIN_SERIAL_MINOR 64 | |
45 | ||
c9607ecc MF |
46 | static struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS]; |
47 | static int nr_active_ports = ARRAY_SIZE(bfin_serial_resource); | |
48 | ||
52e15f0e SZ |
49 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
50 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
51 | ||
52 | # ifndef CONFIG_SERIAL_BFIN_PIO | |
53 | # error KGDB only support UART in PIO mode. | |
54 | # endif | |
55 | ||
56 | static int kgdboc_port_line; | |
57 | static int kgdboc_break_enabled; | |
58 | #endif | |
194de561 BW |
59 | /* |
60 | * Setup for console. Argument comes from the menuconfig | |
61 | */ | |
62 | #define DMA_RX_XCOUNT 512 | |
63 | #define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT) | |
64 | ||
0aef4564 | 65 | #define DMA_RX_FLUSH_JIFFIES (HZ / 50) |
194de561 BW |
66 | |
67 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
68 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart); | |
69 | #else | |
194de561 | 70 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart); |
194de561 BW |
71 | #endif |
72 | ||
80d5c474 GY |
73 | static void bfin_serial_reset_irda(struct uart_port *port); |
74 | ||
d307d36a SZ |
75 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
76 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
77 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
78 | { | |
79 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80 | if (uart->cts_pin < 0) | |
81 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
82 | ||
83 | /* CTS PIN is negative assertive. */ | |
84 | if (UART_GET_CTS(uart)) | |
85 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
86 | else | |
87 | return TIOCM_DSR | TIOCM_CAR; | |
88 | } | |
89 | ||
90 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
91 | { | |
92 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
93 | if (uart->rts_pin < 0) | |
94 | return; | |
95 | ||
96 | /* RTS PIN is negative assertive. */ | |
97 | if (mctrl & TIOCM_RTS) | |
98 | UART_ENABLE_RTS(uart); | |
99 | else | |
100 | UART_DISABLE_RTS(uart); | |
101 | } | |
102 | ||
103 | /* | |
104 | * Handle any change of modem status signal. | |
105 | */ | |
106 | static irqreturn_t bfin_serial_mctrl_cts_int(int irq, void *dev_id) | |
107 | { | |
108 | struct bfin_serial_port *uart = dev_id; | |
109 | unsigned int status; | |
110 | ||
111 | status = bfin_serial_get_mctrl(&uart->port); | |
112 | uart_handle_cts_change(&uart->port, status & TIOCM_CTS); | |
113 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
114 | uart->scts = 1; | |
115 | UART_CLEAR_SCTS(uart); | |
116 | UART_CLEAR_IER(uart, EDSSI); | |
117 | #endif | |
118 | ||
119 | return IRQ_HANDLED; | |
120 | } | |
121 | #else | |
122 | static unsigned int bfin_serial_get_mctrl(struct uart_port *port) | |
123 | { | |
124 | return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR; | |
125 | } | |
126 | ||
127 | static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl) | |
128 | { | |
129 | } | |
130 | #endif | |
131 | ||
194de561 BW |
132 | /* |
133 | * interrupts are disabled on entry | |
134 | */ | |
135 | static void bfin_serial_stop_tx(struct uart_port *port) | |
136 | { | |
137 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
68a784cb | 138 | #ifdef CONFIG_SERIAL_BFIN_DMA |
0711d857 | 139 | struct circ_buf *xmit = &uart->port.info->xmit; |
68a784cb | 140 | #endif |
194de561 | 141 | |
f4d640c9 | 142 | while (!(UART_GET_LSR(uart) & TEMT)) |
0711d857 | 143 | cpu_relax(); |
f4d640c9 | 144 | |
194de561 BW |
145 | #ifdef CONFIG_SERIAL_BFIN_DMA |
146 | disable_dma(uart->tx_dma_channel); | |
0711d857 SZ |
147 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
148 | uart->port.icount.tx += uart->tx_count; | |
149 | uart->tx_count = 0; | |
150 | uart->tx_done = 1; | |
f4d640c9 RH |
151 | #else |
152 | #ifdef CONFIG_BF54x | |
f4d640c9 RH |
153 | /* Clear TFI bit */ |
154 | UART_PUT_LSR(uart, TFI); | |
194de561 | 155 | #endif |
89bf6dc5 | 156 | UART_CLEAR_IER(uart, ETBEI); |
f4d640c9 | 157 | #endif |
194de561 BW |
158 | } |
159 | ||
160 | /* | |
161 | * port is locked and interrupts are disabled | |
162 | */ | |
163 | static void bfin_serial_start_tx(struct uart_port *port) | |
164 | { | |
165 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
80d5c474 GY |
166 | struct tty_struct *tty = uart->port.info->port.tty; |
167 | ||
d307d36a | 168 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 169 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
170 | uart->scts = 0; |
171 | uart_handle_cts_change(&uart->port, uart->scts); | |
172 | } | |
173 | #endif | |
174 | ||
80d5c474 GY |
175 | /* |
176 | * To avoid losting RX interrupt, we reset IR function | |
177 | * before sending data. | |
178 | */ | |
179 | if (tty->termios->c_line == N_IRDA) | |
180 | bfin_serial_reset_irda(port); | |
194de561 BW |
181 | |
182 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
0711d857 SZ |
183 | if (uart->tx_done) |
184 | bfin_serial_dma_tx_chars(uart); | |
f4d640c9 | 185 | #else |
f4d640c9 | 186 | UART_SET_IER(uart, ETBEI); |
a359cca7 | 187 | bfin_serial_tx_chars(uart); |
f4d640c9 | 188 | #endif |
194de561 BW |
189 | } |
190 | ||
191 | /* | |
192 | * Interrupts are enabled | |
193 | */ | |
194 | static void bfin_serial_stop_rx(struct uart_port *port) | |
195 | { | |
196 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
52e15f0e | 197 | |
f4d640c9 | 198 | UART_CLEAR_IER(uart, ERBFI); |
194de561 BW |
199 | } |
200 | ||
201 | /* | |
202 | * Set the modem control timer to fire immediately. | |
203 | */ | |
204 | static void bfin_serial_enable_ms(struct uart_port *port) | |
205 | { | |
206 | } | |
207 | ||
474f1a66 | 208 | |
50e2e15a | 209 | #if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO) |
8851c71e MF |
210 | # define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold) |
211 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v)) | |
212 | #else | |
213 | # define UART_GET_ANOMALY_THRESHOLD(uart) 0 | |
214 | # define UART_SET_ANOMALY_THRESHOLD(uart, v) | |
215 | #endif | |
216 | ||
194de561 | 217 | #ifdef CONFIG_SERIAL_BFIN_PIO |
194de561 BW |
218 | static void bfin_serial_rx_chars(struct bfin_serial_port *uart) |
219 | { | |
52e15f0e | 220 | struct tty_struct *tty = NULL; |
194de561 | 221 | unsigned int status, ch, flg; |
8851c71e | 222 | static struct timeval anomaly_start = { .tv_sec = 0 }; |
194de561 | 223 | |
759eb040 | 224 | status = UART_GET_LSR(uart); |
0bcfd70e MF |
225 | UART_CLEAR_LSR(uart); |
226 | ||
227 | ch = UART_GET_CHAR(uart); | |
194de561 BW |
228 | uart->port.icount.rx++; |
229 | ||
52e15f0e SZ |
230 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
231 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
232 | if (kgdb_connected && kgdboc_port_line == uart->port.line) | |
233 | if (ch == 0x3) {/* Ctrl + C */ | |
234 | kgdb_breakpoint(); | |
474f1a66 | 235 | return; |
474f1a66 | 236 | } |
52e15f0e | 237 | |
df04baf1 | 238 | if (!uart->port.info || !uart->port.info->port.tty) |
52e15f0e | 239 | return; |
474f1a66 | 240 | #endif |
df04baf1 | 241 | tty = uart->port.info->port.tty; |
bbf275f0 | 242 | |
50e2e15a | 243 | if (ANOMALY_05000363) { |
8851c71e MF |
244 | /* The BF533 (and BF561) family of processors have a nice anomaly |
245 | * where they continuously generate characters for a "single" break. | |
bbf275f0 | 246 | * We have to basically ignore this flood until the "next" valid |
8851c71e MF |
247 | * character comes across. Due to the nature of the flood, it is |
248 | * not possible to reliably catch bytes that are sent too quickly | |
249 | * after this break. So application code talking to the Blackfin | |
250 | * which sends a break signal must allow at least 1.5 character | |
251 | * times after the end of the break for things to stabilize. This | |
252 | * timeout was picked as it must absolutely be larger than 1 | |
253 | * character time +/- some percent. So 1.5 sounds good. All other | |
254 | * Blackfin families operate properly. Woo. | |
bbf275f0 | 255 | */ |
8851c71e MF |
256 | if (anomaly_start.tv_sec) { |
257 | struct timeval curr; | |
258 | suseconds_t usecs; | |
259 | ||
260 | if ((~ch & (~ch + 1)) & 0xff) | |
261 | goto known_good_char; | |
262 | ||
263 | do_gettimeofday(&curr); | |
264 | if (curr.tv_sec - anomaly_start.tv_sec > 1) | |
265 | goto known_good_char; | |
266 | ||
267 | usecs = 0; | |
268 | if (curr.tv_sec != anomaly_start.tv_sec) | |
269 | usecs += USEC_PER_SEC; | |
270 | usecs += curr.tv_usec - anomaly_start.tv_usec; | |
271 | ||
272 | if (usecs > UART_GET_ANOMALY_THRESHOLD(uart)) | |
273 | goto known_good_char; | |
274 | ||
275 | if (ch) | |
276 | anomaly_start.tv_sec = 0; | |
277 | else | |
278 | anomaly_start = curr; | |
279 | ||
280 | return; | |
281 | ||
282 | known_good_char: | |
e482a237 | 283 | status &= ~BI; |
8851c71e | 284 | anomaly_start.tv_sec = 0; |
bbf275f0 | 285 | } |
194de561 | 286 | } |
194de561 BW |
287 | |
288 | if (status & BI) { | |
50e2e15a | 289 | if (ANOMALY_05000363) |
8851c71e MF |
290 | if (bfin_revid() < 5) |
291 | do_gettimeofday(&anomaly_start); | |
194de561 BW |
292 | uart->port.icount.brk++; |
293 | if (uart_handle_break(&uart->port)) | |
294 | goto ignore_char; | |
9808901b | 295 | status &= ~(PE | FE); |
2ac5ee47 MF |
296 | } |
297 | if (status & PE) | |
194de561 | 298 | uart->port.icount.parity++; |
2ac5ee47 | 299 | if (status & OE) |
194de561 | 300 | uart->port.icount.overrun++; |
2ac5ee47 | 301 | if (status & FE) |
194de561 | 302 | uart->port.icount.frame++; |
2ac5ee47 MF |
303 | |
304 | status &= uart->port.read_status_mask; | |
305 | ||
306 | if (status & BI) | |
307 | flg = TTY_BREAK; | |
308 | else if (status & PE) | |
309 | flg = TTY_PARITY; | |
310 | else if (status & FE) | |
311 | flg = TTY_FRAME; | |
312 | else | |
194de561 BW |
313 | flg = TTY_NORMAL; |
314 | ||
315 | if (uart_handle_sysrq_char(&uart->port, ch)) | |
316 | goto ignore_char; | |
194de561 | 317 | |
2ac5ee47 MF |
318 | uart_insert_char(&uart->port, status, OE, ch, flg); |
319 | ||
320 | ignore_char: | |
321 | tty_flip_buffer_push(tty); | |
194de561 BW |
322 | } |
323 | ||
324 | static void bfin_serial_tx_chars(struct bfin_serial_port *uart) | |
325 | { | |
326 | struct circ_buf *xmit = &uart->port.info->xmit; | |
327 | ||
194de561 | 328 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
5ffdeea2 SZ |
329 | #ifdef CONFIG_BF54x |
330 | /* Clear TFI bit */ | |
331 | UART_PUT_LSR(uart, TFI); | |
332 | #endif | |
0efa4f2c SZ |
333 | /* Anomaly notes: |
334 | * 05000215 - we always clear ETBEI within last UART TX | |
335 | * interrupt to end a string. It is always set | |
336 | * when start a new tx. | |
337 | */ | |
5ffdeea2 | 338 | UART_CLEAR_IER(uart, ETBEI); |
194de561 BW |
339 | return; |
340 | } | |
341 | ||
f30ac0ce SZ |
342 | if (uart->port.x_char) { |
343 | UART_PUT_CHAR(uart, uart->port.x_char); | |
344 | uart->port.icount.tx++; | |
345 | uart->port.x_char = 0; | |
346 | } | |
347 | ||
759eb040 SZ |
348 | while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) { |
349 | UART_PUT_CHAR(uart, xmit->buf[xmit->tail]); | |
350 | xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); | |
351 | uart->port.icount.tx++; | |
352 | SSYNC(); | |
353 | } | |
194de561 BW |
354 | |
355 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) | |
356 | uart_write_wakeup(&uart->port); | |
194de561 BW |
357 | } |
358 | ||
5c4e472b AL |
359 | static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id) |
360 | { | |
361 | struct bfin_serial_port *uart = dev_id; | |
362 | ||
f4d640c9 | 363 | spin_lock(&uart->port.lock); |
0bcfd70e | 364 | while (UART_GET_LSR(uart) & DR) |
f4d640c9 | 365 | bfin_serial_rx_chars(uart); |
f4d640c9 | 366 | spin_unlock(&uart->port.lock); |
759eb040 | 367 | |
5c4e472b AL |
368 | return IRQ_HANDLED; |
369 | } | |
370 | ||
371 | static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id) | |
194de561 BW |
372 | { |
373 | struct bfin_serial_port *uart = dev_id; | |
194de561 | 374 | |
d307d36a | 375 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 376 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port) & TIOCM_CTS)) { |
d307d36a SZ |
377 | uart->scts = 0; |
378 | uart_handle_cts_change(&uart->port, uart->scts); | |
379 | } | |
380 | #endif | |
f4d640c9 | 381 | spin_lock(&uart->port.lock); |
0bcfd70e | 382 | if (UART_GET_LSR(uart) & THRE) |
f4d640c9 | 383 | bfin_serial_tx_chars(uart); |
f4d640c9 | 384 | spin_unlock(&uart->port.lock); |
759eb040 | 385 | |
194de561 BW |
386 | return IRQ_HANDLED; |
387 | } | |
4cb4f22b | 388 | #endif |
194de561 | 389 | |
194de561 BW |
390 | #ifdef CONFIG_SERIAL_BFIN_DMA |
391 | static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart) | |
392 | { | |
393 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 394 | |
194de561 BW |
395 | uart->tx_done = 0; |
396 | ||
1b73351c | 397 | if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) { |
0711d857 | 398 | uart->tx_count = 0; |
1b73351c SZ |
399 | uart->tx_done = 1; |
400 | return; | |
401 | } | |
402 | ||
194de561 BW |
403 | if (uart->port.x_char) { |
404 | UART_PUT_CHAR(uart, uart->port.x_char); | |
405 | uart->port.icount.tx++; | |
406 | uart->port.x_char = 0; | |
194de561 | 407 | } |
1b73351c | 408 | |
194de561 BW |
409 | uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE); |
410 | if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail)) | |
411 | uart->tx_count = UART_XMIT_SIZE - xmit->tail; | |
412 | blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail), | |
413 | (unsigned long)(xmit->buf+xmit->tail+uart->tx_count)); | |
414 | set_dma_config(uart->tx_dma_channel, | |
415 | set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP, | |
416 | INTR_ON_BUF, | |
417 | DIMENSION_LINEAR, | |
2047e40d MH |
418 | DATA_SIZE_8, |
419 | DMA_SYNC_RESTART)); | |
194de561 BW |
420 | set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail)); |
421 | set_dma_x_count(uart->tx_dma_channel, uart->tx_count); | |
422 | set_dma_x_modify(uart->tx_dma_channel, 1); | |
f9d36da9 | 423 | SSYNC(); |
194de561 | 424 | enable_dma(uart->tx_dma_channel); |
99ee7b5f | 425 | |
f4d640c9 | 426 | UART_SET_IER(uart, ETBEI); |
194de561 BW |
427 | } |
428 | ||
2ac5ee47 | 429 | static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart) |
194de561 | 430 | { |
a88487c7 | 431 | struct tty_struct *tty = uart->port.info->port.tty; |
194de561 BW |
432 | int i, flg, status; |
433 | ||
434 | status = UART_GET_LSR(uart); | |
0bcfd70e MF |
435 | UART_CLEAR_LSR(uart); |
436 | ||
56f5de8f SZ |
437 | uart->port.icount.rx += |
438 | CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail, | |
439 | UART_XMIT_SIZE); | |
194de561 BW |
440 | |
441 | if (status & BI) { | |
442 | uart->port.icount.brk++; | |
443 | if (uart_handle_break(&uart->port)) | |
444 | goto dma_ignore_char; | |
9808901b | 445 | status &= ~(PE | FE); |
2ac5ee47 MF |
446 | } |
447 | if (status & PE) | |
194de561 | 448 | uart->port.icount.parity++; |
2ac5ee47 | 449 | if (status & OE) |
194de561 | 450 | uart->port.icount.overrun++; |
2ac5ee47 | 451 | if (status & FE) |
194de561 | 452 | uart->port.icount.frame++; |
2ac5ee47 MF |
453 | |
454 | status &= uart->port.read_status_mask; | |
455 | ||
456 | if (status & BI) | |
457 | flg = TTY_BREAK; | |
458 | else if (status & PE) | |
459 | flg = TTY_PARITY; | |
460 | else if (status & FE) | |
461 | flg = TTY_FRAME; | |
462 | else | |
194de561 BW |
463 | flg = TTY_NORMAL; |
464 | ||
8c4210e3 | 465 | for (i = uart->rx_dma_buf.tail; ; i++) { |
56f5de8f SZ |
466 | if (i >= UART_XMIT_SIZE) |
467 | i = 0; | |
8c4210e3 SZ |
468 | if (i == uart->rx_dma_buf.head) |
469 | break; | |
56f5de8f SZ |
470 | if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i])) |
471 | uart_insert_char(&uart->port, status, OE, | |
472 | uart->rx_dma_buf.buf[i], flg); | |
194de561 | 473 | } |
2ac5ee47 MF |
474 | |
475 | dma_ignore_char: | |
194de561 BW |
476 | tty_flip_buffer_push(tty); |
477 | } | |
478 | ||
479 | void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart) | |
480 | { | |
59e4e3e6 MF |
481 | int x_pos, pos; |
482 | unsigned long flags; | |
68a784cb SZ |
483 | |
484 | spin_lock_irqsave(&uart->port.lock, flags); | |
194de561 | 485 | |
8516c568 SZ |
486 | /* 2D DMA RX buffer ring is used. Because curr_y_count and |
487 | * curr_x_count can't be read as an atomic operation, | |
488 | * curr_y_count should be read before curr_x_count. When | |
489 | * curr_x_count is read, curr_y_count may already indicate | |
490 | * next buffer line. But, the position calculated here is | |
491 | * still indicate the old line. The wrong position data may | |
492 | * be smaller than current buffer tail, which cause garbages | |
493 | * are received if it is not prohibit. | |
494 | */ | |
56f5de8f SZ |
495 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); |
496 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); | |
497 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; | |
35ff6935 | 498 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
56f5de8f SZ |
499 | uart->rx_dma_nrows = 0; |
500 | x_pos = DMA_RX_XCOUNT - x_pos; | |
194de561 BW |
501 | if (x_pos == DMA_RX_XCOUNT) |
502 | x_pos = 0; | |
503 | ||
504 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos; | |
8516c568 SZ |
505 | /* Ignore receiving data if new position is in the same line of |
506 | * current buffer tail and small. | |
507 | */ | |
508 | if (pos > uart->rx_dma_buf.tail || | |
509 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
56f5de8f | 510 | uart->rx_dma_buf.head = pos; |
194de561 | 511 | bfin_serial_dma_rx_chars(uart); |
56f5de8f | 512 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; |
194de561 | 513 | } |
0aef4564 | 514 | |
68a784cb SZ |
515 | spin_unlock_irqrestore(&uart->port.lock, flags); |
516 | ||
0a278423 | 517 | mod_timer(&(uart->rx_dma_timer), jiffies + DMA_RX_FLUSH_JIFFIES); |
194de561 BW |
518 | } |
519 | ||
520 | static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id) | |
521 | { | |
522 | struct bfin_serial_port *uart = dev_id; | |
523 | struct circ_buf *xmit = &uart->port.info->xmit; | |
194de561 | 524 | |
d307d36a | 525 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
daba0280 | 526 | if (uart->scts && !(bfin_serial_get_mctrl(&uart->port)&TIOCM_CTS)) { |
d307d36a SZ |
527 | uart->scts = 0; |
528 | uart_handle_cts_change(&uart->port, uart->scts); | |
529 | } | |
530 | #endif | |
531 | ||
194de561 BW |
532 | spin_lock(&uart->port.lock); |
533 | if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) { | |
194de561 | 534 | disable_dma(uart->tx_dma_channel); |
0711d857 | 535 | clear_dma_irqstat(uart->tx_dma_channel); |
0efa4f2c SZ |
536 | /* Anomaly notes: |
537 | * 05000215 - we always clear ETBEI within last UART TX | |
538 | * interrupt to end a string. It is always set | |
539 | * when start a new tx. | |
540 | */ | |
f4d640c9 | 541 | UART_CLEAR_IER(uart, ETBEI); |
0711d857 SZ |
542 | xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1); |
543 | uart->port.icount.tx += uart->tx_count; | |
1b73351c | 544 | |
56f5de8f SZ |
545 | if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) |
546 | uart_write_wakeup(&uart->port); | |
547 | ||
1b73351c | 548 | bfin_serial_dma_tx_chars(uart); |
194de561 BW |
549 | } |
550 | ||
551 | spin_unlock(&uart->port.lock); | |
552 | return IRQ_HANDLED; | |
553 | } | |
554 | ||
555 | static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id) | |
556 | { | |
557 | struct bfin_serial_port *uart = dev_id; | |
558 | unsigned short irqstat; | |
35ff6935 | 559 | int x_pos, pos; |
0711d857 | 560 | |
194de561 BW |
561 | spin_lock(&uart->port.lock); |
562 | irqstat = get_dma_curr_irqstat(uart->rx_dma_channel); | |
563 | clear_dma_irqstat(uart->rx_dma_channel); | |
8516c568 SZ |
564 | |
565 | uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel); | |
35ff6935 | 566 | x_pos = get_dma_curr_xcount(uart->rx_dma_channel); |
8516c568 | 567 | uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows; |
35ff6935 | 568 | if (uart->rx_dma_nrows == DMA_RX_YCOUNT || x_pos == 0) |
8516c568 SZ |
569 | uart->rx_dma_nrows = 0; |
570 | ||
571 | pos = uart->rx_dma_nrows * DMA_RX_XCOUNT; | |
572 | if (pos > uart->rx_dma_buf.tail || | |
573 | uart->rx_dma_nrows < (uart->rx_dma_buf.tail/DMA_RX_XCOUNT)) { | |
574 | uart->rx_dma_buf.head = pos; | |
575 | bfin_serial_dma_rx_chars(uart); | |
576 | uart->rx_dma_buf.tail = uart->rx_dma_buf.head; | |
577 | } | |
578 | ||
194de561 | 579 | spin_unlock(&uart->port.lock); |
0aef4564 | 580 | |
194de561 BW |
581 | return IRQ_HANDLED; |
582 | } | |
583 | #endif | |
584 | ||
585 | /* | |
586 | * Return TIOCSER_TEMT when transmitter is not busy. | |
587 | */ | |
588 | static unsigned int bfin_serial_tx_empty(struct uart_port *port) | |
589 | { | |
590 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
591 | unsigned short lsr; | |
592 | ||
593 | lsr = UART_GET_LSR(uart); | |
594 | if (lsr & TEMT) | |
595 | return TIOCSER_TEMT; | |
596 | else | |
597 | return 0; | |
598 | } | |
599 | ||
194de561 BW |
600 | static void bfin_serial_break_ctl(struct uart_port *port, int break_state) |
601 | { | |
cf686762 MF |
602 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; |
603 | u16 lcr = UART_GET_LCR(uart); | |
604 | if (break_state) | |
605 | lcr |= SB; | |
606 | else | |
607 | lcr &= ~SB; | |
608 | UART_PUT_LCR(uart, lcr); | |
609 | SSYNC(); | |
194de561 BW |
610 | } |
611 | ||
612 | static int bfin_serial_startup(struct uart_port *port) | |
613 | { | |
614 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
615 | ||
616 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
617 | dma_addr_t dma_handle; | |
618 | ||
619 | if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) { | |
620 | printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n"); | |
621 | return -EBUSY; | |
622 | } | |
623 | ||
624 | if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) { | |
625 | printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n"); | |
626 | free_dma(uart->rx_dma_channel); | |
627 | return -EBUSY; | |
628 | } | |
629 | ||
630 | set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart); | |
631 | set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart); | |
632 | ||
633 | uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA); | |
634 | uart->rx_dma_buf.head = 0; | |
635 | uart->rx_dma_buf.tail = 0; | |
636 | uart->rx_dma_nrows = 0; | |
637 | ||
638 | set_dma_config(uart->rx_dma_channel, | |
639 | set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO, | |
640 | INTR_ON_ROW, DIMENSION_2D, | |
2047e40d MH |
641 | DATA_SIZE_8, |
642 | DMA_SYNC_RESTART)); | |
194de561 BW |
643 | set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT); |
644 | set_dma_x_modify(uart->rx_dma_channel, 1); | |
645 | set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT); | |
646 | set_dma_y_modify(uart->rx_dma_channel, 1); | |
647 | set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf); | |
648 | enable_dma(uart->rx_dma_channel); | |
649 | ||
650 | uart->rx_dma_timer.data = (unsigned long)(uart); | |
651 | uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout; | |
652 | uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES; | |
653 | add_timer(&(uart->rx_dma_timer)); | |
654 | #else | |
6f95570e | 655 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
656 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
657 | if (kgdboc_port_line == uart->port.line && kgdboc_break_enabled) | |
658 | kgdboc_break_enabled = 0; | |
659 | else { | |
660 | # endif | |
a359cca7 SZ |
661 | if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED, |
662 | "BFIN_UART_RX", uart)) { | |
194de561 BW |
663 | printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n"); |
664 | return -EBUSY; | |
665 | } | |
666 | ||
667 | if (request_irq | |
5c4e472b | 668 | (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED, |
194de561 BW |
669 | "BFIN_UART_TX", uart)) { |
670 | printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n"); | |
671 | free_irq(uart->port.irq, uart); | |
672 | return -EBUSY; | |
673 | } | |
ab2375f2 SZ |
674 | |
675 | # ifdef CONFIG_BF54x | |
676 | { | |
677 | unsigned uart_dma_ch_rx, uart_dma_ch_tx; | |
678 | ||
679 | switch (uart->port.irq) { | |
680 | case IRQ_UART3_RX: | |
681 | uart_dma_ch_rx = CH_UART3_RX; | |
682 | uart_dma_ch_tx = CH_UART3_TX; | |
683 | break; | |
684 | case IRQ_UART2_RX: | |
685 | uart_dma_ch_rx = CH_UART2_RX; | |
686 | uart_dma_ch_tx = CH_UART2_TX; | |
687 | break; | |
688 | default: | |
689 | uart_dma_ch_rx = uart_dma_ch_tx = 0; | |
690 | break; | |
691 | }; | |
692 | ||
693 | if (uart_dma_ch_rx && | |
694 | request_dma(uart_dma_ch_rx, "BFIN_UART_RX") < 0) { | |
695 | printk(KERN_NOTICE"Fail to attach UART interrupt\n"); | |
696 | free_irq(uart->port.irq, uart); | |
697 | free_irq(uart->port.irq + 1, uart); | |
698 | return -EBUSY; | |
699 | } | |
700 | if (uart_dma_ch_tx && | |
701 | request_dma(uart_dma_ch_tx, "BFIN_UART_TX") < 0) { | |
702 | printk(KERN_NOTICE "Fail to attach UART interrupt\n"); | |
703 | free_dma(uart_dma_ch_rx); | |
704 | free_irq(uart->port.irq, uart); | |
705 | free_irq(uart->port.irq + 1, uart); | |
706 | return -EBUSY; | |
707 | } | |
708 | } | |
709 | # endif | |
6f95570e | 710 | # if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
52e15f0e SZ |
711 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) |
712 | } | |
713 | # endif | |
6f95570e SZ |
714 | #endif |
715 | ||
716 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS | |
717 | if (uart->cts_pin >= 0) { | |
718 | if (request_irq(gpio_to_irq(uart->cts_pin), | |
719 | bfin_serial_mctrl_cts_int, | |
720 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | | |
721 | IRQF_DISABLED, "BFIN_UART_CTS", uart)) { | |
722 | uart->cts_pin = -1; | |
723 | pr_info("Unable to attach BlackFin UART CTS interrupt.\ | |
724 | So, disable it.\n"); | |
725 | } | |
726 | } | |
727 | if (uart->rts_pin >= 0) { | |
728 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
729 | gpio_direction_output(uart->rts_pin, 0); | |
730 | } | |
194de561 | 731 | #endif |
d307d36a SZ |
732 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS |
733 | if (request_irq(uart->status_irq, | |
734 | bfin_serial_mctrl_cts_int, | |
735 | IRQF_DISABLED, "BFIN_UART_MODEM_STATUS", uart)) { | |
736 | pr_info("Unable to attach BlackFin UART Modem \ | |
737 | Status interrupt.\n"); | |
738 | } | |
739 | ||
740 | if (uart->cts_pin >= 0) { | |
741 | gpio_request(uart->cts_pin, DRIVER_NAME); | |
742 | gpio_direction_output(uart->cts_pin, 1); | |
743 | } | |
744 | if (uart->rts_pin >= 0) { | |
745 | gpio_request(uart->rts_pin, DRIVER_NAME); | |
746 | gpio_direction_output(uart->rts_pin, 0); | |
747 | } | |
748 | ||
749 | /* CTS RTS PINs are negative assertive. */ | |
750 | UART_PUT_MCR(uart, ACTS); | |
751 | UART_SET_IER(uart, EDSSI); | |
752 | #endif | |
753 | ||
f4d640c9 | 754 | UART_SET_IER(uart, ERBFI); |
194de561 BW |
755 | return 0; |
756 | } | |
757 | ||
758 | static void bfin_serial_shutdown(struct uart_port *port) | |
759 | { | |
760 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
761 | ||
762 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
763 | disable_dma(uart->tx_dma_channel); | |
764 | free_dma(uart->tx_dma_channel); | |
765 | disable_dma(uart->rx_dma_channel); | |
766 | free_dma(uart->rx_dma_channel); | |
767 | del_timer(&(uart->rx_dma_timer)); | |
75b780bd | 768 | dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0); |
194de561 | 769 | #else |
ab2375f2 SZ |
770 | #ifdef CONFIG_BF54x |
771 | switch (uart->port.irq) { | |
772 | case IRQ_UART3_RX: | |
773 | free_dma(CH_UART3_RX); | |
774 | free_dma(CH_UART3_TX); | |
775 | break; | |
776 | case IRQ_UART2_RX: | |
777 | free_dma(CH_UART2_RX); | |
778 | free_dma(CH_UART2_TX); | |
779 | break; | |
780 | default: | |
781 | break; | |
782 | }; | |
474f1a66 | 783 | #endif |
194de561 BW |
784 | free_irq(uart->port.irq, uart); |
785 | free_irq(uart->port.irq+1, uart); | |
786 | #endif | |
6f95570e | 787 | |
d307d36a | 788 | #ifdef CONFIG_SERIAL_BFIN_CTSRTS |
6f95570e SZ |
789 | if (uart->cts_pin >= 0) |
790 | free_irq(gpio_to_irq(uart->cts_pin), uart); | |
791 | if (uart->rts_pin >= 0) | |
792 | gpio_free(uart->rts_pin); | |
d307d36a SZ |
793 | #endif |
794 | #ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS | |
795 | if (uart->cts_pin >= 0) | |
796 | gpio_free(uart->cts_pin); | |
797 | if (uart->rts_pin >= 0) | |
798 | gpio_free(uart->rts_pin); | |
799 | if (UART_GET_IER(uart) && EDSSI) | |
800 | free_irq(uart->status_irq, uart); | |
801 | #endif | |
194de561 BW |
802 | } |
803 | ||
804 | static void | |
805 | bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios, | |
806 | struct ktermios *old) | |
807 | { | |
808 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
809 | unsigned long flags; | |
810 | unsigned int baud, quot; | |
0c44a86d | 811 | unsigned short val, ier, lcr = 0; |
194de561 BW |
812 | |
813 | switch (termios->c_cflag & CSIZE) { | |
814 | case CS8: | |
815 | lcr = WLS(8); | |
816 | break; | |
817 | case CS7: | |
818 | lcr = WLS(7); | |
819 | break; | |
820 | case CS6: | |
821 | lcr = WLS(6); | |
822 | break; | |
823 | case CS5: | |
824 | lcr = WLS(5); | |
825 | break; | |
826 | default: | |
827 | printk(KERN_ERR "%s: word lengh not supported\n", | |
71cc2c21 | 828 | __func__); |
194de561 BW |
829 | } |
830 | ||
84507794 SZ |
831 | /* Anomaly notes: |
832 | * 05000231 - STOP bit is always set to 1 whatever the user is set. | |
833 | */ | |
834 | if (termios->c_cflag & CSTOPB) { | |
835 | if (ANOMALY_05000231) | |
836 | printk(KERN_WARNING "STOP bits other than 1 is not " | |
837 | "supported in case of anomaly 05000231.\n"); | |
838 | else | |
839 | lcr |= STB; | |
840 | } | |
19aa6382 | 841 | if (termios->c_cflag & PARENB) |
194de561 | 842 | lcr |= PEN; |
19aa6382 MF |
843 | if (!(termios->c_cflag & PARODD)) |
844 | lcr |= EPS; | |
845 | if (termios->c_cflag & CMSPAR) | |
846 | lcr |= STP; | |
194de561 | 847 | |
2ac5ee47 MF |
848 | port->read_status_mask = OE; |
849 | if (termios->c_iflag & INPCK) | |
850 | port->read_status_mask |= (FE | PE); | |
851 | if (termios->c_iflag & (BRKINT | PARMRK)) | |
852 | port->read_status_mask |= BI; | |
194de561 | 853 | |
2ac5ee47 MF |
854 | /* |
855 | * Characters to ignore | |
856 | */ | |
857 | port->ignore_status_mask = 0; | |
858 | if (termios->c_iflag & IGNPAR) | |
859 | port->ignore_status_mask |= FE | PE; | |
860 | if (termios->c_iflag & IGNBRK) { | |
861 | port->ignore_status_mask |= BI; | |
862 | /* | |
863 | * If we're ignoring parity and break indicators, | |
864 | * ignore overruns too (for real raw support). | |
865 | */ | |
866 | if (termios->c_iflag & IGNPAR) | |
867 | port->ignore_status_mask |= OE; | |
868 | } | |
194de561 BW |
869 | |
870 | baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); | |
f4487101 | 871 | quot = uart_get_divisor(port, baud) - ANOMALY_05000230; |
194de561 BW |
872 | spin_lock_irqsave(&uart->port.lock, flags); |
873 | ||
8851c71e MF |
874 | UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15); |
875 | ||
194de561 BW |
876 | /* Disable UART */ |
877 | ier = UART_GET_IER(uart); | |
1feaa51d | 878 | UART_DISABLE_INTS(uart); |
194de561 BW |
879 | |
880 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 881 | UART_SET_DLAB(uart); |
194de561 BW |
882 | |
883 | UART_PUT_DLL(uart, quot & 0xFF); | |
194de561 BW |
884 | UART_PUT_DLH(uart, (quot >> 8) & 0xFF); |
885 | SSYNC(); | |
886 | ||
887 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 888 | UART_CLEAR_DLAB(uart); |
194de561 BW |
889 | |
890 | UART_PUT_LCR(uart, lcr); | |
891 | ||
892 | /* Enable UART */ | |
1feaa51d | 893 | UART_ENABLE_INTS(uart, ier); |
194de561 BW |
894 | |
895 | val = UART_GET_GCTL(uart); | |
896 | val |= UCEN; | |
897 | UART_PUT_GCTL(uart, val); | |
898 | ||
b3ef5aba GY |
899 | /* Port speed changed, update the per-port timeout. */ |
900 | uart_update_timeout(port, termios->c_cflag, baud); | |
901 | ||
194de561 BW |
902 | spin_unlock_irqrestore(&uart->port.lock, flags); |
903 | } | |
904 | ||
905 | static const char *bfin_serial_type(struct uart_port *port) | |
906 | { | |
907 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
908 | ||
909 | return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL; | |
910 | } | |
911 | ||
912 | /* | |
913 | * Release the memory region(s) being used by 'port'. | |
914 | */ | |
915 | static void bfin_serial_release_port(struct uart_port *port) | |
916 | { | |
917 | } | |
918 | ||
919 | /* | |
920 | * Request the memory region(s) being used by 'port'. | |
921 | */ | |
922 | static int bfin_serial_request_port(struct uart_port *port) | |
923 | { | |
924 | return 0; | |
925 | } | |
926 | ||
927 | /* | |
928 | * Configure/autoconfigure the port. | |
929 | */ | |
930 | static void bfin_serial_config_port(struct uart_port *port, int flags) | |
931 | { | |
932 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
933 | ||
934 | if (flags & UART_CONFIG_TYPE && | |
935 | bfin_serial_request_port(&uart->port) == 0) | |
936 | uart->port.type = PORT_BFIN; | |
937 | } | |
938 | ||
939 | /* | |
940 | * Verify the new serial_struct (for TIOCSSERIAL). | |
941 | * The only change we allow are to the flags and type, and | |
942 | * even then only between PORT_BFIN and PORT_UNKNOWN | |
943 | */ | |
944 | static int | |
945 | bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser) | |
946 | { | |
947 | return 0; | |
948 | } | |
949 | ||
7d01b475 GY |
950 | /* |
951 | * Enable the IrDA function if tty->ldisc.num is N_IRDA. | |
952 | * In other cases, disable IrDA function. | |
953 | */ | |
3b8458a9 | 954 | static void bfin_serial_set_ldisc(struct uart_port *port) |
7d01b475 | 955 | { |
3b8458a9 | 956 | int line = port->line; |
7d01b475 GY |
957 | unsigned short val; |
958 | ||
a88487c7 | 959 | if (line >= port->info->port.tty->driver->num) |
7d01b475 GY |
960 | return; |
961 | ||
b1cbefe5 | 962 | switch (port->info->port.tty->termios->c_line) { |
7d01b475 GY |
963 | case N_IRDA: |
964 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
965 | val |= (IREN | RPOLC); | |
966 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
967 | break; | |
968 | default: | |
969 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
970 | val &= ~(IREN | RPOLC); | |
971 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
972 | } | |
973 | } | |
974 | ||
6f95570e SZ |
975 | static void bfin_serial_reset_irda(struct uart_port *port) |
976 | { | |
977 | int line = port->line; | |
978 | unsigned short val; | |
979 | ||
980 | val = UART_GET_GCTL(&bfin_serial_ports[line]); | |
981 | val &= ~(IREN | RPOLC); | |
982 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
983 | SSYNC(); | |
984 | val |= (IREN | RPOLC); | |
985 | UART_PUT_GCTL(&bfin_serial_ports[line], val); | |
986 | SSYNC(); | |
987 | } | |
988 | ||
52e15f0e | 989 | #ifdef CONFIG_CONSOLE_POLL |
0efa4f2c SZ |
990 | /* Anomaly notes: |
991 | * 05000099 - Because we only use THRE in poll_put and DR in poll_get, | |
992 | * losing other bits of UART_LSR is not a problem here. | |
993 | */ | |
52e15f0e SZ |
994 | static void bfin_serial_poll_put_char(struct uart_port *port, unsigned char chr) |
995 | { | |
996 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
997 | ||
998 | while (!(UART_GET_LSR(uart) & THRE)) | |
999 | cpu_relax(); | |
1000 | ||
1001 | UART_CLEAR_DLAB(uart); | |
1002 | UART_PUT_CHAR(uart, (unsigned char)chr); | |
1003 | } | |
1004 | ||
1005 | static int bfin_serial_poll_get_char(struct uart_port *port) | |
1006 | { | |
1007 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1008 | unsigned char chr; | |
1009 | ||
1010 | while (!(UART_GET_LSR(uart) & DR)) | |
1011 | cpu_relax(); | |
1012 | ||
1013 | UART_CLEAR_DLAB(uart); | |
1014 | chr = UART_GET_CHAR(uart); | |
1015 | ||
1016 | return chr; | |
1017 | } | |
1018 | #endif | |
1019 | ||
1020 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ | |
1021 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1022 | static void bfin_kgdboc_port_shutdown(struct uart_port *port) | |
1023 | { | |
1024 | if (kgdboc_break_enabled) { | |
1025 | kgdboc_break_enabled = 0; | |
1026 | bfin_serial_shutdown(port); | |
1027 | } | |
1028 | } | |
1029 | ||
1030 | static int bfin_kgdboc_port_startup(struct uart_port *port) | |
1031 | { | |
1032 | kgdboc_port_line = port->line; | |
1033 | kgdboc_break_enabled = !bfin_serial_startup(port); | |
1034 | return 0; | |
1035 | } | |
1036 | #endif | |
1037 | ||
194de561 BW |
1038 | static struct uart_ops bfin_serial_pops = { |
1039 | .tx_empty = bfin_serial_tx_empty, | |
1040 | .set_mctrl = bfin_serial_set_mctrl, | |
1041 | .get_mctrl = bfin_serial_get_mctrl, | |
1042 | .stop_tx = bfin_serial_stop_tx, | |
1043 | .start_tx = bfin_serial_start_tx, | |
1044 | .stop_rx = bfin_serial_stop_rx, | |
1045 | .enable_ms = bfin_serial_enable_ms, | |
1046 | .break_ctl = bfin_serial_break_ctl, | |
1047 | .startup = bfin_serial_startup, | |
1048 | .shutdown = bfin_serial_shutdown, | |
1049 | .set_termios = bfin_serial_set_termios, | |
3b8458a9 | 1050 | .set_ldisc = bfin_serial_set_ldisc, |
194de561 BW |
1051 | .type = bfin_serial_type, |
1052 | .release_port = bfin_serial_release_port, | |
1053 | .request_port = bfin_serial_request_port, | |
1054 | .config_port = bfin_serial_config_port, | |
1055 | .verify_port = bfin_serial_verify_port, | |
52e15f0e SZ |
1056 | #if defined(CONFIG_KGDB_SERIAL_CONSOLE) || \ |
1057 | defined(CONFIG_KGDB_SERIAL_CONSOLE_MODULE) | |
1058 | .kgdboc_port_startup = bfin_kgdboc_port_startup, | |
1059 | .kgdboc_port_shutdown = bfin_kgdboc_port_shutdown, | |
1060 | #endif | |
1061 | #ifdef CONFIG_CONSOLE_POLL | |
1062 | .poll_put_char = bfin_serial_poll_put_char, | |
1063 | .poll_get_char = bfin_serial_poll_get_char, | |
1064 | #endif | |
194de561 BW |
1065 | }; |
1066 | ||
6f95570e SZ |
1067 | static void __init bfin_serial_hw_init(void) |
1068 | { | |
1069 | #ifdef CONFIG_SERIAL_BFIN_UART0 | |
1070 | peripheral_request(P_UART0_TX, DRIVER_NAME); | |
1071 | peripheral_request(P_UART0_RX, DRIVER_NAME); | |
1072 | #endif | |
1073 | ||
1074 | #ifdef CONFIG_SERIAL_BFIN_UART1 | |
1075 | peripheral_request(P_UART1_TX, DRIVER_NAME); | |
1076 | peripheral_request(P_UART1_RX, DRIVER_NAME); | |
1077 | ||
1078 | # if defined(CONFIG_BFIN_UART1_CTSRTS) && defined(CONFIG_BF54x) | |
1079 | peripheral_request(P_UART1_RTS, DRIVER_NAME); | |
1080 | peripheral_request(P_UART1_CTS, DRIVER_NAME); | |
1081 | # endif | |
1082 | #endif | |
1083 | ||
1084 | #ifdef CONFIG_SERIAL_BFIN_UART2 | |
1085 | peripheral_request(P_UART2_TX, DRIVER_NAME); | |
1086 | peripheral_request(P_UART2_RX, DRIVER_NAME); | |
1087 | #endif | |
1088 | ||
1089 | #ifdef CONFIG_SERIAL_BFIN_UART3 | |
1090 | peripheral_request(P_UART3_TX, DRIVER_NAME); | |
1091 | peripheral_request(P_UART3_RX, DRIVER_NAME); | |
1092 | ||
1093 | # if defined(CONFIG_BFIN_UART3_CTSRTS) && defined(CONFIG_BF54x) | |
1094 | peripheral_request(P_UART3_RTS, DRIVER_NAME); | |
1095 | peripheral_request(P_UART3_CTS, DRIVER_NAME); | |
1096 | # endif | |
1097 | #endif | |
1098 | } | |
1099 | ||
194de561 BW |
1100 | static void __init bfin_serial_init_ports(void) |
1101 | { | |
1102 | static int first = 1; | |
1103 | int i; | |
1104 | ||
1105 | if (!first) | |
1106 | return; | |
1107 | first = 0; | |
1108 | ||
6f95570e SZ |
1109 | bfin_serial_hw_init(); |
1110 | ||
c9607ecc | 1111 | for (i = 0; i < nr_active_ports; i++) { |
194de561 | 1112 | bfin_serial_ports[i].port.uartclk = get_sclk(); |
b3ef5aba | 1113 | bfin_serial_ports[i].port.fifosize = BFIN_UART_TX_FIFO_SIZE; |
194de561 BW |
1114 | bfin_serial_ports[i].port.ops = &bfin_serial_pops; |
1115 | bfin_serial_ports[i].port.line = i; | |
1116 | bfin_serial_ports[i].port.iotype = UPIO_MEM; | |
1117 | bfin_serial_ports[i].port.membase = | |
1118 | (void __iomem *)bfin_serial_resource[i].uart_base_addr; | |
1119 | bfin_serial_ports[i].port.mapbase = | |
1120 | bfin_serial_resource[i].uart_base_addr; | |
1121 | bfin_serial_ports[i].port.irq = | |
1122 | bfin_serial_resource[i].uart_irq; | |
d307d36a SZ |
1123 | bfin_serial_ports[i].status_irq = |
1124 | bfin_serial_resource[i].uart_status_irq; | |
194de561 BW |
1125 | bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF; |
1126 | #ifdef CONFIG_SERIAL_BFIN_DMA | |
1127 | bfin_serial_ports[i].tx_done = 1; | |
1128 | bfin_serial_ports[i].tx_count = 0; | |
1129 | bfin_serial_ports[i].tx_dma_channel = | |
1130 | bfin_serial_resource[i].uart_tx_dma_channel; | |
1131 | bfin_serial_ports[i].rx_dma_channel = | |
1132 | bfin_serial_resource[i].uart_rx_dma_channel; | |
1133 | init_timer(&(bfin_serial_ports[i].rx_dma_timer)); | |
194de561 | 1134 | #endif |
d307d36a SZ |
1135 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1136 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 BW |
1137 | bfin_serial_ports[i].cts_pin = |
1138 | bfin_serial_resource[i].uart_cts_pin; | |
1139 | bfin_serial_ports[i].rts_pin = | |
1140 | bfin_serial_resource[i].uart_rts_pin; | |
1141 | #endif | |
194de561 BW |
1142 | } |
1143 | } | |
1144 | ||
b6efa1ea | 1145 | #if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK) |
194de561 BW |
1146 | /* |
1147 | * If the port was already initialised (eg, by a boot loader), | |
1148 | * try to determine the current setup. | |
1149 | */ | |
1150 | static void __init | |
1151 | bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud, | |
1152 | int *parity, int *bits) | |
1153 | { | |
1154 | unsigned short status; | |
1155 | ||
1156 | status = UART_GET_IER(uart) & (ERBFI | ETBEI); | |
1157 | if (status == (ERBFI | ETBEI)) { | |
1158 | /* ok, the port was enabled */ | |
45828b81 | 1159 | u16 lcr, dlh, dll; |
194de561 BW |
1160 | |
1161 | lcr = UART_GET_LCR(uart); | |
1162 | ||
1163 | *parity = 'n'; | |
1164 | if (lcr & PEN) { | |
1165 | if (lcr & EPS) | |
1166 | *parity = 'e'; | |
1167 | else | |
1168 | *parity = 'o'; | |
1169 | } | |
1170 | switch (lcr & 0x03) { | |
1171 | case 0: *bits = 5; break; | |
1172 | case 1: *bits = 6; break; | |
1173 | case 2: *bits = 7; break; | |
1174 | case 3: *bits = 8; break; | |
1175 | } | |
1176 | /* Set DLAB in LCR to Access DLL and DLH */ | |
45828b81 | 1177 | UART_SET_DLAB(uart); |
194de561 BW |
1178 | |
1179 | dll = UART_GET_DLL(uart); | |
1180 | dlh = UART_GET_DLH(uart); | |
1181 | ||
1182 | /* Clear DLAB in LCR to Access THR RBR IER */ | |
45828b81 | 1183 | UART_CLEAR_DLAB(uart); |
194de561 BW |
1184 | |
1185 | *baud = get_sclk() / (16*(dll | dlh << 8)); | |
1186 | } | |
71cc2c21 | 1187 | pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __func__, *baud, *parity, *bits); |
194de561 | 1188 | } |
0ae53640 | 1189 | |
0ae53640 | 1190 | static struct uart_driver bfin_serial_reg; |
194de561 BW |
1191 | |
1192 | static int __init | |
1193 | bfin_serial_console_setup(struct console *co, char *options) | |
1194 | { | |
1195 | struct bfin_serial_port *uart; | |
1196 | int baud = 57600; | |
1197 | int bits = 8; | |
1198 | int parity = 'n'; | |
d307d36a SZ |
1199 | # if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1200 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
194de561 | 1201 | int flow = 'r'; |
b6efa1ea | 1202 | # else |
194de561 | 1203 | int flow = 'n'; |
0ae53640 | 1204 | # endif |
194de561 BW |
1205 | |
1206 | /* | |
1207 | * Check whether an invalid uart number has been specified, and | |
1208 | * if so, search for the first available port that does have | |
1209 | * console support. | |
1210 | */ | |
c9607ecc | 1211 | if (co->index == -1 || co->index >= nr_active_ports) |
194de561 BW |
1212 | co->index = 0; |
1213 | uart = &bfin_serial_ports[co->index]; | |
1214 | ||
1215 | if (options) | |
1216 | uart_parse_options(options, &baud, &parity, &bits, &flow); | |
1217 | else | |
1218 | bfin_serial_console_get_options(uart, &baud, &parity, &bits); | |
1219 | ||
1220 | return uart_set_options(&uart->port, co, baud, parity, bits, flow); | |
0ae53640 RG |
1221 | } |
1222 | #endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) || | |
1223 | defined (CONFIG_EARLY_PRINTK) */ | |
1224 | ||
1225 | #ifdef CONFIG_SERIAL_BFIN_CONSOLE | |
1226 | static void bfin_serial_console_putchar(struct uart_port *port, int ch) | |
1227 | { | |
1228 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1229 | while (!(UART_GET_LSR(uart) & THRE)) | |
1230 | barrier(); | |
1231 | UART_PUT_CHAR(uart, ch); | |
1232 | SSYNC(); | |
1233 | } | |
1234 | ||
1235 | /* | |
1236 | * Interrupts are disabled on entering | |
1237 | */ | |
1238 | static void | |
1239 | bfin_serial_console_write(struct console *co, const char *s, unsigned int count) | |
1240 | { | |
1241 | struct bfin_serial_port *uart = &bfin_serial_ports[co->index]; | |
59e4e3e6 | 1242 | unsigned long flags; |
0ae53640 RG |
1243 | |
1244 | spin_lock_irqsave(&uart->port.lock, flags); | |
1245 | uart_console_write(&uart->port, s, count, bfin_serial_console_putchar); | |
1246 | spin_unlock_irqrestore(&uart->port.lock, flags); | |
1247 | ||
194de561 BW |
1248 | } |
1249 | ||
194de561 BW |
1250 | static struct console bfin_serial_console = { |
1251 | .name = BFIN_SERIAL_NAME, | |
1252 | .write = bfin_serial_console_write, | |
1253 | .device = uart_console_device, | |
1254 | .setup = bfin_serial_console_setup, | |
1255 | .flags = CON_PRINTBUFFER, | |
1256 | .index = -1, | |
1257 | .data = &bfin_serial_reg, | |
1258 | }; | |
1259 | ||
1260 | static int __init bfin_serial_rs_console_init(void) | |
1261 | { | |
1262 | bfin_serial_init_ports(); | |
1263 | register_console(&bfin_serial_console); | |
52e15f0e | 1264 | |
194de561 BW |
1265 | return 0; |
1266 | } | |
1267 | console_initcall(bfin_serial_rs_console_init); | |
1268 | ||
1269 | #define BFIN_SERIAL_CONSOLE &bfin_serial_console | |
1270 | #else | |
1271 | #define BFIN_SERIAL_CONSOLE NULL | |
0ae53640 RG |
1272 | #endif /* CONFIG_SERIAL_BFIN_CONSOLE */ |
1273 | ||
1274 | ||
1275 | #ifdef CONFIG_EARLY_PRINTK | |
1276 | static __init void early_serial_putc(struct uart_port *port, int ch) | |
1277 | { | |
1278 | unsigned timeout = 0xffff; | |
1279 | struct bfin_serial_port *uart = (struct bfin_serial_port *)port; | |
1280 | ||
1281 | while ((!(UART_GET_LSR(uart) & THRE)) && --timeout) | |
1282 | cpu_relax(); | |
1283 | UART_PUT_CHAR(uart, ch); | |
1284 | } | |
1285 | ||
1286 | static __init void early_serial_write(struct console *con, const char *s, | |
1287 | unsigned int n) | |
1288 | { | |
1289 | struct bfin_serial_port *uart = &bfin_serial_ports[con->index]; | |
1290 | unsigned int i; | |
1291 | ||
1292 | for (i = 0; i < n; i++, s++) { | |
1293 | if (*s == '\n') | |
1294 | early_serial_putc(&uart->port, '\r'); | |
1295 | early_serial_putc(&uart->port, *s); | |
1296 | } | |
1297 | } | |
1298 | ||
7de7c55b RG |
1299 | /* |
1300 | * This should have a .setup or .early_setup in it, but then things get called | |
1301 | * without the command line options, and the baud rate gets messed up - so | |
1302 | * don't let the common infrastructure play with things. (see calls to setup | |
1303 | * & earlysetup in ./kernel/printk.c:register_console() | |
1304 | */ | |
c1113400 | 1305 | static struct __initdata console bfin_early_serial_console = { |
0ae53640 RG |
1306 | .name = "early_BFuart", |
1307 | .write = early_serial_write, | |
1308 | .device = uart_console_device, | |
1309 | .flags = CON_PRINTBUFFER, | |
0ae53640 RG |
1310 | .index = -1, |
1311 | .data = &bfin_serial_reg, | |
1312 | }; | |
1313 | ||
1314 | struct console __init *bfin_earlyserial_init(unsigned int port, | |
1315 | unsigned int cflag) | |
1316 | { | |
1317 | struct bfin_serial_port *uart; | |
1318 | struct ktermios t; | |
1319 | ||
c9607ecc | 1320 | if (port == -1 || port >= nr_active_ports) |
0ae53640 RG |
1321 | port = 0; |
1322 | bfin_serial_init_ports(); | |
1323 | bfin_early_serial_console.index = port; | |
0ae53640 RG |
1324 | uart = &bfin_serial_ports[port]; |
1325 | t.c_cflag = cflag; | |
1326 | t.c_iflag = 0; | |
1327 | t.c_oflag = 0; | |
1328 | t.c_lflag = ICANON; | |
1329 | t.c_line = port; | |
1330 | bfin_serial_set_termios(&uart->port, &t, &t); | |
1331 | return &bfin_early_serial_console; | |
1332 | } | |
1333 | ||
b6efa1ea | 1334 | #endif /* CONFIG_EARLY_PRINTK */ |
194de561 BW |
1335 | |
1336 | static struct uart_driver bfin_serial_reg = { | |
1337 | .owner = THIS_MODULE, | |
1338 | .driver_name = "bfin-uart", | |
1339 | .dev_name = BFIN_SERIAL_NAME, | |
1340 | .major = BFIN_SERIAL_MAJOR, | |
1341 | .minor = BFIN_SERIAL_MINOR, | |
2ade9729 | 1342 | .nr = BFIN_UART_NR_PORTS, |
194de561 BW |
1343 | .cons = BFIN_SERIAL_CONSOLE, |
1344 | }; | |
1345 | ||
1346 | static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state) | |
1347 | { | |
ccfbc3e1 | 1348 | int i; |
194de561 | 1349 | |
c9607ecc | 1350 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1351 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1352 | continue; | |
1353 | uart_suspend_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1354 | } | |
194de561 BW |
1355 | |
1356 | return 0; | |
1357 | } | |
1358 | ||
1359 | static int bfin_serial_resume(struct platform_device *dev) | |
1360 | { | |
ccfbc3e1 | 1361 | int i; |
194de561 | 1362 | |
c9607ecc | 1363 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1364 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1365 | continue; | |
1366 | uart_resume_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1367 | } | |
194de561 BW |
1368 | |
1369 | return 0; | |
1370 | } | |
1371 | ||
1372 | static int bfin_serial_probe(struct platform_device *dev) | |
1373 | { | |
1374 | struct resource *res = dev->resource; | |
1375 | int i; | |
1376 | ||
1377 | for (i = 0; i < dev->num_resources; i++, res++) | |
1378 | if (res->flags & IORESOURCE_MEM) | |
1379 | break; | |
1380 | ||
1381 | if (i < dev->num_resources) { | |
c9607ecc | 1382 | for (i = 0; i < nr_active_ports; i++, res++) { |
194de561 BW |
1383 | if (bfin_serial_ports[i].port.mapbase != res->start) |
1384 | continue; | |
1385 | bfin_serial_ports[i].port.dev = &dev->dev; | |
1386 | uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
194de561 BW |
1387 | } |
1388 | } | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
ccfbc3e1 | 1393 | static int bfin_serial_remove(struct platform_device *dev) |
194de561 | 1394 | { |
ccfbc3e1 | 1395 | int i; |
194de561 | 1396 | |
c9607ecc | 1397 | for (i = 0; i < nr_active_ports; i++) { |
ccfbc3e1 SZ |
1398 | if (bfin_serial_ports[i].port.dev != &dev->dev) |
1399 | continue; | |
1400 | uart_remove_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port); | |
1401 | bfin_serial_ports[i].port.dev = NULL; | |
d307d36a SZ |
1402 | #if defined(CONFIG_SERIAL_BFIN_CTSRTS) || \ |
1403 | defined(CONFIG_SERIAL_BFIN_HARD_CTSRTS) | |
ccfbc3e1 SZ |
1404 | gpio_free(bfin_serial_ports[i].cts_pin); |
1405 | gpio_free(bfin_serial_ports[i].rts_pin); | |
194de561 | 1406 | #endif |
ccfbc3e1 | 1407 | } |
194de561 BW |
1408 | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | static struct platform_driver bfin_serial_driver = { | |
1413 | .probe = bfin_serial_probe, | |
1414 | .remove = bfin_serial_remove, | |
1415 | .suspend = bfin_serial_suspend, | |
1416 | .resume = bfin_serial_resume, | |
1417 | .driver = { | |
1418 | .name = "bfin-uart", | |
e169c139 | 1419 | .owner = THIS_MODULE, |
194de561 BW |
1420 | }, |
1421 | }; | |
1422 | ||
1423 | static int __init bfin_serial_init(void) | |
1424 | { | |
1425 | int ret; | |
1426 | ||
1427 | pr_info("Serial: Blackfin serial driver\n"); | |
1428 | ||
1429 | bfin_serial_init_ports(); | |
1430 | ||
1431 | ret = uart_register_driver(&bfin_serial_reg); | |
1432 | if (ret == 0) { | |
1433 | ret = platform_driver_register(&bfin_serial_driver); | |
1434 | if (ret) { | |
1435 | pr_debug("uart register failed\n"); | |
1436 | uart_unregister_driver(&bfin_serial_reg); | |
1437 | } | |
1438 | } | |
1439 | return ret; | |
1440 | } | |
1441 | ||
1442 | static void __exit bfin_serial_exit(void) | |
1443 | { | |
1444 | platform_driver_unregister(&bfin_serial_driver); | |
1445 | uart_unregister_driver(&bfin_serial_reg); | |
1446 | } | |
1447 | ||
52e15f0e | 1448 | |
194de561 BW |
1449 | module_init(bfin_serial_init); |
1450 | module_exit(bfin_serial_exit); | |
1451 | ||
1452 | MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>"); | |
1453 | MODULE_DESCRIPTION("Blackfin generic serial port driver"); | |
1454 | MODULE_LICENSE("GPL"); | |
1455 | MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR); | |
e169c139 | 1456 | MODULE_ALIAS("platform:bfin-uart"); |