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Blackfin Serial Driver: the uart break anomaly has been given its own number, so...
[net-next-2.6.git] / drivers / serial / bfin_5xx.c
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194de561 1/*
1ba7a3ee 2 * Blackfin On-Chip Serial Driver
194de561 3 *
1ba7a3ee 4 * Copyright 2006-2007 Analog Devices Inc.
194de561 5 *
1ba7a3ee 6 * Enter bugs at http://blackfin.uclinux.org/
194de561 7 *
1ba7a3ee 8 * Licensed under the GPL-2 or later.
194de561
BW
9 */
10
11#if defined(CONFIG_SERIAL_BFIN_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
12#define SUPPORT_SYSRQ
13#endif
14
15#include <linux/module.h>
16#include <linux/ioport.h>
17#include <linux/init.h>
18#include <linux/console.h>
19#include <linux/sysrq.h>
20#include <linux/platform_device.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/serial_core.h>
24
474f1a66
SZ
25#ifdef CONFIG_KGDB_UART
26#include <linux/kgdb.h>
27#include <asm/irq_regs.h>
28#endif
29
194de561
BW
30#include <asm/gpio.h>
31#include <asm/mach/bfin_serial_5xx.h>
32
33#ifdef CONFIG_SERIAL_BFIN_DMA
34#include <linux/dma-mapping.h>
35#include <asm/io.h>
36#include <asm/irq.h>
37#include <asm/cacheflush.h>
38#endif
39
40/* UART name and device definitions */
41#define BFIN_SERIAL_NAME "ttyBF"
42#define BFIN_SERIAL_MAJOR 204
43#define BFIN_SERIAL_MINOR 64
44
45/*
46 * Setup for console. Argument comes from the menuconfig
47 */
48#define DMA_RX_XCOUNT 512
49#define DMA_RX_YCOUNT (PAGE_SIZE / DMA_RX_XCOUNT)
50
0aef4564 51#define DMA_RX_FLUSH_JIFFIES (HZ / 50)
194de561
BW
52
53#ifdef CONFIG_SERIAL_BFIN_DMA
54static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart);
55#else
194de561 56static void bfin_serial_tx_chars(struct bfin_serial_port *uart);
194de561
BW
57#endif
58
59static void bfin_serial_mctrl_check(struct bfin_serial_port *uart);
60
61/*
62 * interrupts are disabled on entry
63 */
64static void bfin_serial_stop_tx(struct uart_port *port)
65{
66 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
0711d857 67 struct circ_buf *xmit = &uart->port.info->xmit;
1b73351c 68#if !defined(CONFIG_BF54x) && !defined(CONFIG_SERIAL_BFIN_DMA)
759eb040
SZ
69 unsigned short ier;
70#endif
194de561 71
f4d640c9 72 while (!(UART_GET_LSR(uart) & TEMT))
0711d857 73 cpu_relax();
f4d640c9 74
194de561
BW
75#ifdef CONFIG_SERIAL_BFIN_DMA
76 disable_dma(uart->tx_dma_channel);
0711d857
SZ
77 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
78 uart->port.icount.tx += uart->tx_count;
79 uart->tx_count = 0;
80 uart->tx_done = 1;
f4d640c9
RH
81#else
82#ifdef CONFIG_BF54x
f4d640c9
RH
83 /* Clear TFI bit */
84 UART_PUT_LSR(uart, TFI);
85 UART_CLEAR_IER(uart, ETBEI);
194de561 86#else
194de561
BW
87 ier = UART_GET_IER(uart);
88 ier &= ~ETBEI;
89 UART_PUT_IER(uart, ier);
90#endif
f4d640c9 91#endif
194de561
BW
92}
93
94/*
95 * port is locked and interrupts are disabled
96 */
97static void bfin_serial_start_tx(struct uart_port *port)
98{
99 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
100
101#ifdef CONFIG_SERIAL_BFIN_DMA
0711d857
SZ
102 if (uart->tx_done)
103 bfin_serial_dma_tx_chars(uart);
f4d640c9
RH
104#else
105#ifdef CONFIG_BF54x
106 UART_SET_IER(uart, ETBEI);
194de561
BW
107#else
108 unsigned short ier;
109 ier = UART_GET_IER(uart);
110 ier |= ETBEI;
111 UART_PUT_IER(uart, ier);
194de561 112#endif
a359cca7 113 bfin_serial_tx_chars(uart);
f4d640c9 114#endif
194de561
BW
115}
116
117/*
118 * Interrupts are enabled
119 */
120static void bfin_serial_stop_rx(struct uart_port *port)
121{
122 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
a359cca7
SZ
123#ifdef CONFIG_KGDB_UART
124 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
125#endif
f4d640c9
RH
126#ifdef CONFIG_BF54x
127 UART_CLEAR_IER(uart, ERBFI);
128#else
194de561
BW
129 unsigned short ier;
130
131 ier = UART_GET_IER(uart);
132 ier &= ~ERBFI;
133 UART_PUT_IER(uart, ier);
f4d640c9 134#endif
a359cca7
SZ
135#ifdef CONFIG_KGDB_UART
136 }
137#endif
194de561
BW
138}
139
140/*
141 * Set the modem control timer to fire immediately.
142 */
143static void bfin_serial_enable_ms(struct uart_port *port)
144{
145}
146
474f1a66
SZ
147#ifdef CONFIG_KGDB_UART
148static int kgdb_entry_state;
149
150void kgdb_put_debug_char(int chr)
151{
152 struct bfin_serial_port *uart;
153
2ade9729
GY
154 if (CONFIG_KGDB_UART_PORT < 0
155 || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS)
474f1a66
SZ
156 uart = &bfin_serial_ports[0];
157 else
158 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
159
160 while (!(UART_GET_LSR(uart) & THRE)) {
d5148ffa 161 SSYNC();
474f1a66 162 }
a359cca7
SZ
163
164#ifndef CONFIG_BF54x
474f1a66 165 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 166 SSYNC();
a359cca7 167#endif
474f1a66 168 UART_PUT_CHAR(uart, (unsigned char)chr);
d5148ffa 169 SSYNC();
474f1a66
SZ
170}
171
172int kgdb_get_debug_char(void)
173{
174 struct bfin_serial_port *uart;
175 unsigned char chr;
176
2ade9729
GY
177 if (CONFIG_KGDB_UART_PORT < 0
178 || CONFIG_KGDB_UART_PORT >= BFIN_UART_NR_PORTS)
474f1a66
SZ
179 uart = &bfin_serial_ports[0];
180 else
181 uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
182
183 while(!(UART_GET_LSR(uart) & DR)) {
d5148ffa 184 SSYNC();
474f1a66 185 }
a359cca7 186#ifndef CONFIG_BF54x
474f1a66 187 UART_PUT_LCR(uart, UART_GET_LCR(uart)&(~DLAB));
d5148ffa 188 SSYNC();
a359cca7 189#endif
474f1a66 190 chr = UART_GET_CHAR(uart);
d5148ffa 191 SSYNC();
474f1a66
SZ
192
193 return chr;
194}
195#endif
196
50e2e15a 197#if ANOMALY_05000363 && defined(CONFIG_SERIAL_BFIN_PIO)
8851c71e
MF
198# define UART_GET_ANOMALY_THRESHOLD(uart) ((uart)->anomaly_threshold)
199# define UART_SET_ANOMALY_THRESHOLD(uart, v) ((uart)->anomaly_threshold = (v))
200#else
201# define UART_GET_ANOMALY_THRESHOLD(uart) 0
202# define UART_SET_ANOMALY_THRESHOLD(uart, v)
203#endif
204
194de561 205#ifdef CONFIG_SERIAL_BFIN_PIO
194de561
BW
206static void bfin_serial_rx_chars(struct bfin_serial_port *uart)
207{
2ac5ee47 208 struct tty_struct *tty = uart->port.info->tty;
194de561 209 unsigned int status, ch, flg;
8851c71e 210 static struct timeval anomaly_start = { .tv_sec = 0 };
474f1a66
SZ
211#ifdef CONFIG_KGDB_UART
212 struct pt_regs *regs = get_irq_regs();
213#endif
194de561 214
759eb040 215 status = UART_GET_LSR(uart);
0bcfd70e
MF
216 UART_CLEAR_LSR(uart);
217
218 ch = UART_GET_CHAR(uart);
194de561
BW
219 uart->port.icount.rx++;
220
474f1a66
SZ
221#ifdef CONFIG_KGDB_UART
222 if (uart->port.line == CONFIG_KGDB_UART_PORT) {
223 if (uart->port.cons->index == CONFIG_KGDB_UART_PORT && ch == 0x1) { /* Ctrl + A */
224 kgdb_breakkey_pressed(regs);
225 return;
226 } else if (kgdb_entry_state == 0 && ch == '$') {/* connection from KGDB */
227 kgdb_entry_state = 1;
228 } else if (kgdb_entry_state == 1 && ch == 'q') {
229 kgdb_entry_state = 0;
230 kgdb_breakkey_pressed(regs);
231 return;
232 } else if (ch == 0x3) {/* Ctrl + C */
233 kgdb_entry_state = 0;
234 kgdb_breakkey_pressed(regs);
235 return;
236 } else {
237 kgdb_entry_state = 0;
238 }
239 }
240#endif
bbf275f0 241
50e2e15a 242 if (ANOMALY_05000363) {
8851c71e
MF
243 /* The BF533 (and BF561) family of processors have a nice anomaly
244 * where they continuously generate characters for a "single" break.
bbf275f0 245 * We have to basically ignore this flood until the "next" valid
8851c71e
MF
246 * character comes across. Due to the nature of the flood, it is
247 * not possible to reliably catch bytes that are sent too quickly
248 * after this break. So application code talking to the Blackfin
249 * which sends a break signal must allow at least 1.5 character
250 * times after the end of the break for things to stabilize. This
251 * timeout was picked as it must absolutely be larger than 1
252 * character time +/- some percent. So 1.5 sounds good. All other
253 * Blackfin families operate properly. Woo.
bbf275f0 254 */
8851c71e
MF
255 if (anomaly_start.tv_sec) {
256 struct timeval curr;
257 suseconds_t usecs;
258
259 if ((~ch & (~ch + 1)) & 0xff)
260 goto known_good_char;
261
262 do_gettimeofday(&curr);
263 if (curr.tv_sec - anomaly_start.tv_sec > 1)
264 goto known_good_char;
265
266 usecs = 0;
267 if (curr.tv_sec != anomaly_start.tv_sec)
268 usecs += USEC_PER_SEC;
269 usecs += curr.tv_usec - anomaly_start.tv_usec;
270
271 if (usecs > UART_GET_ANOMALY_THRESHOLD(uart))
272 goto known_good_char;
273
274 if (ch)
275 anomaly_start.tv_sec = 0;
276 else
277 anomaly_start = curr;
278
279 return;
280
281 known_good_char:
282 anomaly_start.tv_sec = 0;
bbf275f0 283 }
194de561 284 }
194de561
BW
285
286 if (status & BI) {
50e2e15a 287 if (ANOMALY_05000363)
8851c71e
MF
288 if (bfin_revid() < 5)
289 do_gettimeofday(&anomaly_start);
194de561
BW
290 uart->port.icount.brk++;
291 if (uart_handle_break(&uart->port))
292 goto ignore_char;
9808901b 293 status &= ~(PE | FE);
2ac5ee47
MF
294 }
295 if (status & PE)
194de561 296 uart->port.icount.parity++;
2ac5ee47 297 if (status & OE)
194de561 298 uart->port.icount.overrun++;
2ac5ee47 299 if (status & FE)
194de561 300 uart->port.icount.frame++;
2ac5ee47
MF
301
302 status &= uart->port.read_status_mask;
303
304 if (status & BI)
305 flg = TTY_BREAK;
306 else if (status & PE)
307 flg = TTY_PARITY;
308 else if (status & FE)
309 flg = TTY_FRAME;
310 else
194de561
BW
311 flg = TTY_NORMAL;
312
313 if (uart_handle_sysrq_char(&uart->port, ch))
314 goto ignore_char;
194de561 315
2ac5ee47
MF
316 uart_insert_char(&uart->port, status, OE, ch, flg);
317
318 ignore_char:
319 tty_flip_buffer_push(tty);
194de561
BW
320}
321
322static void bfin_serial_tx_chars(struct bfin_serial_port *uart)
323{
324 struct circ_buf *xmit = &uart->port.info->xmit;
325
326 if (uart->port.x_char) {
327 UART_PUT_CHAR(uart, uart->port.x_char);
328 uart->port.icount.tx++;
329 uart->port.x_char = 0;
194de561
BW
330 }
331 /*
332 * Check the modem control lines before
333 * transmitting anything.
334 */
335 bfin_serial_mctrl_check(uart);
336
337 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
338 bfin_serial_stop_tx(&uart->port);
339 return;
340 }
341
759eb040
SZ
342 while ((UART_GET_LSR(uart) & THRE) && xmit->tail != xmit->head) {
343 UART_PUT_CHAR(uart, xmit->buf[xmit->tail]);
344 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
345 uart->port.icount.tx++;
346 SSYNC();
347 }
194de561
BW
348
349 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
350 uart_write_wakeup(&uart->port);
351
352 if (uart_circ_empty(xmit))
353 bfin_serial_stop_tx(&uart->port);
354}
355
5c4e472b
AL
356static irqreturn_t bfin_serial_rx_int(int irq, void *dev_id)
357{
358 struct bfin_serial_port *uart = dev_id;
359
f4d640c9 360 spin_lock(&uart->port.lock);
0bcfd70e 361 while (UART_GET_LSR(uart) & DR)
f4d640c9 362 bfin_serial_rx_chars(uart);
f4d640c9 363 spin_unlock(&uart->port.lock);
759eb040 364
5c4e472b
AL
365 return IRQ_HANDLED;
366}
367
368static irqreturn_t bfin_serial_tx_int(int irq, void *dev_id)
194de561
BW
369{
370 struct bfin_serial_port *uart = dev_id;
194de561 371
f4d640c9 372 spin_lock(&uart->port.lock);
0bcfd70e 373 if (UART_GET_LSR(uart) & THRE)
f4d640c9 374 bfin_serial_tx_chars(uart);
f4d640c9 375 spin_unlock(&uart->port.lock);
759eb040 376
194de561
BW
377 return IRQ_HANDLED;
378}
4cb4f22b 379#endif
194de561 380
4cb4f22b 381#ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561
BW
382static void bfin_serial_do_work(struct work_struct *work)
383{
384 struct bfin_serial_port *uart = container_of(work, struct bfin_serial_port, cts_workqueue);
385
386 bfin_serial_mctrl_check(uart);
387}
194de561
BW
388#endif
389
390#ifdef CONFIG_SERIAL_BFIN_DMA
391static void bfin_serial_dma_tx_chars(struct bfin_serial_port *uart)
392{
393 struct circ_buf *xmit = &uart->port.info->xmit;
394 unsigned short ier;
194de561 395
194de561
BW
396 uart->tx_done = 0;
397
1b73351c 398 if (uart_circ_empty(xmit) || uart_tx_stopped(&uart->port)) {
0711d857 399 uart->tx_count = 0;
1b73351c
SZ
400 uart->tx_done = 1;
401 return;
402 }
403
194de561
BW
404 if (uart->port.x_char) {
405 UART_PUT_CHAR(uart, uart->port.x_char);
406 uart->port.icount.tx++;
407 uart->port.x_char = 0;
194de561 408 }
1b73351c 409
194de561
BW
410 /*
411 * Check the modem control lines before
412 * transmitting anything.
413 */
414 bfin_serial_mctrl_check(uart);
415
194de561
BW
416 uart->tx_count = CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE);
417 if (uart->tx_count > (UART_XMIT_SIZE - xmit->tail))
418 uart->tx_count = UART_XMIT_SIZE - xmit->tail;
419 blackfin_dcache_flush_range((unsigned long)(xmit->buf+xmit->tail),
420 (unsigned long)(xmit->buf+xmit->tail+uart->tx_count));
421 set_dma_config(uart->tx_dma_channel,
422 set_bfin_dma_config(DIR_READ, DMA_FLOW_STOP,
423 INTR_ON_BUF,
424 DIMENSION_LINEAR,
2047e40d
MH
425 DATA_SIZE_8,
426 DMA_SYNC_RESTART));
194de561
BW
427 set_dma_start_addr(uart->tx_dma_channel, (unsigned long)(xmit->buf+xmit->tail));
428 set_dma_x_count(uart->tx_dma_channel, uart->tx_count);
429 set_dma_x_modify(uart->tx_dma_channel, 1);
430 enable_dma(uart->tx_dma_channel);
99ee7b5f 431
f4d640c9
RH
432#ifdef CONFIG_BF54x
433 UART_SET_IER(uart, ETBEI);
434#else
194de561
BW
435 ier = UART_GET_IER(uart);
436 ier |= ETBEI;
437 UART_PUT_IER(uart, ier);
f4d640c9 438#endif
194de561
BW
439}
440
2ac5ee47 441static void bfin_serial_dma_rx_chars(struct bfin_serial_port *uart)
194de561
BW
442{
443 struct tty_struct *tty = uart->port.info->tty;
444 int i, flg, status;
445
446 status = UART_GET_LSR(uart);
0bcfd70e
MF
447 UART_CLEAR_LSR(uart);
448
56f5de8f
SZ
449 uart->port.icount.rx +=
450 CIRC_CNT(uart->rx_dma_buf.head, uart->rx_dma_buf.tail,
451 UART_XMIT_SIZE);
194de561
BW
452
453 if (status & BI) {
454 uart->port.icount.brk++;
455 if (uart_handle_break(&uart->port))
456 goto dma_ignore_char;
9808901b 457 status &= ~(PE | FE);
2ac5ee47
MF
458 }
459 if (status & PE)
194de561 460 uart->port.icount.parity++;
2ac5ee47 461 if (status & OE)
194de561 462 uart->port.icount.overrun++;
2ac5ee47 463 if (status & FE)
194de561 464 uart->port.icount.frame++;
2ac5ee47
MF
465
466 status &= uart->port.read_status_mask;
467
468 if (status & BI)
469 flg = TTY_BREAK;
470 else if (status & PE)
471 flg = TTY_PARITY;
472 else if (status & FE)
473 flg = TTY_FRAME;
474 else
194de561
BW
475 flg = TTY_NORMAL;
476
56f5de8f
SZ
477 for (i = uart->rx_dma_buf.tail; i != uart->rx_dma_buf.head; i++) {
478 if (i >= UART_XMIT_SIZE)
479 i = 0;
480 if (!uart_handle_sysrq_char(&uart->port, uart->rx_dma_buf.buf[i]))
481 uart_insert_char(&uart->port, status, OE,
482 uart->rx_dma_buf.buf[i], flg);
194de561 483 }
2ac5ee47
MF
484
485 dma_ignore_char:
194de561
BW
486 tty_flip_buffer_push(tty);
487}
488
489void bfin_serial_rx_dma_timeout(struct bfin_serial_port *uart)
490{
491 int x_pos, pos;
194de561 492
56f5de8f
SZ
493 uart->rx_dma_nrows = get_dma_curr_ycount(uart->rx_dma_channel);
494 x_pos = get_dma_curr_xcount(uart->rx_dma_channel);
495 uart->rx_dma_nrows = DMA_RX_YCOUNT - uart->rx_dma_nrows;
496 if (uart->rx_dma_nrows == DMA_RX_YCOUNT)
497 uart->rx_dma_nrows = 0;
498 x_pos = DMA_RX_XCOUNT - x_pos;
194de561
BW
499 if (x_pos == DMA_RX_XCOUNT)
500 x_pos = 0;
501
502 pos = uart->rx_dma_nrows * DMA_RX_XCOUNT + x_pos;
56f5de8f
SZ
503 if (pos != uart->rx_dma_buf.tail) {
504 uart->rx_dma_buf.head = pos;
194de561 505 bfin_serial_dma_rx_chars(uart);
56f5de8f 506 uart->rx_dma_buf.tail = uart->rx_dma_buf.head;
194de561 507 }
0aef4564 508
194de561
BW
509 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
510 add_timer(&(uart->rx_dma_timer));
511}
512
513static irqreturn_t bfin_serial_dma_tx_int(int irq, void *dev_id)
514{
515 struct bfin_serial_port *uart = dev_id;
516 struct circ_buf *xmit = &uart->port.info->xmit;
517 unsigned short ier;
518
519 spin_lock(&uart->port.lock);
520 if (!(get_dma_curr_irqstat(uart->tx_dma_channel)&DMA_RUN)) {
194de561 521 disable_dma(uart->tx_dma_channel);
0711d857 522 clear_dma_irqstat(uart->tx_dma_channel);
f4d640c9
RH
523#ifdef CONFIG_BF54x
524 UART_CLEAR_IER(uart, ETBEI);
525#else
194de561
BW
526 ier = UART_GET_IER(uart);
527 ier &= ~ETBEI;
528 UART_PUT_IER(uart, ier);
f4d640c9 529#endif
0711d857
SZ
530 xmit->tail = (xmit->tail + uart->tx_count) & (UART_XMIT_SIZE - 1);
531 uart->port.icount.tx += uart->tx_count;
1b73351c 532
56f5de8f
SZ
533 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
534 uart_write_wakeup(&uart->port);
535
1b73351c 536 bfin_serial_dma_tx_chars(uart);
194de561
BW
537 }
538
539 spin_unlock(&uart->port.lock);
540 return IRQ_HANDLED;
541}
542
543static irqreturn_t bfin_serial_dma_rx_int(int irq, void *dev_id)
544{
545 struct bfin_serial_port *uart = dev_id;
546 unsigned short irqstat;
0711d857 547
194de561
BW
548 spin_lock(&uart->port.lock);
549 irqstat = get_dma_curr_irqstat(uart->rx_dma_channel);
550 clear_dma_irqstat(uart->rx_dma_channel);
194de561 551 spin_unlock(&uart->port.lock);
0aef4564
SZ
552
553 del_timer(&(uart->rx_dma_timer));
554 uart->rx_dma_timer.expires = jiffies;
555 add_timer(&(uart->rx_dma_timer));
556
194de561
BW
557 return IRQ_HANDLED;
558}
559#endif
560
561/*
562 * Return TIOCSER_TEMT when transmitter is not busy.
563 */
564static unsigned int bfin_serial_tx_empty(struct uart_port *port)
565{
566 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
567 unsigned short lsr;
568
569 lsr = UART_GET_LSR(uart);
570 if (lsr & TEMT)
571 return TIOCSER_TEMT;
572 else
573 return 0;
574}
575
576static unsigned int bfin_serial_get_mctrl(struct uart_port *port)
577{
578#ifdef CONFIG_SERIAL_BFIN_CTSRTS
579 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
580 if (uart->cts_pin < 0)
581 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
582
db288381
SZ
583# ifdef BF54x
584 if (UART_GET_MSR(uart) & CTS)
585# else
194de561 586 if (gpio_get_value(uart->cts_pin))
db288381 587# endif
194de561
BW
588 return TIOCM_DSR | TIOCM_CAR;
589 else
590#endif
591 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
592}
593
594static void bfin_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
595{
596#ifdef CONFIG_SERIAL_BFIN_CTSRTS
597 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
598 if (uart->rts_pin < 0)
599 return;
600
601 if (mctrl & TIOCM_RTS)
db288381
SZ
602# ifdef BF54x
603 UART_PUT_MCR(uart, UART_GET_MCR(uart) & ~MRTS);
604# else
194de561 605 gpio_set_value(uart->rts_pin, 0);
db288381 606# endif
194de561 607 else
db288381
SZ
608# ifdef BF54x
609 UART_PUT_MCR(uart, UART_GET_MCR(uart) | MRTS);
610# else
194de561 611 gpio_set_value(uart->rts_pin, 1);
db288381 612# endif
194de561
BW
613#endif
614}
615
616/*
617 * Handle any change of modem status signal since we were last called.
618 */
619static void bfin_serial_mctrl_check(struct bfin_serial_port *uart)
620{
621#ifdef CONFIG_SERIAL_BFIN_CTSRTS
622 unsigned int status;
194de561
BW
623 struct uart_info *info = uart->port.info;
624 struct tty_struct *tty = info->tty;
625
626 status = bfin_serial_get_mctrl(&uart->port);
4cb4f22b 627 uart_handle_cts_change(&uart->port, status & TIOCM_CTS);
194de561
BW
628 if (!(status & TIOCM_CTS)) {
629 tty->hw_stopped = 1;
4cb4f22b 630 schedule_work(&uart->cts_workqueue);
194de561
BW
631 } else {
632 tty->hw_stopped = 0;
633 }
194de561
BW
634#endif
635}
636
637/*
638 * Interrupts are always disabled.
639 */
640static void bfin_serial_break_ctl(struct uart_port *port, int break_state)
641{
cf686762
MF
642 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
643 u16 lcr = UART_GET_LCR(uart);
644 if (break_state)
645 lcr |= SB;
646 else
647 lcr &= ~SB;
648 UART_PUT_LCR(uart, lcr);
649 SSYNC();
194de561
BW
650}
651
652static int bfin_serial_startup(struct uart_port *port)
653{
654 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
655
656#ifdef CONFIG_SERIAL_BFIN_DMA
657 dma_addr_t dma_handle;
658
659 if (request_dma(uart->rx_dma_channel, "BFIN_UART_RX") < 0) {
660 printk(KERN_NOTICE "Unable to attach Blackfin UART RX DMA channel\n");
661 return -EBUSY;
662 }
663
664 if (request_dma(uart->tx_dma_channel, "BFIN_UART_TX") < 0) {
665 printk(KERN_NOTICE "Unable to attach Blackfin UART TX DMA channel\n");
666 free_dma(uart->rx_dma_channel);
667 return -EBUSY;
668 }
669
670 set_dma_callback(uart->rx_dma_channel, bfin_serial_dma_rx_int, uart);
671 set_dma_callback(uart->tx_dma_channel, bfin_serial_dma_tx_int, uart);
672
673 uart->rx_dma_buf.buf = (unsigned char *)dma_alloc_coherent(NULL, PAGE_SIZE, &dma_handle, GFP_DMA);
674 uart->rx_dma_buf.head = 0;
675 uart->rx_dma_buf.tail = 0;
676 uart->rx_dma_nrows = 0;
677
678 set_dma_config(uart->rx_dma_channel,
679 set_bfin_dma_config(DIR_WRITE, DMA_FLOW_AUTO,
680 INTR_ON_ROW, DIMENSION_2D,
2047e40d
MH
681 DATA_SIZE_8,
682 DMA_SYNC_RESTART));
194de561
BW
683 set_dma_x_count(uart->rx_dma_channel, DMA_RX_XCOUNT);
684 set_dma_x_modify(uart->rx_dma_channel, 1);
685 set_dma_y_count(uart->rx_dma_channel, DMA_RX_YCOUNT);
686 set_dma_y_modify(uart->rx_dma_channel, 1);
687 set_dma_start_addr(uart->rx_dma_channel, (unsigned long)uart->rx_dma_buf.buf);
688 enable_dma(uart->rx_dma_channel);
689
690 uart->rx_dma_timer.data = (unsigned long)(uart);
691 uart->rx_dma_timer.function = (void *)bfin_serial_rx_dma_timeout;
692 uart->rx_dma_timer.expires = jiffies + DMA_RX_FLUSH_JIFFIES;
693 add_timer(&(uart->rx_dma_timer));
694#else
a359cca7
SZ
695 if (request_irq(uart->port.irq, bfin_serial_rx_int, IRQF_DISABLED,
696 "BFIN_UART_RX", uart)) {
474f1a66 697# ifdef CONFIG_KGDB_UART
a359cca7 698 if (uart->port.line != CONFIG_KGDB_UART_PORT) {
474f1a66 699# endif
194de561
BW
700 printk(KERN_NOTICE "Unable to attach BlackFin UART RX interrupt\n");
701 return -EBUSY;
a359cca7
SZ
702# ifdef CONFIG_KGDB_UART
703 }
704# endif
194de561
BW
705 }
706
a359cca7 707
194de561 708 if (request_irq
5c4e472b 709 (uart->port.irq+1, bfin_serial_tx_int, IRQF_DISABLED,
194de561
BW
710 "BFIN_UART_TX", uart)) {
711 printk(KERN_NOTICE "Unable to attach BlackFin UART TX interrupt\n");
712 free_irq(uart->port.irq, uart);
713 return -EBUSY;
714 }
715#endif
f4d640c9
RH
716#ifdef CONFIG_BF54x
717 UART_SET_IER(uart, ERBFI);
718#else
194de561 719 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
f4d640c9 720#endif
194de561
BW
721 return 0;
722}
723
724static void bfin_serial_shutdown(struct uart_port *port)
725{
726 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
727
728#ifdef CONFIG_SERIAL_BFIN_DMA
729 disable_dma(uart->tx_dma_channel);
730 free_dma(uart->tx_dma_channel);
731 disable_dma(uart->rx_dma_channel);
732 free_dma(uart->rx_dma_channel);
733 del_timer(&(uart->rx_dma_timer));
75b780bd 734 dma_free_coherent(NULL, PAGE_SIZE, uart->rx_dma_buf.buf, 0);
194de561 735#else
474f1a66
SZ
736#ifdef CONFIG_KGDB_UART
737 if (uart->port.line != CONFIG_KGDB_UART_PORT)
738#endif
194de561
BW
739 free_irq(uart->port.irq, uart);
740 free_irq(uart->port.irq+1, uart);
741#endif
742}
743
744static void
745bfin_serial_set_termios(struct uart_port *port, struct ktermios *termios,
746 struct ktermios *old)
747{
748 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
749 unsigned long flags;
750 unsigned int baud, quot;
0c44a86d 751 unsigned short val, ier, lcr = 0;
194de561
BW
752
753 switch (termios->c_cflag & CSIZE) {
754 case CS8:
755 lcr = WLS(8);
756 break;
757 case CS7:
758 lcr = WLS(7);
759 break;
760 case CS6:
761 lcr = WLS(6);
762 break;
763 case CS5:
764 lcr = WLS(5);
765 break;
766 default:
767 printk(KERN_ERR "%s: word lengh not supported\n",
768 __FUNCTION__);
769 }
770
771 if (termios->c_cflag & CSTOPB)
772 lcr |= STB;
19aa6382 773 if (termios->c_cflag & PARENB)
194de561 774 lcr |= PEN;
19aa6382
MF
775 if (!(termios->c_cflag & PARODD))
776 lcr |= EPS;
777 if (termios->c_cflag & CMSPAR)
778 lcr |= STP;
194de561 779
2ac5ee47
MF
780 port->read_status_mask = OE;
781 if (termios->c_iflag & INPCK)
782 port->read_status_mask |= (FE | PE);
783 if (termios->c_iflag & (BRKINT | PARMRK))
784 port->read_status_mask |= BI;
194de561 785
2ac5ee47
MF
786 /*
787 * Characters to ignore
788 */
789 port->ignore_status_mask = 0;
790 if (termios->c_iflag & IGNPAR)
791 port->ignore_status_mask |= FE | PE;
792 if (termios->c_iflag & IGNBRK) {
793 port->ignore_status_mask |= BI;
794 /*
795 * If we're ignoring parity and break indicators,
796 * ignore overruns too (for real raw support).
797 */
798 if (termios->c_iflag & IGNPAR)
799 port->ignore_status_mask |= OE;
800 }
194de561
BW
801
802 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
803 quot = uart_get_divisor(port, baud);
804 spin_lock_irqsave(&uart->port.lock, flags);
805
8851c71e
MF
806 UART_SET_ANOMALY_THRESHOLD(uart, USEC_PER_SEC / baud * 15);
807
194de561
BW
808 /* Disable UART */
809 ier = UART_GET_IER(uart);
f4d640c9
RH
810#ifdef CONFIG_BF54x
811 UART_CLEAR_IER(uart, 0xF);
812#else
194de561 813 UART_PUT_IER(uart, 0);
f4d640c9 814#endif
194de561 815
f4d640c9 816#ifndef CONFIG_BF54x
194de561
BW
817 /* Set DLAB in LCR to Access DLL and DLH */
818 val = UART_GET_LCR(uart);
819 val |= DLAB;
820 UART_PUT_LCR(uart, val);
821 SSYNC();
f4d640c9 822#endif
194de561
BW
823
824 UART_PUT_DLL(uart, quot & 0xFF);
825 SSYNC();
826 UART_PUT_DLH(uart, (quot >> 8) & 0xFF);
827 SSYNC();
828
f4d640c9 829#ifndef CONFIG_BF54x
194de561
BW
830 /* Clear DLAB in LCR to Access THR RBR IER */
831 val = UART_GET_LCR(uart);
832 val &= ~DLAB;
833 UART_PUT_LCR(uart, val);
834 SSYNC();
f4d640c9 835#endif
194de561
BW
836
837 UART_PUT_LCR(uart, lcr);
838
839 /* Enable UART */
f4d640c9
RH
840#ifdef CONFIG_BF54x
841 UART_SET_IER(uart, ier);
842#else
194de561 843 UART_PUT_IER(uart, ier);
f4d640c9 844#endif
194de561
BW
845
846 val = UART_GET_GCTL(uart);
847 val |= UCEN;
848 UART_PUT_GCTL(uart, val);
849
850 spin_unlock_irqrestore(&uart->port.lock, flags);
851}
852
853static const char *bfin_serial_type(struct uart_port *port)
854{
855 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
856
857 return uart->port.type == PORT_BFIN ? "BFIN-UART" : NULL;
858}
859
860/*
861 * Release the memory region(s) being used by 'port'.
862 */
863static void bfin_serial_release_port(struct uart_port *port)
864{
865}
866
867/*
868 * Request the memory region(s) being used by 'port'.
869 */
870static int bfin_serial_request_port(struct uart_port *port)
871{
872 return 0;
873}
874
875/*
876 * Configure/autoconfigure the port.
877 */
878static void bfin_serial_config_port(struct uart_port *port, int flags)
879{
880 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
881
882 if (flags & UART_CONFIG_TYPE &&
883 bfin_serial_request_port(&uart->port) == 0)
884 uart->port.type = PORT_BFIN;
885}
886
887/*
888 * Verify the new serial_struct (for TIOCSSERIAL).
889 * The only change we allow are to the flags and type, and
890 * even then only between PORT_BFIN and PORT_UNKNOWN
891 */
892static int
893bfin_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
894{
895 return 0;
896}
897
7d01b475
GY
898/*
899 * Enable the IrDA function if tty->ldisc.num is N_IRDA.
900 * In other cases, disable IrDA function.
901 */
902static void bfin_set_ldisc(struct tty_struct *tty)
903{
904 int line = tty->index;
905 unsigned short val;
906
907 if (line >= tty->driver->num)
908 return;
909
910 switch (tty->ldisc.num) {
911 case N_IRDA:
912 val = UART_GET_GCTL(&bfin_serial_ports[line]);
913 val |= (IREN | RPOLC);
914 UART_PUT_GCTL(&bfin_serial_ports[line], val);
915 break;
916 default:
917 val = UART_GET_GCTL(&bfin_serial_ports[line]);
918 val &= ~(IREN | RPOLC);
919 UART_PUT_GCTL(&bfin_serial_ports[line], val);
920 }
921}
922
194de561
BW
923static struct uart_ops bfin_serial_pops = {
924 .tx_empty = bfin_serial_tx_empty,
925 .set_mctrl = bfin_serial_set_mctrl,
926 .get_mctrl = bfin_serial_get_mctrl,
927 .stop_tx = bfin_serial_stop_tx,
928 .start_tx = bfin_serial_start_tx,
929 .stop_rx = bfin_serial_stop_rx,
930 .enable_ms = bfin_serial_enable_ms,
931 .break_ctl = bfin_serial_break_ctl,
932 .startup = bfin_serial_startup,
933 .shutdown = bfin_serial_shutdown,
934 .set_termios = bfin_serial_set_termios,
935 .type = bfin_serial_type,
936 .release_port = bfin_serial_release_port,
937 .request_port = bfin_serial_request_port,
938 .config_port = bfin_serial_config_port,
939 .verify_port = bfin_serial_verify_port,
940};
941
942static void __init bfin_serial_init_ports(void)
943{
944 static int first = 1;
945 int i;
946
947 if (!first)
948 return;
949 first = 0;
950
951 for (i = 0; i < nr_ports; i++) {
952 bfin_serial_ports[i].port.uartclk = get_sclk();
953 bfin_serial_ports[i].port.ops = &bfin_serial_pops;
954 bfin_serial_ports[i].port.line = i;
955 bfin_serial_ports[i].port.iotype = UPIO_MEM;
956 bfin_serial_ports[i].port.membase =
957 (void __iomem *)bfin_serial_resource[i].uart_base_addr;
958 bfin_serial_ports[i].port.mapbase =
959 bfin_serial_resource[i].uart_base_addr;
960 bfin_serial_ports[i].port.irq =
961 bfin_serial_resource[i].uart_irq;
962 bfin_serial_ports[i].port.flags = UPF_BOOT_AUTOCONF;
963#ifdef CONFIG_SERIAL_BFIN_DMA
964 bfin_serial_ports[i].tx_done = 1;
965 bfin_serial_ports[i].tx_count = 0;
966 bfin_serial_ports[i].tx_dma_channel =
967 bfin_serial_resource[i].uart_tx_dma_channel;
968 bfin_serial_ports[i].rx_dma_channel =
969 bfin_serial_resource[i].uart_rx_dma_channel;
970 init_timer(&(bfin_serial_ports[i].rx_dma_timer));
194de561
BW
971#endif
972#ifdef CONFIG_SERIAL_BFIN_CTSRTS
4cb4f22b 973 INIT_WORK(&bfin_serial_ports[i].cts_workqueue, bfin_serial_do_work);
194de561
BW
974 bfin_serial_ports[i].cts_pin =
975 bfin_serial_resource[i].uart_cts_pin;
976 bfin_serial_ports[i].rts_pin =
977 bfin_serial_resource[i].uart_rts_pin;
978#endif
979 bfin_serial_hw_init(&bfin_serial_ports[i]);
194de561 980 }
f4d640c9 981
194de561
BW
982}
983
984#ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
985/*
986 * If the port was already initialised (eg, by a boot loader),
987 * try to determine the current setup.
988 */
989static void __init
990bfin_serial_console_get_options(struct bfin_serial_port *uart, int *baud,
991 int *parity, int *bits)
992{
993 unsigned short status;
994
995 status = UART_GET_IER(uart) & (ERBFI | ETBEI);
996 if (status == (ERBFI | ETBEI)) {
997 /* ok, the port was enabled */
998 unsigned short lcr, val;
999 unsigned short dlh, dll;
1000
1001 lcr = UART_GET_LCR(uart);
1002
1003 *parity = 'n';
1004 if (lcr & PEN) {
1005 if (lcr & EPS)
1006 *parity = 'e';
1007 else
1008 *parity = 'o';
1009 }
1010 switch (lcr & 0x03) {
1011 case 0: *bits = 5; break;
1012 case 1: *bits = 6; break;
1013 case 2: *bits = 7; break;
1014 case 3: *bits = 8; break;
1015 }
f4d640c9 1016#ifndef CONFIG_BF54x
194de561
BW
1017 /* Set DLAB in LCR to Access DLL and DLH */
1018 val = UART_GET_LCR(uart);
1019 val |= DLAB;
1020 UART_PUT_LCR(uart, val);
f4d640c9 1021#endif
194de561
BW
1022
1023 dll = UART_GET_DLL(uart);
1024 dlh = UART_GET_DLH(uart);
1025
f4d640c9 1026#ifndef CONFIG_BF54x
194de561
BW
1027 /* Clear DLAB in LCR to Access THR RBR IER */
1028 val = UART_GET_LCR(uart);
1029 val &= ~DLAB;
1030 UART_PUT_LCR(uart, val);
f4d640c9 1031#endif
194de561
BW
1032
1033 *baud = get_sclk() / (16*(dll | dlh << 8));
1034 }
1035 pr_debug("%s:baud = %d, parity = %c, bits= %d\n", __FUNCTION__, *baud, *parity, *bits);
1036}
0ae53640
RG
1037#endif
1038
1039#if defined(CONFIG_SERIAL_BFIN_CONSOLE) || defined(CONFIG_EARLY_PRINTK)
1040static struct uart_driver bfin_serial_reg;
194de561
BW
1041
1042static int __init
1043bfin_serial_console_setup(struct console *co, char *options)
1044{
1045 struct bfin_serial_port *uart;
0ae53640 1046# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
1047 int baud = 57600;
1048 int bits = 8;
1049 int parity = 'n';
0ae53640 1050# ifdef CONFIG_SERIAL_BFIN_CTSRTS
194de561 1051 int flow = 'r';
0ae53640 1052# else
194de561 1053 int flow = 'n';
0ae53640
RG
1054# endif
1055# endif
194de561
BW
1056
1057 /*
1058 * Check whether an invalid uart number has been specified, and
1059 * if so, search for the first available port that does have
1060 * console support.
1061 */
1062 if (co->index == -1 || co->index >= nr_ports)
1063 co->index = 0;
1064 uart = &bfin_serial_ports[co->index];
1065
0ae53640 1066# ifdef CONFIG_SERIAL_BFIN_CONSOLE
194de561
BW
1067 if (options)
1068 uart_parse_options(options, &baud, &parity, &bits, &flow);
1069 else
1070 bfin_serial_console_get_options(uart, &baud, &parity, &bits);
1071
1072 return uart_set_options(&uart->port, co, baud, parity, bits, flow);
0ae53640
RG
1073# else
1074 return 0;
1075# endif
1076}
1077#endif /* defined (CONFIG_SERIAL_BFIN_CONSOLE) ||
1078 defined (CONFIG_EARLY_PRINTK) */
1079
1080#ifdef CONFIG_SERIAL_BFIN_CONSOLE
1081static void bfin_serial_console_putchar(struct uart_port *port, int ch)
1082{
1083 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1084 while (!(UART_GET_LSR(uart) & THRE))
1085 barrier();
1086 UART_PUT_CHAR(uart, ch);
1087 SSYNC();
1088}
1089
1090/*
1091 * Interrupts are disabled on entering
1092 */
1093static void
1094bfin_serial_console_write(struct console *co, const char *s, unsigned int count)
1095{
1096 struct bfin_serial_port *uart = &bfin_serial_ports[co->index];
1097 int flags = 0;
1098
1099 spin_lock_irqsave(&uart->port.lock, flags);
1100 uart_console_write(&uart->port, s, count, bfin_serial_console_putchar);
1101 spin_unlock_irqrestore(&uart->port.lock, flags);
1102
194de561
BW
1103}
1104
194de561
BW
1105static struct console bfin_serial_console = {
1106 .name = BFIN_SERIAL_NAME,
1107 .write = bfin_serial_console_write,
1108 .device = uart_console_device,
1109 .setup = bfin_serial_console_setup,
1110 .flags = CON_PRINTBUFFER,
1111 .index = -1,
1112 .data = &bfin_serial_reg,
1113};
1114
1115static int __init bfin_serial_rs_console_init(void)
1116{
1117 bfin_serial_init_ports();
1118 register_console(&bfin_serial_console);
474f1a66
SZ
1119#ifdef CONFIG_KGDB_UART
1120 kgdb_entry_state = 0;
1121 init_kgdb_uart();
1122#endif
194de561
BW
1123 return 0;
1124}
1125console_initcall(bfin_serial_rs_console_init);
1126
1127#define BFIN_SERIAL_CONSOLE &bfin_serial_console
1128#else
1129#define BFIN_SERIAL_CONSOLE NULL
0ae53640
RG
1130#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
1131
1132
1133#ifdef CONFIG_EARLY_PRINTK
1134static __init void early_serial_putc(struct uart_port *port, int ch)
1135{
1136 unsigned timeout = 0xffff;
1137 struct bfin_serial_port *uart = (struct bfin_serial_port *)port;
1138
1139 while ((!(UART_GET_LSR(uart) & THRE)) && --timeout)
1140 cpu_relax();
1141 UART_PUT_CHAR(uart, ch);
1142}
1143
1144static __init void early_serial_write(struct console *con, const char *s,
1145 unsigned int n)
1146{
1147 struct bfin_serial_port *uart = &bfin_serial_ports[con->index];
1148 unsigned int i;
1149
1150 for (i = 0; i < n; i++, s++) {
1151 if (*s == '\n')
1152 early_serial_putc(&uart->port, '\r');
1153 early_serial_putc(&uart->port, *s);
1154 }
1155}
1156
1157static struct __init console bfin_early_serial_console = {
1158 .name = "early_BFuart",
1159 .write = early_serial_write,
1160 .device = uart_console_device,
1161 .flags = CON_PRINTBUFFER,
1162 .setup = bfin_serial_console_setup,
1163 .index = -1,
1164 .data = &bfin_serial_reg,
1165};
1166
1167struct console __init *bfin_earlyserial_init(unsigned int port,
1168 unsigned int cflag)
1169{
1170 struct bfin_serial_port *uart;
1171 struct ktermios t;
1172
1173 if (port == -1 || port >= nr_ports)
1174 port = 0;
1175 bfin_serial_init_ports();
1176 bfin_early_serial_console.index = port;
0ae53640
RG
1177 uart = &bfin_serial_ports[port];
1178 t.c_cflag = cflag;
1179 t.c_iflag = 0;
1180 t.c_oflag = 0;
1181 t.c_lflag = ICANON;
1182 t.c_line = port;
1183 bfin_serial_set_termios(&uart->port, &t, &t);
1184 return &bfin_early_serial_console;
1185}
1186
1187#endif /* CONFIG_SERIAL_BFIN_CONSOLE */
194de561
BW
1188
1189static struct uart_driver bfin_serial_reg = {
1190 .owner = THIS_MODULE,
1191 .driver_name = "bfin-uart",
1192 .dev_name = BFIN_SERIAL_NAME,
1193 .major = BFIN_SERIAL_MAJOR,
1194 .minor = BFIN_SERIAL_MINOR,
2ade9729 1195 .nr = BFIN_UART_NR_PORTS,
194de561
BW
1196 .cons = BFIN_SERIAL_CONSOLE,
1197};
1198
1199static int bfin_serial_suspend(struct platform_device *dev, pm_message_t state)
1200{
1201 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1202
1203 if (uart)
1204 uart_suspend_port(&bfin_serial_reg, &uart->port);
1205
1206 return 0;
1207}
1208
1209static int bfin_serial_resume(struct platform_device *dev)
1210{
1211 struct bfin_serial_port *uart = platform_get_drvdata(dev);
1212
1213 if (uart)
1214 uart_resume_port(&bfin_serial_reg, &uart->port);
1215
1216 return 0;
1217}
1218
1219static int bfin_serial_probe(struct platform_device *dev)
1220{
1221 struct resource *res = dev->resource;
1222 int i;
1223
1224 for (i = 0; i < dev->num_resources; i++, res++)
1225 if (res->flags & IORESOURCE_MEM)
1226 break;
1227
1228 if (i < dev->num_resources) {
1229 for (i = 0; i < nr_ports; i++, res++) {
1230 if (bfin_serial_ports[i].port.mapbase != res->start)
1231 continue;
1232 bfin_serial_ports[i].port.dev = &dev->dev;
1233 uart_add_one_port(&bfin_serial_reg, &bfin_serial_ports[i].port);
1234 platform_set_drvdata(dev, &bfin_serial_ports[i]);
1235 }
1236 }
1237
1238 return 0;
1239}
1240
1241static int bfin_serial_remove(struct platform_device *pdev)
1242{
1243 struct bfin_serial_port *uart = platform_get_drvdata(pdev);
1244
1245
1246#ifdef CONFIG_SERIAL_BFIN_CTSRTS
1247 gpio_free(uart->cts_pin);
1248 gpio_free(uart->rts_pin);
1249#endif
1250
1251 platform_set_drvdata(pdev, NULL);
1252
1253 if (uart)
1254 uart_remove_one_port(&bfin_serial_reg, &uart->port);
1255
1256 return 0;
1257}
1258
1259static struct platform_driver bfin_serial_driver = {
1260 .probe = bfin_serial_probe,
1261 .remove = bfin_serial_remove,
1262 .suspend = bfin_serial_suspend,
1263 .resume = bfin_serial_resume,
1264 .driver = {
1265 .name = "bfin-uart",
e169c139 1266 .owner = THIS_MODULE,
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1267 },
1268};
1269
1270static int __init bfin_serial_init(void)
1271{
1272 int ret;
474f1a66
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1273#ifdef CONFIG_KGDB_UART
1274 struct bfin_serial_port *uart = &bfin_serial_ports[CONFIG_KGDB_UART_PORT];
a359cca7 1275 struct ktermios t;
474f1a66 1276#endif
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1277
1278 pr_info("Serial: Blackfin serial driver\n");
1279
1280 bfin_serial_init_ports();
1281
1282 ret = uart_register_driver(&bfin_serial_reg);
1283 if (ret == 0) {
7d01b475 1284 bfin_serial_reg.tty_driver->set_ldisc = bfin_set_ldisc;
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1285 ret = platform_driver_register(&bfin_serial_driver);
1286 if (ret) {
1287 pr_debug("uart register failed\n");
1288 uart_unregister_driver(&bfin_serial_reg);
1289 }
1290 }
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1291#ifdef CONFIG_KGDB_UART
1292 if (uart->port.cons->index != CONFIG_KGDB_UART_PORT) {
a359cca7 1293 request_irq(uart->port.irq, bfin_serial_rx_int,
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1294 IRQF_DISABLED, "BFIN_UART_RX", uart);
1295 pr_info("Request irq for kgdb uart port\n");
a359cca7
SZ
1296#ifdef CONFIG_BF54x
1297 UART_SET_IER(uart, ERBFI);
1298#else
474f1a66 1299 UART_PUT_IER(uart, UART_GET_IER(uart) | ERBFI);
a359cca7 1300#endif
d5148ffa 1301 SSYNC();
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1302 t.c_cflag = CS8|B57600;
1303 t.c_iflag = 0;
1304 t.c_oflag = 0;
1305 t.c_lflag = ICANON;
1306 t.c_line = CONFIG_KGDB_UART_PORT;
1307 bfin_serial_set_termios(&uart->port, &t, &t);
1308 }
1309#endif
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1310 return ret;
1311}
1312
1313static void __exit bfin_serial_exit(void)
1314{
1315 platform_driver_unregister(&bfin_serial_driver);
1316 uart_unregister_driver(&bfin_serial_reg);
1317}
1318
1319module_init(bfin_serial_init);
1320module_exit(bfin_serial_exit);
1321
1322MODULE_AUTHOR("Aubrey.Li <aubrey.li@analog.com>");
1323MODULE_DESCRIPTION("Blackfin generic serial port driver");
1324MODULE_LICENSE("GPL");
1325MODULE_ALIAS_CHARDEV_MAJOR(BFIN_SERIAL_MAJOR);
e169c139 1326MODULE_ALIAS("platform:bfin-uart");