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Merge branch 'tty-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh...
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4 33#include <linux/tty.h>
cd3ecad1 34#include <linux/ratelimit.h>
1da177e4
LT		 35#include <linux/tty_flip.h>
36#include <linux/serial_reg.h>
37#include <linux/serial_core.h>
38#include <linux/serial.h>
39#include <linux/serial_8250.h>
78512ece 40#include <linux/nmi.h>
f392ecfa 41#include <linux/mutex.h>
5a0e3ad6 42#include <linux/slab.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
b70ac771
DM		 49#ifdef CONFIG_SPARC
50#include "suncore.h"
51#endif
52
1da177e4
LT		 53/*
54 * Configuration:
40663cc7 55 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 56 * is unsafe when used on edge-triggered interrupts.
57 */
408b664a 58static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 59
a61c2d78
DJ		 60static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
61
8440838b
DM		 62static struct uart_driver serial8250_reg;
63
64static int serial_index(struct uart_port *port)
65{
66 return (serial8250_reg.minor - 64) + port->line;
67}
68
d41a4b51
CE		 69static unsigned int skip_txen_test; /* force skip of txen test at init time */
70
1da177e4
LT		 71/*
72 * Debugging.
73 */
74#if 0
75#define DEBUG_AUTOCONF(fmt...) printk(fmt)
76#else
77#define DEBUG_AUTOCONF(fmt...) do { } while (0)
78#endif
79
80#if 0
81#define DEBUG_INTR(fmt...) printk(fmt)
82#else
83#define DEBUG_INTR(fmt...) do { } while (0)
84#endif
85
86#define PASS_LIMIT 256
87
bca47613
DH		 88#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
89
90
1da177e4
LT		 91/*
92 * We default to IRQ0 for the "no irq" hack. Some
93 * machine types want others as well - they're free
94 * to redefine this in their header file.
95 */
96#define is_real_interrupt(irq) ((irq) != 0)
97
1da177e4
LT		 98#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
99#define CONFIG_SERIAL_DETECT_IRQ 1
100#endif
1da177e4
LT		 101#ifdef CONFIG_SERIAL_8250_MANY_PORTS
102#define CONFIG_SERIAL_MANY_PORTS 1
103#endif
104
105/*
106 * HUB6 is always on. This will be removed once the header
107 * files have been cleaned.
108 */
109#define CONFIG_HUB6 1
110
a4ed1e41 111#include <asm/serial.h>
1da177e4
LT		 112/*
113 * SERIAL_PORT_DFNS tells us about built-in ports that have no
114 * standard enumeration mechanism. Platforms that can find all
115 * serial ports via mechanisms like ACPI or PCI need not supply it.
116 */
117#ifndef SERIAL_PORT_DFNS
118#define SERIAL_PORT_DFNS
119#endif
120
cb3592be 121static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 122 SERIAL_PORT_DFNS /* defined in asm/serial.h */
123};
124
026d02a2 125#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 126
127#ifdef CONFIG_SERIAL_8250_RSA
128
129#define PORT_RSA_MAX 4
130static unsigned long probe_rsa[PORT_RSA_MAX];
131static unsigned int probe_rsa_count;
132#endif /* CONFIG_SERIAL_8250_RSA */
133
134struct uart_8250_port {
135 struct uart_port port;
136 struct timer_list timer; /* "no irq" timer */
137 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 138 unsigned short capabilities; /* port capabilities */
139 unsigned short bugs; /* port bugs */
1da177e4 140 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 141 unsigned char acr;
142 unsigned char ier;
143 unsigned char lcr;
144 unsigned char mcr;
145 unsigned char mcr_mask; /* mask of user bits */
146 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 147 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 148
149 /*
150 * Some bits in registers are cleared on a read, so they must
151 * be saved whenever the register is read but the bits will not
152 * be immediately processed.
153 */
154#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
155 unsigned char lsr_saved_flags;
156#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
157 unsigned char msr_saved_flags;
1da177e4
LT		 158};
159
160struct irq_info {
25db8ad5
AC		 161 struct hlist_node node;
162 int irq;
163 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 164 struct list_head *head;
165};
166
25db8ad5
AC		 167#define NR_IRQ_HASH 32 /* Can be adjusted later */
168static struct hlist_head irq_lists[NR_IRQ_HASH];
169static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 170
171/*
172 * Here we define the default xmit fifo size used for each type of UART.
173 */
174static const struct serial8250_config uart_config[] = {
175 [PORT_UNKNOWN] = {
176 .name = "unknown",
177 .fifo_size = 1,
178 .tx_loadsz = 1,
179 },
180 [PORT_8250] = {
181 .name = "8250",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16450] = {
186 .name = "16450",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16550] = {
191 .name = "16550",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550A] = {
196 .name = "16550A",
197 .fifo_size = 16,
198 .tx_loadsz = 16,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO,
201 },
202 [PORT_CIRRUS] = {
203 .name = "Cirrus",
204 .fifo_size = 1,
205 .tx_loadsz = 1,
206 },
207 [PORT_16650] = {
208 .name = "ST16650",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
212 },
213 [PORT_16650V2] = {
214 .name = "ST16650V2",
215 .fifo_size = 32,
216 .tx_loadsz = 16,
217 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
218 UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_16750] = {
222 .name = "TI16750",
223 .fifo_size = 64,
224 .tx_loadsz = 64,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
226 UART_FCR7_64BYTE,
227 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
228 },
229 [PORT_STARTECH] = {
230 .name = "Startech",
231 .fifo_size = 1,
232 .tx_loadsz = 1,
233 },
234 [PORT_16C950] = {
235 .name = "16C950/954",
236 .fifo_size = 128,
237 .tx_loadsz = 128,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
7a56aa45 239 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
1da177e4
LT		 240 },
241 [PORT_16654] = {
242 .name = "ST16654",
243 .fifo_size = 64,
244 .tx_loadsz = 32,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
246 UART_FCR_T_TRIG_10,
247 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
248 },
249 [PORT_16850] = {
250 .name = "XR16850",
251 .fifo_size = 128,
252 .tx_loadsz = 128,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
254 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
255 },
256 [PORT_RSA] = {
257 .name = "RSA",
258 .fifo_size = 2048,
259 .tx_loadsz = 2048,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
261 .flags = UART_CAP_FIFO,
262 },
263 [PORT_NS16550A] = {
264 .name = "NS16550A",
265 .fifo_size = 16,
266 .tx_loadsz = 16,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
268 .flags = UART_CAP_FIFO | UART_NATSEMI,
269 },
270 [PORT_XSCALE] = {
271 .name = "XScale",
272 .fifo_size = 32,
273 .tx_loadsz = 32,
274 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
275 .flags = UART_CAP_FIFO | UART_CAP_UUE,
276 },
bd71c182
TK		 277 [PORT_RM9000] = {
278 .name = "RM9000",
279 .fifo_size = 16,
280 .tx_loadsz = 16,
281 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 282 .flags = UART_CAP_FIFO,
283 },
284 [PORT_OCTEON] = {
285 .name = "OCTEON",
286 .fifo_size = 64,
287 .tx_loadsz = 64,
288 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 289 .flags = UART_CAP_FIFO,
290 },
08e0992f
FF		 291 [PORT_AR7] = {
292 .name = "AR7",
293 .fifo_size = 16,
294 .tx_loadsz = 16,
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
296 .flags = UART_CAP_FIFO | UART_CAP_AFE,
297 },
235dae5d
PL		 298 [PORT_U6_16550A] = {
299 .name = "U6_16550A",
300 .fifo_size = 64,
301 .tx_loadsz = 64,
302 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
303 .flags = UART_CAP_FIFO | UART_CAP_AFE,
304 },
1da177e4
LT		 305};
306
12bf3f24 307#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 308
309/* Au1x00 UART hardware has a weird register layout */
310static const u8 au_io_in_map[] = {
311 [UART_RX] = 0,
312 [UART_IER] = 2,
313 [UART_IIR] = 3,
314 [UART_LCR] = 5,
315 [UART_MCR] = 6,
316 [UART_LSR] = 7,
317 [UART_MSR] = 8,
318};
319
320static const u8 au_io_out_map[] = {
321 [UART_TX] = 1,
322 [UART_IER] = 2,
323 [UART_FCR] = 4,
324 [UART_LCR] = 5,
325 [UART_MCR] = 6,
326};
327
328/* sane hardware needs no mapping */
7d6a07d1 329static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 330{
7d6a07d1 331 if (p->iotype != UPIO_AU)
21c614a7
PA		 332 return offset;
333 return au_io_in_map[offset];
334}
335
7d6a07d1 336static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 337{
7d6a07d1 338 if (p->iotype != UPIO_AU)
21c614a7
PA		 339 return offset;
340 return au_io_out_map[offset];
341}
342
6f803cd0 343#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 344
345static const u8
346 regmap_in[8] = {
347 [UART_RX] = 0x00,
348 [UART_IER] = 0x0c,
349 [UART_IIR] = 0x14,
350 [UART_LCR] = 0x1c,
351 [UART_MCR] = 0x20,
352 [UART_LSR] = 0x24,
353 [UART_MSR] = 0x28,
354 [UART_SCR] = 0x2c
355 },
356 regmap_out[8] = {
357 [UART_TX] = 0x04,
358 [UART_IER] = 0x0c,
359 [UART_FCR] = 0x18,
360 [UART_LCR] = 0x1c,
361 [UART_MCR] = 0x20,
362 [UART_LSR] = 0x24,
363 [UART_MSR] = 0x28,
364 [UART_SCR] = 0x2c
365 };
366
7d6a07d1 367static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 368{
7d6a07d1 369 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 370 return offset;
371 return regmap_in[offset];
372}
373
7d6a07d1 374static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 375{
7d6a07d1 376 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 377 return offset;
378 return regmap_out[offset];
379}
380
21c614a7
PA		 381#else
382
383/* sane hardware needs no mapping */
384#define map_8250_in_reg(up, offset) (offset)
385#define map_8250_out_reg(up, offset) (offset)
386
387#endif
388
7d6a07d1 389static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 390{
7d6a07d1
DD		 391 offset = map_8250_in_reg(p, offset) << p->regshift;
392 outb(p->hub6 - 1 + offset, p->iobase);
393 return inb(p->iobase + 1);
394}
1da177e4 395
7d6a07d1
DD		 396static void hub6_serial_out(struct uart_port *p, int offset, int value)
397{
398 offset = map_8250_out_reg(p, offset) << p->regshift;
399 outb(p->hub6 - 1 + offset, p->iobase);
400 outb(value, p->iobase + 1);
401}
1da177e4 402
7d6a07d1
DD		 403static unsigned int mem_serial_in(struct uart_port *p, int offset)
404{
405 offset = map_8250_in_reg(p, offset) << p->regshift;
406 return readb(p->membase + offset);
407}
1da177e4 408
7d6a07d1
DD		 409static void mem_serial_out(struct uart_port *p, int offset, int value)
410{
411 offset = map_8250_out_reg(p, offset) << p->regshift;
412 writeb(value, p->membase + offset);
413}
414
415static void mem32_serial_out(struct uart_port *p, int offset, int value)
416{
417 offset = map_8250_out_reg(p, offset) << p->regshift;
418 writel(value, p->membase + offset);
419}
420
421static unsigned int mem32_serial_in(struct uart_port *p, int offset)
422{
423 offset = map_8250_in_reg(p, offset) << p->regshift;
424 return readl(p->membase + offset);
425}
1da177e4 426
7d6a07d1
DD		 427static unsigned int au_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return __raw_readl(p->membase + offset);
431}
432
433static void au_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 __raw_writel(value, p->membase + offset);
437}
21c614a7 438
7d6a07d1
DD		 439static unsigned int tsi_serial_in(struct uart_port *p, int offset)
440{
441 unsigned int tmp;
442 offset = map_8250_in_reg(p, offset) << p->regshift;
443 if (offset == UART_IIR) {
444 tmp = readl(p->membase + (UART_IIR & ~3));
445 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
446 } else
447 return readb(p->membase + offset);
448}
3be91ec7 449
7d6a07d1
DD		 450static void tsi_serial_out(struct uart_port *p, int offset, int value)
451{
452 offset = map_8250_out_reg(p, offset) << p->regshift;
453 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
454 writeb(value, p->membase + offset);
1da177e4
LT		 455}
456
7d6a07d1 457static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 458{
beab697a 459 int save_offset = offset;
7d6a07d1
DD		 460 offset = map_8250_out_reg(p, offset) << p->regshift;
461 /* Save the LCR value so it can be re-written when a
462 * Busy Detect interrupt occurs. */
463 if (save_offset == UART_LCR) {
464 struct uart_8250_port *up = (struct uart_8250_port *)p;
465 up->lcr = value;
466 }
467 writeb(value, p->membase + offset);
468 /* Read the IER to ensure any interrupt is cleared before
469 * returning from ISR. */
470 if (save_offset == UART_TX || save_offset == UART_IER)
471 value = p->serial_in(p, UART_IER);
472}
1da177e4 473
7d6a07d1
DD		 474static unsigned int io_serial_in(struct uart_port *p, int offset)
475{
476 offset = map_8250_in_reg(p, offset) << p->regshift;
477 return inb(p->iobase + offset);
478}
479
480static void io_serial_out(struct uart_port *p, int offset, int value)
481{
482 offset = map_8250_out_reg(p, offset) << p->regshift;
483 outb(value, p->iobase + offset);
484}
485
486static void set_io_from_upio(struct uart_port *p)
487{
b8e7e40a 488 struct uart_8250_port *up = (struct uart_8250_port *)p;
7d6a07d1 489 switch (p->iotype) {
1da177e4 490 case UPIO_HUB6:
7d6a07d1
DD		 491 p->serial_in = hub6_serial_in;
492 p->serial_out = hub6_serial_out;
1da177e4
LT		 493 break;
494
495 case UPIO_MEM:
7d6a07d1
DD		 496 p->serial_in = mem_serial_in;
497 p->serial_out = mem_serial_out;
1da177e4
LT		 498 break;
499
bd71c182 500 case UPIO_RM9000:
1da177e4 501 case UPIO_MEM32:
7d6a07d1
DD		 502 p->serial_in = mem32_serial_in;
503 p->serial_out = mem32_serial_out;
1da177e4
LT		 504 break;
505
21c614a7 506 case UPIO_AU:
7d6a07d1
DD		 507 p->serial_in = au_serial_in;
508 p->serial_out = au_serial_out;
21c614a7 509 break;
12bf3f24 510
3be91ec7 511 case UPIO_TSI:
7d6a07d1
DD		 512 p->serial_in = tsi_serial_in;
513 p->serial_out = tsi_serial_out;
3be91ec7 514 break;
21c614a7 515
beab697a 516 case UPIO_DWAPB:
7d6a07d1
DD		 517 p->serial_in = mem_serial_in;
518 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 519 break;
520
1da177e4 521 default:
7d6a07d1
DD		 522 p->serial_in = io_serial_in;
523 p->serial_out = io_serial_out;
524 break;
1da177e4 525 }
b8e7e40a
AC		 526 /* Remember loaded iotype */
527 up->cur_iotype = p->iotype;
1da177e4
LT		 528}
529
40b36daa
AW		 530static void
531serial_out_sync(struct uart_8250_port *up, int offset, int value)
532{
7d6a07d1
DD		 533 struct uart_port *p = &up->port;
534 switch (p->iotype) {
40b36daa
AW		 535 case UPIO_MEM:
536 case UPIO_MEM32:
40b36daa 537 case UPIO_AU:
beab697a 538 case UPIO_DWAPB:
7d6a07d1
DD		 539 p->serial_out(p, offset, value);
540 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 541 break;
542 default:
7d6a07d1 543 p->serial_out(p, offset, value);
40b36daa
AW		 544 }
545}
546
7d6a07d1
DD		 547#define serial_in(up, offset) \
548 (up->port.serial_in(&(up)->port, (offset)))
549#define serial_out(up, offset, value) \
550 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 551/*
552 * We used to support using pause I/O for certain machines. We
553 * haven't supported this for a while, but just in case it's badly
554 * needed for certain old 386 machines, I've left these #define's
555 * in....
556 */
557#define serial_inp(up, offset) serial_in(up, offset)
558#define serial_outp(up, offset, value) serial_out(up, offset, value)
559
b32b19b8
JAH		 560/* Uart divisor latch read */
561static inline int _serial_dl_read(struct uart_8250_port *up)
562{
563 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
564}
565
566/* Uart divisor latch write */
567static inline void _serial_dl_write(struct uart_8250_port *up, int value)
568{
569 serial_outp(up, UART_DLL, value & 0xff);
570 serial_outp(up, UART_DLM, value >> 8 & 0xff);
571}
572
12bf3f24 573#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 574/* Au1x00 haven't got a standard divisor latch */
575static int serial_dl_read(struct uart_8250_port *up)
576{
577 if (up->port.iotype == UPIO_AU)
578 return __raw_readl(up->port.membase + 0x28);
579 else
580 return _serial_dl_read(up);
581}
582
583static void serial_dl_write(struct uart_8250_port *up, int value)
584{
585 if (up->port.iotype == UPIO_AU)
586 __raw_writel(value, up->port.membase + 0x28);
587 else
588 _serial_dl_write(up, value);
589}
6f803cd0 590#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 591static int serial_dl_read(struct uart_8250_port *up)
592{
593 return (up->port.iotype == UPIO_RM9000) ?
594 (((__raw_readl(up->port.membase + 0x10) << 8) |
595 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
596 _serial_dl_read(up);
597}
598
599static void serial_dl_write(struct uart_8250_port *up, int value)
600{
601 if (up->port.iotype == UPIO_RM9000) {
602 __raw_writel(value, up->port.membase + 0x08);
603 __raw_writel(value >> 8, up->port.membase + 0x10);
604 } else {
605 _serial_dl_write(up, value);
606 }
607}
b32b19b8
JAH		 608#else
609#define serial_dl_read(up) _serial_dl_read(up)
610#define serial_dl_write(up, value) _serial_dl_write(up, value)
611#endif
1da177e4
LT		 612
613/*
614 * For the 16C950
615 */
616static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
617{
618 serial_out(up, UART_SCR, offset);
619 serial_out(up, UART_ICR, value);
620}
621
622static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
623{
624 unsigned int value;
625
626 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
627 serial_out(up, UART_SCR, offset);
628 value = serial_in(up, UART_ICR);
629 serial_icr_write(up, UART_ACR, up->acr);
630
631 return value;
632}
633
634/*
635 * FIFO support.
636 */
b5d674ab 637static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 638{
639 if (p->capabilities & UART_CAP_FIFO) {
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
641 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
642 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
643 serial_outp(p, UART_FCR, 0);
644 }
645}
646
647/*
648 * IER sleep support. UARTs which have EFRs need the "extended
649 * capability" bit enabled. Note that on XR16C850s, we need to
650 * reset LCR to write to IER.
651 */
b5d674ab 652static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 653{
654 if (p->capabilities & UART_CAP_SLEEP) {
655 if (p->capabilities & UART_CAP_EFR) {
656 serial_outp(p, UART_LCR, 0xBF);
657 serial_outp(p, UART_EFR, UART_EFR_ECB);
658 serial_outp(p, UART_LCR, 0);
659 }
660 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
661 if (p->capabilities & UART_CAP_EFR) {
662 serial_outp(p, UART_LCR, 0xBF);
663 serial_outp(p, UART_EFR, 0);
664 serial_outp(p, UART_LCR, 0);
665 }
666 }
667}
668
669#ifdef CONFIG_SERIAL_8250_RSA
670/*
671 * Attempts to turn on the RSA FIFO. Returns zero on failure.
672 * We set the port uart clock rate if we succeed.
673 */
674static int __enable_rsa(struct uart_8250_port *up)
675{
676 unsigned char mode;
677 int result;
678
679 mode = serial_inp(up, UART_RSA_MSR);
680 result = mode & UART_RSA_MSR_FIFO;
681
682 if (!result) {
683 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
684 mode = serial_inp(up, UART_RSA_MSR);
685 result = mode & UART_RSA_MSR_FIFO;
686 }
687
688 if (result)
689 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
690
691 return result;
692}
693
694static void enable_rsa(struct uart_8250_port *up)
695{
696 if (up->port.type == PORT_RSA) {
697 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
698 spin_lock_irq(&up->port.lock);
699 __enable_rsa(up);
700 spin_unlock_irq(&up->port.lock);
701 }
702 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
703 serial_outp(up, UART_RSA_FRR, 0);
704 }
705}
706
707/*
708 * Attempts to turn off the RSA FIFO. Returns zero on failure.
709 * It is unknown why interrupts were disabled in here. However,
710 * the caller is expected to preserve this behaviour by grabbing
711 * the spinlock before calling this function.
712 */
713static void disable_rsa(struct uart_8250_port *up)
714{
715 unsigned char mode;
716 int result;
717
718 if (up->port.type == PORT_RSA &&
719 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
720 spin_lock_irq(&up->port.lock);
721
722 mode = serial_inp(up, UART_RSA_MSR);
723 result = !(mode & UART_RSA_MSR_FIFO);
724
725 if (!result) {
726 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
727 mode = serial_inp(up, UART_RSA_MSR);
728 result = !(mode & UART_RSA_MSR_FIFO);
729 }
730
731 if (result)
732 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
733 spin_unlock_irq(&up->port.lock);
734 }
735}
736#endif /* CONFIG_SERIAL_8250_RSA */
737
738/*
739 * This is a quickie test to see how big the FIFO is.
740 * It doesn't work at all the time, more's the pity.
741 */
742static int size_fifo(struct uart_8250_port *up)
743{
b32b19b8
JAH		 744 unsigned char old_fcr, old_mcr, old_lcr;
745 unsigned short old_dl;
1da177e4
LT		 746 int count;
747
748 old_lcr = serial_inp(up, UART_LCR);
749 serial_outp(up, UART_LCR, 0);
750 old_fcr = serial_inp(up, UART_FCR);
751 old_mcr = serial_inp(up, UART_MCR);
752 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
753 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
754 serial_outp(up, UART_MCR, UART_MCR_LOOP);
755 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 756 old_dl = serial_dl_read(up);
757 serial_dl_write(up, 0x0001);
1da177e4
LT		 758 serial_outp(up, UART_LCR, 0x03);
759 for (count = 0; count < 256; count++)
760 serial_outp(up, UART_TX, count);
761 mdelay(20);/* FIXME - schedule_timeout */
762 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
763 (count < 256); count++)
764 serial_inp(up, UART_RX);
765 serial_outp(up, UART_FCR, old_fcr);
766 serial_outp(up, UART_MCR, old_mcr);
767 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 768 serial_dl_write(up, old_dl);
1da177e4
LT		 769 serial_outp(up, UART_LCR, old_lcr);
770
771 return count;
772}
773
774/*
775 * Read UART ID using the divisor method - set DLL and DLM to zero
776 * and the revision will be in DLL and device type in DLM. We
777 * preserve the device state across this.
778 */
779static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
780{
781 unsigned char old_dll, old_dlm, old_lcr;
782 unsigned int id;
783
784 old_lcr = serial_inp(p, UART_LCR);
785 serial_outp(p, UART_LCR, UART_LCR_DLAB);
786
787 old_dll = serial_inp(p, UART_DLL);
788 old_dlm = serial_inp(p, UART_DLM);
789
790 serial_outp(p, UART_DLL, 0);
791 serial_outp(p, UART_DLM, 0);
792
793 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
794
795 serial_outp(p, UART_DLL, old_dll);
796 serial_outp(p, UART_DLM, old_dlm);
797 serial_outp(p, UART_LCR, old_lcr);
798
799 return id;
800}
801
802/*
803 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
804 * When this function is called we know it is at least a StarTech
805 * 16650 V2, but it might be one of several StarTech UARTs, or one of
806 * its clones. (We treat the broken original StarTech 16650 V1 as a
807 * 16550, and why not? Startech doesn't seem to even acknowledge its
808 * existence.)
bd71c182 809 *
1da177e4
LT		 810 * What evil have men's minds wrought...
811 */
812static void autoconfig_has_efr(struct uart_8250_port *up)
813{
814 unsigned int id1, id2, id3, rev;
815
816 /*
817 * Everything with an EFR has SLEEP
818 */
819 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
820
821 /*
822 * First we check to see if it's an Oxford Semiconductor UART.
823 *
824 * If we have to do this here because some non-National
825 * Semiconductor clone chips lock up if you try writing to the
826 * LSR register (which serial_icr_read does)
827 */
828
829 /*
830 * Check for Oxford Semiconductor 16C950.
831 *
832 * EFR [4] must be set else this test fails.
833 *
834 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
835 * claims that it's needed for 952 dual UART's (which are not
836 * recommended for new designs).
837 */
838 up->acr = 0;
839 serial_out(up, UART_LCR, 0xBF);
840 serial_out(up, UART_EFR, UART_EFR_ECB);
841 serial_out(up, UART_LCR, 0x00);
842 id1 = serial_icr_read(up, UART_ID1);
843 id2 = serial_icr_read(up, UART_ID2);
844 id3 = serial_icr_read(up, UART_ID3);
845 rev = serial_icr_read(up, UART_REV);
846
847 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
848
849 if (id1 == 0x16 && id2 == 0xC9 &&
850 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
851 up->port.type = PORT_16C950;
4ba5e35d
RK		 852
853 /*
854 * Enable work around for the Oxford Semiconductor 952 rev B
855 * chip which causes it to seriously miscalculate baud rates
856 * when DLL is 0.
857 */
858 if (id3 == 0x52 && rev == 0x01)
859 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 860 return;
861 }
bd71c182 862
1da177e4
LT		 863 /*
864 * We check for a XR16C850 by setting DLL and DLM to 0, and then
865 * reading back DLL and DLM. The chip type depends on the DLM
866 * value read back:
867 * 0x10 - XR16C850 and the DLL contains the chip revision.
868 * 0x12 - XR16C2850.
869 * 0x14 - XR16C854.
870 */
871 id1 = autoconfig_read_divisor_id(up);
872 DEBUG_AUTOCONF("850id=%04x ", id1);
873
874 id2 = id1 >> 8;
875 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 876 up->port.type = PORT_16850;
877 return;
878 }
879
880 /*
881 * It wasn't an XR16C850.
882 *
883 * We distinguish between the '654 and the '650 by counting
884 * how many bytes are in the FIFO. I'm using this for now,
885 * since that's the technique that was sent to me in the
886 * serial driver update, but I'm not convinced this works.
887 * I've had problems doing this in the past. -TYT
888 */
889 if (size_fifo(up) == 64)
890 up->port.type = PORT_16654;
891 else
892 up->port.type = PORT_16650V2;
893}
894
895/*
896 * We detected a chip without a FIFO. Only two fall into
897 * this category - the original 8250 and the 16450. The
898 * 16450 has a scratch register (accessible with LCR=0)
899 */
900static void autoconfig_8250(struct uart_8250_port *up)
901{
902 unsigned char scratch, status1, status2;
903
904 up->port.type = PORT_8250;
905
906 scratch = serial_in(up, UART_SCR);
907 serial_outp(up, UART_SCR, 0xa5);
908 status1 = serial_in(up, UART_SCR);
909 serial_outp(up, UART_SCR, 0x5a);
910 status2 = serial_in(up, UART_SCR);
911 serial_outp(up, UART_SCR, scratch);
912
913 if (status1 == 0xa5 && status2 == 0x5a)
914 up->port.type = PORT_16450;
915}
916
917static int broken_efr(struct uart_8250_port *up)
918{
919 /*
920 * Exar ST16C2550 "A2" devices incorrectly detect as
921 * having an EFR, and report an ID of 0x0201. See
631dd1a8 922 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1da177e4
LT		 923 */
924 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
925 return 1;
926
927 return 0;
928}
929
930/*
931 * We know that the chip has FIFOs. Does it have an EFR? The
932 * EFR is located in the same register position as the IIR and
933 * we know the top two bits of the IIR are currently set. The
934 * EFR should contain zero. Try to read the EFR.
935 */
936static void autoconfig_16550a(struct uart_8250_port *up)
937{
938 unsigned char status1, status2;
939 unsigned int iersave;
940
941 up->port.type = PORT_16550A;
942 up->capabilities |= UART_CAP_FIFO;
943
944 /*
945 * Check for presence of the EFR when DLAB is set.
946 * Only ST16C650V1 UARTs pass this test.
947 */
948 serial_outp(up, UART_LCR, UART_LCR_DLAB);
949 if (serial_in(up, UART_EFR) == 0) {
950 serial_outp(up, UART_EFR, 0xA8);
951 if (serial_in(up, UART_EFR) != 0) {
952 DEBUG_AUTOCONF("EFRv1 ");
953 up->port.type = PORT_16650;
954 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
955 } else {
956 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
957 }
958 serial_outp(up, UART_EFR, 0);
959 return;
960 }
961
962 /*
963 * Maybe it requires 0xbf to be written to the LCR.
964 * (other ST16C650V2 UARTs, TI16C752A, etc)
965 */
966 serial_outp(up, UART_LCR, 0xBF);
967 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
968 DEBUG_AUTOCONF("EFRv2 ");
969 autoconfig_has_efr(up);
970 return;
971 }
972
973 /*
974 * Check for a National Semiconductor SuperIO chip.
975 * Attempt to switch to bank 2, read the value of the LOOP bit
976 * from EXCR1. Switch back to bank 0, change it in MCR. Then
977 * switch back to bank 2, read it from EXCR1 again and check
978 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 979 */
980 serial_outp(up, UART_LCR, 0);
981 status1 = serial_in(up, UART_MCR);
982 serial_outp(up, UART_LCR, 0xE0);
983 status2 = serial_in(up, 0x02); /* EXCR1 */
984
985 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
986 serial_outp(up, UART_LCR, 0);
987 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
988 serial_outp(up, UART_LCR, 0xE0);
989 status2 = serial_in(up, 0x02); /* EXCR1 */
990 serial_outp(up, UART_LCR, 0);
991 serial_outp(up, UART_MCR, status1);
992
993 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 994 unsigned short quot;
995
1da177e4 996 serial_outp(up, UART_LCR, 0xE0);
857dde2e 997
b32b19b8 998 quot = serial_dl_read(up);
857dde2e
DW		 999 quot <<= 3;
1000
b5b82df6 1001 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 1002 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1003 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1004 serial_outp(up, 0x04, status1);
bd71c182 1005
b32b19b8 1006 serial_dl_write(up, quot);
857dde2e 1007
1da177e4 1008 serial_outp(up, UART_LCR, 0);
1da177e4 1009
857dde2e 1010 up->port.uartclk = 921600*16;
1da177e4
LT		 1011 up->port.type = PORT_NS16550A;
1012 up->capabilities |= UART_NATSEMI;
1013 return;
1014 }
1015 }
1016
1017 /*
1018 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1019 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1020 * Try setting it with and without DLAB set. Cheap clones
1021 * set bit 5 without DLAB set.
1022 */
1023 serial_outp(up, UART_LCR, 0);
1024 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1025 status1 = serial_in(up, UART_IIR) >> 5;
1026 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1027 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1028 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1029 status2 = serial_in(up, UART_IIR) >> 5;
1030 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1031 serial_outp(up, UART_LCR, 0);
1032
1033 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1034
1035 if (status1 == 6 && status2 == 7) {
1036 up->port.type = PORT_16750;
1037 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1038 return;
1039 }
1040
1041 /*
1042 * Try writing and reading the UART_IER_UUE bit (b6).
1043 * If it works, this is probably one of the Xscale platform's
1044 * internal UARTs.
1045 * We're going to explicitly set the UUE bit to 0 before
1046 * trying to write and read a 1 just to make sure it's not
1047 * already a 1 and maybe locked there before we even start start.
1048 */
1049 iersave = serial_in(up, UART_IER);
1050 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1051 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1052 /*
1053 * OK it's in a known zero state, try writing and reading
1054 * without disturbing the current state of the other bits.
1055 */
1056 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1057 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1058 /*
1059 * It's an Xscale.
1060 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1061 */
1062 DEBUG_AUTOCONF("Xscale ");
1063 up->port.type = PORT_XSCALE;
1064 up->capabilities |= UART_CAP_UUE;
1065 return;
1066 }
1067 } else {
1068 /*
1069 * If we got here we couldn't force the IER_UUE bit to 0.
1070 * Log it and continue.
1071 */
1072 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1073 }
1074 serial_outp(up, UART_IER, iersave);
235dae5d
PL		 1075
1076 /*
1077 * We distinguish between 16550A and U6 16550A by counting
1078 * how many bytes are in the FIFO.
1079 */
1080 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1081 up->port.type = PORT_U6_16550A;
1082 up->capabilities |= UART_CAP_AFE;
1083 }
1da177e4
LT		 1084}
1085
1086/*
1087 * This routine is called by rs_init() to initialize a specific serial
1088 * port. It determines what type of UART chip this serial port is
1089 * using: 8250, 16450, 16550, 16550A. The important question is
1090 * whether or not this UART is a 16550A or not, since this will
1091 * determine whether or not we can use its FIFO features or not.
1092 */
1093static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1094{
1095 unsigned char status1, scratch, scratch2, scratch3;
1096 unsigned char save_lcr, save_mcr;
1097 unsigned long flags;
1098
1099 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1100 return;
1101
80647b95 1102 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1103 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1104
1105 /*
1106 * We really do need global IRQs disabled here - we're going to
1107 * be frobbing the chips IRQ enable register to see if it exists.
1108 */
1109 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1110
1111 up->capabilities = 0;
4ba5e35d 1112 up->bugs = 0;
1da177e4
LT		 1113
1114 if (!(up->port.flags & UPF_BUGGY_UART)) {
1115 /*
1116 * Do a simple existence test first; if we fail this,
1117 * there's no point trying anything else.
bd71c182 1118 *
1da177e4
LT		 1119 * 0x80 is used as a nonsense port to prevent against
1120 * false positives due to ISA bus float. The
1121 * assumption is that 0x80 is a non-existent port;
1122 * which should be safe since include/asm/io.h also
1123 * makes this assumption.
1124 *
1125 * Note: this is safe as long as MCR bit 4 is clear
1126 * and the device is in "PC" mode.
1127 */
1128 scratch = serial_inp(up, UART_IER);
1129 serial_outp(up, UART_IER, 0);
1130#ifdef __i386__
1131 outb(0xff, 0x080);
1132#endif
48212008
TH		 1133 /*
1134 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1135 * 16C754B) allow only to modify them if an EFR bit is set.
1136 */
1137 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1138 serial_outp(up, UART_IER, 0x0F);
1139#ifdef __i386__
1140 outb(0, 0x080);
1141#endif
48212008 1142 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1143 serial_outp(up, UART_IER, scratch);
1144 if (scratch2 != 0 || scratch3 != 0x0F) {
1145 /*
1146 * We failed; there's nothing here
1147 */
1148 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1149 scratch2, scratch3);
1150 goto out;
1151 }
1152 }
1153
1154 save_mcr = serial_in(up, UART_MCR);
1155 save_lcr = serial_in(up, UART_LCR);
1156
bd71c182 1157 /*
1da177e4
LT		 1158 * Check to see if a UART is really there. Certain broken
1159 * internal modems based on the Rockwell chipset fail this
1160 * test, because they apparently don't implement the loopback
1161 * test mode. So this test is skipped on the COM 1 through
1162 * COM 4 ports. This *should* be safe, since no board
1163 * manufacturer would be stupid enough to design a board
1164 * that conflicts with COM 1-4 --- we hope!
1165 */
1166 if (!(up->port.flags & UPF_SKIP_TEST)) {
1167 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1168 status1 = serial_inp(up, UART_MSR) & 0xF0;
1169 serial_outp(up, UART_MCR, save_mcr);
1170 if (status1 != 0x90) {
1171 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1172 status1);
1173 goto out;
1174 }
1175 }
1176
1177 /*
1178 * We're pretty sure there's a port here. Lets find out what
1179 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1180 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1181 * determines what we test for next.
1182 *
1183 * We also initialise the EFR (if any) to zero for later. The
1184 * EFR occupies the same register location as the FCR and IIR.
1185 */
1186 serial_outp(up, UART_LCR, 0xBF);
1187 serial_outp(up, UART_EFR, 0);
1188 serial_outp(up, UART_LCR, 0);
1189
1190 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1191 scratch = serial_in(up, UART_IIR) >> 6;
1192
1193 DEBUG_AUTOCONF("iir=%d ", scratch);
1194
1195 switch (scratch) {
1196 case 0:
1197 autoconfig_8250(up);
1198 break;
1199 case 1:
1200 up->port.type = PORT_UNKNOWN;
1201 break;
1202 case 2:
1203 up->port.type = PORT_16550;
1204 break;
1205 case 3:
1206 autoconfig_16550a(up);
1207 break;
1208 }
1209
1210#ifdef CONFIG_SERIAL_8250_RSA
1211 /*
1212 * Only probe for RSA ports if we got the region.
1213 */
1214 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1215 int i;
1216
1217 for (i = 0 ; i < probe_rsa_count; ++i) {
1218 if (probe_rsa[i] == up->port.iobase &&
1219 __enable_rsa(up)) {
1220 up->port.type = PORT_RSA;
1221 break;
1222 }
1223 }
1224 }
1225#endif
21c614a7 1226
1da177e4
LT		 1227 serial_outp(up, UART_LCR, save_lcr);
1228
1229 if (up->capabilities != uart_config[up->port.type].flags) {
1230 printk(KERN_WARNING
1231 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1232 serial_index(&up->port), up->capabilities,
1233 uart_config[up->port.type].flags);
1da177e4
LT		 1234 }
1235
1236 up->port.fifosize = uart_config[up->port.type].fifo_size;
1237 up->capabilities = uart_config[up->port.type].flags;
1238 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1239
1240 if (up->port.type == PORT_UNKNOWN)
1241 goto out;
1242
1243 /*
1244 * Reset the UART.
1245 */
1246#ifdef CONFIG_SERIAL_8250_RSA
1247 if (up->port.type == PORT_RSA)
1248 serial_outp(up, UART_RSA_FRR, 0);
1249#endif
1250 serial_outp(up, UART_MCR, save_mcr);
1251 serial8250_clear_fifos(up);
40b36daa 1252 serial_in(up, UART_RX);
5c8c755c
LB		 1253 if (up->capabilities & UART_CAP_UUE)
1254 serial_outp(up, UART_IER, UART_IER_UUE);
1255 else
1256 serial_outp(up, UART_IER, 0);
1da177e4 1257
bd71c182 1258 out:
1da177e4 1259 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1260 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1261}
1262
1263static void autoconfig_irq(struct uart_8250_port *up)
1264{
1265 unsigned char save_mcr, save_ier;
1266 unsigned char save_ICP = 0;
1267 unsigned int ICP = 0;
1268 unsigned long irqs;
1269 int irq;
1270
1271 if (up->port.flags & UPF_FOURPORT) {
1272 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1273 save_ICP = inb_p(ICP);
1274 outb_p(0x80, ICP);
1275 (void) inb_p(ICP);
1276 }
1277
1278 /* forget possible initially masked and pending IRQ */
1279 probe_irq_off(probe_irq_on());
1280 save_mcr = serial_inp(up, UART_MCR);
1281 save_ier = serial_inp(up, UART_IER);
1282 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1283
1da177e4
LT		 1284 irqs = probe_irq_on();
1285 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1286 udelay(10);
1287 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1288 serial_outp(up, UART_MCR,
1289 UART_MCR_DTR | UART_MCR_RTS);
1290 } else {
1291 serial_outp(up, UART_MCR,
1292 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1293 }
1294 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1295 (void)serial_inp(up, UART_LSR);
1296 (void)serial_inp(up, UART_RX);
1297 (void)serial_inp(up, UART_IIR);
1298 (void)serial_inp(up, UART_MSR);
1299 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1300 udelay(20);
1da177e4
LT		 1301 irq = probe_irq_off(irqs);
1302
1303 serial_outp(up, UART_MCR, save_mcr);
1304 serial_outp(up, UART_IER, save_ier);
1305
1306 if (up->port.flags & UPF_FOURPORT)
1307 outb_p(save_ICP, ICP);
1308
1309 up->port.irq = (irq > 0) ? irq : 0;
1310}
1311
e763b90c
RK		 1312static inline void __stop_tx(struct uart_8250_port *p)
1313{
1314 if (p->ier & UART_IER_THRI) {
1315 p->ier &= ~UART_IER_THRI;
1316 serial_out(p, UART_IER, p->ier);
1317 }
1318}
1319
b129a8cc 1320static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1321{
1322 struct uart_8250_port *up = (struct uart_8250_port *)port;
1323
e763b90c 1324 __stop_tx(up);
1da177e4
LT		 1325
1326 /*
e763b90c 1327 * We really want to stop the transmitter from sending.
1da177e4 1328 */
e763b90c 1329 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1330 up->acr |= UART_ACR_TXDIS;
1331 serial_icr_write(up, UART_ACR, up->acr);
1332 }
1333}
1334
55d3b282
RK		 1335static void transmit_chars(struct uart_8250_port *up);
1336
b129a8cc 1337static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1338{
1339 struct uart_8250_port *up = (struct uart_8250_port *)port;
1340
1341 if (!(up->ier & UART_IER_THRI)) {
1342 up->ier |= UART_IER_THRI;
1343 serial_out(up, UART_IER, up->ier);
55d3b282 1344
67f7654e 1345 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1346 unsigned char lsr;
55d3b282 1347 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1348 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1349 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1350 (lsr & UART_LSR_THRE) :
1351 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1352 transmit_chars(up);
1353 }
1da177e4 1354 }
e763b90c 1355
1da177e4 1356 /*
e763b90c 1357 * Re-enable the transmitter if we disabled it.
1da177e4 1358 */
e763b90c 1359 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1360 up->acr &= ~UART_ACR_TXDIS;
1361 serial_icr_write(up, UART_ACR, up->acr);
1362 }
1363}
1364
1365static void serial8250_stop_rx(struct uart_port *port)
1366{
1367 struct uart_8250_port *up = (struct uart_8250_port *)port;
1368
1369 up->ier &= ~UART_IER_RLSI;
1370 up->port.read_status_mask &= ~UART_LSR_DR;
1371 serial_out(up, UART_IER, up->ier);
1372}
1373
1374static void serial8250_enable_ms(struct uart_port *port)
1375{
1376 struct uart_8250_port *up = (struct uart_8250_port *)port;
1377
21c614a7
PA		 1378 /* no MSR capabilities */
1379 if (up->bugs & UART_BUG_NOMSR)
1380 return;
1381
1da177e4
LT		 1382 up->ier |= UART_IER_MSI;
1383 serial_out(up, UART_IER, up->ier);
1384}
1385
ea8874dc 1386static void
cc79aa9d 1387receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1388{
ebd2c8f6 1389 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1390 unsigned char ch, lsr = *status;
1391 int max_count = 256;
1392 char flag;
1393
1394 do {
7500b1f6
AR		 1395 if (likely(lsr & UART_LSR_DR))
1396 ch = serial_inp(up, UART_RX);
1397 else
1398 /*
1399 * Intel 82571 has a Serial Over Lan device that will
1400 * set UART_LSR_BI without setting UART_LSR_DR when
1401 * it receives a break. To avoid reading from the
1402 * receive buffer without UART_LSR_DR bit set, we
1403 * just force the read character to be 0
1404 */
1405 ch = 0;
1406
1da177e4
LT		 1407 flag = TTY_NORMAL;
1408 up->port.icount.rx++;
1409
ad4c2aa6
CM		 1410 lsr |= up->lsr_saved_flags;
1411 up->lsr_saved_flags = 0;
1da177e4 1412
ad4c2aa6 1413 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1414 /*
1415 * For statistics only
1416 */
1417 if (lsr & UART_LSR_BI) {
1418 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1419 up->port.icount.brk++;
1420 /*
1421 * We do the SysRQ and SAK checking
1422 * here because otherwise the break
1423 * may get masked by ignore_status_mask
1424 * or read_status_mask.
1425 */
1426 if (uart_handle_break(&up->port))
1427 goto ignore_char;
1428 } else if (lsr & UART_LSR_PE)
1429 up->port.icount.parity++;
1430 else if (lsr & UART_LSR_FE)
1431 up->port.icount.frame++;
1432 if (lsr & UART_LSR_OE)
1433 up->port.icount.overrun++;
1434
1435 /*
23907eb8 1436 * Mask off conditions which should be ignored.
1da177e4
LT		 1437 */
1438 lsr &= up->port.read_status_mask;
1439
1440 if (lsr & UART_LSR_BI) {
1441 DEBUG_INTR("handling break....");
1442 flag = TTY_BREAK;
1443 } else if (lsr & UART_LSR_PE)
1444 flag = TTY_PARITY;
1445 else if (lsr & UART_LSR_FE)
1446 flag = TTY_FRAME;
1447 }
7d12e780 1448 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1449 goto ignore_char;
05ab3014
RK		 1450
1451 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1452
6f803cd0 1453ignore_char:
1da177e4 1454 lsr = serial_inp(up, UART_LSR);
7500b1f6 1455 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1456 spin_unlock(&up->port.lock);
1457 tty_flip_buffer_push(tty);
1458 spin_lock(&up->port.lock);
1459 *status = lsr;
1460}
1461
ea8874dc 1462static void transmit_chars(struct uart_8250_port *up)
1da177e4 1463{
ebd2c8f6 1464 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1465 int count;
1466
1467 if (up->port.x_char) {
1468 serial_outp(up, UART_TX, up->port.x_char);
1469 up->port.icount.tx++;
1470 up->port.x_char = 0;
1471 return;
1472 }
b129a8cc
RK		 1473 if (uart_tx_stopped(&up->port)) {
1474 serial8250_stop_tx(&up->port);
1475 return;
1476 }
1477 if (uart_circ_empty(xmit)) {
e763b90c 1478 __stop_tx(up);
1da177e4
LT		 1479 return;
1480 }
1481
1482 count = up->tx_loadsz;
1483 do {
1484 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1485 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1486 up->port.icount.tx++;
1487 if (uart_circ_empty(xmit))
1488 break;
1489 } while (--count > 0);
1490
1491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1492 uart_write_wakeup(&up->port);
1493
1494 DEBUG_INTR("THRE...");
1495
1496 if (uart_circ_empty(xmit))
e763b90c 1497 __stop_tx(up);
1da177e4
LT		 1498}
1499
2af7cd68 1500static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1501{
2af7cd68
RK		 1502 unsigned int status = serial_in(up, UART_MSR);
1503
ad4c2aa6
CM		 1504 status |= up->msr_saved_flags;
1505 up->msr_saved_flags = 0;
fdc30b3d 1506 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1507 up->port.state != NULL) {
2af7cd68
RK		 1508 if (status & UART_MSR_TERI)
1509 up->port.icount.rng++;
1510 if (status & UART_MSR_DDSR)
1511 up->port.icount.dsr++;
1512 if (status & UART_MSR_DDCD)
1513 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1514 if (status & UART_MSR_DCTS)
1515 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1516
bdc04e31 1517 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1518 }
1da177e4 1519
2af7cd68 1520 return status;
1da177e4
LT		 1521}
1522
1523/*
1524 * This handles the interrupt from one port.
1525 */
b5d674ab 1526static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1527{
45e24601 1528 unsigned int status;
4bf3631c 1529 unsigned long flags;
45e24601 1530
4bf3631c 1531 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1532
1533 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1534
1535 DEBUG_INTR("status = %x...", status);
1536
7500b1f6 1537 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1538 receive_chars(up, &status);
1da177e4
LT		 1539 check_modem_status(up);
1540 if (status & UART_LSR_THRE)
1541 transmit_chars(up);
45e24601 1542
4bf3631c 1543 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1544}
1545
1546/*
1547 * This is the serial driver's interrupt routine.
1548 *
1549 * Arjan thinks the old way was overly complex, so it got simplified.
1550 * Alan disagrees, saying that need the complexity to handle the weird
1551 * nature of ISA shared interrupts. (This is a special exception.)
1552 *
1553 * In order to handle ISA shared interrupts properly, we need to check
1554 * that all ports have been serviced, and therefore the ISA interrupt
1555 * line has been de-asserted.
1556 *
1557 * This means we need to loop through all ports. checking that they
1558 * don't have an interrupt pending.
1559 */
7d12e780 1560static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1561{
1562 struct irq_info *i = dev_id;
1563 struct list_head *l, *end = NULL;
1564 int pass_counter = 0, handled = 0;
1565
1566 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1567
1568 spin_lock(&i->lock);
1569
1570 l = i->head;
1571 do {
1572 struct uart_8250_port *up;
1573 unsigned int iir;
1574
1575 up = list_entry(l, struct uart_8250_port, list);
1576
1577 iir = serial_in(up, UART_IIR);
1578 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1579 serial8250_handle_port(up);
1da177e4
LT		 1580
1581 handled = 1;
1582
beab697a
MSJ		 1583 end = NULL;
1584 } else if (up->port.iotype == UPIO_DWAPB &&
1585 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1586 /* The DesignWare APB UART has an Busy Detect (0x07)
1587 * interrupt meaning an LCR write attempt occured while the
1588 * UART was busy. The interrupt must be cleared by reading
1589 * the UART status register (USR) and the LCR re-written. */
1590 unsigned int status;
1591 status = *(volatile u32 *)up->port.private_data;
1592 serial_out(up, UART_LCR, up->lcr);
1593
1594 handled = 1;
1595
1da177e4
LT		 1596 end = NULL;
1597 } else if (end == NULL)
1598 end = l;
1599
1600 l = l->next;
1601
1602 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1603 /* If we hit this, we're dead. */
cd3ecad1
DD		 1604 printk_ratelimited(KERN_ERR
1605 "serial8250: too much work for irq%d\n", irq);
1da177e4
LT		 1606 break;
1607 }
1608 } while (l != end);
1609
1610 spin_unlock(&i->lock);
1611
1612 DEBUG_INTR("end.\n");
1613
1614 return IRQ_RETVAL(handled);
1615}
1616
1617/*
1618 * To support ISA shared interrupts, we need to have one interrupt
1619 * handler that ensures that the IRQ line has been deasserted
1620 * before returning. Failing to do this will result in the IRQ
1621 * line being stuck active, and, since ISA irqs are edge triggered,
1622 * no more IRQs will be seen.
1623 */
1624static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1625{
1626 spin_lock_irq(&i->lock);
1627
1628 if (!list_empty(i->head)) {
1629 if (i->head == &up->list)
1630 i->head = i->head->next;
1631 list_del(&up->list);
1632 } else {
1633 BUG_ON(i->head != &up->list);
1634 i->head = NULL;
1635 }
1da177e4 1636 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1637 /* List empty so throw away the hash node */
1638 if (i->head == NULL) {
1639 hlist_del(&i->node);
1640 kfree(i);
1641 }
1da177e4
LT		 1642}
1643
1644static int serial_link_irq_chain(struct uart_8250_port *up)
1645{
25db8ad5
AC		 1646 struct hlist_head *h;
1647 struct hlist_node *n;
1648 struct irq_info *i;
40663cc7 1649 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1650
25db8ad5
AC		 1651 mutex_lock(&hash_mutex);
1652
1653 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1654
1655 hlist_for_each(n, h) {
1656 i = hlist_entry(n, struct irq_info, node);
1657 if (i->irq == up->port.irq)
1658 break;
1659 }
1660
1661 if (n == NULL) {
1662 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1663 if (i == NULL) {
1664 mutex_unlock(&hash_mutex);
1665 return -ENOMEM;
1666 }
1667 spin_lock_init(&i->lock);
1668 i->irq = up->port.irq;
1669 hlist_add_head(&i->node, h);
1670 }
1671 mutex_unlock(&hash_mutex);
1672
1da177e4
LT		 1673 spin_lock_irq(&i->lock);
1674
1675 if (i->head) {
1676 list_add(&up->list, i->head);
1677 spin_unlock_irq(&i->lock);
1678
1679 ret = 0;
1680 } else {
1681 INIT_LIST_HEAD(&up->list);
1682 i->head = &up->list;
1683 spin_unlock_irq(&i->lock);
1c2f0493 1684 irq_flags |= up->port.irqflags;
1da177e4
LT		 1685 ret = request_irq(up->port.irq, serial8250_interrupt,
1686 irq_flags, "serial", i);
1687 if (ret < 0)
1688 serial_do_unlink(i, up);
1689 }
1690
1691 return ret;
1692}
1693
1694static void serial_unlink_irq_chain(struct uart_8250_port *up)
1695{
25db8ad5
AC		 1696 struct irq_info *i;
1697 struct hlist_node *n;
1698 struct hlist_head *h;
1da177e4 1699
25db8ad5
AC		 1700 mutex_lock(&hash_mutex);
1701
1702 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1703
1704 hlist_for_each(n, h) {
1705 i = hlist_entry(n, struct irq_info, node);
1706 if (i->irq == up->port.irq)
1707 break;
1708 }
1709
1710 BUG_ON(n == NULL);
1da177e4
LT		 1711 BUG_ON(i->head == NULL);
1712
1713 if (list_empty(i->head))
1714 free_irq(up->port.irq, i);
1715
1716 serial_do_unlink(i, up);
25db8ad5 1717 mutex_unlock(&hash_mutex);
1da177e4
LT		 1718}
1719
1720/*
1721 * This function is used to handle ports that do not have an
1722 * interrupt. This doesn't work very well for 16450's, but gives
1723 * barely passable results for a 16550A. (Although at the expense
1724 * of much CPU overhead).
1725 */
1726static void serial8250_timeout(unsigned long data)
1727{
1728 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1729 unsigned int iir;
1730
1731 iir = serial_in(up, UART_IIR);
45e24601 1732 if (!(iir & UART_IIR_NO_INT))
7d12e780 1733 serial8250_handle_port(up);
54381067 1734 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
40b36daa
AW		 1735}
1736
1737static void serial8250_backup_timeout(unsigned long data)
1738{
1739 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1740 unsigned int iir, ier = 0, lsr;
1741 unsigned long flags;
40b36daa
AW		 1742
1743 /*
1744 * Must disable interrupts or else we risk racing with the interrupt
1745 * based handler.
1746 */
1747 if (is_real_interrupt(up->port.irq)) {
1748 ier = serial_in(up, UART_IER);
1749 serial_out(up, UART_IER, 0);
1750 }
1da177e4 1751
40b36daa
AW		 1752 iir = serial_in(up, UART_IIR);
1753
1754 /*
1755 * This should be a safe test for anyone who doesn't trust the
1756 * IIR bits on their UART, but it's specifically designed for
1757 * the "Diva" UART used on the management processor on many HP
1758 * ia64 and parisc boxes.
1759 */
ad4c2aa6
CM		 1760 spin_lock_irqsave(&up->port.lock, flags);
1761 lsr = serial_in(up, UART_LSR);
1762 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1763 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1764 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1765 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1766 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1767 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1768 iir |= UART_IIR_THRI;
1769 }
1770
1771 if (!(iir & UART_IIR_NO_INT))
1772 serial8250_handle_port(up);
1773
1774 if (is_real_interrupt(up->port.irq))
1775 serial_out(up, UART_IER, ier);
1776
1777 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0 1778 mod_timer(&up->timer,
54381067 1779 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1da177e4
LT		 1780}
1781
1782static unsigned int serial8250_tx_empty(struct uart_port *port)
1783{
1784 struct uart_8250_port *up = (struct uart_8250_port *)port;
1785 unsigned long flags;
ad4c2aa6 1786 unsigned int lsr;
1da177e4
LT		 1787
1788 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1789 lsr = serial_in(up, UART_LSR);
1790 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1791 spin_unlock_irqrestore(&up->port.lock, flags);
1792
bca47613 1793 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1794}
1795
1796static unsigned int serial8250_get_mctrl(struct uart_port *port)
1797{
1798 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1799 unsigned int status;
1da177e4
LT		 1800 unsigned int ret;
1801
2af7cd68 1802 status = check_modem_status(up);
1da177e4
LT		 1803
1804 ret = 0;
1805 if (status & UART_MSR_DCD)
1806 ret |= TIOCM_CAR;
1807 if (status & UART_MSR_RI)
1808 ret |= TIOCM_RNG;
1809 if (status & UART_MSR_DSR)
1810 ret |= TIOCM_DSR;
1811 if (status & UART_MSR_CTS)
1812 ret |= TIOCM_CTS;
1813 return ret;
1814}
1815
1816static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1817{
1818 struct uart_8250_port *up = (struct uart_8250_port *)port;
1819 unsigned char mcr = 0;
1820
1821 if (mctrl & TIOCM_RTS)
1822 mcr |= UART_MCR_RTS;
1823 if (mctrl & TIOCM_DTR)
1824 mcr |= UART_MCR_DTR;
1825 if (mctrl & TIOCM_OUT1)
1826 mcr |= UART_MCR_OUT1;
1827 if (mctrl & TIOCM_OUT2)
1828 mcr |= UART_MCR_OUT2;
1829 if (mctrl & TIOCM_LOOP)
1830 mcr |= UART_MCR_LOOP;
1831
1832 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1833
1834 serial_out(up, UART_MCR, mcr);
1835}
1836
1837static void serial8250_break_ctl(struct uart_port *port, int break_state)
1838{
1839 struct uart_8250_port *up = (struct uart_8250_port *)port;
1840 unsigned long flags;
1841
1842 spin_lock_irqsave(&up->port.lock, flags);
1843 if (break_state == -1)
1844 up->lcr |= UART_LCR_SBC;
1845 else
1846 up->lcr &= ~UART_LCR_SBC;
1847 serial_out(up, UART_LCR, up->lcr);
1848 spin_unlock_irqrestore(&up->port.lock, flags);
1849}
1850
40b36daa
AW		 1851/*
1852 * Wait for transmitter & holding register to empty
1853 */
b5d674ab 1854static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1855{
1856 unsigned int status, tmout = 10000;
1857
1858 /* Wait up to 10ms for the character(s) to be sent. */
97d303b7 1859 for (;;) {
40b36daa
AW		 1860 status = serial_in(up, UART_LSR);
1861
ad4c2aa6 1862 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa 1863
97d303b7
DD		 1864 if ((status & bits) == bits)
1865 break;
40b36daa
AW		 1866 if (--tmout == 0)
1867 break;
1868 udelay(1);
97d303b7 1869 }
40b36daa
AW		 1870
1871 /* Wait up to 1s for flow control if necessary */
1872 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1873 unsigned int tmout;
1874 for (tmout = 1000000; tmout; tmout--) {
1875 unsigned int msr = serial_in(up, UART_MSR);
1876 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1877 if (msr & UART_MSR_CTS)
1878 break;
40b36daa
AW		 1879 udelay(1);
1880 touch_nmi_watchdog();
1881 }
1882 }
1883}
1884
f2d937f3
JW		 1885#ifdef CONFIG_CONSOLE_POLL
1886/*
1887 * Console polling routines for writing and reading from the uart while
1888 * in an interrupt or debug context.
1889 */
1890
1891static int serial8250_get_poll_char(struct uart_port *port)
1892{
1893 struct uart_8250_port *up = (struct uart_8250_port *)port;
1894 unsigned char lsr = serial_inp(up, UART_LSR);
1895
f5316b4a
JW		 1896 if (!(lsr & UART_LSR_DR))
1897 return NO_POLL_CHAR;
f2d937f3
JW		 1898
1899 return serial_inp(up, UART_RX);
1900}
1901
1902
1903static void serial8250_put_poll_char(struct uart_port *port,
1904 unsigned char c)
1905{
1906 unsigned int ier;
1907 struct uart_8250_port *up = (struct uart_8250_port *)port;
1908
1909 /*
1910 * First save the IER then disable the interrupts
1911 */
1912 ier = serial_in(up, UART_IER);
1913 if (up->capabilities & UART_CAP_UUE)
1914 serial_out(up, UART_IER, UART_IER_UUE);
1915 else
1916 serial_out(up, UART_IER, 0);
1917
1918 wait_for_xmitr(up, BOTH_EMPTY);
1919 /*
1920 * Send the character out.
1921 * If a LF, also do CR...
1922 */
1923 serial_out(up, UART_TX, c);
1924 if (c == 10) {
1925 wait_for_xmitr(up, BOTH_EMPTY);
1926 serial_out(up, UART_TX, 13);
1927 }
1928
1929 /*
1930 * Finally, wait for transmitter to become empty
1931 * and restore the IER
1932 */
1933 wait_for_xmitr(up, BOTH_EMPTY);
1934 serial_out(up, UART_IER, ier);
1935}
1936
1937#endif /* CONFIG_CONSOLE_POLL */
1938
1da177e4
LT		 1939static int serial8250_startup(struct uart_port *port)
1940{
1941 struct uart_8250_port *up = (struct uart_8250_port *)port;
1942 unsigned long flags;
55d3b282 1943 unsigned char lsr, iir;
1da177e4
LT		 1944 int retval;
1945
1946 up->capabilities = uart_config[up->port.type].flags;
1947 up->mcr = 0;
1948
b8e7e40a
AC		 1949 if (up->port.iotype != up->cur_iotype)
1950 set_io_from_upio(port);
1951
1da177e4
LT		 1952 if (up->port.type == PORT_16C950) {
1953 /* Wake up and initialize UART */
1954 up->acr = 0;
1955 serial_outp(up, UART_LCR, 0xBF);
1956 serial_outp(up, UART_EFR, UART_EFR_ECB);
1957 serial_outp(up, UART_IER, 0);
1958 serial_outp(up, UART_LCR, 0);
1959 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1960 serial_outp(up, UART_LCR, 0xBF);
1961 serial_outp(up, UART_EFR, UART_EFR_ECB);
1962 serial_outp(up, UART_LCR, 0);
1963 }
1964
1965#ifdef CONFIG_SERIAL_8250_RSA
1966 /*
1967 * If this is an RSA port, see if we can kick it up to the
1968 * higher speed clock.
1969 */
1970 enable_rsa(up);
1971#endif
1972
1973 /*
1974 * Clear the FIFO buffers and disable them.
7f927fcc 1975 * (they will be reenabled in set_termios())
1da177e4
LT		 1976 */
1977 serial8250_clear_fifos(up);
1978
1979 /*
1980 * Clear the interrupt registers.
1981 */
1982 (void) serial_inp(up, UART_LSR);
1983 (void) serial_inp(up, UART_RX);
1984 (void) serial_inp(up, UART_IIR);
1985 (void) serial_inp(up, UART_MSR);
1986
1987 /*
1988 * At this point, there's no way the LSR could still be 0xff;
1989 * if it is, then bail out, because there's likely no UART
1990 * here.
1991 */
1992 if (!(up->port.flags & UPF_BUGGY_UART) &&
1993 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 1994 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1995 serial_index(&up->port));
1da177e4
LT		 1996 return -ENODEV;
1997 }
1998
1999 /*
2000 * For a XR16C850, we need to set the trigger levels
2001 */
2002 if (up->port.type == PORT_16850) {
2003 unsigned char fctr;
2004
2005 serial_outp(up, UART_LCR, 0xbf);
2006
2007 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2008 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2009 serial_outp(up, UART_TRG, UART_TRG_96);
2010 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2011 serial_outp(up, UART_TRG, UART_TRG_96);
2012
2013 serial_outp(up, UART_LCR, 0);
2014 }
2015
40b36daa 2016 if (is_real_interrupt(up->port.irq)) {
01c194d9 2017 unsigned char iir1;
40b36daa
AW		 2018 /*
2019 * Test for UARTs that do not reassert THRE when the
2020 * transmitter is idle and the interrupt has already
2021 * been cleared. Real 16550s should always reassert
2022 * this interrupt whenever the transmitter is idle and
2023 * the interrupt is enabled. Delays are necessary to
2024 * allow register changes to become visible.
2025 */
c389d27b 2026 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2027 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2028 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2029
2030 wait_for_xmitr(up, UART_LSR_THRE);
2031 serial_out_sync(up, UART_IER, UART_IER_THRI);
2032 udelay(1); /* allow THRE to set */
01c194d9 2033 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2034 serial_out(up, UART_IER, 0);
2035 serial_out_sync(up, UART_IER, UART_IER_THRI);
2036 udelay(1); /* allow a working UART time to re-assert THRE */
2037 iir = serial_in(up, UART_IIR);
2038 serial_out(up, UART_IER, 0);
2039
1c2f0493 2040 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2041 enable_irq(up->port.irq);
c389d27b 2042 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2043
2044 /*
2045 * If the interrupt is not reasserted, setup a timer to
2046 * kick the UART on a regular basis.
2047 */
01c194d9 2048 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2049 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2050 pr_debug("ttyS%d - using backup timer\n",
2051 serial_index(port));
40b36daa
AW		 2052 }
2053 }
2054
363f66fe
WN		 2055 /*
2056 * The above check will only give an accurate result the first time
2057 * the port is opened so this value needs to be preserved.
2058 */
2059 if (up->bugs & UART_BUG_THRE) {
2060 up->timer.function = serial8250_backup_timeout;
2061 up->timer.data = (unsigned long)up;
2062 mod_timer(&up->timer, jiffies +
54381067 2063 uart_poll_timeout(port) + HZ / 5);
363f66fe
WN		 2064 }
2065
1da177e4
LT		 2066 /*
2067 * If the "interrupt" for this port doesn't correspond with any
2068 * hardware interrupt, we use a timer-based system. The original
2069 * driver used to do this with IRQ0.
2070 */
2071 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2072 up->timer.data = (unsigned long)up;
54381067 2073 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
1da177e4
LT		 2074 } else {
2075 retval = serial_link_irq_chain(up);
2076 if (retval)
2077 return retval;
2078 }
2079
2080 /*
2081 * Now, initialize the UART
2082 */
2083 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2084
2085 spin_lock_irqsave(&up->port.lock, flags);
2086 if (up->port.flags & UPF_FOURPORT) {
2087 if (!is_real_interrupt(up->port.irq))
2088 up->port.mctrl |= TIOCM_OUT1;
2089 } else
2090 /*
2091 * Most PC uarts need OUT2 raised to enable interrupts.
2092 */
2093 if (is_real_interrupt(up->port.irq))
2094 up->port.mctrl |= TIOCM_OUT2;
2095
2096 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2097
b6adea33
MCC		 2098 /* Serial over Lan (SoL) hack:
2099 Intel 8257x Gigabit ethernet chips have a
2100 16550 emulation, to be used for Serial Over Lan.
2101 Those chips take a longer time than a normal
2102 serial device to signalize that a transmission
2103 data was queued. Due to that, the above test generally
2104 fails. One solution would be to delay the reading of
2105 iir. However, this is not reliable, since the timeout
2106 is variable. So, let's just don't test if we receive
2107 TX irq. This way, we'll never enable UART_BUG_TXEN.
2108 */
d41a4b51 2109 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2110 goto dont_test_tx_en;
2111
55d3b282
RK		 2112 /*
2113 * Do a quick test to see if we receive an
2114 * interrupt when we enable the TX irq.
2115 */
2116 serial_outp(up, UART_IER, UART_IER_THRI);
2117 lsr = serial_in(up, UART_LSR);
2118 iir = serial_in(up, UART_IIR);
2119 serial_outp(up, UART_IER, 0);
2120
2121 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2122 if (!(up->bugs & UART_BUG_TXEN)) {
2123 up->bugs |= UART_BUG_TXEN;
55d3b282 2124 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2125 serial_index(port));
55d3b282
RK		 2126 }
2127 } else {
67f7654e 2128 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2129 }
2130
b6adea33 2131dont_test_tx_en:
1da177e4
LT		 2132 spin_unlock_irqrestore(&up->port.lock, flags);
2133
ad4c2aa6
CM		 2134 /*
2135 * Clear the interrupt registers again for luck, and clear the
2136 * saved flags to avoid getting false values from polling
2137 * routines or the previous session.
2138 */
2139 serial_inp(up, UART_LSR);
2140 serial_inp(up, UART_RX);
2141 serial_inp(up, UART_IIR);
2142 serial_inp(up, UART_MSR);
2143 up->lsr_saved_flags = 0;
2144 up->msr_saved_flags = 0;
2145
1da177e4
LT		 2146 /*
2147 * Finally, enable interrupts. Note: Modem status interrupts
2148 * are set via set_termios(), which will be occurring imminently
2149 * anyway, so we don't enable them here.
2150 */
2151 up->ier = UART_IER_RLSI | UART_IER_RDI;
2152 serial_outp(up, UART_IER, up->ier);
2153
2154 if (up->port.flags & UPF_FOURPORT) {
2155 unsigned int icp;
2156 /*
2157 * Enable interrupts on the AST Fourport board
2158 */
2159 icp = (up->port.iobase & 0xfe0) | 0x01f;
2160 outb_p(0x80, icp);
2161 (void) inb_p(icp);
2162 }
2163
1da177e4
LT		 2164 return 0;
2165}
2166
2167static void serial8250_shutdown(struct uart_port *port)
2168{
2169 struct uart_8250_port *up = (struct uart_8250_port *)port;
2170 unsigned long flags;
2171
2172 /*
2173 * Disable interrupts from this port
2174 */
2175 up->ier = 0;
2176 serial_outp(up, UART_IER, 0);
2177
2178 spin_lock_irqsave(&up->port.lock, flags);
2179 if (up->port.flags & UPF_FOURPORT) {
2180 /* reset interrupts on the AST Fourport board */
2181 inb((up->port.iobase & 0xfe0) | 0x1f);
2182 up->port.mctrl |= TIOCM_OUT1;
2183 } else
2184 up->port.mctrl &= ~TIOCM_OUT2;
2185
2186 serial8250_set_mctrl(&up->port, up->port.mctrl);
2187 spin_unlock_irqrestore(&up->port.lock, flags);
2188
2189 /*
2190 * Disable break condition and FIFOs
2191 */
2192 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2193 serial8250_clear_fifos(up);
2194
2195#ifdef CONFIG_SERIAL_8250_RSA
2196 /*
2197 * Reset the RSA board back to 115kbps compat mode.
2198 */
2199 disable_rsa(up);
2200#endif
2201
2202 /*
2203 * Read data port to reset things, and then unlink from
2204 * the IRQ chain.
2205 */
2206 (void) serial_in(up, UART_RX);
2207
40b36daa
AW		 2208 del_timer_sync(&up->timer);
2209 up->timer.function = serial8250_timeout;
2210 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2211 serial_unlink_irq_chain(up);
2212}
2213
2214static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2215{
2216 unsigned int quot;
2217
2218 /*
2219 * Handle magic divisors for baud rates above baud_base on
2220 * SMSC SuperIO chips.
2221 */
2222 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2223 baud == (port->uartclk/4))
2224 quot = 0x8001;
2225 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2226 baud == (port->uartclk/8))
2227 quot = 0x8002;
2228 else
2229 quot = uart_get_divisor(port, baud);
2230
2231 return quot;
2232}
2233
235dae5d
PL		 2234void
2235serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2236 struct ktermios *old)
1da177e4
LT		 2237{
2238 struct uart_8250_port *up = (struct uart_8250_port *)port;
2239 unsigned char cval, fcr = 0;
2240 unsigned long flags;
2241 unsigned int baud, quot;
2242
2243 switch (termios->c_cflag & CSIZE) {
2244 case CS5:
0a8b80c5 2245 cval = UART_LCR_WLEN5;
1da177e4
LT		 2246 break;
2247 case CS6:
0a8b80c5 2248 cval = UART_LCR_WLEN6;
1da177e4
LT		 2249 break;
2250 case CS7:
0a8b80c5 2251 cval = UART_LCR_WLEN7;
1da177e4
LT		 2252 break;
2253 default:
2254 case CS8:
0a8b80c5 2255 cval = UART_LCR_WLEN8;
1da177e4
LT		 2256 break;
2257 }
2258
2259 if (termios->c_cflag & CSTOPB)
0a8b80c5 2260 cval |= UART_LCR_STOP;
1da177e4
LT		 2261 if (termios->c_cflag & PARENB)
2262 cval |= UART_LCR_PARITY;
2263 if (!(termios->c_cflag & PARODD))
2264 cval |= UART_LCR_EPAR;
2265#ifdef CMSPAR
2266 if (termios->c_cflag & CMSPAR)
2267 cval |= UART_LCR_SPAR;
2268#endif
2269
2270 /*
2271 * Ask the core to calculate the divisor for us.
2272 */
24d481ec
AV		 2273 baud = uart_get_baud_rate(port, termios, old,
2274 port->uartclk / 16 / 0xffff,
2275 port->uartclk / 16);
1da177e4
LT		 2276 quot = serial8250_get_divisor(port, baud);
2277
2278 /*
4ba5e35d 2279 * Oxford Semi 952 rev B workaround
1da177e4 2280 */
4ba5e35d 2281 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2282 quot++;
1da177e4
LT		 2283
2284 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2285 if (baud < 2400)
2286 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2287 else
2288 fcr = uart_config[up->port.type].fcr;
2289 }
2290
2291 /*
2292 * MCR-based auto flow control. When AFE is enabled, RTS will be
2293 * deasserted when the receive FIFO contains more characters than
2294 * the trigger, or the MCR RTS bit is cleared. In the case where
2295 * the remote UART is not using CTS auto flow control, we must
2296 * have sufficient FIFO entries for the latency of the remote
2297 * UART to respond. IOW, at least 32 bytes of FIFO.
2298 */
2299 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2300 up->mcr &= ~UART_MCR_AFE;
2301 if (termios->c_cflag & CRTSCTS)
2302 up->mcr |= UART_MCR_AFE;
2303 }
2304
2305 /*
2306 * Ok, we're now changing the port state. Do it with
2307 * interrupts disabled.
2308 */
2309 spin_lock_irqsave(&up->port.lock, flags);
2310
2311 /*
2312 * Update the per-port timeout.
2313 */
2314 uart_update_timeout(port, termios->c_cflag, baud);
2315
2316 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2317 if (termios->c_iflag & INPCK)
2318 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2319 if (termios->c_iflag & (BRKINT | PARMRK))
2320 up->port.read_status_mask |= UART_LSR_BI;
2321
2322 /*
2323 * Characteres to ignore
2324 */
2325 up->port.ignore_status_mask = 0;
2326 if (termios->c_iflag & IGNPAR)
2327 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2328 if (termios->c_iflag & IGNBRK) {
2329 up->port.ignore_status_mask |= UART_LSR_BI;
2330 /*
2331 * If we're ignoring parity and break indicators,
2332 * ignore overruns too (for real raw support).
2333 */
2334 if (termios->c_iflag & IGNPAR)
2335 up->port.ignore_status_mask |= UART_LSR_OE;
2336 }
2337
2338 /*
2339 * ignore all characters if CREAD is not set
2340 */
2341 if ((termios->c_cflag & CREAD) == 0)
2342 up->port.ignore_status_mask |= UART_LSR_DR;
2343
2344 /*
2345 * CTS flow control flag and modem status interrupts
47d3904f
LR		 2346 * Only disable MSI if no threads are waiting in
2347 * serial_core::uart_wait_modem_status
1da177e4 2348 */
47d3904f
LR		 2349 if (!waitqueue_active(&up->port.state->port.delta_msr_wait))
2350 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2351 if (!(up->bugs & UART_BUG_NOMSR) &&
2352 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2353 up->ier |= UART_IER_MSI;
2354 if (up->capabilities & UART_CAP_UUE)
2355 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2356
2357 serial_out(up, UART_IER, up->ier);
2358
2359 if (up->capabilities & UART_CAP_EFR) {
2360 unsigned char efr = 0;
2361 /*
2362 * TI16C752/Startech hardware flow control. FIXME:
2363 * - TI16C752 requires control thresholds to be set.
2364 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2365 */
2366 if (termios->c_cflag & CRTSCTS)
2367 efr |= UART_EFR_CTS;
2368
2369 serial_outp(up, UART_LCR, 0xBF);
2370 serial_outp(up, UART_EFR, efr);
2371 }
2372
f2eda27d 2373#ifdef CONFIG_ARCH_OMAP
255341c6 2374 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2375 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2376 if (baud == 115200) {
2377 quot = 1;
2378 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2379 } else
2380 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2381 }
2382#endif
2383
1da177e4
LT		 2384 if (up->capabilities & UART_NATSEMI) {
2385 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2386 serial_outp(up, UART_LCR, 0xe0);
2387 } else {
2388 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2389 }
2390
b32b19b8 2391 serial_dl_write(up, quot);
1da177e4
LT		 2392
2393 /*
2394 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2395 * is written without DLAB set, this mode will be disabled.
2396 */
2397 if (up->port.type == PORT_16750)
2398 serial_outp(up, UART_FCR, fcr);
2399
2400 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2401 up->lcr = cval; /* Save LCR */
2402 if (up->port.type != PORT_16750) {
2403 if (fcr & UART_FCR_ENABLE_FIFO) {
2404 /* emulated UARTs (Lucent Venus 167x) need two steps */
2405 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2406 }
2407 serial_outp(up, UART_FCR, fcr); /* set fcr */
2408 }
2409 serial8250_set_mctrl(&up->port, up->port.mctrl);
2410 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2411 /* Don't rewrite B0 */
2412 if (tty_termios_baud_rate(termios))
2413 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4 2414}
235dae5d
PL		 2415EXPORT_SYMBOL(serial8250_do_set_termios);
2416
2417static void
2418serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2419 struct ktermios *old)
2420{
2421 if (port->set_termios)
2422 port->set_termios(port, termios, old);
2423 else
2424 serial8250_do_set_termios(port, termios, old);
2425}
1da177e4 2426
dc77f161 2427static void
a0821df6 2428serial8250_set_ldisc(struct uart_port *port, int new)
dc77f161 2429{
a0821df6 2430 if (new == N_PPS) {
dc77f161
RG		 2431 port->flags |= UPF_HARDPPS_CD;
2432 serial8250_enable_ms(port);
2433 } else
2434 port->flags &= ~UPF_HARDPPS_CD;
2435}
2436
c161afe9
ML		 2437
2438void serial8250_do_pm(struct uart_port *port, unsigned int state,
2439 unsigned int oldstate)
1da177e4
LT		 2440{
2441 struct uart_8250_port *p = (struct uart_8250_port *)port;
2442
2443 serial8250_set_sleep(p, state != 0);
c161afe9
ML		 2444}
2445EXPORT_SYMBOL(serial8250_do_pm);
1da177e4 2446
c161afe9
ML		 2447static void
2448serial8250_pm(struct uart_port *port, unsigned int state,
2449 unsigned int oldstate)
2450{
2451 if (port->pm)
2452 port->pm(port, state, oldstate);
2453 else
2454 serial8250_do_pm(port, state, oldstate);
1da177e4
LT		 2455}
2456
f2eda27d
RK		 2457static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2458{
2459 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2460 return 0x1000;
f2eda27d
RK		 2461#ifdef CONFIG_ARCH_OMAP
2462 if (is_omap_port(pt))
2463 return 0x16 << pt->port.regshift;
2464#endif
2465 return 8 << pt->port.regshift;
2466}
2467
1da177e4
LT		 2468/*
2469 * Resource handling.
2470 */
2471static int serial8250_request_std_resource(struct uart_8250_port *up)
2472{
f2eda27d 2473 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2474 int ret = 0;
2475
2476 switch (up->port.iotype) {
85835f44 2477 case UPIO_AU:
0b30d668
SS		 2478 case UPIO_TSI:
2479 case UPIO_MEM32:
1da177e4 2480 case UPIO_MEM:
beab697a 2481 case UPIO_DWAPB:
1da177e4
LT		 2482 if (!up->port.mapbase)
2483 break;
2484
2485 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2486 ret = -EBUSY;
2487 break;
2488 }
2489
2490 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2491 up->port.membase = ioremap_nocache(up->port.mapbase,
2492 size);
1da177e4
LT		 2493 if (!up->port.membase) {
2494 release_mem_region(up->port.mapbase, size);
2495 ret = -ENOMEM;
2496 }
2497 }
2498 break;
2499
2500 case UPIO_HUB6:
2501 case UPIO_PORT:
2502 if (!request_region(up->port.iobase, size, "serial"))
2503 ret = -EBUSY;
2504 break;
2505 }
2506 return ret;
2507}
2508
2509static void serial8250_release_std_resource(struct uart_8250_port *up)
2510{
f2eda27d 2511 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2512
2513 switch (up->port.iotype) {
85835f44 2514 case UPIO_AU:
0b30d668
SS		 2515 case UPIO_TSI:
2516 case UPIO_MEM32:
1da177e4 2517 case UPIO_MEM:
beab697a 2518 case UPIO_DWAPB:
1da177e4
LT		 2519 if (!up->port.mapbase)
2520 break;
2521
2522 if (up->port.flags & UPF_IOREMAP) {
2523 iounmap(up->port.membase);
2524 up->port.membase = NULL;
2525 }
2526
2527 release_mem_region(up->port.mapbase, size);
2528 break;
2529
2530 case UPIO_HUB6:
2531 case UPIO_PORT:
2532 release_region(up->port.iobase, size);
2533 break;
2534 }
2535}
2536
2537static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2538{
2539 unsigned long start = UART_RSA_BASE << up->port.regshift;
2540 unsigned int size = 8 << up->port.regshift;
0b30d668 2541 int ret = -EINVAL;
1da177e4
LT		 2542
2543 switch (up->port.iotype) {
1da177e4
LT		 2544 case UPIO_HUB6:
2545 case UPIO_PORT:
2546 start += up->port.iobase;
0b30d668
SS		 2547 if (request_region(start, size, "serial-rsa"))
2548 ret = 0;
2549 else
1da177e4
LT		 2550 ret = -EBUSY;
2551 break;
2552 }
2553
2554 return ret;
2555}
2556
2557static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2558{
2559 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2560 unsigned int size = 8 << up->port.regshift;
2561
2562 switch (up->port.iotype) {
1da177e4
LT		 2563 case UPIO_HUB6:
2564 case UPIO_PORT:
2565 release_region(up->port.iobase + offset, size);
2566 break;
2567 }
2568}
2569
2570static void serial8250_release_port(struct uart_port *port)
2571{
2572 struct uart_8250_port *up = (struct uart_8250_port *)port;
2573
2574 serial8250_release_std_resource(up);
2575 if (up->port.type == PORT_RSA)
2576 serial8250_release_rsa_resource(up);
2577}
2578
2579static int serial8250_request_port(struct uart_port *port)
2580{
2581 struct uart_8250_port *up = (struct uart_8250_port *)port;
2582 int ret = 0;
2583
2584 ret = serial8250_request_std_resource(up);
2585 if (ret == 0 && up->port.type == PORT_RSA) {
2586 ret = serial8250_request_rsa_resource(up);
2587 if (ret < 0)
2588 serial8250_release_std_resource(up);
2589 }
2590
2591 return ret;
2592}
2593
2594static void serial8250_config_port(struct uart_port *port, int flags)
2595{
2596 struct uart_8250_port *up = (struct uart_8250_port *)port;
2597 int probeflags = PROBE_ANY;
2598 int ret;
2599
1da177e4
LT		 2600 /*
2601 * Find the region that we can probe for. This in turn
2602 * tells us whether we can probe for the type of port.
2603 */
2604 ret = serial8250_request_std_resource(up);
2605 if (ret < 0)
2606 return;
2607
2608 ret = serial8250_request_rsa_resource(up);
2609 if (ret < 0)
2610 probeflags &= ~PROBE_RSA;
2611
b8e7e40a
AC		 2612 if (up->port.iotype != up->cur_iotype)
2613 set_io_from_upio(port);
2614
1da177e4
LT		 2615 if (flags & UART_CONFIG_TYPE)
2616 autoconfig(up, probeflags);
b2b13cdf 2617
b2b13cdf
ML		 2618 /* if access method is AU, it is a 16550 with a quirk */
2619 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2620 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2621
1da177e4
LT		 2622 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2623 autoconfig_irq(up);
2624
2625 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2626 serial8250_release_rsa_resource(up);
2627 if (up->port.type == PORT_UNKNOWN)
2628 serial8250_release_std_resource(up);
2629}
2630
2631static int
2632serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2633{
a62c4133 2634 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2635 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2636 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2637 ser->type == PORT_STARTECH)
2638 return -EINVAL;
2639 return 0;
2640}
2641
2642static const char *
2643serial8250_type(struct uart_port *port)
2644{
2645 int type = port->type;
2646
2647 if (type >= ARRAY_SIZE(uart_config))
2648 type = 0;
2649 return uart_config[type].name;
2650}
2651
2652static struct uart_ops serial8250_pops = {
2653 .tx_empty = serial8250_tx_empty,
2654 .set_mctrl = serial8250_set_mctrl,
2655 .get_mctrl = serial8250_get_mctrl,
2656 .stop_tx = serial8250_stop_tx,
2657 .start_tx = serial8250_start_tx,
2658 .stop_rx = serial8250_stop_rx,
2659 .enable_ms = serial8250_enable_ms,
2660 .break_ctl = serial8250_break_ctl,
2661 .startup = serial8250_startup,
2662 .shutdown = serial8250_shutdown,
2663 .set_termios = serial8250_set_termios,
dc77f161 2664 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2665 .pm = serial8250_pm,
2666 .type = serial8250_type,
2667 .release_port = serial8250_release_port,
2668 .request_port = serial8250_request_port,
2669 .config_port = serial8250_config_port,
2670 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2671#ifdef CONFIG_CONSOLE_POLL
2672 .poll_get_char = serial8250_get_poll_char,
2673 .poll_put_char = serial8250_put_poll_char,
2674#endif
1da177e4
LT		 2675};
2676
2677static struct uart_8250_port serial8250_ports[UART_NR];
2678
af7f3743
AC		 2679static void (*serial8250_isa_config)(int port, struct uart_port *up,
2680 unsigned short *capabilities);
2681
2682void serial8250_set_isa_configurator(
2683 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2684{
2685 serial8250_isa_config = v;
2686}
2687EXPORT_SYMBOL(serial8250_set_isa_configurator);
2688
1da177e4
LT		 2689static void __init serial8250_isa_init_ports(void)
2690{
2691 struct uart_8250_port *up;
2692 static int first = 1;
4c0ebb80 2693 int i, irqflag = 0;
1da177e4
LT		 2694
2695 if (!first)
2696 return;
2697 first = 0;
2698
a61c2d78 2699 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2700 struct uart_8250_port *up = &serial8250_ports[i];
2701
2702 up->port.line = i;
2703 spin_lock_init(&up->port.lock);
2704
2705 init_timer(&up->timer);
2706 up->timer.function = serial8250_timeout;
2707
2708 /*
2709 * ALPHA_KLUDGE_MCR needs to be killed.
2710 */
2711 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2712 up->mcr_force = ALPHA_KLUDGE_MCR;
2713
2714 up->port.ops = &serial8250_pops;
2715 }
2716
4c0ebb80
AGR		 2717 if (share_irqs)
2718 irqflag = IRQF_SHARED;
2719
44454bcd 2720 for (i = 0, up = serial8250_ports;
a61c2d78 2721 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2722 i++, up++) {
2723 up->port.iobase = old_serial_port[i].port;
2724 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2725 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2726 up->port.uartclk = old_serial_port[i].baud_base * 16;
2727 up->port.flags = old_serial_port[i].flags;
2728 up->port.hub6 = old_serial_port[i].hub6;
2729 up->port.membase = old_serial_port[i].iomem_base;
2730 up->port.iotype = old_serial_port[i].io_type;
2731 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2732 set_io_from_upio(&up->port);
4c0ebb80 2733 up->port.irqflags |= irqflag;
af7f3743
AC		 2734 if (serial8250_isa_config != NULL)
2735 serial8250_isa_config(i, &up->port, &up->capabilities);
2736
1da177e4
LT		 2737 }
2738}
2739
b5d228cc
SL		 2740static void
2741serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2742{
2743 up->port.type = type;
2744 up->port.fifosize = uart_config[type].fifo_size;
2745 up->capabilities = uart_config[type].flags;
2746 up->tx_loadsz = uart_config[type].tx_loadsz;
2747}
2748
1da177e4
LT		 2749static void __init
2750serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2751{
2752 int i;
2753
b8e7e40a
AC		 2754 for (i = 0; i < nr_uarts; i++) {
2755 struct uart_8250_port *up = &serial8250_ports[i];
2756 up->cur_iotype = 0xFF;
2757 }
2758
1da177e4
LT		 2759 serial8250_isa_init_ports();
2760
a61c2d78 2761 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2762 struct uart_8250_port *up = &serial8250_ports[i];
2763
2764 up->port.dev = dev;
b5d228cc
SL		 2765
2766 if (up->port.flags & UPF_FIXED_TYPE)
2767 serial8250_init_fixed_type_port(up, up->port.type);
2768
1da177e4
LT		 2769 uart_add_one_port(drv, &up->port);
2770 }
2771}
2772
2773#ifdef CONFIG_SERIAL_8250_CONSOLE
2774
d358788f
RK		 2775static void serial8250_console_putchar(struct uart_port *port, int ch)
2776{
2777 struct uart_8250_port *up = (struct uart_8250_port *)port;
2778
2779 wait_for_xmitr(up, UART_LSR_THRE);
2780 serial_out(up, UART_TX, ch);
2781}
2782
1da177e4
LT		 2783/*
2784 * Print a string to the serial port trying not to disturb
2785 * any possible real use of the port...
2786 *
2787 * The console_lock must be held when we get here.
2788 */
2789static void
2790serial8250_console_write(struct console *co, const char *s, unsigned int count)
2791{
2792 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2793 unsigned long flags;
1da177e4 2794 unsigned int ier;
d8a5a8d7 2795 int locked = 1;
1da177e4 2796
78512ece
AM		 2797 touch_nmi_watchdog();
2798
68aa2c0d
AM		 2799 local_irq_save(flags);
2800 if (up->port.sysrq) {
2801 /* serial8250_handle_port() already took the lock */
2802 locked = 0;
2803 } else if (oops_in_progress) {
2804 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2805 } else
68aa2c0d 2806 spin_lock(&up->port.lock);
d8a5a8d7 2807
1da177e4 2808 /*
dc7bf130 2809 * First save the IER then disable the interrupts
1da177e4
LT		 2810 */
2811 ier = serial_in(up, UART_IER);
2812
2813 if (up->capabilities & UART_CAP_UUE)
2814 serial_out(up, UART_IER, UART_IER_UUE);
2815 else
2816 serial_out(up, UART_IER, 0);
2817
d358788f 2818 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2819
2820 /*
2821 * Finally, wait for transmitter to become empty
2822 * and restore the IER
2823 */
f91a3715 2824 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2825 serial_out(up, UART_IER, ier);
d8a5a8d7 2826
ad4c2aa6
CM		 2827 /*
2828 * The receive handling will happen properly because the
2829 * receive ready bit will still be set; it is not cleared
2830 * on read. However, modem control will not, we must
2831 * call it if we have saved something in the saved flags
2832 * while processing with interrupts off.
2833 */
2834 if (up->msr_saved_flags)
2835 check_modem_status(up);
2836
d8a5a8d7 2837 if (locked)
68aa2c0d
AM		 2838 spin_unlock(&up->port.lock);
2839 local_irq_restore(flags);
1da177e4
LT		 2840}
2841
118c0ace 2842static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2843{
2844 struct uart_port *port;
2845 int baud = 9600;
2846 int bits = 8;
2847 int parity = 'n';
2848 int flow = 'n';
2849
2850 /*
2851 * Check whether an invalid uart number has been specified, and
2852 * if so, search for the first available port that does have
2853 * console support.
2854 */
a61c2d78 2855 if (co->index >= nr_uarts)
1da177e4
LT		 2856 co->index = 0;
2857 port = &serial8250_ports[co->index].port;
2858 if (!port->iobase && !port->membase)
2859 return -ENODEV;
2860
2861 if (options)
2862 uart_parse_options(options, &baud, &parity, &bits, &flow);
2863
2864 return uart_set_options(port, co, baud, parity, bits, flow);
2865}
2866
b6b1d877 2867static int serial8250_console_early_setup(void)
18a8bd94
YL		 2868{
2869 return serial8250_find_port_for_earlycon();
2870}
2871
1da177e4
LT		 2872static struct console serial8250_console = {
2873 .name = "ttyS",
2874 .write = serial8250_console_write,
2875 .device = uart_console_device,
2876 .setup = serial8250_console_setup,
18a8bd94 2877 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2878 .flags = CON_PRINTBUFFER,
2879 .index = -1,
2880 .data = &serial8250_reg,
2881};
2882
2883static int __init serial8250_console_init(void)
2884{
05d81d22
EB		 2885 if (nr_uarts > UART_NR)
2886 nr_uarts = UART_NR;
2887
1da177e4
LT		 2888 serial8250_isa_init_ports();
2889 register_console(&serial8250_console);
2890 return 0;
2891}
2892console_initcall(serial8250_console_init);
2893
18a8bd94 2894int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2895{
2896 int line;
2897 struct uart_port *port;
2898
a61c2d78 2899 for (line = 0; line < nr_uarts; line++) {
1da177e4 2900 port = &serial8250_ports[line].port;
50aec3b5 2901 if (uart_match_port(p, port))
1da177e4
LT		 2902 return line;
2903 }
2904 return -ENODEV;
2905}
2906
1da177e4
LT		 2907#define SERIAL8250_CONSOLE &serial8250_console
2908#else
2909#define SERIAL8250_CONSOLE NULL
2910#endif
2911
2912static struct uart_driver serial8250_reg = {
2913 .owner = THIS_MODULE,
2914 .driver_name = "serial",
1da177e4
LT		 2915 .dev_name = "ttyS",
2916 .major = TTY_MAJOR,
2917 .minor = 64,
1da177e4
LT		 2918 .cons = SERIAL8250_CONSOLE,
2919};
2920
d856c666
RK		 2921/*
2922 * early_serial_setup - early registration for 8250 ports
2923 *
2924 * Setup an 8250 port structure prior to console initialisation. Use
2925 * after console initialisation will cause undefined behaviour.
2926 */
1da177e4
LT		 2927int __init early_serial_setup(struct uart_port *port)
2928{
b430428a
DD		 2929 struct uart_port *p;
2930
1da177e4
LT		 2931 if (port->line >= ARRAY_SIZE(serial8250_ports))
2932 return -ENODEV;
2933
2934 serial8250_isa_init_ports();
b430428a
DD		 2935 p = &serial8250_ports[port->line].port;
2936 p->iobase = port->iobase;
2937 p->membase = port->membase;
2938 p->irq = port->irq;
1c2f0493 2939 p->irqflags = port->irqflags;
b430428a
DD		 2940 p->uartclk = port->uartclk;
2941 p->fifosize = port->fifosize;
2942 p->regshift = port->regshift;
2943 p->iotype = port->iotype;
2944 p->flags = port->flags;
2945 p->mapbase = port->mapbase;
2946 p->private_data = port->private_data;
125c97d8
HD		 2947 p->type = port->type;
2948 p->line = port->line;
7d6a07d1
DD		 2949
2950 set_io_from_upio(p);
2951 if (port->serial_in)
2952 p->serial_in = port->serial_in;
2953 if (port->serial_out)
2954 p->serial_out = port->serial_out;
2955
1da177e4
LT		 2956 return 0;
2957}
2958
2959/**
2960 * serial8250_suspend_port - suspend one serial port
2961 * @line: serial line number
1da177e4
LT		 2962 *
2963 * Suspend one serial port.
2964 */
2965void serial8250_suspend_port(int line)
2966{
2967 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2968}
2969
2970/**
2971 * serial8250_resume_port - resume one serial port
2972 * @line: serial line number
1da177e4
LT		 2973 *
2974 * Resume one serial port.
2975 */
2976void serial8250_resume_port(int line)
2977{
b5b82df6
DW		 2978 struct uart_8250_port *up = &serial8250_ports[line];
2979
2980 if (up->capabilities & UART_NATSEMI) {
2981 unsigned char tmp;
2982
2983 /* Ensure it's still in high speed mode */
2984 serial_outp(up, UART_LCR, 0xE0);
2985
2986 tmp = serial_in(up, 0x04); /* EXCR2 */
2987 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2988 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2989 serial_outp(up, 0x04, tmp);
2990
2991 serial_outp(up, UART_LCR, 0);
2992 }
2993 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2994}
2995
2996/*
2997 * Register a set of serial devices attached to a platform device. The
2998 * list is terminated with a zero flags entry, which means we expect
2999 * all entries to have at least UPF_BOOT_AUTOCONF set.
3000 */
3ae5eaec 3001static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 3002{
3ae5eaec 3003 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 3004 struct uart_port port;
4c0ebb80 3005 int ret, i, irqflag = 0;
1da177e4
LT		 3006
3007 memset(&port, 0, sizeof(struct uart_port));
3008
4c0ebb80
AGR		 3009 if (share_irqs)
3010 irqflag = IRQF_SHARED;
3011
ec9f47cd 3012 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 3013 port.iobase = p->iobase;
3014 port.membase = p->membase;
3015 port.irq = p->irq;
1c2f0493 3016 port.irqflags = p->irqflags;
74a19741
WN		 3017 port.uartclk = p->uartclk;
3018 port.regshift = p->regshift;
3019 port.iotype = p->iotype;
3020 port.flags = p->flags;
3021 port.mapbase = p->mapbase;
3022 port.hub6 = p->hub6;
3023 port.private_data = p->private_data;
8e23fcc8 3024 port.type = p->type;
7d6a07d1
DD		 3025 port.serial_in = p->serial_in;
3026 port.serial_out = p->serial_out;
235dae5d 3027 port.set_termios = p->set_termios;
c161afe9 3028 port.pm = p->pm;
74a19741 3029 port.dev = &dev->dev;
4c0ebb80 3030 port.irqflags |= irqflag;
ec9f47cd
RK		 3031 ret = serial8250_register_port(&port);
3032 if (ret < 0) {
3ae5eaec 3033 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 3034 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3035 p->iobase, (unsigned long long)p->mapbase,
3036 p->irq, ret);
ec9f47cd 3037 }
1da177e4
LT		 3038 }
3039 return 0;
3040}
3041
3042/*
3043 * Remove serial ports registered against a platform device.
3044 */
3ae5eaec 3045static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3046{
3047 int i;
3048
a61c2d78 3049 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3050 struct uart_8250_port *up = &serial8250_ports[i];
3051
3ae5eaec 3052 if (up->port.dev == &dev->dev)
1da177e4
LT		 3053 serial8250_unregister_port(i);
3054 }
3055 return 0;
3056}
3057
3ae5eaec 3058static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3059{
3060 int i;
3061
1da177e4
LT		 3062 for (i = 0; i < UART_NR; i++) {
3063 struct uart_8250_port *up = &serial8250_ports[i];
3064
3ae5eaec 3065 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3066 uart_suspend_port(&serial8250_reg, &up->port);
3067 }
3068
3069 return 0;
3070}
3071
3ae5eaec 3072static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3073{
3074 int i;
3075
1da177e4
LT		 3076 for (i = 0; i < UART_NR; i++) {
3077 struct uart_8250_port *up = &serial8250_ports[i];
3078
3ae5eaec 3079 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3080 serial8250_resume_port(i);
1da177e4
LT		 3081 }
3082
3083 return 0;
3084}
3085
3ae5eaec 3086static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3087 .probe = serial8250_probe,
3088 .remove = __devexit_p(serial8250_remove),
3089 .suspend = serial8250_suspend,
3090 .resume = serial8250_resume,
3ae5eaec
RK		 3091 .driver = {
3092 .name = "serial8250",
7493a314 3093 .owner = THIS_MODULE,
3ae5eaec 3094 },
1da177e4
LT		 3095};
3096
3097/*
3098 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3099 * in the table in include/asm/serial.h
3100 */
3101static struct platform_device *serial8250_isa_devs;
3102
3103/*
3104 * serial8250_register_port and serial8250_unregister_port allows for
3105 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3106 * modems and PCI multiport cards.
3107 */
f392ecfa 3108static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3109
3110static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3111{
3112 int i;
3113
3114 /*
3115 * First, find a port entry which matches.
3116 */
a61c2d78 3117 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3118 if (uart_match_port(&serial8250_ports[i].port, port))
3119 return &serial8250_ports[i];
3120
3121 /*
3122 * We didn't find a matching entry, so look for the first
3123 * free entry. We look for one which hasn't been previously
3124 * used (indicated by zero iobase).
3125 */
a61c2d78 3126 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3127 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3128 serial8250_ports[i].port.iobase == 0)
3129 return &serial8250_ports[i];
3130
3131 /*
3132 * That also failed. Last resort is to find any entry which
3133 * doesn't have a real port associated with it.
3134 */
a61c2d78 3135 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3136 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3137 return &serial8250_ports[i];
3138
3139 return NULL;
3140}
3141
3142/**
3143 * serial8250_register_port - register a serial port
3144 * @port: serial port template
3145 *
3146 * Configure the serial port specified by the request. If the
3147 * port exists and is in use, it is hung up and unregistered
3148 * first.
3149 *
3150 * The port is then probed and if necessary the IRQ is autodetected
3151 * If this fails an error is returned.
3152 *
3153 * On success the port is ready to use and the line number is returned.
3154 */
3155int serial8250_register_port(struct uart_port *port)
3156{
3157 struct uart_8250_port *uart;
3158 int ret = -ENOSPC;
3159
3160 if (port->uartclk == 0)
3161 return -EINVAL;
3162
f392ecfa 3163 mutex_lock(&serial_mutex);
1da177e4
LT		 3164
3165 uart = serial8250_find_match_or_unused(port);
3166 if (uart) {
3167 uart_remove_one_port(&serial8250_reg, &uart->port);
3168
74a19741
WN		 3169 uart->port.iobase = port->iobase;
3170 uart->port.membase = port->membase;
3171 uart->port.irq = port->irq;
1c2f0493 3172 uart->port.irqflags = port->irqflags;
74a19741
WN		 3173 uart->port.uartclk = port->uartclk;
3174 uart->port.fifosize = port->fifosize;
3175 uart->port.regshift = port->regshift;
3176 uart->port.iotype = port->iotype;
3177 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3178 uart->port.mapbase = port->mapbase;
3179 uart->port.private_data = port->private_data;
1da177e4
LT		 3180 if (port->dev)
3181 uart->port.dev = port->dev;
8e23fcc8 3182
b5d228cc
SL		 3183 if (port->flags & UPF_FIXED_TYPE)
3184 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3185
7d6a07d1
DD		 3186 set_io_from_upio(&uart->port);
3187 /* Possibly override default I/O functions. */
3188 if (port->serial_in)
3189 uart->port.serial_in = port->serial_in;
3190 if (port->serial_out)
3191 uart->port.serial_out = port->serial_out;
235dae5d
PL		 3192 /* Possibly override set_termios call */
3193 if (port->set_termios)
3194 uart->port.set_termios = port->set_termios;
c161afe9
ML		 3195 if (port->pm)
3196 uart->port.pm = port->pm;
1da177e4 3197
af7f3743
AC		 3198 if (serial8250_isa_config != NULL)
3199 serial8250_isa_config(0, &uart->port,
3200 &uart->capabilities);
3201
1da177e4
LT		 3202 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3203 if (ret == 0)
3204 ret = uart->port.line;
3205 }
f392ecfa 3206 mutex_unlock(&serial_mutex);
1da177e4
LT		 3207
3208 return ret;
3209}
3210EXPORT_SYMBOL(serial8250_register_port);
3211
3212/**
3213 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3214 * @line: serial line number
3215 *
3216 * Remove one serial port. This may not be called from interrupt
3217 * context. We hand the port back to the our control.
3218 */
3219void serial8250_unregister_port(int line)
3220{
3221 struct uart_8250_port *uart = &serial8250_ports[line];
3222
f392ecfa 3223 mutex_lock(&serial_mutex);
1da177e4
LT		 3224 uart_remove_one_port(&serial8250_reg, &uart->port);
3225 if (serial8250_isa_devs) {
3226 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3227 uart->port.type = PORT_UNKNOWN;
3228 uart->port.dev = &serial8250_isa_devs->dev;
3229 uart_add_one_port(&serial8250_reg, &uart->port);
3230 } else {
3231 uart->port.dev = NULL;
3232 }
f392ecfa 3233 mutex_unlock(&serial_mutex);
1da177e4
LT		 3234}
3235EXPORT_SYMBOL(serial8250_unregister_port);
3236
3237static int __init serial8250_init(void)
3238{
25db8ad5 3239 int ret;
1da177e4 3240
a61c2d78
DJ		 3241 if (nr_uarts > UART_NR)
3242 nr_uarts = UART_NR;
3243
f1fb9bb8 3244 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3245 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3246 share_irqs ? "en" : "dis");
3247
b70ac771
DM		 3248#ifdef CONFIG_SPARC
3249 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3250#else
3251 serial8250_reg.nr = UART_NR;
1da177e4 3252 ret = uart_register_driver(&serial8250_reg);
b70ac771 3253#endif
1da177e4
LT		 3254 if (ret)
3255 goto out;
3256
7493a314
DT		 3257 serial8250_isa_devs = platform_device_alloc("serial8250",
3258 PLAT8250_DEV_LEGACY);
3259 if (!serial8250_isa_devs) {
3260 ret = -ENOMEM;
bc965a7f 3261 goto unreg_uart_drv;
1da177e4
LT		 3262 }
3263
7493a314
DT		 3264 ret = platform_device_add(serial8250_isa_devs);
3265 if (ret)
3266 goto put_dev;
3267
1da177e4
LT		 3268 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3269
bc965a7f
RK		 3270 ret = platform_driver_register(&serial8250_isa_driver);
3271 if (ret == 0)
3272 goto out;
1da177e4 3273
bc965a7f 3274 platform_device_del(serial8250_isa_devs);
25db8ad5 3275put_dev:
7493a314 3276 platform_device_put(serial8250_isa_devs);
25db8ad5 3277unreg_uart_drv:
b70ac771
DM		 3278#ifdef CONFIG_SPARC
3279 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3280#else
1da177e4 3281 uart_unregister_driver(&serial8250_reg);
b70ac771 3282#endif
25db8ad5 3283out:
1da177e4
LT		 3284 return ret;
3285}
3286
3287static void __exit serial8250_exit(void)
3288{
3289 struct platform_device *isa_dev = serial8250_isa_devs;
3290
3291 /*
3292 * This tells serial8250_unregister_port() not to re-register
3293 * the ports (thereby making serial8250_isa_driver permanently
3294 * in use.)
3295 */
3296 serial8250_isa_devs = NULL;
3297
3ae5eaec 3298 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3299 platform_device_unregister(isa_dev);
3300
b70ac771
DM		 3301#ifdef CONFIG_SPARC
3302 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3303#else
1da177e4 3304 uart_unregister_driver(&serial8250_reg);
b70ac771 3305#endif
1da177e4
LT		 3306}
3307
3308module_init(serial8250_init);
3309module_exit(serial8250_exit);
3310
3311EXPORT_SYMBOL(serial8250_suspend_port);
3312EXPORT_SYMBOL(serial8250_resume_port);
3313
3314MODULE_LICENSE("GPL");
d87a6d95 3315MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3316
3317module_param(share_irqs, uint, 0644);
3318MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3319 " (unsafe)");
3320
a61c2d78
DJ		 3321module_param(nr_uarts, uint, 0644);
3322MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3323
d41a4b51
CE		 3324module_param(skip_txen_test, uint, 0644);
3325MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3326
1da177e4
LT		 3327#ifdef CONFIG_SERIAL_8250_RSA
3328module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3329MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3330#endif
3331MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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