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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
1da177e4
LT		 22
23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
1da177e4 33#include <linux/delay.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4
LT		 35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_reg.h>
38#include <linux/serial_core.h>
39#include <linux/serial.h>
40#include <linux/serial_8250.h>
78512ece 41#include <linux/nmi.h>
f392ecfa 42#include <linux/mutex.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
40663cc7 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 55
a61c2d78
DJ		 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
1da177e4
LT		 58/*
59 * Debugging.
60 */
61#if 0
62#define DEBUG_AUTOCONF(fmt...) printk(fmt)
63#else
64#define DEBUG_AUTOCONF(fmt...) do { } while (0)
65#endif
66
67#if 0
68#define DEBUG_INTR(fmt...) printk(fmt)
69#else
70#define DEBUG_INTR(fmt...) do { } while (0)
71#endif
72
73#define PASS_LIMIT 256
74
75/*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80#define is_real_interrupt(irq) ((irq) != 0)
81
1da177e4
LT		 82#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83#define CONFIG_SERIAL_DETECT_IRQ 1
84#endif
1da177e4
LT		 85#ifdef CONFIG_SERIAL_8250_MANY_PORTS
86#define CONFIG_SERIAL_MANY_PORTS 1
87#endif
88
89/*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93#define CONFIG_HUB6 1
94
95#include <asm/serial.h>
96
97/*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102#ifndef SERIAL_PORT_DFNS
103#define SERIAL_PORT_DFNS
104#endif
105
cb3592be 106static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108};
109
026d02a2 110#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 111
112#ifdef CONFIG_SERIAL_8250_RSA
113
114#define PORT_RSA_MAX 4
115static unsigned long probe_rsa[PORT_RSA_MAX];
116static unsigned int probe_rsa_count;
117#endif /* CONFIG_SERIAL_8250_RSA */
118
119struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
1da177e4 125 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
133
134 /*
135 * We provide a per-port pm hook.
136 */
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
139};
140
141struct irq_info {
142 spinlock_t lock;
143 struct list_head *head;
144};
145
146static struct irq_info irq_lists[NR_IRQS];
147
148/*
149 * Here we define the default xmit fifo size used for each type of UART.
150 */
151static const struct serial8250_config uart_config[] = {
152 [PORT_UNKNOWN] = {
153 .name = "unknown",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_8250] = {
158 .name = "8250",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16450] = {
163 .name = "16450",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550] = {
168 .name = "16550",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16550A] = {
173 .name = "16550A",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
178 },
179 [PORT_CIRRUS] = {
180 .name = "Cirrus",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16650] = {
185 .name = "ST16650",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 },
190 [PORT_16650V2] = {
191 .name = "ST16650V2",
192 .fifo_size = 32,
193 .tx_loadsz = 16,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_00,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16750] = {
199 .name = "TI16750",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
203 UART_FCR7_64BYTE,
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
205 },
206 [PORT_STARTECH] = {
207 .name = "Startech",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16C950] = {
212 .name = "16C950/954",
213 .fifo_size = 128,
214 .tx_loadsz = 128,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
217 },
218 [PORT_16654] = {
219 .name = "ST16654",
220 .fifo_size = 64,
221 .tx_loadsz = 32,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16850] = {
227 .name = "XR16850",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
232 },
233 [PORT_RSA] = {
234 .name = "RSA",
235 .fifo_size = 2048,
236 .tx_loadsz = 2048,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_NS16550A] = {
241 .name = "NS16550A",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
246 },
247 [PORT_XSCALE] = {
248 .name = "XScale",
249 .fifo_size = 32,
250 .tx_loadsz = 32,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
253 },
254};
255
21c614a7
PA		 256#ifdef CONFIG_SERIAL_8250_AU1X00
257
258/* Au1x00 UART hardware has a weird register layout */
259static const u8 au_io_in_map[] = {
260 [UART_RX] = 0,
261 [UART_IER] = 2,
262 [UART_IIR] = 3,
263 [UART_LCR] = 5,
264 [UART_MCR] = 6,
265 [UART_LSR] = 7,
266 [UART_MSR] = 8,
267};
268
269static const u8 au_io_out_map[] = {
270 [UART_TX] = 1,
271 [UART_IER] = 2,
272 [UART_FCR] = 4,
273 [UART_LCR] = 5,
274 [UART_MCR] = 6,
275};
276
277/* sane hardware needs no mapping */
278static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
279{
280 if (up->port.iotype != UPIO_AU)
281 return offset;
282 return au_io_in_map[offset];
283}
284
285static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
286{
287 if (up->port.iotype != UPIO_AU)
288 return offset;
289 return au_io_out_map[offset];
290}
291
292#else
293
294/* sane hardware needs no mapping */
295#define map_8250_in_reg(up, offset) (offset)
296#define map_8250_out_reg(up, offset) (offset)
297
298#endif
299
ea8874dc 300static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 301{
3be91ec7 302 unsigned int tmp;
21c614a7 303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 304
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
309
310 case UPIO_MEM:
311 return readb(up->port.membase + offset);
312
313 case UPIO_MEM32:
314 return readl(up->port.membase + offset);
315
21c614a7
PA		 316#ifdef CONFIG_SERIAL_8250_AU1X00
317 case UPIO_AU:
318 return __raw_readl(up->port.membase + offset);
319#endif
320
3be91ec7
ZR		 321 case UPIO_TSI:
322 if (offset == UART_IIR) {
9e84b60e
AV		 323 tmp = readl(up->port.membase + (UART_IIR & ~3));
324 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
3be91ec7
ZR		 325 } else
326 return readb(up->port.membase + offset);
327
1da177e4
LT		 328 default:
329 return inb(up->port.iobase + offset);
330 }
331}
332
ea8874dc 333static void
1da177e4
LT		 334serial_out(struct uart_8250_port *up, int offset, int value)
335{
21c614a7 336 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 337
338 switch (up->port.iotype) {
339 case UPIO_HUB6:
340 outb(up->port.hub6 - 1 + offset, up->port.iobase);
341 outb(value, up->port.iobase + 1);
342 break;
343
344 case UPIO_MEM:
345 writeb(value, up->port.membase + offset);
346 break;
347
348 case UPIO_MEM32:
349 writel(value, up->port.membase + offset);
350 break;
351
21c614a7
PA		 352#ifdef CONFIG_SERIAL_8250_AU1X00
353 case UPIO_AU:
354 __raw_writel(value, up->port.membase + offset);
355 break;
356#endif
3be91ec7
ZR		 357 case UPIO_TSI:
358 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
359 writeb(value, up->port.membase + offset);
360 break;
21c614a7 361
1da177e4
LT		 362 default:
363 outb(value, up->port.iobase + offset);
364 }
365}
366
367/*
368 * We used to support using pause I/O for certain machines. We
369 * haven't supported this for a while, but just in case it's badly
370 * needed for certain old 386 machines, I've left these #define's
371 * in....
372 */
373#define serial_inp(up, offset) serial_in(up, offset)
374#define serial_outp(up, offset, value) serial_out(up, offset, value)
375
b32b19b8
JAH		 376/* Uart divisor latch read */
377static inline int _serial_dl_read(struct uart_8250_port *up)
378{
379 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
380}
381
382/* Uart divisor latch write */
383static inline void _serial_dl_write(struct uart_8250_port *up, int value)
384{
385 serial_outp(up, UART_DLL, value & 0xff);
386 serial_outp(up, UART_DLM, value >> 8 & 0xff);
387}
388
389#ifdef CONFIG_SERIAL_8250_AU1X00
390/* Au1x00 haven't got a standard divisor latch */
391static int serial_dl_read(struct uart_8250_port *up)
392{
393 if (up->port.iotype == UPIO_AU)
394 return __raw_readl(up->port.membase + 0x28);
395 else
396 return _serial_dl_read(up);
397}
398
399static void serial_dl_write(struct uart_8250_port *up, int value)
400{
401 if (up->port.iotype == UPIO_AU)
402 __raw_writel(value, up->port.membase + 0x28);
403 else
404 _serial_dl_write(up, value);
405}
406#else
407#define serial_dl_read(up) _serial_dl_read(up)
408#define serial_dl_write(up, value) _serial_dl_write(up, value)
409#endif
1da177e4
LT		 410
411/*
412 * For the 16C950
413 */
414static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
415{
416 serial_out(up, UART_SCR, offset);
417 serial_out(up, UART_ICR, value);
418}
419
420static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
421{
422 unsigned int value;
423
424 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
425 serial_out(up, UART_SCR, offset);
426 value = serial_in(up, UART_ICR);
427 serial_icr_write(up, UART_ACR, up->acr);
428
429 return value;
430}
431
432/*
433 * FIFO support.
434 */
435static inline void serial8250_clear_fifos(struct uart_8250_port *p)
436{
437 if (p->capabilities & UART_CAP_FIFO) {
438 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
439 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
440 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
441 serial_outp(p, UART_FCR, 0);
442 }
443}
444
445/*
446 * IER sleep support. UARTs which have EFRs need the "extended
447 * capability" bit enabled. Note that on XR16C850s, we need to
448 * reset LCR to write to IER.
449 */
450static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
451{
452 if (p->capabilities & UART_CAP_SLEEP) {
453 if (p->capabilities & UART_CAP_EFR) {
454 serial_outp(p, UART_LCR, 0xBF);
455 serial_outp(p, UART_EFR, UART_EFR_ECB);
456 serial_outp(p, UART_LCR, 0);
457 }
458 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
459 if (p->capabilities & UART_CAP_EFR) {
460 serial_outp(p, UART_LCR, 0xBF);
461 serial_outp(p, UART_EFR, 0);
462 serial_outp(p, UART_LCR, 0);
463 }
464 }
465}
466
467#ifdef CONFIG_SERIAL_8250_RSA
468/*
469 * Attempts to turn on the RSA FIFO. Returns zero on failure.
470 * We set the port uart clock rate if we succeed.
471 */
472static int __enable_rsa(struct uart_8250_port *up)
473{
474 unsigned char mode;
475 int result;
476
477 mode = serial_inp(up, UART_RSA_MSR);
478 result = mode & UART_RSA_MSR_FIFO;
479
480 if (!result) {
481 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
482 mode = serial_inp(up, UART_RSA_MSR);
483 result = mode & UART_RSA_MSR_FIFO;
484 }
485
486 if (result)
487 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
488
489 return result;
490}
491
492static void enable_rsa(struct uart_8250_port *up)
493{
494 if (up->port.type == PORT_RSA) {
495 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
496 spin_lock_irq(&up->port.lock);
497 __enable_rsa(up);
498 spin_unlock_irq(&up->port.lock);
499 }
500 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
501 serial_outp(up, UART_RSA_FRR, 0);
502 }
503}
504
505/*
506 * Attempts to turn off the RSA FIFO. Returns zero on failure.
507 * It is unknown why interrupts were disabled in here. However,
508 * the caller is expected to preserve this behaviour by grabbing
509 * the spinlock before calling this function.
510 */
511static void disable_rsa(struct uart_8250_port *up)
512{
513 unsigned char mode;
514 int result;
515
516 if (up->port.type == PORT_RSA &&
517 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
518 spin_lock_irq(&up->port.lock);
519
520 mode = serial_inp(up, UART_RSA_MSR);
521 result = !(mode & UART_RSA_MSR_FIFO);
522
523 if (!result) {
524 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
525 mode = serial_inp(up, UART_RSA_MSR);
526 result = !(mode & UART_RSA_MSR_FIFO);
527 }
528
529 if (result)
530 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
531 spin_unlock_irq(&up->port.lock);
532 }
533}
534#endif /* CONFIG_SERIAL_8250_RSA */
535
536/*
537 * This is a quickie test to see how big the FIFO is.
538 * It doesn't work at all the time, more's the pity.
539 */
540static int size_fifo(struct uart_8250_port *up)
541{
b32b19b8
JAH		 542 unsigned char old_fcr, old_mcr, old_lcr;
543 unsigned short old_dl;
1da177e4
LT		 544 int count;
545
546 old_lcr = serial_inp(up, UART_LCR);
547 serial_outp(up, UART_LCR, 0);
548 old_fcr = serial_inp(up, UART_FCR);
549 old_mcr = serial_inp(up, UART_MCR);
550 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
551 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
552 serial_outp(up, UART_MCR, UART_MCR_LOOP);
553 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 554 old_dl = serial_dl_read(up);
555 serial_dl_write(up, 0x0001);
1da177e4
LT		 556 serial_outp(up, UART_LCR, 0x03);
557 for (count = 0; count < 256; count++)
558 serial_outp(up, UART_TX, count);
559 mdelay(20);/* FIXME - schedule_timeout */
560 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
561 (count < 256); count++)
562 serial_inp(up, UART_RX);
563 serial_outp(up, UART_FCR, old_fcr);
564 serial_outp(up, UART_MCR, old_mcr);
565 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 566 serial_dl_write(up, old_dl);
1da177e4
LT		 567 serial_outp(up, UART_LCR, old_lcr);
568
569 return count;
570}
571
572/*
573 * Read UART ID using the divisor method - set DLL and DLM to zero
574 * and the revision will be in DLL and device type in DLM. We
575 * preserve the device state across this.
576 */
577static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
578{
579 unsigned char old_dll, old_dlm, old_lcr;
580 unsigned int id;
581
582 old_lcr = serial_inp(p, UART_LCR);
583 serial_outp(p, UART_LCR, UART_LCR_DLAB);
584
585 old_dll = serial_inp(p, UART_DLL);
586 old_dlm = serial_inp(p, UART_DLM);
587
588 serial_outp(p, UART_DLL, 0);
589 serial_outp(p, UART_DLM, 0);
590
591 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
592
593 serial_outp(p, UART_DLL, old_dll);
594 serial_outp(p, UART_DLM, old_dlm);
595 serial_outp(p, UART_LCR, old_lcr);
596
597 return id;
598}
599
600/*
601 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
602 * When this function is called we know it is at least a StarTech
603 * 16650 V2, but it might be one of several StarTech UARTs, or one of
604 * its clones. (We treat the broken original StarTech 16650 V1 as a
605 * 16550, and why not? Startech doesn't seem to even acknowledge its
606 * existence.)
607 *
608 * What evil have men's minds wrought...
609 */
610static void autoconfig_has_efr(struct uart_8250_port *up)
611{
612 unsigned int id1, id2, id3, rev;
613
614 /*
615 * Everything with an EFR has SLEEP
616 */
617 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
618
619 /*
620 * First we check to see if it's an Oxford Semiconductor UART.
621 *
622 * If we have to do this here because some non-National
623 * Semiconductor clone chips lock up if you try writing to the
624 * LSR register (which serial_icr_read does)
625 */
626
627 /*
628 * Check for Oxford Semiconductor 16C950.
629 *
630 * EFR [4] must be set else this test fails.
631 *
632 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
633 * claims that it's needed for 952 dual UART's (which are not
634 * recommended for new designs).
635 */
636 up->acr = 0;
637 serial_out(up, UART_LCR, 0xBF);
638 serial_out(up, UART_EFR, UART_EFR_ECB);
639 serial_out(up, UART_LCR, 0x00);
640 id1 = serial_icr_read(up, UART_ID1);
641 id2 = serial_icr_read(up, UART_ID2);
642 id3 = serial_icr_read(up, UART_ID3);
643 rev = serial_icr_read(up, UART_REV);
644
645 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
646
647 if (id1 == 0x16 && id2 == 0xC9 &&
648 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
649 up->port.type = PORT_16C950;
4ba5e35d
RK		 650
651 /*
652 * Enable work around for the Oxford Semiconductor 952 rev B
653 * chip which causes it to seriously miscalculate baud rates
654 * when DLL is 0.
655 */
656 if (id3 == 0x52 && rev == 0x01)
657 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 658 return;
659 }
660
661 /*
662 * We check for a XR16C850 by setting DLL and DLM to 0, and then
663 * reading back DLL and DLM. The chip type depends on the DLM
664 * value read back:
665 * 0x10 - XR16C850 and the DLL contains the chip revision.
666 * 0x12 - XR16C2850.
667 * 0x14 - XR16C854.
668 */
669 id1 = autoconfig_read_divisor_id(up);
670 DEBUG_AUTOCONF("850id=%04x ", id1);
671
672 id2 = id1 >> 8;
673 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 674 up->port.type = PORT_16850;
675 return;
676 }
677
678 /*
679 * It wasn't an XR16C850.
680 *
681 * We distinguish between the '654 and the '650 by counting
682 * how many bytes are in the FIFO. I'm using this for now,
683 * since that's the technique that was sent to me in the
684 * serial driver update, but I'm not convinced this works.
685 * I've had problems doing this in the past. -TYT
686 */
687 if (size_fifo(up) == 64)
688 up->port.type = PORT_16654;
689 else
690 up->port.type = PORT_16650V2;
691}
692
693/*
694 * We detected a chip without a FIFO. Only two fall into
695 * this category - the original 8250 and the 16450. The
696 * 16450 has a scratch register (accessible with LCR=0)
697 */
698static void autoconfig_8250(struct uart_8250_port *up)
699{
700 unsigned char scratch, status1, status2;
701
702 up->port.type = PORT_8250;
703
704 scratch = serial_in(up, UART_SCR);
705 serial_outp(up, UART_SCR, 0xa5);
706 status1 = serial_in(up, UART_SCR);
707 serial_outp(up, UART_SCR, 0x5a);
708 status2 = serial_in(up, UART_SCR);
709 serial_outp(up, UART_SCR, scratch);
710
711 if (status1 == 0xa5 && status2 == 0x5a)
712 up->port.type = PORT_16450;
713}
714
715static int broken_efr(struct uart_8250_port *up)
716{
717 /*
718 * Exar ST16C2550 "A2" devices incorrectly detect as
719 * having an EFR, and report an ID of 0x0201. See
720 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
721 */
722 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
723 return 1;
724
725 return 0;
726}
727
728/*
729 * We know that the chip has FIFOs. Does it have an EFR? The
730 * EFR is located in the same register position as the IIR and
731 * we know the top two bits of the IIR are currently set. The
732 * EFR should contain zero. Try to read the EFR.
733 */
734static void autoconfig_16550a(struct uart_8250_port *up)
735{
736 unsigned char status1, status2;
737 unsigned int iersave;
738
739 up->port.type = PORT_16550A;
740 up->capabilities |= UART_CAP_FIFO;
741
742 /*
743 * Check for presence of the EFR when DLAB is set.
744 * Only ST16C650V1 UARTs pass this test.
745 */
746 serial_outp(up, UART_LCR, UART_LCR_DLAB);
747 if (serial_in(up, UART_EFR) == 0) {
748 serial_outp(up, UART_EFR, 0xA8);
749 if (serial_in(up, UART_EFR) != 0) {
750 DEBUG_AUTOCONF("EFRv1 ");
751 up->port.type = PORT_16650;
752 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
753 } else {
754 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
755 }
756 serial_outp(up, UART_EFR, 0);
757 return;
758 }
759
760 /*
761 * Maybe it requires 0xbf to be written to the LCR.
762 * (other ST16C650V2 UARTs, TI16C752A, etc)
763 */
764 serial_outp(up, UART_LCR, 0xBF);
765 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
766 DEBUG_AUTOCONF("EFRv2 ");
767 autoconfig_has_efr(up);
768 return;
769 }
770
771 /*
772 * Check for a National Semiconductor SuperIO chip.
773 * Attempt to switch to bank 2, read the value of the LOOP bit
774 * from EXCR1. Switch back to bank 0, change it in MCR. Then
775 * switch back to bank 2, read it from EXCR1 again and check
776 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 777 */
778 serial_outp(up, UART_LCR, 0);
779 status1 = serial_in(up, UART_MCR);
780 serial_outp(up, UART_LCR, 0xE0);
781 status2 = serial_in(up, 0x02); /* EXCR1 */
782
783 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
784 serial_outp(up, UART_LCR, 0);
785 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
786 serial_outp(up, UART_LCR, 0xE0);
787 status2 = serial_in(up, 0x02); /* EXCR1 */
788 serial_outp(up, UART_LCR, 0);
789 serial_outp(up, UART_MCR, status1);
790
791 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 792 unsigned short quot;
793
1da177e4 794 serial_outp(up, UART_LCR, 0xE0);
857dde2e 795
b32b19b8 796 quot = serial_dl_read(up);
857dde2e
DW		 797 quot <<= 3;
798
1da177e4
LT		 799 status1 = serial_in(up, 0x04); /* EXCR1 */
800 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
801 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
802 serial_outp(up, 0x04, status1);
857dde2e 803
b32b19b8 804 serial_dl_write(up, quot);
857dde2e 805
1da177e4 806 serial_outp(up, UART_LCR, 0);
1da177e4 807
857dde2e 808 up->port.uartclk = 921600*16;
1da177e4
LT		 809 up->port.type = PORT_NS16550A;
810 up->capabilities |= UART_NATSEMI;
811 return;
812 }
813 }
814
815 /*
816 * No EFR. Try to detect a TI16750, which only sets bit 5 of
817 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
818 * Try setting it with and without DLAB set. Cheap clones
819 * set bit 5 without DLAB set.
820 */
821 serial_outp(up, UART_LCR, 0);
822 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
823 status1 = serial_in(up, UART_IIR) >> 5;
824 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
825 serial_outp(up, UART_LCR, UART_LCR_DLAB);
826 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
827 status2 = serial_in(up, UART_IIR) >> 5;
828 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
829 serial_outp(up, UART_LCR, 0);
830
831 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
832
833 if (status1 == 6 && status2 == 7) {
834 up->port.type = PORT_16750;
835 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
836 return;
837 }
838
839 /*
840 * Try writing and reading the UART_IER_UUE bit (b6).
841 * If it works, this is probably one of the Xscale platform's
842 * internal UARTs.
843 * We're going to explicitly set the UUE bit to 0 before
844 * trying to write and read a 1 just to make sure it's not
845 * already a 1 and maybe locked there before we even start start.
846 */
847 iersave = serial_in(up, UART_IER);
848 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
849 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
850 /*
851 * OK it's in a known zero state, try writing and reading
852 * without disturbing the current state of the other bits.
853 */
854 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
855 if (serial_in(up, UART_IER) & UART_IER_UUE) {
856 /*
857 * It's an Xscale.
858 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
859 */
860 DEBUG_AUTOCONF("Xscale ");
861 up->port.type = PORT_XSCALE;
862 up->capabilities |= UART_CAP_UUE;
863 return;
864 }
865 } else {
866 /*
867 * If we got here we couldn't force the IER_UUE bit to 0.
868 * Log it and continue.
869 */
870 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
871 }
872 serial_outp(up, UART_IER, iersave);
873}
874
875/*
876 * This routine is called by rs_init() to initialize a specific serial
877 * port. It determines what type of UART chip this serial port is
878 * using: 8250, 16450, 16550, 16550A. The important question is
879 * whether or not this UART is a 16550A or not, since this will
880 * determine whether or not we can use its FIFO features or not.
881 */
882static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
883{
884 unsigned char status1, scratch, scratch2, scratch3;
885 unsigned char save_lcr, save_mcr;
886 unsigned long flags;
887
888 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
889 return;
890
891 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
892 up->port.line, up->port.iobase, up->port.membase);
893
894 /*
895 * We really do need global IRQs disabled here - we're going to
896 * be frobbing the chips IRQ enable register to see if it exists.
897 */
898 spin_lock_irqsave(&up->port.lock, flags);
899// save_flags(flags); cli();
900
901 up->capabilities = 0;
4ba5e35d 902 up->bugs = 0;
1da177e4
LT		 903
904 if (!(up->port.flags & UPF_BUGGY_UART)) {
905 /*
906 * Do a simple existence test first; if we fail this,
907 * there's no point trying anything else.
908 *
909 * 0x80 is used as a nonsense port to prevent against
910 * false positives due to ISA bus float. The
911 * assumption is that 0x80 is a non-existent port;
912 * which should be safe since include/asm/io.h also
913 * makes this assumption.
914 *
915 * Note: this is safe as long as MCR bit 4 is clear
916 * and the device is in "PC" mode.
917 */
918 scratch = serial_inp(up, UART_IER);
919 serial_outp(up, UART_IER, 0);
920#ifdef __i386__
921 outb(0xff, 0x080);
922#endif
48212008
TH		 923 /*
924 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
925 * 16C754B) allow only to modify them if an EFR bit is set.
926 */
927 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 928 serial_outp(up, UART_IER, 0x0F);
929#ifdef __i386__
930 outb(0, 0x080);
931#endif
48212008 932 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 933 serial_outp(up, UART_IER, scratch);
934 if (scratch2 != 0 || scratch3 != 0x0F) {
935 /*
936 * We failed; there's nothing here
937 */
938 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
939 scratch2, scratch3);
940 goto out;
941 }
942 }
943
944 save_mcr = serial_in(up, UART_MCR);
945 save_lcr = serial_in(up, UART_LCR);
946
947 /*
948 * Check to see if a UART is really there. Certain broken
949 * internal modems based on the Rockwell chipset fail this
950 * test, because they apparently don't implement the loopback
951 * test mode. So this test is skipped on the COM 1 through
952 * COM 4 ports. This *should* be safe, since no board
953 * manufacturer would be stupid enough to design a board
954 * that conflicts with COM 1-4 --- we hope!
955 */
956 if (!(up->port.flags & UPF_SKIP_TEST)) {
957 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
958 status1 = serial_inp(up, UART_MSR) & 0xF0;
959 serial_outp(up, UART_MCR, save_mcr);
960 if (status1 != 0x90) {
961 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
962 status1);
963 goto out;
964 }
965 }
966
967 /*
968 * We're pretty sure there's a port here. Lets find out what
969 * type of port it is. The IIR top two bits allows us to find
6f0d618f 970 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 971 * determines what we test for next.
972 *
973 * We also initialise the EFR (if any) to zero for later. The
974 * EFR occupies the same register location as the FCR and IIR.
975 */
976 serial_outp(up, UART_LCR, 0xBF);
977 serial_outp(up, UART_EFR, 0);
978 serial_outp(up, UART_LCR, 0);
979
980 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
981 scratch = serial_in(up, UART_IIR) >> 6;
982
983 DEBUG_AUTOCONF("iir=%d ", scratch);
984
985 switch (scratch) {
986 case 0:
987 autoconfig_8250(up);
988 break;
989 case 1:
990 up->port.type = PORT_UNKNOWN;
991 break;
992 case 2:
993 up->port.type = PORT_16550;
994 break;
995 case 3:
996 autoconfig_16550a(up);
997 break;
998 }
999
1000#ifdef CONFIG_SERIAL_8250_RSA
1001 /*
1002 * Only probe for RSA ports if we got the region.
1003 */
1004 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1005 int i;
1006
1007 for (i = 0 ; i < probe_rsa_count; ++i) {
1008 if (probe_rsa[i] == up->port.iobase &&
1009 __enable_rsa(up)) {
1010 up->port.type = PORT_RSA;
1011 break;
1012 }
1013 }
1014 }
1015#endif
21c614a7
PA		 1016
1017#ifdef CONFIG_SERIAL_8250_AU1X00
1018 /* if access method is AU, it is a 16550 with a quirk */
1019 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1020 up->bugs |= UART_BUG_NOMSR;
1021#endif
1022
1da177e4
LT		 1023 serial_outp(up, UART_LCR, save_lcr);
1024
1025 if (up->capabilities != uart_config[up->port.type].flags) {
1026 printk(KERN_WARNING
1027 "ttyS%d: detected caps %08x should be %08x\n",
1028 up->port.line, up->capabilities,
1029 uart_config[up->port.type].flags);
1030 }
1031
1032 up->port.fifosize = uart_config[up->port.type].fifo_size;
1033 up->capabilities = uart_config[up->port.type].flags;
1034 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1035
1036 if (up->port.type == PORT_UNKNOWN)
1037 goto out;
1038
1039 /*
1040 * Reset the UART.
1041 */
1042#ifdef CONFIG_SERIAL_8250_RSA
1043 if (up->port.type == PORT_RSA)
1044 serial_outp(up, UART_RSA_FRR, 0);
1045#endif
1046 serial_outp(up, UART_MCR, save_mcr);
1047 serial8250_clear_fifos(up);
1048 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1049 if (up->capabilities & UART_CAP_UUE)
1050 serial_outp(up, UART_IER, UART_IER_UUE);
1051 else
1052 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1053
1054 out:
1055 spin_unlock_irqrestore(&up->port.lock, flags);
1056// restore_flags(flags);
1057 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1058}
1059
1060static void autoconfig_irq(struct uart_8250_port *up)
1061{
1062 unsigned char save_mcr, save_ier;
1063 unsigned char save_ICP = 0;
1064 unsigned int ICP = 0;
1065 unsigned long irqs;
1066 int irq;
1067
1068 if (up->port.flags & UPF_FOURPORT) {
1069 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1070 save_ICP = inb_p(ICP);
1071 outb_p(0x80, ICP);
1072 (void) inb_p(ICP);
1073 }
1074
1075 /* forget possible initially masked and pending IRQ */
1076 probe_irq_off(probe_irq_on());
1077 save_mcr = serial_inp(up, UART_MCR);
1078 save_ier = serial_inp(up, UART_IER);
1079 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1080
1081 irqs = probe_irq_on();
1082 serial_outp(up, UART_MCR, 0);
1083 udelay (10);
1084 if (up->port.flags & UPF_FOURPORT) {
1085 serial_outp(up, UART_MCR,
1086 UART_MCR_DTR | UART_MCR_RTS);
1087 } else {
1088 serial_outp(up, UART_MCR,
1089 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1090 }
1091 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1092 (void)serial_inp(up, UART_LSR);
1093 (void)serial_inp(up, UART_RX);
1094 (void)serial_inp(up, UART_IIR);
1095 (void)serial_inp(up, UART_MSR);
1096 serial_outp(up, UART_TX, 0xFF);
1097 udelay (20);
1098 irq = probe_irq_off(irqs);
1099
1100 serial_outp(up, UART_MCR, save_mcr);
1101 serial_outp(up, UART_IER, save_ier);
1102
1103 if (up->port.flags & UPF_FOURPORT)
1104 outb_p(save_ICP, ICP);
1105
1106 up->port.irq = (irq > 0) ? irq : 0;
1107}
1108
e763b90c
RK		 1109static inline void __stop_tx(struct uart_8250_port *p)
1110{
1111 if (p->ier & UART_IER_THRI) {
1112 p->ier &= ~UART_IER_THRI;
1113 serial_out(p, UART_IER, p->ier);
1114 }
1115}
1116
b129a8cc 1117static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1118{
1119 struct uart_8250_port *up = (struct uart_8250_port *)port;
1120
e763b90c 1121 __stop_tx(up);
1da177e4
LT		 1122
1123 /*
e763b90c 1124 * We really want to stop the transmitter from sending.
1da177e4 1125 */
e763b90c 1126 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1127 up->acr |= UART_ACR_TXDIS;
1128 serial_icr_write(up, UART_ACR, up->acr);
1129 }
1130}
1131
55d3b282
RK		 1132static void transmit_chars(struct uart_8250_port *up);
1133
b129a8cc 1134static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1135{
1136 struct uart_8250_port *up = (struct uart_8250_port *)port;
1137
1138 if (!(up->ier & UART_IER_THRI)) {
1139 up->ier |= UART_IER_THRI;
1140 serial_out(up, UART_IER, up->ier);
55d3b282 1141
67f7654e 1142 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1143 unsigned char lsr, iir;
1144 lsr = serial_in(up, UART_LSR);
1145 iir = serial_in(up, UART_IIR);
1146 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1147 transmit_chars(up);
1148 }
1da177e4 1149 }
e763b90c 1150
1da177e4 1151 /*
e763b90c 1152 * Re-enable the transmitter if we disabled it.
1da177e4 1153 */
e763b90c 1154 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1155 up->acr &= ~UART_ACR_TXDIS;
1156 serial_icr_write(up, UART_ACR, up->acr);
1157 }
1158}
1159
1160static void serial8250_stop_rx(struct uart_port *port)
1161{
1162 struct uart_8250_port *up = (struct uart_8250_port *)port;
1163
1164 up->ier &= ~UART_IER_RLSI;
1165 up->port.read_status_mask &= ~UART_LSR_DR;
1166 serial_out(up, UART_IER, up->ier);
1167}
1168
1169static void serial8250_enable_ms(struct uart_port *port)
1170{
1171 struct uart_8250_port *up = (struct uart_8250_port *)port;
1172
21c614a7
PA		 1173 /* no MSR capabilities */
1174 if (up->bugs & UART_BUG_NOMSR)
1175 return;
1176
1da177e4
LT		 1177 up->ier |= UART_IER_MSI;
1178 serial_out(up, UART_IER, up->ier);
1179}
1180
ea8874dc 1181static void
7d12e780 1182receive_chars(struct uart_8250_port *up, int *status)
1da177e4
LT		 1183{
1184 struct tty_struct *tty = up->port.info->tty;
1185 unsigned char ch, lsr = *status;
1186 int max_count = 256;
1187 char flag;
1188
1189 do {
1da177e4
LT		 1190 ch = serial_inp(up, UART_RX);
1191 flag = TTY_NORMAL;
1192 up->port.icount.rx++;
1193
1194#ifdef CONFIG_SERIAL_8250_CONSOLE
1195 /*
1196 * Recover the break flag from console xmit
1197 */
1198 if (up->port.line == up->port.cons->index) {
1199 lsr |= up->lsr_break_flag;
1200 up->lsr_break_flag = 0;
1201 }
1202#endif
1203
1204 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1205 UART_LSR_FE | UART_LSR_OE))) {
1206 /*
1207 * For statistics only
1208 */
1209 if (lsr & UART_LSR_BI) {
1210 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1211 up->port.icount.brk++;
1212 /*
1213 * We do the SysRQ and SAK checking
1214 * here because otherwise the break
1215 * may get masked by ignore_status_mask
1216 * or read_status_mask.
1217 */
1218 if (uart_handle_break(&up->port))
1219 goto ignore_char;
1220 } else if (lsr & UART_LSR_PE)
1221 up->port.icount.parity++;
1222 else if (lsr & UART_LSR_FE)
1223 up->port.icount.frame++;
1224 if (lsr & UART_LSR_OE)
1225 up->port.icount.overrun++;
1226
1227 /*
23907eb8 1228 * Mask off conditions which should be ignored.
1da177e4
LT		 1229 */
1230 lsr &= up->port.read_status_mask;
1231
1232 if (lsr & UART_LSR_BI) {
1233 DEBUG_INTR("handling break....");
1234 flag = TTY_BREAK;
1235 } else if (lsr & UART_LSR_PE)
1236 flag = TTY_PARITY;
1237 else if (lsr & UART_LSR_FE)
1238 flag = TTY_FRAME;
1239 }
7d12e780 1240 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1241 goto ignore_char;
05ab3014
RK		 1242
1243 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1244
1da177e4
LT		 1245 ignore_char:
1246 lsr = serial_inp(up, UART_LSR);
1247 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1248 spin_unlock(&up->port.lock);
1249 tty_flip_buffer_push(tty);
1250 spin_lock(&up->port.lock);
1251 *status = lsr;
1252}
1253
ea8874dc 1254static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1255{
1256 struct circ_buf *xmit = &up->port.info->xmit;
1257 int count;
1258
1259 if (up->port.x_char) {
1260 serial_outp(up, UART_TX, up->port.x_char);
1261 up->port.icount.tx++;
1262 up->port.x_char = 0;
1263 return;
1264 }
b129a8cc
RK		 1265 if (uart_tx_stopped(&up->port)) {
1266 serial8250_stop_tx(&up->port);
1267 return;
1268 }
1269 if (uart_circ_empty(xmit)) {
e763b90c 1270 __stop_tx(up);
1da177e4
LT		 1271 return;
1272 }
1273
1274 count = up->tx_loadsz;
1275 do {
1276 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1277 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1278 up->port.icount.tx++;
1279 if (uart_circ_empty(xmit))
1280 break;
1281 } while (--count > 0);
1282
1283 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1284 uart_write_wakeup(&up->port);
1285
1286 DEBUG_INTR("THRE...");
1287
1288 if (uart_circ_empty(xmit))
e763b90c 1289 __stop_tx(up);
1da177e4
LT		 1290}
1291
2af7cd68 1292static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1293{
2af7cd68
RK		 1294 unsigned int status = serial_in(up, UART_MSR);
1295
1296 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1297 if (status & UART_MSR_TERI)
1298 up->port.icount.rng++;
1299 if (status & UART_MSR_DDSR)
1300 up->port.icount.dsr++;
1301 if (status & UART_MSR_DDCD)
1302 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1303 if (status & UART_MSR_DCTS)
1304 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1305
1306 wake_up_interruptible(&up->port.info->delta_msr_wait);
1307 }
1da177e4 1308
2af7cd68 1309 return status;
1da177e4
LT		 1310}
1311
1312/*
1313 * This handles the interrupt from one port.
1314 */
1315static inline void
7d12e780 1316serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1317{
45e24601
RK		 1318 unsigned int status;
1319
1320 spin_lock(&up->port.lock);
1321
1322 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1323
1324 DEBUG_INTR("status = %x...", status);
1325
1326 if (status & UART_LSR_DR)
7d12e780 1327 receive_chars(up, &status);
1da177e4
LT		 1328 check_modem_status(up);
1329 if (status & UART_LSR_THRE)
1330 transmit_chars(up);
45e24601
RK		 1331
1332 spin_unlock(&up->port.lock);
1da177e4
LT		 1333}
1334
1335/*
1336 * This is the serial driver's interrupt routine.
1337 *
1338 * Arjan thinks the old way was overly complex, so it got simplified.
1339 * Alan disagrees, saying that need the complexity to handle the weird
1340 * nature of ISA shared interrupts. (This is a special exception.)
1341 *
1342 * In order to handle ISA shared interrupts properly, we need to check
1343 * that all ports have been serviced, and therefore the ISA interrupt
1344 * line has been de-asserted.
1345 *
1346 * This means we need to loop through all ports. checking that they
1347 * don't have an interrupt pending.
1348 */
7d12e780 1349static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1350{
1351 struct irq_info *i = dev_id;
1352 struct list_head *l, *end = NULL;
1353 int pass_counter = 0, handled = 0;
1354
1355 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1356
1357 spin_lock(&i->lock);
1358
1359 l = i->head;
1360 do {
1361 struct uart_8250_port *up;
1362 unsigned int iir;
1363
1364 up = list_entry(l, struct uart_8250_port, list);
1365
1366 iir = serial_in(up, UART_IIR);
1367 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1368 serial8250_handle_port(up);
1da177e4
LT		 1369
1370 handled = 1;
1371
1372 end = NULL;
1373 } else if (end == NULL)
1374 end = l;
1375
1376 l = l->next;
1377
1378 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1379 /* If we hit this, we're dead. */
1380 printk(KERN_ERR "serial8250: too much work for "
1381 "irq%d\n", irq);
1382 break;
1383 }
1384 } while (l != end);
1385
1386 spin_unlock(&i->lock);
1387
1388 DEBUG_INTR("end.\n");
1389
1390 return IRQ_RETVAL(handled);
1391}
1392
1393/*
1394 * To support ISA shared interrupts, we need to have one interrupt
1395 * handler that ensures that the IRQ line has been deasserted
1396 * before returning. Failing to do this will result in the IRQ
1397 * line being stuck active, and, since ISA irqs are edge triggered,
1398 * no more IRQs will be seen.
1399 */
1400static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1401{
1402 spin_lock_irq(&i->lock);
1403
1404 if (!list_empty(i->head)) {
1405 if (i->head == &up->list)
1406 i->head = i->head->next;
1407 list_del(&up->list);
1408 } else {
1409 BUG_ON(i->head != &up->list);
1410 i->head = NULL;
1411 }
1412
1413 spin_unlock_irq(&i->lock);
1414}
1415
1416static int serial_link_irq_chain(struct uart_8250_port *up)
1417{
1418 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1419 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1420
1421 spin_lock_irq(&i->lock);
1422
1423 if (i->head) {
1424 list_add(&up->list, i->head);
1425 spin_unlock_irq(&i->lock);
1426
1427 ret = 0;
1428 } else {
1429 INIT_LIST_HEAD(&up->list);
1430 i->head = &up->list;
1431 spin_unlock_irq(&i->lock);
1432
1433 ret = request_irq(up->port.irq, serial8250_interrupt,
1434 irq_flags, "serial", i);
1435 if (ret < 0)
1436 serial_do_unlink(i, up);
1437 }
1438
1439 return ret;
1440}
1441
1442static void serial_unlink_irq_chain(struct uart_8250_port *up)
1443{
1444 struct irq_info *i = irq_lists + up->port.irq;
1445
1446 BUG_ON(i->head == NULL);
1447
1448 if (list_empty(i->head))
1449 free_irq(up->port.irq, i);
1450
1451 serial_do_unlink(i, up);
1452}
1453
1454/*
1455 * This function is used to handle ports that do not have an
1456 * interrupt. This doesn't work very well for 16450's, but gives
1457 * barely passable results for a 16550A. (Although at the expense
1458 * of much CPU overhead).
1459 */
1460static void serial8250_timeout(unsigned long data)
1461{
1462 struct uart_8250_port *up = (struct uart_8250_port *)data;
1463 unsigned int timeout;
1464 unsigned int iir;
1465
1466 iir = serial_in(up, UART_IIR);
45e24601 1467 if (!(iir & UART_IIR_NO_INT))
7d12e780 1468 serial8250_handle_port(up);
1da177e4
LT		 1469
1470 timeout = up->port.timeout;
1471 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1472 mod_timer(&up->timer, jiffies + timeout);
1473}
1474
1475static unsigned int serial8250_tx_empty(struct uart_port *port)
1476{
1477 struct uart_8250_port *up = (struct uart_8250_port *)port;
1478 unsigned long flags;
1479 unsigned int ret;
1480
1481 spin_lock_irqsave(&up->port.lock, flags);
1482 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1483 spin_unlock_irqrestore(&up->port.lock, flags);
1484
1485 return ret;
1486}
1487
1488static unsigned int serial8250_get_mctrl(struct uart_port *port)
1489{
1490 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1491 unsigned int status;
1da177e4
LT		 1492 unsigned int ret;
1493
2af7cd68 1494 status = check_modem_status(up);
1da177e4
LT		 1495
1496 ret = 0;
1497 if (status & UART_MSR_DCD)
1498 ret |= TIOCM_CAR;
1499 if (status & UART_MSR_RI)
1500 ret |= TIOCM_RNG;
1501 if (status & UART_MSR_DSR)
1502 ret |= TIOCM_DSR;
1503 if (status & UART_MSR_CTS)
1504 ret |= TIOCM_CTS;
1505 return ret;
1506}
1507
1508static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1509{
1510 struct uart_8250_port *up = (struct uart_8250_port *)port;
1511 unsigned char mcr = 0;
1512
1513 if (mctrl & TIOCM_RTS)
1514 mcr |= UART_MCR_RTS;
1515 if (mctrl & TIOCM_DTR)
1516 mcr |= UART_MCR_DTR;
1517 if (mctrl & TIOCM_OUT1)
1518 mcr |= UART_MCR_OUT1;
1519 if (mctrl & TIOCM_OUT2)
1520 mcr |= UART_MCR_OUT2;
1521 if (mctrl & TIOCM_LOOP)
1522 mcr |= UART_MCR_LOOP;
1523
1524 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1525
1526 serial_out(up, UART_MCR, mcr);
1527}
1528
1529static void serial8250_break_ctl(struct uart_port *port, int break_state)
1530{
1531 struct uart_8250_port *up = (struct uart_8250_port *)port;
1532 unsigned long flags;
1533
1534 spin_lock_irqsave(&up->port.lock, flags);
1535 if (break_state == -1)
1536 up->lcr |= UART_LCR_SBC;
1537 else
1538 up->lcr &= ~UART_LCR_SBC;
1539 serial_out(up, UART_LCR, up->lcr);
1540 spin_unlock_irqrestore(&up->port.lock, flags);
1541}
1542
1543static int serial8250_startup(struct uart_port *port)
1544{
1545 struct uart_8250_port *up = (struct uart_8250_port *)port;
1546 unsigned long flags;
55d3b282 1547 unsigned char lsr, iir;
1da177e4
LT		 1548 int retval;
1549
1550 up->capabilities = uart_config[up->port.type].flags;
1551 up->mcr = 0;
1552
1553 if (up->port.type == PORT_16C950) {
1554 /* Wake up and initialize UART */
1555 up->acr = 0;
1556 serial_outp(up, UART_LCR, 0xBF);
1557 serial_outp(up, UART_EFR, UART_EFR_ECB);
1558 serial_outp(up, UART_IER, 0);
1559 serial_outp(up, UART_LCR, 0);
1560 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1561 serial_outp(up, UART_LCR, 0xBF);
1562 serial_outp(up, UART_EFR, UART_EFR_ECB);
1563 serial_outp(up, UART_LCR, 0);
1564 }
1565
1566#ifdef CONFIG_SERIAL_8250_RSA
1567 /*
1568 * If this is an RSA port, see if we can kick it up to the
1569 * higher speed clock.
1570 */
1571 enable_rsa(up);
1572#endif
1573
1574 /*
1575 * Clear the FIFO buffers and disable them.
7f927fcc 1576 * (they will be reenabled in set_termios())
1da177e4
LT		 1577 */
1578 serial8250_clear_fifos(up);
1579
1580 /*
1581 * Clear the interrupt registers.
1582 */
1583 (void) serial_inp(up, UART_LSR);
1584 (void) serial_inp(up, UART_RX);
1585 (void) serial_inp(up, UART_IIR);
1586 (void) serial_inp(up, UART_MSR);
1587
1588 /*
1589 * At this point, there's no way the LSR could still be 0xff;
1590 * if it is, then bail out, because there's likely no UART
1591 * here.
1592 */
1593 if (!(up->port.flags & UPF_BUGGY_UART) &&
1594 (serial_inp(up, UART_LSR) == 0xff)) {
1595 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1596 return -ENODEV;
1597 }
1598
1599 /*
1600 * For a XR16C850, we need to set the trigger levels
1601 */
1602 if (up->port.type == PORT_16850) {
1603 unsigned char fctr;
1604
1605 serial_outp(up, UART_LCR, 0xbf);
1606
1607 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1608 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1609 serial_outp(up, UART_TRG, UART_TRG_96);
1610 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1611 serial_outp(up, UART_TRG, UART_TRG_96);
1612
1613 serial_outp(up, UART_LCR, 0);
1614 }
1615
1616 /*
1617 * If the "interrupt" for this port doesn't correspond with any
1618 * hardware interrupt, we use a timer-based system. The original
1619 * driver used to do this with IRQ0.
1620 */
1621 if (!is_real_interrupt(up->port.irq)) {
1622 unsigned int timeout = up->port.timeout;
1623
1624 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1625
1626 up->timer.data = (unsigned long)up;
1627 mod_timer(&up->timer, jiffies + timeout);
1628 } else {
1629 retval = serial_link_irq_chain(up);
1630 if (retval)
1631 return retval;
1632 }
1633
1634 /*
1635 * Now, initialize the UART
1636 */
1637 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1638
1639 spin_lock_irqsave(&up->port.lock, flags);
1640 if (up->port.flags & UPF_FOURPORT) {
1641 if (!is_real_interrupt(up->port.irq))
1642 up->port.mctrl |= TIOCM_OUT1;
1643 } else
1644 /*
1645 * Most PC uarts need OUT2 raised to enable interrupts.
1646 */
1647 if (is_real_interrupt(up->port.irq))
1648 up->port.mctrl |= TIOCM_OUT2;
1649
1650 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1651
1652 /*
1653 * Do a quick test to see if we receive an
1654 * interrupt when we enable the TX irq.
1655 */
1656 serial_outp(up, UART_IER, UART_IER_THRI);
1657 lsr = serial_in(up, UART_LSR);
1658 iir = serial_in(up, UART_IIR);
1659 serial_outp(up, UART_IER, 0);
1660
1661 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1662 if (!(up->bugs & UART_BUG_TXEN)) {
1663 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1664 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1665 port->line);
1666 }
1667 } else {
67f7654e 1668 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1669 }
1670
1da177e4
LT		 1671 spin_unlock_irqrestore(&up->port.lock, flags);
1672
1673 /*
1674 * Finally, enable interrupts. Note: Modem status interrupts
1675 * are set via set_termios(), which will be occurring imminently
1676 * anyway, so we don't enable them here.
1677 */
1678 up->ier = UART_IER_RLSI | UART_IER_RDI;
1679 serial_outp(up, UART_IER, up->ier);
1680
1681 if (up->port.flags & UPF_FOURPORT) {
1682 unsigned int icp;
1683 /*
1684 * Enable interrupts on the AST Fourport board
1685 */
1686 icp = (up->port.iobase & 0xfe0) | 0x01f;
1687 outb_p(0x80, icp);
1688 (void) inb_p(icp);
1689 }
1690
1691 /*
1692 * And clear the interrupt registers again for luck.
1693 */
1694 (void) serial_inp(up, UART_LSR);
1695 (void) serial_inp(up, UART_RX);
1696 (void) serial_inp(up, UART_IIR);
1697 (void) serial_inp(up, UART_MSR);
1698
1699 return 0;
1700}
1701
1702static void serial8250_shutdown(struct uart_port *port)
1703{
1704 struct uart_8250_port *up = (struct uart_8250_port *)port;
1705 unsigned long flags;
1706
1707 /*
1708 * Disable interrupts from this port
1709 */
1710 up->ier = 0;
1711 serial_outp(up, UART_IER, 0);
1712
1713 spin_lock_irqsave(&up->port.lock, flags);
1714 if (up->port.flags & UPF_FOURPORT) {
1715 /* reset interrupts on the AST Fourport board */
1716 inb((up->port.iobase & 0xfe0) | 0x1f);
1717 up->port.mctrl |= TIOCM_OUT1;
1718 } else
1719 up->port.mctrl &= ~TIOCM_OUT2;
1720
1721 serial8250_set_mctrl(&up->port, up->port.mctrl);
1722 spin_unlock_irqrestore(&up->port.lock, flags);
1723
1724 /*
1725 * Disable break condition and FIFOs
1726 */
1727 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1728 serial8250_clear_fifos(up);
1729
1730#ifdef CONFIG_SERIAL_8250_RSA
1731 /*
1732 * Reset the RSA board back to 115kbps compat mode.
1733 */
1734 disable_rsa(up);
1735#endif
1736
1737 /*
1738 * Read data port to reset things, and then unlink from
1739 * the IRQ chain.
1740 */
1741 (void) serial_in(up, UART_RX);
1742
1743 if (!is_real_interrupt(up->port.irq))
1744 del_timer_sync(&up->timer);
1745 else
1746 serial_unlink_irq_chain(up);
1747}
1748
1749static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1750{
1751 unsigned int quot;
1752
1753 /*
1754 * Handle magic divisors for baud rates above baud_base on
1755 * SMSC SuperIO chips.
1756 */
1757 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1758 baud == (port->uartclk/4))
1759 quot = 0x8001;
1760 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1761 baud == (port->uartclk/8))
1762 quot = 0x8002;
1763 else
1764 quot = uart_get_divisor(port, baud);
1765
1766 return quot;
1767}
1768
1769static void
606d099c
AC		 1770serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
1771 struct ktermios *old)
1da177e4
LT		 1772{
1773 struct uart_8250_port *up = (struct uart_8250_port *)port;
1774 unsigned char cval, fcr = 0;
1775 unsigned long flags;
1776 unsigned int baud, quot;
1777
1778 switch (termios->c_cflag & CSIZE) {
1779 case CS5:
0a8b80c5 1780 cval = UART_LCR_WLEN5;
1da177e4
LT		 1781 break;
1782 case CS6:
0a8b80c5 1783 cval = UART_LCR_WLEN6;
1da177e4
LT		 1784 break;
1785 case CS7:
0a8b80c5 1786 cval = UART_LCR_WLEN7;
1da177e4
LT		 1787 break;
1788 default:
1789 case CS8:
0a8b80c5 1790 cval = UART_LCR_WLEN8;
1da177e4
LT		 1791 break;
1792 }
1793
1794 if (termios->c_cflag & CSTOPB)
0a8b80c5 1795 cval |= UART_LCR_STOP;
1da177e4
LT		 1796 if (termios->c_cflag & PARENB)
1797 cval |= UART_LCR_PARITY;
1798 if (!(termios->c_cflag & PARODD))
1799 cval |= UART_LCR_EPAR;
1800#ifdef CMSPAR
1801 if (termios->c_cflag & CMSPAR)
1802 cval |= UART_LCR_SPAR;
1803#endif
1804
1805 /*
1806 * Ask the core to calculate the divisor for us.
1807 */
1808 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1809 quot = serial8250_get_divisor(port, baud);
1810
1811 /*
4ba5e35d 1812 * Oxford Semi 952 rev B workaround
1da177e4 1813 */
4ba5e35d 1814 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1815 quot ++;
1816
1817 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1818 if (baud < 2400)
1819 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1820 else
1821 fcr = uart_config[up->port.type].fcr;
1822 }
1823
1824 /*
1825 * MCR-based auto flow control. When AFE is enabled, RTS will be
1826 * deasserted when the receive FIFO contains more characters than
1827 * the trigger, or the MCR RTS bit is cleared. In the case where
1828 * the remote UART is not using CTS auto flow control, we must
1829 * have sufficient FIFO entries for the latency of the remote
1830 * UART to respond. IOW, at least 32 bytes of FIFO.
1831 */
1832 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1833 up->mcr &= ~UART_MCR_AFE;
1834 if (termios->c_cflag & CRTSCTS)
1835 up->mcr |= UART_MCR_AFE;
1836 }
1837
1838 /*
1839 * Ok, we're now changing the port state. Do it with
1840 * interrupts disabled.
1841 */
1842 spin_lock_irqsave(&up->port.lock, flags);
1843
1844 /*
1845 * Update the per-port timeout.
1846 */
1847 uart_update_timeout(port, termios->c_cflag, baud);
1848
1849 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1850 if (termios->c_iflag & INPCK)
1851 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1852 if (termios->c_iflag & (BRKINT | PARMRK))
1853 up->port.read_status_mask |= UART_LSR_BI;
1854
1855 /*
1856 * Characteres to ignore
1857 */
1858 up->port.ignore_status_mask = 0;
1859 if (termios->c_iflag & IGNPAR)
1860 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1861 if (termios->c_iflag & IGNBRK) {
1862 up->port.ignore_status_mask |= UART_LSR_BI;
1863 /*
1864 * If we're ignoring parity and break indicators,
1865 * ignore overruns too (for real raw support).
1866 */
1867 if (termios->c_iflag & IGNPAR)
1868 up->port.ignore_status_mask |= UART_LSR_OE;
1869 }
1870
1871 /*
1872 * ignore all characters if CREAD is not set
1873 */
1874 if ((termios->c_cflag & CREAD) == 0)
1875 up->port.ignore_status_mask |= UART_LSR_DR;
1876
1877 /*
1878 * CTS flow control flag and modem status interrupts
1879 */
1880 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1881 if (!(up->bugs & UART_BUG_NOMSR) &&
1882 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1883 up->ier |= UART_IER_MSI;
1884 if (up->capabilities & UART_CAP_UUE)
1885 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1886
1887 serial_out(up, UART_IER, up->ier);
1888
1889 if (up->capabilities & UART_CAP_EFR) {
1890 unsigned char efr = 0;
1891 /*
1892 * TI16C752/Startech hardware flow control. FIXME:
1893 * - TI16C752 requires control thresholds to be set.
1894 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1895 */
1896 if (termios->c_cflag & CRTSCTS)
1897 efr |= UART_EFR_CTS;
1898
1899 serial_outp(up, UART_LCR, 0xBF);
1900 serial_outp(up, UART_EFR, efr);
1901 }
1902
255341c6
JM		 1903#ifdef CONFIG_ARCH_OMAP15XX
1904 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
1905 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
1906 if (baud == 115200) {
1907 quot = 1;
1908 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
1909 } else
1910 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
1911 }
1912#endif
1913
1da177e4
LT		 1914 if (up->capabilities & UART_NATSEMI) {
1915 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1916 serial_outp(up, UART_LCR, 0xe0);
1917 } else {
1918 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1919 }
1920
b32b19b8 1921 serial_dl_write(up, quot);
1da177e4
LT		 1922
1923 /*
1924 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1925 * is written without DLAB set, this mode will be disabled.
1926 */
1927 if (up->port.type == PORT_16750)
1928 serial_outp(up, UART_FCR, fcr);
1929
1930 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1931 up->lcr = cval; /* Save LCR */
1932 if (up->port.type != PORT_16750) {
1933 if (fcr & UART_FCR_ENABLE_FIFO) {
1934 /* emulated UARTs (Lucent Venus 167x) need two steps */
1935 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1936 }
1937 serial_outp(up, UART_FCR, fcr); /* set fcr */
1938 }
1939 serial8250_set_mctrl(&up->port, up->port.mctrl);
1940 spin_unlock_irqrestore(&up->port.lock, flags);
1941}
1942
1943static void
1944serial8250_pm(struct uart_port *port, unsigned int state,
1945 unsigned int oldstate)
1946{
1947 struct uart_8250_port *p = (struct uart_8250_port *)port;
1948
1949 serial8250_set_sleep(p, state != 0);
1950
1951 if (p->pm)
1952 p->pm(port, state, oldstate);
1953}
1954
1955/*
1956 * Resource handling.
1957 */
1958static int serial8250_request_std_resource(struct uart_8250_port *up)
1959{
1960 unsigned int size = 8 << up->port.regshift;
1961 int ret = 0;
1962
1963 switch (up->port.iotype) {
85835f44
SS		 1964 case UPIO_AU:
1965 size = 0x100000;
1966 /* fall thru */
0b30d668
SS		 1967 case UPIO_TSI:
1968 case UPIO_MEM32:
1da177e4
LT		 1969 case UPIO_MEM:
1970 if (!up->port.mapbase)
1971 break;
1972
1973 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1974 ret = -EBUSY;
1975 break;
1976 }
1977
1978 if (up->port.flags & UPF_IOREMAP) {
1979 up->port.membase = ioremap(up->port.mapbase, size);
1980 if (!up->port.membase) {
1981 release_mem_region(up->port.mapbase, size);
1982 ret = -ENOMEM;
1983 }
1984 }
1985 break;
1986
1987 case UPIO_HUB6:
1988 case UPIO_PORT:
1989 if (!request_region(up->port.iobase, size, "serial"))
1990 ret = -EBUSY;
1991 break;
1992 }
1993 return ret;
1994}
1995
1996static void serial8250_release_std_resource(struct uart_8250_port *up)
1997{
1998 unsigned int size = 8 << up->port.regshift;
1999
2000 switch (up->port.iotype) {
85835f44
SS		 2001 case UPIO_AU:
2002 size = 0x100000;
2003 /* fall thru */
0b30d668
SS		 2004 case UPIO_TSI:
2005 case UPIO_MEM32:
1da177e4
LT		 2006 case UPIO_MEM:
2007 if (!up->port.mapbase)
2008 break;
2009
2010 if (up->port.flags & UPF_IOREMAP) {
2011 iounmap(up->port.membase);
2012 up->port.membase = NULL;
2013 }
2014
2015 release_mem_region(up->port.mapbase, size);
2016 break;
2017
2018 case UPIO_HUB6:
2019 case UPIO_PORT:
2020 release_region(up->port.iobase, size);
2021 break;
2022 }
2023}
2024
2025static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2026{
2027 unsigned long start = UART_RSA_BASE << up->port.regshift;
2028 unsigned int size = 8 << up->port.regshift;
0b30d668 2029 int ret = -EINVAL;
1da177e4
LT		 2030
2031 switch (up->port.iotype) {
1da177e4
LT		 2032 case UPIO_HUB6:
2033 case UPIO_PORT:
2034 start += up->port.iobase;
0b30d668
SS		 2035 if (request_region(start, size, "serial-rsa"))
2036 ret = 0;
2037 else
1da177e4
LT		 2038 ret = -EBUSY;
2039 break;
2040 }
2041
2042 return ret;
2043}
2044
2045static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2046{
2047 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2048 unsigned int size = 8 << up->port.regshift;
2049
2050 switch (up->port.iotype) {
1da177e4
LT		 2051 case UPIO_HUB6:
2052 case UPIO_PORT:
2053 release_region(up->port.iobase + offset, size);
2054 break;
2055 }
2056}
2057
2058static void serial8250_release_port(struct uart_port *port)
2059{
2060 struct uart_8250_port *up = (struct uart_8250_port *)port;
2061
2062 serial8250_release_std_resource(up);
2063 if (up->port.type == PORT_RSA)
2064 serial8250_release_rsa_resource(up);
2065}
2066
2067static int serial8250_request_port(struct uart_port *port)
2068{
2069 struct uart_8250_port *up = (struct uart_8250_port *)port;
2070 int ret = 0;
2071
2072 ret = serial8250_request_std_resource(up);
2073 if (ret == 0 && up->port.type == PORT_RSA) {
2074 ret = serial8250_request_rsa_resource(up);
2075 if (ret < 0)
2076 serial8250_release_std_resource(up);
2077 }
2078
2079 return ret;
2080}
2081
2082static void serial8250_config_port(struct uart_port *port, int flags)
2083{
2084 struct uart_8250_port *up = (struct uart_8250_port *)port;
2085 int probeflags = PROBE_ANY;
2086 int ret;
2087
1da177e4
LT		 2088 /*
2089 * Find the region that we can probe for. This in turn
2090 * tells us whether we can probe for the type of port.
2091 */
2092 ret = serial8250_request_std_resource(up);
2093 if (ret < 0)
2094 return;
2095
2096 ret = serial8250_request_rsa_resource(up);
2097 if (ret < 0)
2098 probeflags &= ~PROBE_RSA;
2099
2100 if (flags & UART_CONFIG_TYPE)
2101 autoconfig(up, probeflags);
2102 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2103 autoconfig_irq(up);
2104
2105 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2106 serial8250_release_rsa_resource(up);
2107 if (up->port.type == PORT_UNKNOWN)
2108 serial8250_release_std_resource(up);
2109}
2110
2111static int
2112serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2113{
2114 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2115 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2116 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2117 ser->type == PORT_STARTECH)
2118 return -EINVAL;
2119 return 0;
2120}
2121
2122static const char *
2123serial8250_type(struct uart_port *port)
2124{
2125 int type = port->type;
2126
2127 if (type >= ARRAY_SIZE(uart_config))
2128 type = 0;
2129 return uart_config[type].name;
2130}
2131
2132static struct uart_ops serial8250_pops = {
2133 .tx_empty = serial8250_tx_empty,
2134 .set_mctrl = serial8250_set_mctrl,
2135 .get_mctrl = serial8250_get_mctrl,
2136 .stop_tx = serial8250_stop_tx,
2137 .start_tx = serial8250_start_tx,
2138 .stop_rx = serial8250_stop_rx,
2139 .enable_ms = serial8250_enable_ms,
2140 .break_ctl = serial8250_break_ctl,
2141 .startup = serial8250_startup,
2142 .shutdown = serial8250_shutdown,
2143 .set_termios = serial8250_set_termios,
2144 .pm = serial8250_pm,
2145 .type = serial8250_type,
2146 .release_port = serial8250_release_port,
2147 .request_port = serial8250_request_port,
2148 .config_port = serial8250_config_port,
2149 .verify_port = serial8250_verify_port,
2150};
2151
2152static struct uart_8250_port serial8250_ports[UART_NR];
2153
2154static void __init serial8250_isa_init_ports(void)
2155{
2156 struct uart_8250_port *up;
2157 static int first = 1;
2158 int i;
2159
2160 if (!first)
2161 return;
2162 first = 0;
2163
a61c2d78 2164 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2165 struct uart_8250_port *up = &serial8250_ports[i];
2166
2167 up->port.line = i;
2168 spin_lock_init(&up->port.lock);
2169
2170 init_timer(&up->timer);
2171 up->timer.function = serial8250_timeout;
2172
2173 /*
2174 * ALPHA_KLUDGE_MCR needs to be killed.
2175 */
2176 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2177 up->mcr_force = ALPHA_KLUDGE_MCR;
2178
2179 up->port.ops = &serial8250_pops;
2180 }
2181
44454bcd 2182 for (i = 0, up = serial8250_ports;
a61c2d78 2183 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2184 i++, up++) {
2185 up->port.iobase = old_serial_port[i].port;
2186 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2187 up->port.uartclk = old_serial_port[i].baud_base * 16;
2188 up->port.flags = old_serial_port[i].flags;
2189 up->port.hub6 = old_serial_port[i].hub6;
2190 up->port.membase = old_serial_port[i].iomem_base;
2191 up->port.iotype = old_serial_port[i].io_type;
2192 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2193 if (share_irqs)
2194 up->port.flags |= UPF_SHARE_IRQ;
2195 }
2196}
2197
2198static void __init
2199serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2200{
2201 int i;
2202
2203 serial8250_isa_init_ports();
2204
a61c2d78 2205 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2206 struct uart_8250_port *up = &serial8250_ports[i];
2207
2208 up->port.dev = dev;
2209 uart_add_one_port(drv, &up->port);
2210 }
2211}
2212
2213#ifdef CONFIG_SERIAL_8250_CONSOLE
2214
2215#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2216
2217/*
2218 * Wait for transmitter & holding register to empty
2219 */
f91a3715 2220static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1da177e4
LT		 2221{
2222 unsigned int status, tmout = 10000;
2223
2224 /* Wait up to 10ms for the character(s) to be sent. */
2225 do {
2226 status = serial_in(up, UART_LSR);
2227
2228 if (status & UART_LSR_BI)
2229 up->lsr_break_flag = UART_LSR_BI;
2230
2231 if (--tmout == 0)
2232 break;
2233 udelay(1);
f91a3715 2234 } while ((status & bits) != bits);
1da177e4
LT		 2235
2236 /* Wait up to 1s for flow control if necessary */
2237 if (up->port.flags & UPF_CONS_FLOW) {
2238 tmout = 1000000;
e480af09 2239 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
1da177e4 2240 udelay(1);
e480af09
DJ		 2241 touch_nmi_watchdog();
2242 }
1da177e4
LT		 2243 }
2244}
2245
d358788f
RK		 2246static void serial8250_console_putchar(struct uart_port *port, int ch)
2247{
2248 struct uart_8250_port *up = (struct uart_8250_port *)port;
2249
2250 wait_for_xmitr(up, UART_LSR_THRE);
2251 serial_out(up, UART_TX, ch);
2252}
2253
1da177e4
LT		 2254/*
2255 * Print a string to the serial port trying not to disturb
2256 * any possible real use of the port...
2257 *
2258 * The console_lock must be held when we get here.
2259 */
2260static void
2261serial8250_console_write(struct console *co, const char *s, unsigned int count)
2262{
2263 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2264 unsigned long flags;
1da177e4 2265 unsigned int ier;
d8a5a8d7 2266 int locked = 1;
1da177e4 2267
78512ece
AM		 2268 touch_nmi_watchdog();
2269
68aa2c0d
AM		 2270 local_irq_save(flags);
2271 if (up->port.sysrq) {
2272 /* serial8250_handle_port() already took the lock */
2273 locked = 0;
2274 } else if (oops_in_progress) {
2275 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2276 } else
68aa2c0d 2277 spin_lock(&up->port.lock);
d8a5a8d7 2278
1da177e4 2279 /*
dc7bf130 2280 * First save the IER then disable the interrupts
1da177e4
LT		 2281 */
2282 ier = serial_in(up, UART_IER);
2283
2284 if (up->capabilities & UART_CAP_UUE)
2285 serial_out(up, UART_IER, UART_IER_UUE);
2286 else
2287 serial_out(up, UART_IER, 0);
2288
d358788f 2289 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2290
2291 /*
2292 * Finally, wait for transmitter to become empty
2293 * and restore the IER
2294 */
f91a3715 2295 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2296 serial_out(up, UART_IER, ier);
d8a5a8d7
RK		 2297
2298 if (locked)
68aa2c0d
AM		 2299 spin_unlock(&up->port.lock);
2300 local_irq_restore(flags);
1da177e4
LT		 2301}
2302
118c0ace 2303static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2304{
2305 struct uart_port *port;
2306 int baud = 9600;
2307 int bits = 8;
2308 int parity = 'n';
2309 int flow = 'n';
2310
2311 /*
2312 * Check whether an invalid uart number has been specified, and
2313 * if so, search for the first available port that does have
2314 * console support.
2315 */
a61c2d78 2316 if (co->index >= nr_uarts)
1da177e4
LT		 2317 co->index = 0;
2318 port = &serial8250_ports[co->index].port;
2319 if (!port->iobase && !port->membase)
2320 return -ENODEV;
2321
2322 if (options)
2323 uart_parse_options(options, &baud, &parity, &bits, &flow);
2324
2325 return uart_set_options(port, co, baud, parity, bits, flow);
2326}
2327
2328static struct uart_driver serial8250_reg;
2329static struct console serial8250_console = {
2330 .name = "ttyS",
2331 .write = serial8250_console_write,
2332 .device = uart_console_device,
2333 .setup = serial8250_console_setup,
2334 .flags = CON_PRINTBUFFER,
2335 .index = -1,
2336 .data = &serial8250_reg,
2337};
2338
2339static int __init serial8250_console_init(void)
2340{
2341 serial8250_isa_init_ports();
2342 register_console(&serial8250_console);
2343 return 0;
2344}
2345console_initcall(serial8250_console_init);
2346
2347static int __init find_port(struct uart_port *p)
2348{
2349 int line;
2350 struct uart_port *port;
2351
a61c2d78 2352 for (line = 0; line < nr_uarts; line++) {
1da177e4 2353 port = &serial8250_ports[line].port;
50aec3b5 2354 if (uart_match_port(p, port))
1da177e4
LT		 2355 return line;
2356 }
2357 return -ENODEV;
2358}
2359
2360int __init serial8250_start_console(struct uart_port *port, char *options)
2361{
2362 int line;
2363
2364 line = find_port(port);
2365 if (line < 0)
2366 return -ENODEV;
2367
2368 add_preferred_console("ttyS", line, options);
2369 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2370 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2371 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2372 (unsigned long) port->iobase, options);
2373 if (!(serial8250_console.flags & CON_ENABLED)) {
2374 serial8250_console.flags &= ~CON_PRINTBUFFER;
2375 register_console(&serial8250_console);
2376 }
2377 return line;
2378}
2379
2380#define SERIAL8250_CONSOLE &serial8250_console
2381#else
2382#define SERIAL8250_CONSOLE NULL
2383#endif
2384
2385static struct uart_driver serial8250_reg = {
2386 .owner = THIS_MODULE,
2387 .driver_name = "serial",
1da177e4
LT		 2388 .dev_name = "ttyS",
2389 .major = TTY_MAJOR,
2390 .minor = 64,
2391 .nr = UART_NR,
2392 .cons = SERIAL8250_CONSOLE,
2393};
2394
d856c666
RK		 2395/*
2396 * early_serial_setup - early registration for 8250 ports
2397 *
2398 * Setup an 8250 port structure prior to console initialisation. Use
2399 * after console initialisation will cause undefined behaviour.
2400 */
1da177e4
LT		 2401int __init early_serial_setup(struct uart_port *port)
2402{
2403 if (port->line >= ARRAY_SIZE(serial8250_ports))
2404 return -ENODEV;
2405
2406 serial8250_isa_init_ports();
2407 serial8250_ports[port->line].port = *port;
2408 serial8250_ports[port->line].port.ops = &serial8250_pops;
2409 return 0;
2410}
2411
2412/**
2413 * serial8250_suspend_port - suspend one serial port
2414 * @line: serial line number
1da177e4
LT		 2415 *
2416 * Suspend one serial port.
2417 */
2418void serial8250_suspend_port(int line)
2419{
2420 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2421}
2422
2423/**
2424 * serial8250_resume_port - resume one serial port
2425 * @line: serial line number
1da177e4
LT		 2426 *
2427 * Resume one serial port.
2428 */
2429void serial8250_resume_port(int line)
2430{
2431 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2432}
2433
2434/*
2435 * Register a set of serial devices attached to a platform device. The
2436 * list is terminated with a zero flags entry, which means we expect
2437 * all entries to have at least UPF_BOOT_AUTOCONF set.
2438 */
3ae5eaec 2439static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2440{
3ae5eaec 2441 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2442 struct uart_port port;
ec9f47cd 2443 int ret, i;
1da177e4
LT		 2444
2445 memset(&port, 0, sizeof(struct uart_port));
2446
ec9f47cd 2447 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2448 port.iobase = p->iobase;
2449 port.membase = p->membase;
2450 port.irq = p->irq;
2451 port.uartclk = p->uartclk;
2452 port.regshift = p->regshift;
2453 port.iotype = p->iotype;
2454 port.flags = p->flags;
2455 port.mapbase = p->mapbase;
ec9f47cd 2456 port.hub6 = p->hub6;
3ae5eaec 2457 port.dev = &dev->dev;
1da177e4
LT		 2458 if (share_irqs)
2459 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2460 ret = serial8250_register_port(&port);
2461 if (ret < 0) {
3ae5eaec 2462 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2463 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2464 p->iobase, p->mapbase, p->irq, ret);
2465 }
1da177e4
LT		 2466 }
2467 return 0;
2468}
2469
2470/*
2471 * Remove serial ports registered against a platform device.
2472 */
3ae5eaec 2473static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2474{
2475 int i;
2476
a61c2d78 2477 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2478 struct uart_8250_port *up = &serial8250_ports[i];
2479
3ae5eaec 2480 if (up->port.dev == &dev->dev)
1da177e4
LT		 2481 serial8250_unregister_port(i);
2482 }
2483 return 0;
2484}
2485
3ae5eaec 2486static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2487{
2488 int i;
2489
1da177e4
LT		 2490 for (i = 0; i < UART_NR; i++) {
2491 struct uart_8250_port *up = &serial8250_ports[i];
2492
3ae5eaec 2493 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2494 uart_suspend_port(&serial8250_reg, &up->port);
2495 }
2496
2497 return 0;
2498}
2499
3ae5eaec 2500static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2501{
2502 int i;
2503
1da177e4
LT		 2504 for (i = 0; i < UART_NR; i++) {
2505 struct uart_8250_port *up = &serial8250_ports[i];
2506
3ae5eaec 2507 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2508 uart_resume_port(&serial8250_reg, &up->port);
2509 }
2510
2511 return 0;
2512}
2513
3ae5eaec 2514static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2515 .probe = serial8250_probe,
2516 .remove = __devexit_p(serial8250_remove),
2517 .suspend = serial8250_suspend,
2518 .resume = serial8250_resume,
3ae5eaec
RK		 2519 .driver = {
2520 .name = "serial8250",
7493a314 2521 .owner = THIS_MODULE,
3ae5eaec 2522 },
1da177e4
LT		 2523};
2524
2525/*
2526 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2527 * in the table in include/asm/serial.h
2528 */
2529static struct platform_device *serial8250_isa_devs;
2530
2531/*
2532 * serial8250_register_port and serial8250_unregister_port allows for
2533 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2534 * modems and PCI multiport cards.
2535 */
f392ecfa 2536static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2537
2538static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2539{
2540 int i;
2541
2542 /*
2543 * First, find a port entry which matches.
2544 */
a61c2d78 2545 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2546 if (uart_match_port(&serial8250_ports[i].port, port))
2547 return &serial8250_ports[i];
2548
2549 /*
2550 * We didn't find a matching entry, so look for the first
2551 * free entry. We look for one which hasn't been previously
2552 * used (indicated by zero iobase).
2553 */
a61c2d78 2554 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2555 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2556 serial8250_ports[i].port.iobase == 0)
2557 return &serial8250_ports[i];
2558
2559 /*
2560 * That also failed. Last resort is to find any entry which
2561 * doesn't have a real port associated with it.
2562 */
a61c2d78 2563 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2564 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2565 return &serial8250_ports[i];
2566
2567 return NULL;
2568}
2569
2570/**
2571 * serial8250_register_port - register a serial port
2572 * @port: serial port template
2573 *
2574 * Configure the serial port specified by the request. If the
2575 * port exists and is in use, it is hung up and unregistered
2576 * first.
2577 *
2578 * The port is then probed and if necessary the IRQ is autodetected
2579 * If this fails an error is returned.
2580 *
2581 * On success the port is ready to use and the line number is returned.
2582 */
2583int serial8250_register_port(struct uart_port *port)
2584{
2585 struct uart_8250_port *uart;
2586 int ret = -ENOSPC;
2587
2588 if (port->uartclk == 0)
2589 return -EINVAL;
2590
f392ecfa 2591 mutex_lock(&serial_mutex);
1da177e4
LT		 2592
2593 uart = serial8250_find_match_or_unused(port);
2594 if (uart) {
2595 uart_remove_one_port(&serial8250_reg, &uart->port);
2596
2597 uart->port.iobase = port->iobase;
2598 uart->port.membase = port->membase;
2599 uart->port.irq = port->irq;
2600 uart->port.uartclk = port->uartclk;
2601 uart->port.fifosize = port->fifosize;
2602 uart->port.regshift = port->regshift;
2603 uart->port.iotype = port->iotype;
2604 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2605 uart->port.mapbase = port->mapbase;
2606 if (port->dev)
2607 uart->port.dev = port->dev;
2608
2609 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2610 if (ret == 0)
2611 ret = uart->port.line;
2612 }
f392ecfa 2613 mutex_unlock(&serial_mutex);
1da177e4
LT		 2614
2615 return ret;
2616}
2617EXPORT_SYMBOL(serial8250_register_port);
2618
2619/**
2620 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2621 * @line: serial line number
2622 *
2623 * Remove one serial port. This may not be called from interrupt
2624 * context. We hand the port back to the our control.
2625 */
2626void serial8250_unregister_port(int line)
2627{
2628 struct uart_8250_port *uart = &serial8250_ports[line];
2629
f392ecfa 2630 mutex_lock(&serial_mutex);
1da177e4
LT		 2631 uart_remove_one_port(&serial8250_reg, &uart->port);
2632 if (serial8250_isa_devs) {
2633 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2634 uart->port.type = PORT_UNKNOWN;
2635 uart->port.dev = &serial8250_isa_devs->dev;
2636 uart_add_one_port(&serial8250_reg, &uart->port);
2637 } else {
2638 uart->port.dev = NULL;
2639 }
f392ecfa 2640 mutex_unlock(&serial_mutex);
1da177e4
LT		 2641}
2642EXPORT_SYMBOL(serial8250_unregister_port);
2643
2644static int __init serial8250_init(void)
2645{
2646 int ret, i;
2647
a61c2d78
DJ		 2648 if (nr_uarts > UART_NR)
2649 nr_uarts = UART_NR;
2650
1da177e4 2651 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2652 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2653 share_irqs ? "en" : "dis");
2654
2655 for (i = 0; i < NR_IRQS; i++)
2656 spin_lock_init(&irq_lists[i].lock);
2657
2658 ret = uart_register_driver(&serial8250_reg);
2659 if (ret)
2660 goto out;
2661
7493a314
DT		 2662 serial8250_isa_devs = platform_device_alloc("serial8250",
2663 PLAT8250_DEV_LEGACY);
2664 if (!serial8250_isa_devs) {
2665 ret = -ENOMEM;
bc965a7f 2666 goto unreg_uart_drv;
1da177e4
LT		 2667 }
2668
7493a314
DT		 2669 ret = platform_device_add(serial8250_isa_devs);
2670 if (ret)
2671 goto put_dev;
2672
1da177e4
LT		 2673 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2674
bc965a7f
RK		 2675 ret = platform_driver_register(&serial8250_isa_driver);
2676 if (ret == 0)
2677 goto out;
1da177e4 2678
bc965a7f 2679 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2680 put_dev:
2681 platform_device_put(serial8250_isa_devs);
7493a314 2682 unreg_uart_drv:
1da177e4
LT		 2683 uart_unregister_driver(&serial8250_reg);
2684 out:
2685 return ret;
2686}
2687
2688static void __exit serial8250_exit(void)
2689{
2690 struct platform_device *isa_dev = serial8250_isa_devs;
2691
2692 /*
2693 * This tells serial8250_unregister_port() not to re-register
2694 * the ports (thereby making serial8250_isa_driver permanently
2695 * in use.)
2696 */
2697 serial8250_isa_devs = NULL;
2698
3ae5eaec 2699 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2700 platform_device_unregister(isa_dev);
2701
2702 uart_unregister_driver(&serial8250_reg);
2703}
2704
2705module_init(serial8250_init);
2706module_exit(serial8250_exit);
2707
2708EXPORT_SYMBOL(serial8250_suspend_port);
2709EXPORT_SYMBOL(serial8250_resume_port);
2710
2711MODULE_LICENSE("GPL");
2712MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2713
2714module_param(share_irqs, uint, 0644);
2715MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2716 " (unsafe)");
2717
a61c2d78
DJ		 2718module_param(nr_uarts, uint, 0644);
2719MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2720
1da177e4
LT		 2721#ifdef CONFIG_SERIAL_8250_RSA
2722module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2723MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2724#endif
2725MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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