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tty: release BTM while sleeping in block_til_ready
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4
LT		 33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
78512ece 39#include <linux/nmi.h>
f392ecfa 40#include <linux/mutex.h>
5a0e3ad6 41#include <linux/slab.h>
1da177e4
LT		 42
43#include <asm/io.h>
44#include <asm/irq.h>
45
46#include "8250.h"
47
b70ac771
DM		 48#ifdef CONFIG_SPARC
49#include "suncore.h"
50#endif
51
1da177e4
LT		 52/*
53 * Configuration:
40663cc7 54 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 55 * is unsafe when used on edge-triggered interrupts.
56 */
408b664a 57static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 58
a61c2d78
DJ		 59static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
60
8440838b
DM		 61static struct uart_driver serial8250_reg;
62
63static int serial_index(struct uart_port *port)
64{
65 return (serial8250_reg.minor - 64) + port->line;
66}
67
d41a4b51
CE		 68static unsigned int skip_txen_test; /* force skip of txen test at init time */
69
1da177e4
LT		 70/*
71 * Debugging.
72 */
73#if 0
74#define DEBUG_AUTOCONF(fmt...) printk(fmt)
75#else
76#define DEBUG_AUTOCONF(fmt...) do { } while (0)
77#endif
78
79#if 0
80#define DEBUG_INTR(fmt...) printk(fmt)
81#else
82#define DEBUG_INTR(fmt...) do { } while (0)
83#endif
84
85#define PASS_LIMIT 256
86
bca47613
DH		 87#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
88
89
1da177e4
LT		 90/*
91 * We default to IRQ0 for the "no irq" hack. Some
92 * machine types want others as well - they're free
93 * to redefine this in their header file.
94 */
95#define is_real_interrupt(irq) ((irq) != 0)
96
1da177e4
LT		 97#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
98#define CONFIG_SERIAL_DETECT_IRQ 1
99#endif
1da177e4
LT		 100#ifdef CONFIG_SERIAL_8250_MANY_PORTS
101#define CONFIG_SERIAL_MANY_PORTS 1
102#endif
103
104/*
105 * HUB6 is always on. This will be removed once the header
106 * files have been cleaned.
107 */
108#define CONFIG_HUB6 1
109
a4ed1e41 110#include <asm/serial.h>
1da177e4
LT		 111/*
112 * SERIAL_PORT_DFNS tells us about built-in ports that have no
113 * standard enumeration mechanism. Platforms that can find all
114 * serial ports via mechanisms like ACPI or PCI need not supply it.
115 */
116#ifndef SERIAL_PORT_DFNS
117#define SERIAL_PORT_DFNS
118#endif
119
cb3592be 120static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 121 SERIAL_PORT_DFNS /* defined in asm/serial.h */
122};
123
026d02a2 124#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 125
126#ifdef CONFIG_SERIAL_8250_RSA
127
128#define PORT_RSA_MAX 4
129static unsigned long probe_rsa[PORT_RSA_MAX];
130static unsigned int probe_rsa_count;
131#endif /* CONFIG_SERIAL_8250_RSA */
132
133struct uart_8250_port {
134 struct uart_port port;
135 struct timer_list timer; /* "no irq" timer */
136 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 137 unsigned short capabilities; /* port capabilities */
138 unsigned short bugs; /* port bugs */
1da177e4 139 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 140 unsigned char acr;
141 unsigned char ier;
142 unsigned char lcr;
143 unsigned char mcr;
144 unsigned char mcr_mask; /* mask of user bits */
145 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 146 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 147
148 /*
149 * Some bits in registers are cleared on a read, so they must
150 * be saved whenever the register is read but the bits will not
151 * be immediately processed.
152 */
153#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
154 unsigned char lsr_saved_flags;
155#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
156 unsigned char msr_saved_flags;
1da177e4
LT		 157
158 /*
159 * We provide a per-port pm hook.
160 */
161 void (*pm)(struct uart_port *port,
162 unsigned int state, unsigned int old);
163};
164
165struct irq_info {
25db8ad5
AC		 166 struct hlist_node node;
167 int irq;
168 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 169 struct list_head *head;
170};
171
25db8ad5
AC		 172#define NR_IRQ_HASH 32 /* Can be adjusted later */
173static struct hlist_head irq_lists[NR_IRQ_HASH];
174static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 175
176/*
177 * Here we define the default xmit fifo size used for each type of UART.
178 */
179static const struct serial8250_config uart_config[] = {
180 [PORT_UNKNOWN] = {
181 .name = "unknown",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_8250] = {
186 .name = "8250",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 },
190 [PORT_16450] = {
191 .name = "16450",
192 .fifo_size = 1,
193 .tx_loadsz = 1,
194 },
195 [PORT_16550] = {
196 .name = "16550",
197 .fifo_size = 1,
198 .tx_loadsz = 1,
199 },
200 [PORT_16550A] = {
201 .name = "16550A",
202 .fifo_size = 16,
203 .tx_loadsz = 16,
204 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
205 .flags = UART_CAP_FIFO,
206 },
207 [PORT_CIRRUS] = {
208 .name = "Cirrus",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 },
212 [PORT_16650] = {
213 .name = "ST16650",
214 .fifo_size = 1,
215 .tx_loadsz = 1,
216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
217 },
218 [PORT_16650V2] = {
219 .name = "ST16650V2",
220 .fifo_size = 32,
221 .tx_loadsz = 16,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_00,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16750] = {
227 .name = "TI16750",
228 .fifo_size = 64,
229 .tx_loadsz = 64,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
231 UART_FCR7_64BYTE,
232 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
233 },
234 [PORT_STARTECH] = {
235 .name = "Startech",
236 .fifo_size = 1,
237 .tx_loadsz = 1,
238 },
239 [PORT_16C950] = {
240 .name = "16C950/954",
241 .fifo_size = 128,
242 .tx_loadsz = 128,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
7a56aa45 244 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
1da177e4
LT		 245 },
246 [PORT_16654] = {
247 .name = "ST16654",
248 .fifo_size = 64,
249 .tx_loadsz = 32,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
251 UART_FCR_T_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_16850] = {
255 .name = "XR16850",
256 .fifo_size = 128,
257 .tx_loadsz = 128,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
260 },
261 [PORT_RSA] = {
262 .name = "RSA",
263 .fifo_size = 2048,
264 .tx_loadsz = 2048,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
266 .flags = UART_CAP_FIFO,
267 },
268 [PORT_NS16550A] = {
269 .name = "NS16550A",
270 .fifo_size = 16,
271 .tx_loadsz = 16,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_NATSEMI,
274 },
275 [PORT_XSCALE] = {
276 .name = "XScale",
277 .fifo_size = 32,
278 .tx_loadsz = 32,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO | UART_CAP_UUE,
281 },
bd71c182
TK		 282 [PORT_RM9000] = {
283 .name = "RM9000",
284 .fifo_size = 16,
285 .tx_loadsz = 16,
286 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 287 .flags = UART_CAP_FIFO,
288 },
289 [PORT_OCTEON] = {
290 .name = "OCTEON",
291 .fifo_size = 64,
292 .tx_loadsz = 64,
293 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 294 .flags = UART_CAP_FIFO,
295 },
08e0992f
FF		 296 [PORT_AR7] = {
297 .name = "AR7",
298 .fifo_size = 16,
299 .tx_loadsz = 16,
300 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
301 .flags = UART_CAP_FIFO | UART_CAP_AFE,
302 },
1da177e4
LT		 303};
304
12bf3f24 305#if defined(CONFIG_MIPS_ALCHEMY)
21c614a7
PA		 306
307/* Au1x00 UART hardware has a weird register layout */
308static const u8 au_io_in_map[] = {
309 [UART_RX] = 0,
310 [UART_IER] = 2,
311 [UART_IIR] = 3,
312 [UART_LCR] = 5,
313 [UART_MCR] = 6,
314 [UART_LSR] = 7,
315 [UART_MSR] = 8,
316};
317
318static const u8 au_io_out_map[] = {
319 [UART_TX] = 1,
320 [UART_IER] = 2,
321 [UART_FCR] = 4,
322 [UART_LCR] = 5,
323 [UART_MCR] = 6,
324};
325
326/* sane hardware needs no mapping */
7d6a07d1 327static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 328{
7d6a07d1 329 if (p->iotype != UPIO_AU)
21c614a7
PA		 330 return offset;
331 return au_io_in_map[offset];
332}
333
7d6a07d1 334static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 335{
7d6a07d1 336 if (p->iotype != UPIO_AU)
21c614a7
PA		 337 return offset;
338 return au_io_out_map[offset];
339}
340
6f803cd0 341#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 342
343static const u8
344 regmap_in[8] = {
345 [UART_RX] = 0x00,
346 [UART_IER] = 0x0c,
347 [UART_IIR] = 0x14,
348 [UART_LCR] = 0x1c,
349 [UART_MCR] = 0x20,
350 [UART_LSR] = 0x24,
351 [UART_MSR] = 0x28,
352 [UART_SCR] = 0x2c
353 },
354 regmap_out[8] = {
355 [UART_TX] = 0x04,
356 [UART_IER] = 0x0c,
357 [UART_FCR] = 0x18,
358 [UART_LCR] = 0x1c,
359 [UART_MCR] = 0x20,
360 [UART_LSR] = 0x24,
361 [UART_MSR] = 0x28,
362 [UART_SCR] = 0x2c
363 };
364
7d6a07d1 365static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 366{
7d6a07d1 367 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 368 return offset;
369 return regmap_in[offset];
370}
371
7d6a07d1 372static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 373{
7d6a07d1 374 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 375 return offset;
376 return regmap_out[offset];
377}
378
21c614a7
PA		 379#else
380
381/* sane hardware needs no mapping */
382#define map_8250_in_reg(up, offset) (offset)
383#define map_8250_out_reg(up, offset) (offset)
384
385#endif
386
7d6a07d1 387static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 388{
7d6a07d1
DD		 389 offset = map_8250_in_reg(p, offset) << p->regshift;
390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
392}
1da177e4 393
7d6a07d1
DD		 394static void hub6_serial_out(struct uart_port *p, int offset, int value)
395{
396 offset = map_8250_out_reg(p, offset) << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
399}
1da177e4 400
7d6a07d1
DD		 401static unsigned int mem_serial_in(struct uart_port *p, int offset)
402{
403 offset = map_8250_in_reg(p, offset) << p->regshift;
404 return readb(p->membase + offset);
405}
1da177e4 406
7d6a07d1
DD		 407static void mem_serial_out(struct uart_port *p, int offset, int value)
408{
409 offset = map_8250_out_reg(p, offset) << p->regshift;
410 writeb(value, p->membase + offset);
411}
412
413static void mem32_serial_out(struct uart_port *p, int offset, int value)
414{
415 offset = map_8250_out_reg(p, offset) << p->regshift;
416 writel(value, p->membase + offset);
417}
418
419static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420{
421 offset = map_8250_in_reg(p, offset) << p->regshift;
422 return readl(p->membase + offset);
423}
1da177e4 424
7d6a07d1
DD		 425static unsigned int au_serial_in(struct uart_port *p, int offset)
426{
427 offset = map_8250_in_reg(p, offset) << p->regshift;
428 return __raw_readl(p->membase + offset);
429}
430
431static void au_serial_out(struct uart_port *p, int offset, int value)
432{
433 offset = map_8250_out_reg(p, offset) << p->regshift;
434 __raw_writel(value, p->membase + offset);
435}
21c614a7 436
7d6a07d1
DD		 437static unsigned int tsi_serial_in(struct uart_port *p, int offset)
438{
439 unsigned int tmp;
440 offset = map_8250_in_reg(p, offset) << p->regshift;
441 if (offset == UART_IIR) {
442 tmp = readl(p->membase + (UART_IIR & ~3));
443 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
444 } else
445 return readb(p->membase + offset);
446}
3be91ec7 447
7d6a07d1
DD		 448static void tsi_serial_out(struct uart_port *p, int offset, int value)
449{
450 offset = map_8250_out_reg(p, offset) << p->regshift;
451 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
452 writeb(value, p->membase + offset);
1da177e4
LT		 453}
454
7d6a07d1 455static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 456{
beab697a 457 int save_offset = offset;
7d6a07d1
DD		 458 offset = map_8250_out_reg(p, offset) << p->regshift;
459 /* Save the LCR value so it can be re-written when a
460 * Busy Detect interrupt occurs. */
461 if (save_offset == UART_LCR) {
462 struct uart_8250_port *up = (struct uart_8250_port *)p;
463 up->lcr = value;
464 }
465 writeb(value, p->membase + offset);
466 /* Read the IER to ensure any interrupt is cleared before
467 * returning from ISR. */
468 if (save_offset == UART_TX || save_offset == UART_IER)
469 value = p->serial_in(p, UART_IER);
470}
1da177e4 471
7d6a07d1
DD		 472static unsigned int io_serial_in(struct uart_port *p, int offset)
473{
474 offset = map_8250_in_reg(p, offset) << p->regshift;
475 return inb(p->iobase + offset);
476}
477
478static void io_serial_out(struct uart_port *p, int offset, int value)
479{
480 offset = map_8250_out_reg(p, offset) << p->regshift;
481 outb(value, p->iobase + offset);
482}
483
484static void set_io_from_upio(struct uart_port *p)
485{
b8e7e40a 486 struct uart_8250_port *up = (struct uart_8250_port *)p;
7d6a07d1 487 switch (p->iotype) {
1da177e4 488 case UPIO_HUB6:
7d6a07d1
DD		 489 p->serial_in = hub6_serial_in;
490 p->serial_out = hub6_serial_out;
1da177e4
LT		 491 break;
492
493 case UPIO_MEM:
7d6a07d1
DD		 494 p->serial_in = mem_serial_in;
495 p->serial_out = mem_serial_out;
1da177e4
LT		 496 break;
497
bd71c182 498 case UPIO_RM9000:
1da177e4 499 case UPIO_MEM32:
7d6a07d1
DD		 500 p->serial_in = mem32_serial_in;
501 p->serial_out = mem32_serial_out;
1da177e4
LT		 502 break;
503
21c614a7 504 case UPIO_AU:
7d6a07d1
DD		 505 p->serial_in = au_serial_in;
506 p->serial_out = au_serial_out;
21c614a7 507 break;
12bf3f24 508
3be91ec7 509 case UPIO_TSI:
7d6a07d1
DD		 510 p->serial_in = tsi_serial_in;
511 p->serial_out = tsi_serial_out;
3be91ec7 512 break;
21c614a7 513
beab697a 514 case UPIO_DWAPB:
7d6a07d1
DD		 515 p->serial_in = mem_serial_in;
516 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 517 break;
518
1da177e4 519 default:
7d6a07d1
DD		 520 p->serial_in = io_serial_in;
521 p->serial_out = io_serial_out;
522 break;
1da177e4 523 }
b8e7e40a
AC		 524 /* Remember loaded iotype */
525 up->cur_iotype = p->iotype;
1da177e4
LT		 526}
527
40b36daa
AW		 528static void
529serial_out_sync(struct uart_8250_port *up, int offset, int value)
530{
7d6a07d1
DD		 531 struct uart_port *p = &up->port;
532 switch (p->iotype) {
40b36daa
AW		 533 case UPIO_MEM:
534 case UPIO_MEM32:
40b36daa 535 case UPIO_AU:
beab697a 536 case UPIO_DWAPB:
7d6a07d1
DD		 537 p->serial_out(p, offset, value);
538 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 539 break;
540 default:
7d6a07d1 541 p->serial_out(p, offset, value);
40b36daa
AW		 542 }
543}
544
7d6a07d1
DD		 545#define serial_in(up, offset) \
546 (up->port.serial_in(&(up)->port, (offset)))
547#define serial_out(up, offset, value) \
548 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 549/*
550 * We used to support using pause I/O for certain machines. We
551 * haven't supported this for a while, but just in case it's badly
552 * needed for certain old 386 machines, I've left these #define's
553 * in....
554 */
555#define serial_inp(up, offset) serial_in(up, offset)
556#define serial_outp(up, offset, value) serial_out(up, offset, value)
557
b32b19b8
JAH		 558/* Uart divisor latch read */
559static inline int _serial_dl_read(struct uart_8250_port *up)
560{
561 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
562}
563
564/* Uart divisor latch write */
565static inline void _serial_dl_write(struct uart_8250_port *up, int value)
566{
567 serial_outp(up, UART_DLL, value & 0xff);
568 serial_outp(up, UART_DLM, value >> 8 & 0xff);
569}
570
12bf3f24 571#if defined(CONFIG_MIPS_ALCHEMY)
b32b19b8
JAH		 572/* Au1x00 haven't got a standard divisor latch */
573static int serial_dl_read(struct uart_8250_port *up)
574{
575 if (up->port.iotype == UPIO_AU)
576 return __raw_readl(up->port.membase + 0x28);
577 else
578 return _serial_dl_read(up);
579}
580
581static void serial_dl_write(struct uart_8250_port *up, int value)
582{
583 if (up->port.iotype == UPIO_AU)
584 __raw_writel(value, up->port.membase + 0x28);
585 else
586 _serial_dl_write(up, value);
587}
6f803cd0 588#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 589static int serial_dl_read(struct uart_8250_port *up)
590{
591 return (up->port.iotype == UPIO_RM9000) ?
592 (((__raw_readl(up->port.membase + 0x10) << 8) |
593 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
594 _serial_dl_read(up);
595}
596
597static void serial_dl_write(struct uart_8250_port *up, int value)
598{
599 if (up->port.iotype == UPIO_RM9000) {
600 __raw_writel(value, up->port.membase + 0x08);
601 __raw_writel(value >> 8, up->port.membase + 0x10);
602 } else {
603 _serial_dl_write(up, value);
604 }
605}
b32b19b8
JAH		 606#else
607#define serial_dl_read(up) _serial_dl_read(up)
608#define serial_dl_write(up, value) _serial_dl_write(up, value)
609#endif
1da177e4
LT		 610
611/*
612 * For the 16C950
613 */
614static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
615{
616 serial_out(up, UART_SCR, offset);
617 serial_out(up, UART_ICR, value);
618}
619
620static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
621{
622 unsigned int value;
623
624 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
625 serial_out(up, UART_SCR, offset);
626 value = serial_in(up, UART_ICR);
627 serial_icr_write(up, UART_ACR, up->acr);
628
629 return value;
630}
631
632/*
633 * FIFO support.
634 */
b5d674ab 635static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 636{
637 if (p->capabilities & UART_CAP_FIFO) {
638 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
640 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
641 serial_outp(p, UART_FCR, 0);
642 }
643}
644
645/*
646 * IER sleep support. UARTs which have EFRs need the "extended
647 * capability" bit enabled. Note that on XR16C850s, we need to
648 * reset LCR to write to IER.
649 */
b5d674ab 650static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 651{
652 if (p->capabilities & UART_CAP_SLEEP) {
653 if (p->capabilities & UART_CAP_EFR) {
654 serial_outp(p, UART_LCR, 0xBF);
655 serial_outp(p, UART_EFR, UART_EFR_ECB);
656 serial_outp(p, UART_LCR, 0);
657 }
658 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
659 if (p->capabilities & UART_CAP_EFR) {
660 serial_outp(p, UART_LCR, 0xBF);
661 serial_outp(p, UART_EFR, 0);
662 serial_outp(p, UART_LCR, 0);
663 }
664 }
665}
666
667#ifdef CONFIG_SERIAL_8250_RSA
668/*
669 * Attempts to turn on the RSA FIFO. Returns zero on failure.
670 * We set the port uart clock rate if we succeed.
671 */
672static int __enable_rsa(struct uart_8250_port *up)
673{
674 unsigned char mode;
675 int result;
676
677 mode = serial_inp(up, UART_RSA_MSR);
678 result = mode & UART_RSA_MSR_FIFO;
679
680 if (!result) {
681 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
682 mode = serial_inp(up, UART_RSA_MSR);
683 result = mode & UART_RSA_MSR_FIFO;
684 }
685
686 if (result)
687 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
688
689 return result;
690}
691
692static void enable_rsa(struct uart_8250_port *up)
693{
694 if (up->port.type == PORT_RSA) {
695 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
696 spin_lock_irq(&up->port.lock);
697 __enable_rsa(up);
698 spin_unlock_irq(&up->port.lock);
699 }
700 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
701 serial_outp(up, UART_RSA_FRR, 0);
702 }
703}
704
705/*
706 * Attempts to turn off the RSA FIFO. Returns zero on failure.
707 * It is unknown why interrupts were disabled in here. However,
708 * the caller is expected to preserve this behaviour by grabbing
709 * the spinlock before calling this function.
710 */
711static void disable_rsa(struct uart_8250_port *up)
712{
713 unsigned char mode;
714 int result;
715
716 if (up->port.type == PORT_RSA &&
717 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
718 spin_lock_irq(&up->port.lock);
719
720 mode = serial_inp(up, UART_RSA_MSR);
721 result = !(mode & UART_RSA_MSR_FIFO);
722
723 if (!result) {
724 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
725 mode = serial_inp(up, UART_RSA_MSR);
726 result = !(mode & UART_RSA_MSR_FIFO);
727 }
728
729 if (result)
730 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
731 spin_unlock_irq(&up->port.lock);
732 }
733}
734#endif /* CONFIG_SERIAL_8250_RSA */
735
736/*
737 * This is a quickie test to see how big the FIFO is.
738 * It doesn't work at all the time, more's the pity.
739 */
740static int size_fifo(struct uart_8250_port *up)
741{
b32b19b8
JAH		 742 unsigned char old_fcr, old_mcr, old_lcr;
743 unsigned short old_dl;
1da177e4
LT		 744 int count;
745
746 old_lcr = serial_inp(up, UART_LCR);
747 serial_outp(up, UART_LCR, 0);
748 old_fcr = serial_inp(up, UART_FCR);
749 old_mcr = serial_inp(up, UART_MCR);
750 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
751 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
752 serial_outp(up, UART_MCR, UART_MCR_LOOP);
753 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 754 old_dl = serial_dl_read(up);
755 serial_dl_write(up, 0x0001);
1da177e4
LT		 756 serial_outp(up, UART_LCR, 0x03);
757 for (count = 0; count < 256; count++)
758 serial_outp(up, UART_TX, count);
759 mdelay(20);/* FIXME - schedule_timeout */
760 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
761 (count < 256); count++)
762 serial_inp(up, UART_RX);
763 serial_outp(up, UART_FCR, old_fcr);
764 serial_outp(up, UART_MCR, old_mcr);
765 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 766 serial_dl_write(up, old_dl);
1da177e4
LT		 767 serial_outp(up, UART_LCR, old_lcr);
768
769 return count;
770}
771
772/*
773 * Read UART ID using the divisor method - set DLL and DLM to zero
774 * and the revision will be in DLL and device type in DLM. We
775 * preserve the device state across this.
776 */
777static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
778{
779 unsigned char old_dll, old_dlm, old_lcr;
780 unsigned int id;
781
782 old_lcr = serial_inp(p, UART_LCR);
783 serial_outp(p, UART_LCR, UART_LCR_DLAB);
784
785 old_dll = serial_inp(p, UART_DLL);
786 old_dlm = serial_inp(p, UART_DLM);
787
788 serial_outp(p, UART_DLL, 0);
789 serial_outp(p, UART_DLM, 0);
790
791 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
792
793 serial_outp(p, UART_DLL, old_dll);
794 serial_outp(p, UART_DLM, old_dlm);
795 serial_outp(p, UART_LCR, old_lcr);
796
797 return id;
798}
799
800/*
801 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
802 * When this function is called we know it is at least a StarTech
803 * 16650 V2, but it might be one of several StarTech UARTs, or one of
804 * its clones. (We treat the broken original StarTech 16650 V1 as a
805 * 16550, and why not? Startech doesn't seem to even acknowledge its
806 * existence.)
bd71c182 807 *
1da177e4
LT		 808 * What evil have men's minds wrought...
809 */
810static void autoconfig_has_efr(struct uart_8250_port *up)
811{
812 unsigned int id1, id2, id3, rev;
813
814 /*
815 * Everything with an EFR has SLEEP
816 */
817 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
818
819 /*
820 * First we check to see if it's an Oxford Semiconductor UART.
821 *
822 * If we have to do this here because some non-National
823 * Semiconductor clone chips lock up if you try writing to the
824 * LSR register (which serial_icr_read does)
825 */
826
827 /*
828 * Check for Oxford Semiconductor 16C950.
829 *
830 * EFR [4] must be set else this test fails.
831 *
832 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
833 * claims that it's needed for 952 dual UART's (which are not
834 * recommended for new designs).
835 */
836 up->acr = 0;
837 serial_out(up, UART_LCR, 0xBF);
838 serial_out(up, UART_EFR, UART_EFR_ECB);
839 serial_out(up, UART_LCR, 0x00);
840 id1 = serial_icr_read(up, UART_ID1);
841 id2 = serial_icr_read(up, UART_ID2);
842 id3 = serial_icr_read(up, UART_ID3);
843 rev = serial_icr_read(up, UART_REV);
844
845 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
846
847 if (id1 == 0x16 && id2 == 0xC9 &&
848 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
849 up->port.type = PORT_16C950;
4ba5e35d
RK		 850
851 /*
852 * Enable work around for the Oxford Semiconductor 952 rev B
853 * chip which causes it to seriously miscalculate baud rates
854 * when DLL is 0.
855 */
856 if (id3 == 0x52 && rev == 0x01)
857 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 858 return;
859 }
bd71c182 860
1da177e4
LT		 861 /*
862 * We check for a XR16C850 by setting DLL and DLM to 0, and then
863 * reading back DLL and DLM. The chip type depends on the DLM
864 * value read back:
865 * 0x10 - XR16C850 and the DLL contains the chip revision.
866 * 0x12 - XR16C2850.
867 * 0x14 - XR16C854.
868 */
869 id1 = autoconfig_read_divisor_id(up);
870 DEBUG_AUTOCONF("850id=%04x ", id1);
871
872 id2 = id1 >> 8;
873 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 874 up->port.type = PORT_16850;
875 return;
876 }
877
878 /*
879 * It wasn't an XR16C850.
880 *
881 * We distinguish between the '654 and the '650 by counting
882 * how many bytes are in the FIFO. I'm using this for now,
883 * since that's the technique that was sent to me in the
884 * serial driver update, but I'm not convinced this works.
885 * I've had problems doing this in the past. -TYT
886 */
887 if (size_fifo(up) == 64)
888 up->port.type = PORT_16654;
889 else
890 up->port.type = PORT_16650V2;
891}
892
893/*
894 * We detected a chip without a FIFO. Only two fall into
895 * this category - the original 8250 and the 16450. The
896 * 16450 has a scratch register (accessible with LCR=0)
897 */
898static void autoconfig_8250(struct uart_8250_port *up)
899{
900 unsigned char scratch, status1, status2;
901
902 up->port.type = PORT_8250;
903
904 scratch = serial_in(up, UART_SCR);
905 serial_outp(up, UART_SCR, 0xa5);
906 status1 = serial_in(up, UART_SCR);
907 serial_outp(up, UART_SCR, 0x5a);
908 status2 = serial_in(up, UART_SCR);
909 serial_outp(up, UART_SCR, scratch);
910
911 if (status1 == 0xa5 && status2 == 0x5a)
912 up->port.type = PORT_16450;
913}
914
915static int broken_efr(struct uart_8250_port *up)
916{
917 /*
918 * Exar ST16C2550 "A2" devices incorrectly detect as
919 * having an EFR, and report an ID of 0x0201. See
920 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
921 */
922 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
923 return 1;
924
925 return 0;
926}
927
928/*
929 * We know that the chip has FIFOs. Does it have an EFR? The
930 * EFR is located in the same register position as the IIR and
931 * we know the top two bits of the IIR are currently set. The
932 * EFR should contain zero. Try to read the EFR.
933 */
934static void autoconfig_16550a(struct uart_8250_port *up)
935{
936 unsigned char status1, status2;
937 unsigned int iersave;
938
939 up->port.type = PORT_16550A;
940 up->capabilities |= UART_CAP_FIFO;
941
942 /*
943 * Check for presence of the EFR when DLAB is set.
944 * Only ST16C650V1 UARTs pass this test.
945 */
946 serial_outp(up, UART_LCR, UART_LCR_DLAB);
947 if (serial_in(up, UART_EFR) == 0) {
948 serial_outp(up, UART_EFR, 0xA8);
949 if (serial_in(up, UART_EFR) != 0) {
950 DEBUG_AUTOCONF("EFRv1 ");
951 up->port.type = PORT_16650;
952 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
953 } else {
954 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
955 }
956 serial_outp(up, UART_EFR, 0);
957 return;
958 }
959
960 /*
961 * Maybe it requires 0xbf to be written to the LCR.
962 * (other ST16C650V2 UARTs, TI16C752A, etc)
963 */
964 serial_outp(up, UART_LCR, 0xBF);
965 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
966 DEBUG_AUTOCONF("EFRv2 ");
967 autoconfig_has_efr(up);
968 return;
969 }
970
971 /*
972 * Check for a National Semiconductor SuperIO chip.
973 * Attempt to switch to bank 2, read the value of the LOOP bit
974 * from EXCR1. Switch back to bank 0, change it in MCR. Then
975 * switch back to bank 2, read it from EXCR1 again and check
976 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 977 */
978 serial_outp(up, UART_LCR, 0);
979 status1 = serial_in(up, UART_MCR);
980 serial_outp(up, UART_LCR, 0xE0);
981 status2 = serial_in(up, 0x02); /* EXCR1 */
982
983 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
984 serial_outp(up, UART_LCR, 0);
985 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
986 serial_outp(up, UART_LCR, 0xE0);
987 status2 = serial_in(up, 0x02); /* EXCR1 */
988 serial_outp(up, UART_LCR, 0);
989 serial_outp(up, UART_MCR, status1);
990
991 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 992 unsigned short quot;
993
1da177e4 994 serial_outp(up, UART_LCR, 0xE0);
857dde2e 995
b32b19b8 996 quot = serial_dl_read(up);
857dde2e
DW		 997 quot <<= 3;
998
b5b82df6 999 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 1000 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1001 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1002 serial_outp(up, 0x04, status1);
bd71c182 1003
b32b19b8 1004 serial_dl_write(up, quot);
857dde2e 1005
1da177e4 1006 serial_outp(up, UART_LCR, 0);
1da177e4 1007
857dde2e 1008 up->port.uartclk = 921600*16;
1da177e4
LT		 1009 up->port.type = PORT_NS16550A;
1010 up->capabilities |= UART_NATSEMI;
1011 return;
1012 }
1013 }
1014
1015 /*
1016 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1017 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1018 * Try setting it with and without DLAB set. Cheap clones
1019 * set bit 5 without DLAB set.
1020 */
1021 serial_outp(up, UART_LCR, 0);
1022 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1023 status1 = serial_in(up, UART_IIR) >> 5;
1024 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1025 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1026 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1027 status2 = serial_in(up, UART_IIR) >> 5;
1028 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1029 serial_outp(up, UART_LCR, 0);
1030
1031 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1032
1033 if (status1 == 6 && status2 == 7) {
1034 up->port.type = PORT_16750;
1035 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1036 return;
1037 }
1038
1039 /*
1040 * Try writing and reading the UART_IER_UUE bit (b6).
1041 * If it works, this is probably one of the Xscale platform's
1042 * internal UARTs.
1043 * We're going to explicitly set the UUE bit to 0 before
1044 * trying to write and read a 1 just to make sure it's not
1045 * already a 1 and maybe locked there before we even start start.
1046 */
1047 iersave = serial_in(up, UART_IER);
1048 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1049 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1050 /*
1051 * OK it's in a known zero state, try writing and reading
1052 * without disturbing the current state of the other bits.
1053 */
1054 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1055 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1056 /*
1057 * It's an Xscale.
1058 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1059 */
1060 DEBUG_AUTOCONF("Xscale ");
1061 up->port.type = PORT_XSCALE;
1062 up->capabilities |= UART_CAP_UUE;
1063 return;
1064 }
1065 } else {
1066 /*
1067 * If we got here we couldn't force the IER_UUE bit to 0.
1068 * Log it and continue.
1069 */
1070 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1071 }
1072 serial_outp(up, UART_IER, iersave);
1073}
1074
1075/*
1076 * This routine is called by rs_init() to initialize a specific serial
1077 * port. It determines what type of UART chip this serial port is
1078 * using: 8250, 16450, 16550, 16550A. The important question is
1079 * whether or not this UART is a 16550A or not, since this will
1080 * determine whether or not we can use its FIFO features or not.
1081 */
1082static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1083{
1084 unsigned char status1, scratch, scratch2, scratch3;
1085 unsigned char save_lcr, save_mcr;
1086 unsigned long flags;
1087
1088 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1089 return;
1090
80647b95 1091 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1092 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1093
1094 /*
1095 * We really do need global IRQs disabled here - we're going to
1096 * be frobbing the chips IRQ enable register to see if it exists.
1097 */
1098 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1099
1100 up->capabilities = 0;
4ba5e35d 1101 up->bugs = 0;
1da177e4
LT		 1102
1103 if (!(up->port.flags & UPF_BUGGY_UART)) {
1104 /*
1105 * Do a simple existence test first; if we fail this,
1106 * there's no point trying anything else.
bd71c182 1107 *
1da177e4
LT		 1108 * 0x80 is used as a nonsense port to prevent against
1109 * false positives due to ISA bus float. The
1110 * assumption is that 0x80 is a non-existent port;
1111 * which should be safe since include/asm/io.h also
1112 * makes this assumption.
1113 *
1114 * Note: this is safe as long as MCR bit 4 is clear
1115 * and the device is in "PC" mode.
1116 */
1117 scratch = serial_inp(up, UART_IER);
1118 serial_outp(up, UART_IER, 0);
1119#ifdef __i386__
1120 outb(0xff, 0x080);
1121#endif
48212008
TH		 1122 /*
1123 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1124 * 16C754B) allow only to modify them if an EFR bit is set.
1125 */
1126 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1127 serial_outp(up, UART_IER, 0x0F);
1128#ifdef __i386__
1129 outb(0, 0x080);
1130#endif
48212008 1131 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1132 serial_outp(up, UART_IER, scratch);
1133 if (scratch2 != 0 || scratch3 != 0x0F) {
1134 /*
1135 * We failed; there's nothing here
1136 */
1137 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1138 scratch2, scratch3);
1139 goto out;
1140 }
1141 }
1142
1143 save_mcr = serial_in(up, UART_MCR);
1144 save_lcr = serial_in(up, UART_LCR);
1145
bd71c182 1146 /*
1da177e4
LT		 1147 * Check to see if a UART is really there. Certain broken
1148 * internal modems based on the Rockwell chipset fail this
1149 * test, because they apparently don't implement the loopback
1150 * test mode. So this test is skipped on the COM 1 through
1151 * COM 4 ports. This *should* be safe, since no board
1152 * manufacturer would be stupid enough to design a board
1153 * that conflicts with COM 1-4 --- we hope!
1154 */
1155 if (!(up->port.flags & UPF_SKIP_TEST)) {
1156 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1157 status1 = serial_inp(up, UART_MSR) & 0xF0;
1158 serial_outp(up, UART_MCR, save_mcr);
1159 if (status1 != 0x90) {
1160 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1161 status1);
1162 goto out;
1163 }
1164 }
1165
1166 /*
1167 * We're pretty sure there's a port here. Lets find out what
1168 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1169 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1170 * determines what we test for next.
1171 *
1172 * We also initialise the EFR (if any) to zero for later. The
1173 * EFR occupies the same register location as the FCR and IIR.
1174 */
1175 serial_outp(up, UART_LCR, 0xBF);
1176 serial_outp(up, UART_EFR, 0);
1177 serial_outp(up, UART_LCR, 0);
1178
1179 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1180 scratch = serial_in(up, UART_IIR) >> 6;
1181
1182 DEBUG_AUTOCONF("iir=%d ", scratch);
1183
1184 switch (scratch) {
1185 case 0:
1186 autoconfig_8250(up);
1187 break;
1188 case 1:
1189 up->port.type = PORT_UNKNOWN;
1190 break;
1191 case 2:
1192 up->port.type = PORT_16550;
1193 break;
1194 case 3:
1195 autoconfig_16550a(up);
1196 break;
1197 }
1198
1199#ifdef CONFIG_SERIAL_8250_RSA
1200 /*
1201 * Only probe for RSA ports if we got the region.
1202 */
1203 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1204 int i;
1205
1206 for (i = 0 ; i < probe_rsa_count; ++i) {
1207 if (probe_rsa[i] == up->port.iobase &&
1208 __enable_rsa(up)) {
1209 up->port.type = PORT_RSA;
1210 break;
1211 }
1212 }
1213 }
1214#endif
21c614a7 1215
1da177e4
LT		 1216 serial_outp(up, UART_LCR, save_lcr);
1217
1218 if (up->capabilities != uart_config[up->port.type].flags) {
1219 printk(KERN_WARNING
1220 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1221 serial_index(&up->port), up->capabilities,
1222 uart_config[up->port.type].flags);
1da177e4
LT		 1223 }
1224
1225 up->port.fifosize = uart_config[up->port.type].fifo_size;
1226 up->capabilities = uart_config[up->port.type].flags;
1227 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1228
1229 if (up->port.type == PORT_UNKNOWN)
1230 goto out;
1231
1232 /*
1233 * Reset the UART.
1234 */
1235#ifdef CONFIG_SERIAL_8250_RSA
1236 if (up->port.type == PORT_RSA)
1237 serial_outp(up, UART_RSA_FRR, 0);
1238#endif
1239 serial_outp(up, UART_MCR, save_mcr);
1240 serial8250_clear_fifos(up);
40b36daa 1241 serial_in(up, UART_RX);
5c8c755c
LB		 1242 if (up->capabilities & UART_CAP_UUE)
1243 serial_outp(up, UART_IER, UART_IER_UUE);
1244 else
1245 serial_outp(up, UART_IER, 0);
1da177e4 1246
bd71c182 1247 out:
1da177e4 1248 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1249 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1250}
1251
1252static void autoconfig_irq(struct uart_8250_port *up)
1253{
1254 unsigned char save_mcr, save_ier;
1255 unsigned char save_ICP = 0;
1256 unsigned int ICP = 0;
1257 unsigned long irqs;
1258 int irq;
1259
1260 if (up->port.flags & UPF_FOURPORT) {
1261 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1262 save_ICP = inb_p(ICP);
1263 outb_p(0x80, ICP);
1264 (void) inb_p(ICP);
1265 }
1266
1267 /* forget possible initially masked and pending IRQ */
1268 probe_irq_off(probe_irq_on());
1269 save_mcr = serial_inp(up, UART_MCR);
1270 save_ier = serial_inp(up, UART_IER);
1271 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1272
1da177e4
LT		 1273 irqs = probe_irq_on();
1274 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1275 udelay(10);
1276 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1277 serial_outp(up, UART_MCR,
1278 UART_MCR_DTR | UART_MCR_RTS);
1279 } else {
1280 serial_outp(up, UART_MCR,
1281 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1282 }
1283 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1284 (void)serial_inp(up, UART_LSR);
1285 (void)serial_inp(up, UART_RX);
1286 (void)serial_inp(up, UART_IIR);
1287 (void)serial_inp(up, UART_MSR);
1288 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1289 udelay(20);
1da177e4
LT		 1290 irq = probe_irq_off(irqs);
1291
1292 serial_outp(up, UART_MCR, save_mcr);
1293 serial_outp(up, UART_IER, save_ier);
1294
1295 if (up->port.flags & UPF_FOURPORT)
1296 outb_p(save_ICP, ICP);
1297
1298 up->port.irq = (irq > 0) ? irq : 0;
1299}
1300
e763b90c
RK		 1301static inline void __stop_tx(struct uart_8250_port *p)
1302{
1303 if (p->ier & UART_IER_THRI) {
1304 p->ier &= ~UART_IER_THRI;
1305 serial_out(p, UART_IER, p->ier);
1306 }
1307}
1308
b129a8cc 1309static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1310{
1311 struct uart_8250_port *up = (struct uart_8250_port *)port;
1312
e763b90c 1313 __stop_tx(up);
1da177e4
LT		 1314
1315 /*
e763b90c 1316 * We really want to stop the transmitter from sending.
1da177e4 1317 */
e763b90c 1318 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1319 up->acr |= UART_ACR_TXDIS;
1320 serial_icr_write(up, UART_ACR, up->acr);
1321 }
1322}
1323
55d3b282
RK		 1324static void transmit_chars(struct uart_8250_port *up);
1325
b129a8cc 1326static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1327{
1328 struct uart_8250_port *up = (struct uart_8250_port *)port;
1329
1330 if (!(up->ier & UART_IER_THRI)) {
1331 up->ier |= UART_IER_THRI;
1332 serial_out(up, UART_IER, up->ier);
55d3b282 1333
67f7654e 1334 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1335 unsigned char lsr;
55d3b282 1336 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1337 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1338 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1339 (lsr & UART_LSR_THRE) :
1340 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1341 transmit_chars(up);
1342 }
1da177e4 1343 }
e763b90c 1344
1da177e4 1345 /*
e763b90c 1346 * Re-enable the transmitter if we disabled it.
1da177e4 1347 */
e763b90c 1348 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1349 up->acr &= ~UART_ACR_TXDIS;
1350 serial_icr_write(up, UART_ACR, up->acr);
1351 }
1352}
1353
1354static void serial8250_stop_rx(struct uart_port *port)
1355{
1356 struct uart_8250_port *up = (struct uart_8250_port *)port;
1357
1358 up->ier &= ~UART_IER_RLSI;
1359 up->port.read_status_mask &= ~UART_LSR_DR;
1360 serial_out(up, UART_IER, up->ier);
1361}
1362
1363static void serial8250_enable_ms(struct uart_port *port)
1364{
1365 struct uart_8250_port *up = (struct uart_8250_port *)port;
1366
21c614a7
PA		 1367 /* no MSR capabilities */
1368 if (up->bugs & UART_BUG_NOMSR)
1369 return;
1370
1da177e4
LT		 1371 up->ier |= UART_IER_MSI;
1372 serial_out(up, UART_IER, up->ier);
1373}
1374
ea8874dc 1375static void
cc79aa9d 1376receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1377{
ebd2c8f6 1378 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1379 unsigned char ch, lsr = *status;
1380 int max_count = 256;
1381 char flag;
1382
1383 do {
7500b1f6
AR		 1384 if (likely(lsr & UART_LSR_DR))
1385 ch = serial_inp(up, UART_RX);
1386 else
1387 /*
1388 * Intel 82571 has a Serial Over Lan device that will
1389 * set UART_LSR_BI without setting UART_LSR_DR when
1390 * it receives a break. To avoid reading from the
1391 * receive buffer without UART_LSR_DR bit set, we
1392 * just force the read character to be 0
1393 */
1394 ch = 0;
1395
1da177e4
LT		 1396 flag = TTY_NORMAL;
1397 up->port.icount.rx++;
1398
ad4c2aa6
CM		 1399 lsr |= up->lsr_saved_flags;
1400 up->lsr_saved_flags = 0;
1da177e4 1401
ad4c2aa6 1402 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1403 /*
1404 * For statistics only
1405 */
1406 if (lsr & UART_LSR_BI) {
1407 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1408 up->port.icount.brk++;
1409 /*
1410 * We do the SysRQ and SAK checking
1411 * here because otherwise the break
1412 * may get masked by ignore_status_mask
1413 * or read_status_mask.
1414 */
1415 if (uart_handle_break(&up->port))
1416 goto ignore_char;
1417 } else if (lsr & UART_LSR_PE)
1418 up->port.icount.parity++;
1419 else if (lsr & UART_LSR_FE)
1420 up->port.icount.frame++;
1421 if (lsr & UART_LSR_OE)
1422 up->port.icount.overrun++;
1423
1424 /*
23907eb8 1425 * Mask off conditions which should be ignored.
1da177e4
LT		 1426 */
1427 lsr &= up->port.read_status_mask;
1428
1429 if (lsr & UART_LSR_BI) {
1430 DEBUG_INTR("handling break....");
1431 flag = TTY_BREAK;
1432 } else if (lsr & UART_LSR_PE)
1433 flag = TTY_PARITY;
1434 else if (lsr & UART_LSR_FE)
1435 flag = TTY_FRAME;
1436 }
7d12e780 1437 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1438 goto ignore_char;
05ab3014
RK		 1439
1440 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1441
6f803cd0 1442ignore_char:
1da177e4 1443 lsr = serial_inp(up, UART_LSR);
7500b1f6 1444 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1445 spin_unlock(&up->port.lock);
1446 tty_flip_buffer_push(tty);
1447 spin_lock(&up->port.lock);
1448 *status = lsr;
1449}
1450
ea8874dc 1451static void transmit_chars(struct uart_8250_port *up)
1da177e4 1452{
ebd2c8f6 1453 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1454 int count;
1455
1456 if (up->port.x_char) {
1457 serial_outp(up, UART_TX, up->port.x_char);
1458 up->port.icount.tx++;
1459 up->port.x_char = 0;
1460 return;
1461 }
b129a8cc
RK		 1462 if (uart_tx_stopped(&up->port)) {
1463 serial8250_stop_tx(&up->port);
1464 return;
1465 }
1466 if (uart_circ_empty(xmit)) {
e763b90c 1467 __stop_tx(up);
1da177e4
LT		 1468 return;
1469 }
1470
1471 count = up->tx_loadsz;
1472 do {
1473 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1474 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1475 up->port.icount.tx++;
1476 if (uart_circ_empty(xmit))
1477 break;
1478 } while (--count > 0);
1479
1480 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1481 uart_write_wakeup(&up->port);
1482
1483 DEBUG_INTR("THRE...");
1484
1485 if (uart_circ_empty(xmit))
e763b90c 1486 __stop_tx(up);
1da177e4
LT		 1487}
1488
2af7cd68 1489static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1490{
2af7cd68
RK		 1491 unsigned int status = serial_in(up, UART_MSR);
1492
ad4c2aa6
CM		 1493 status |= up->msr_saved_flags;
1494 up->msr_saved_flags = 0;
fdc30b3d 1495 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1496 up->port.state != NULL) {
2af7cd68
RK		 1497 if (status & UART_MSR_TERI)
1498 up->port.icount.rng++;
1499 if (status & UART_MSR_DDSR)
1500 up->port.icount.dsr++;
1501 if (status & UART_MSR_DDCD)
1502 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1503 if (status & UART_MSR_DCTS)
1504 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1505
bdc04e31 1506 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1507 }
1da177e4 1508
2af7cd68 1509 return status;
1da177e4
LT		 1510}
1511
1512/*
1513 * This handles the interrupt from one port.
1514 */
b5d674ab 1515static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1516{
45e24601 1517 unsigned int status;
4bf3631c 1518 unsigned long flags;
45e24601 1519
4bf3631c 1520 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1521
1522 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1523
1524 DEBUG_INTR("status = %x...", status);
1525
7500b1f6 1526 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1527 receive_chars(up, &status);
1da177e4
LT		 1528 check_modem_status(up);
1529 if (status & UART_LSR_THRE)
1530 transmit_chars(up);
45e24601 1531
4bf3631c 1532 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1533}
1534
1535/*
1536 * This is the serial driver's interrupt routine.
1537 *
1538 * Arjan thinks the old way was overly complex, so it got simplified.
1539 * Alan disagrees, saying that need the complexity to handle the weird
1540 * nature of ISA shared interrupts. (This is a special exception.)
1541 *
1542 * In order to handle ISA shared interrupts properly, we need to check
1543 * that all ports have been serviced, and therefore the ISA interrupt
1544 * line has been de-asserted.
1545 *
1546 * This means we need to loop through all ports. checking that they
1547 * don't have an interrupt pending.
1548 */
7d12e780 1549static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1550{
1551 struct irq_info *i = dev_id;
1552 struct list_head *l, *end = NULL;
1553 int pass_counter = 0, handled = 0;
1554
1555 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1556
1557 spin_lock(&i->lock);
1558
1559 l = i->head;
1560 do {
1561 struct uart_8250_port *up;
1562 unsigned int iir;
1563
1564 up = list_entry(l, struct uart_8250_port, list);
1565
1566 iir = serial_in(up, UART_IIR);
1567 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1568 serial8250_handle_port(up);
1da177e4
LT		 1569
1570 handled = 1;
1571
beab697a
MSJ		 1572 end = NULL;
1573 } else if (up->port.iotype == UPIO_DWAPB &&
1574 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1575 /* The DesignWare APB UART has an Busy Detect (0x07)
1576 * interrupt meaning an LCR write attempt occured while the
1577 * UART was busy. The interrupt must be cleared by reading
1578 * the UART status register (USR) and the LCR re-written. */
1579 unsigned int status;
1580 status = *(volatile u32 *)up->port.private_data;
1581 serial_out(up, UART_LCR, up->lcr);
1582
1583 handled = 1;
1584
1da177e4
LT		 1585 end = NULL;
1586 } else if (end == NULL)
1587 end = l;
1588
1589 l = l->next;
1590
1591 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1592 /* If we hit this, we're dead. */
1593 printk(KERN_ERR "serial8250: too much work for "
1594 "irq%d\n", irq);
1595 break;
1596 }
1597 } while (l != end);
1598
1599 spin_unlock(&i->lock);
1600
1601 DEBUG_INTR("end.\n");
1602
1603 return IRQ_RETVAL(handled);
1604}
1605
1606/*
1607 * To support ISA shared interrupts, we need to have one interrupt
1608 * handler that ensures that the IRQ line has been deasserted
1609 * before returning. Failing to do this will result in the IRQ
1610 * line being stuck active, and, since ISA irqs are edge triggered,
1611 * no more IRQs will be seen.
1612 */
1613static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1614{
1615 spin_lock_irq(&i->lock);
1616
1617 if (!list_empty(i->head)) {
1618 if (i->head == &up->list)
1619 i->head = i->head->next;
1620 list_del(&up->list);
1621 } else {
1622 BUG_ON(i->head != &up->list);
1623 i->head = NULL;
1624 }
1da177e4 1625 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1626 /* List empty so throw away the hash node */
1627 if (i->head == NULL) {
1628 hlist_del(&i->node);
1629 kfree(i);
1630 }
1da177e4
LT		 1631}
1632
1633static int serial_link_irq_chain(struct uart_8250_port *up)
1634{
25db8ad5
AC		 1635 struct hlist_head *h;
1636 struct hlist_node *n;
1637 struct irq_info *i;
40663cc7 1638 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1639
25db8ad5
AC		 1640 mutex_lock(&hash_mutex);
1641
1642 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1643
1644 hlist_for_each(n, h) {
1645 i = hlist_entry(n, struct irq_info, node);
1646 if (i->irq == up->port.irq)
1647 break;
1648 }
1649
1650 if (n == NULL) {
1651 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1652 if (i == NULL) {
1653 mutex_unlock(&hash_mutex);
1654 return -ENOMEM;
1655 }
1656 spin_lock_init(&i->lock);
1657 i->irq = up->port.irq;
1658 hlist_add_head(&i->node, h);
1659 }
1660 mutex_unlock(&hash_mutex);
1661
1da177e4
LT		 1662 spin_lock_irq(&i->lock);
1663
1664 if (i->head) {
1665 list_add(&up->list, i->head);
1666 spin_unlock_irq(&i->lock);
1667
1668 ret = 0;
1669 } else {
1670 INIT_LIST_HEAD(&up->list);
1671 i->head = &up->list;
1672 spin_unlock_irq(&i->lock);
1c2f0493 1673 irq_flags |= up->port.irqflags;
1da177e4
LT		 1674 ret = request_irq(up->port.irq, serial8250_interrupt,
1675 irq_flags, "serial", i);
1676 if (ret < 0)
1677 serial_do_unlink(i, up);
1678 }
1679
1680 return ret;
1681}
1682
1683static void serial_unlink_irq_chain(struct uart_8250_port *up)
1684{
25db8ad5
AC		 1685 struct irq_info *i;
1686 struct hlist_node *n;
1687 struct hlist_head *h;
1da177e4 1688
25db8ad5
AC		 1689 mutex_lock(&hash_mutex);
1690
1691 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1692
1693 hlist_for_each(n, h) {
1694 i = hlist_entry(n, struct irq_info, node);
1695 if (i->irq == up->port.irq)
1696 break;
1697 }
1698
1699 BUG_ON(n == NULL);
1da177e4
LT		 1700 BUG_ON(i->head == NULL);
1701
1702 if (list_empty(i->head))
1703 free_irq(up->port.irq, i);
1704
1705 serial_do_unlink(i, up);
25db8ad5 1706 mutex_unlock(&hash_mutex);
1da177e4
LT		 1707}
1708
40b36daa
AW		 1709/* Base timer interval for polling */
1710static inline int poll_timeout(int timeout)
1711{
1712 return timeout > 6 ? (timeout / 2 - 2) : 1;
1713}
1714
1da177e4
LT		 1715/*
1716 * This function is used to handle ports that do not have an
1717 * interrupt. This doesn't work very well for 16450's, but gives
1718 * barely passable results for a 16550A. (Although at the expense
1719 * of much CPU overhead).
1720 */
1721static void serial8250_timeout(unsigned long data)
1722{
1723 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1724 unsigned int iir;
1725
1726 iir = serial_in(up, UART_IIR);
45e24601 1727 if (!(iir & UART_IIR_NO_INT))
7d12e780 1728 serial8250_handle_port(up);
40b36daa
AW		 1729 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1730}
1731
1732static void serial8250_backup_timeout(unsigned long data)
1733{
1734 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1735 unsigned int iir, ier = 0, lsr;
1736 unsigned long flags;
40b36daa
AW		 1737
1738 /*
1739 * Must disable interrupts or else we risk racing with the interrupt
1740 * based handler.
1741 */
1742 if (is_real_interrupt(up->port.irq)) {
1743 ier = serial_in(up, UART_IER);
1744 serial_out(up, UART_IER, 0);
1745 }
1da177e4 1746
40b36daa
AW		 1747 iir = serial_in(up, UART_IIR);
1748
1749 /*
1750 * This should be a safe test for anyone who doesn't trust the
1751 * IIR bits on their UART, but it's specifically designed for
1752 * the "Diva" UART used on the management processor on many HP
1753 * ia64 and parisc boxes.
1754 */
ad4c2aa6
CM		 1755 spin_lock_irqsave(&up->port.lock, flags);
1756 lsr = serial_in(up, UART_LSR);
1757 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1758 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1759 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1760 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1761 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1762 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1763 iir |= UART_IIR_THRI;
1764 }
1765
1766 if (!(iir & UART_IIR_NO_INT))
1767 serial8250_handle_port(up);
1768
1769 if (is_real_interrupt(up->port.irq))
1770 serial_out(up, UART_IER, ier);
1771
1772 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1773 mod_timer(&up->timer,
1774 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1775}
1776
1777static unsigned int serial8250_tx_empty(struct uart_port *port)
1778{
1779 struct uart_8250_port *up = (struct uart_8250_port *)port;
1780 unsigned long flags;
ad4c2aa6 1781 unsigned int lsr;
1da177e4
LT		 1782
1783 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1784 lsr = serial_in(up, UART_LSR);
1785 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1786 spin_unlock_irqrestore(&up->port.lock, flags);
1787
bca47613 1788 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1da177e4
LT		 1789}
1790
1791static unsigned int serial8250_get_mctrl(struct uart_port *port)
1792{
1793 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1794 unsigned int status;
1da177e4
LT		 1795 unsigned int ret;
1796
2af7cd68 1797 status = check_modem_status(up);
1da177e4
LT		 1798
1799 ret = 0;
1800 if (status & UART_MSR_DCD)
1801 ret |= TIOCM_CAR;
1802 if (status & UART_MSR_RI)
1803 ret |= TIOCM_RNG;
1804 if (status & UART_MSR_DSR)
1805 ret |= TIOCM_DSR;
1806 if (status & UART_MSR_CTS)
1807 ret |= TIOCM_CTS;
1808 return ret;
1809}
1810
1811static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1812{
1813 struct uart_8250_port *up = (struct uart_8250_port *)port;
1814 unsigned char mcr = 0;
1815
1816 if (mctrl & TIOCM_RTS)
1817 mcr |= UART_MCR_RTS;
1818 if (mctrl & TIOCM_DTR)
1819 mcr |= UART_MCR_DTR;
1820 if (mctrl & TIOCM_OUT1)
1821 mcr |= UART_MCR_OUT1;
1822 if (mctrl & TIOCM_OUT2)
1823 mcr |= UART_MCR_OUT2;
1824 if (mctrl & TIOCM_LOOP)
1825 mcr |= UART_MCR_LOOP;
1826
1827 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1828
1829 serial_out(up, UART_MCR, mcr);
1830}
1831
1832static void serial8250_break_ctl(struct uart_port *port, int break_state)
1833{
1834 struct uart_8250_port *up = (struct uart_8250_port *)port;
1835 unsigned long flags;
1836
1837 spin_lock_irqsave(&up->port.lock, flags);
1838 if (break_state == -1)
1839 up->lcr |= UART_LCR_SBC;
1840 else
1841 up->lcr &= ~UART_LCR_SBC;
1842 serial_out(up, UART_LCR, up->lcr);
1843 spin_unlock_irqrestore(&up->port.lock, flags);
1844}
1845
40b36daa
AW		 1846/*
1847 * Wait for transmitter & holding register to empty
1848 */
b5d674ab 1849static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1850{
1851 unsigned int status, tmout = 10000;
1852
1853 /* Wait up to 10ms for the character(s) to be sent. */
1854 do {
1855 status = serial_in(up, UART_LSR);
1856
ad4c2aa6 1857 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1858
1859 if (--tmout == 0)
1860 break;
1861 udelay(1);
1862 } while ((status & bits) != bits);
1863
1864 /* Wait up to 1s for flow control if necessary */
1865 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1866 unsigned int tmout;
1867 for (tmout = 1000000; tmout; tmout--) {
1868 unsigned int msr = serial_in(up, UART_MSR);
1869 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1870 if (msr & UART_MSR_CTS)
1871 break;
40b36daa
AW		 1872 udelay(1);
1873 touch_nmi_watchdog();
1874 }
1875 }
1876}
1877
f2d937f3
JW		 1878#ifdef CONFIG_CONSOLE_POLL
1879/*
1880 * Console polling routines for writing and reading from the uart while
1881 * in an interrupt or debug context.
1882 */
1883
1884static int serial8250_get_poll_char(struct uart_port *port)
1885{
1886 struct uart_8250_port *up = (struct uart_8250_port *)port;
1887 unsigned char lsr = serial_inp(up, UART_LSR);
1888
f5316b4a
JW		 1889 if (!(lsr & UART_LSR_DR))
1890 return NO_POLL_CHAR;
f2d937f3
JW		 1891
1892 return serial_inp(up, UART_RX);
1893}
1894
1895
1896static void serial8250_put_poll_char(struct uart_port *port,
1897 unsigned char c)
1898{
1899 unsigned int ier;
1900 struct uart_8250_port *up = (struct uart_8250_port *)port;
1901
1902 /*
1903 * First save the IER then disable the interrupts
1904 */
1905 ier = serial_in(up, UART_IER);
1906 if (up->capabilities & UART_CAP_UUE)
1907 serial_out(up, UART_IER, UART_IER_UUE);
1908 else
1909 serial_out(up, UART_IER, 0);
1910
1911 wait_for_xmitr(up, BOTH_EMPTY);
1912 /*
1913 * Send the character out.
1914 * If a LF, also do CR...
1915 */
1916 serial_out(up, UART_TX, c);
1917 if (c == 10) {
1918 wait_for_xmitr(up, BOTH_EMPTY);
1919 serial_out(up, UART_TX, 13);
1920 }
1921
1922 /*
1923 * Finally, wait for transmitter to become empty
1924 * and restore the IER
1925 */
1926 wait_for_xmitr(up, BOTH_EMPTY);
1927 serial_out(up, UART_IER, ier);
1928}
1929
1930#endif /* CONFIG_CONSOLE_POLL */
1931
1da177e4
LT		 1932static int serial8250_startup(struct uart_port *port)
1933{
1934 struct uart_8250_port *up = (struct uart_8250_port *)port;
1935 unsigned long flags;
55d3b282 1936 unsigned char lsr, iir;
1da177e4
LT		 1937 int retval;
1938
1939 up->capabilities = uart_config[up->port.type].flags;
1940 up->mcr = 0;
1941
b8e7e40a
AC		 1942 if (up->port.iotype != up->cur_iotype)
1943 set_io_from_upio(port);
1944
1da177e4
LT		 1945 if (up->port.type == PORT_16C950) {
1946 /* Wake up and initialize UART */
1947 up->acr = 0;
1948 serial_outp(up, UART_LCR, 0xBF);
1949 serial_outp(up, UART_EFR, UART_EFR_ECB);
1950 serial_outp(up, UART_IER, 0);
1951 serial_outp(up, UART_LCR, 0);
1952 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1953 serial_outp(up, UART_LCR, 0xBF);
1954 serial_outp(up, UART_EFR, UART_EFR_ECB);
1955 serial_outp(up, UART_LCR, 0);
1956 }
1957
1958#ifdef CONFIG_SERIAL_8250_RSA
1959 /*
1960 * If this is an RSA port, see if we can kick it up to the
1961 * higher speed clock.
1962 */
1963 enable_rsa(up);
1964#endif
1965
1966 /*
1967 * Clear the FIFO buffers and disable them.
7f927fcc 1968 * (they will be reenabled in set_termios())
1da177e4
LT		 1969 */
1970 serial8250_clear_fifos(up);
1971
1972 /*
1973 * Clear the interrupt registers.
1974 */
1975 (void) serial_inp(up, UART_LSR);
1976 (void) serial_inp(up, UART_RX);
1977 (void) serial_inp(up, UART_IIR);
1978 (void) serial_inp(up, UART_MSR);
1979
1980 /*
1981 * At this point, there's no way the LSR could still be 0xff;
1982 * if it is, then bail out, because there's likely no UART
1983 * here.
1984 */
1985 if (!(up->port.flags & UPF_BUGGY_UART) &&
1986 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 1987 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1988 serial_index(&up->port));
1da177e4
LT		 1989 return -ENODEV;
1990 }
1991
1992 /*
1993 * For a XR16C850, we need to set the trigger levels
1994 */
1995 if (up->port.type == PORT_16850) {
1996 unsigned char fctr;
1997
1998 serial_outp(up, UART_LCR, 0xbf);
1999
2000 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2001 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2002 serial_outp(up, UART_TRG, UART_TRG_96);
2003 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2004 serial_outp(up, UART_TRG, UART_TRG_96);
2005
2006 serial_outp(up, UART_LCR, 0);
2007 }
2008
40b36daa 2009 if (is_real_interrupt(up->port.irq)) {
01c194d9 2010 unsigned char iir1;
40b36daa
AW		 2011 /*
2012 * Test for UARTs that do not reassert THRE when the
2013 * transmitter is idle and the interrupt has already
2014 * been cleared. Real 16550s should always reassert
2015 * this interrupt whenever the transmitter is idle and
2016 * the interrupt is enabled. Delays are necessary to
2017 * allow register changes to become visible.
2018 */
c389d27b 2019 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2020 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2021 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2022
2023 wait_for_xmitr(up, UART_LSR_THRE);
2024 serial_out_sync(up, UART_IER, UART_IER_THRI);
2025 udelay(1); /* allow THRE to set */
01c194d9 2026 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2027 serial_out(up, UART_IER, 0);
2028 serial_out_sync(up, UART_IER, UART_IER_THRI);
2029 udelay(1); /* allow a working UART time to re-assert THRE */
2030 iir = serial_in(up, UART_IIR);
2031 serial_out(up, UART_IER, 0);
2032
1c2f0493 2033 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2034 enable_irq(up->port.irq);
c389d27b 2035 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2036
2037 /*
2038 * If the interrupt is not reasserted, setup a timer to
2039 * kick the UART on a regular basis.
2040 */
01c194d9 2041 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2042 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2043 pr_debug("ttyS%d - using backup timer\n",
2044 serial_index(port));
40b36daa
AW		 2045 }
2046 }
2047
363f66fe
WN		 2048 /*
2049 * The above check will only give an accurate result the first time
2050 * the port is opened so this value needs to be preserved.
2051 */
2052 if (up->bugs & UART_BUG_THRE) {
2053 up->timer.function = serial8250_backup_timeout;
2054 up->timer.data = (unsigned long)up;
2055 mod_timer(&up->timer, jiffies +
2056 poll_timeout(up->port.timeout) + HZ / 5);
2057 }
2058
1da177e4
LT		 2059 /*
2060 * If the "interrupt" for this port doesn't correspond with any
2061 * hardware interrupt, we use a timer-based system. The original
2062 * driver used to do this with IRQ0.
2063 */
2064 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2065 up->timer.data = (unsigned long)up;
40b36daa 2066 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 2067 } else {
2068 retval = serial_link_irq_chain(up);
2069 if (retval)
2070 return retval;
2071 }
2072
2073 /*
2074 * Now, initialize the UART
2075 */
2076 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2077
2078 spin_lock_irqsave(&up->port.lock, flags);
2079 if (up->port.flags & UPF_FOURPORT) {
2080 if (!is_real_interrupt(up->port.irq))
2081 up->port.mctrl |= TIOCM_OUT1;
2082 } else
2083 /*
2084 * Most PC uarts need OUT2 raised to enable interrupts.
2085 */
2086 if (is_real_interrupt(up->port.irq))
2087 up->port.mctrl |= TIOCM_OUT2;
2088
2089 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2090
b6adea33
MCC		 2091 /* Serial over Lan (SoL) hack:
2092 Intel 8257x Gigabit ethernet chips have a
2093 16550 emulation, to be used for Serial Over Lan.
2094 Those chips take a longer time than a normal
2095 serial device to signalize that a transmission
2096 data was queued. Due to that, the above test generally
2097 fails. One solution would be to delay the reading of
2098 iir. However, this is not reliable, since the timeout
2099 is variable. So, let's just don't test if we receive
2100 TX irq. This way, we'll never enable UART_BUG_TXEN.
2101 */
d41a4b51 2102 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2103 goto dont_test_tx_en;
2104
55d3b282
RK		 2105 /*
2106 * Do a quick test to see if we receive an
2107 * interrupt when we enable the TX irq.
2108 */
2109 serial_outp(up, UART_IER, UART_IER_THRI);
2110 lsr = serial_in(up, UART_LSR);
2111 iir = serial_in(up, UART_IIR);
2112 serial_outp(up, UART_IER, 0);
2113
2114 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2115 if (!(up->bugs & UART_BUG_TXEN)) {
2116 up->bugs |= UART_BUG_TXEN;
55d3b282 2117 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2118 serial_index(port));
55d3b282
RK		 2119 }
2120 } else {
67f7654e 2121 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2122 }
2123
b6adea33 2124dont_test_tx_en:
1da177e4
LT		 2125 spin_unlock_irqrestore(&up->port.lock, flags);
2126
ad4c2aa6
CM		 2127 /*
2128 * Clear the interrupt registers again for luck, and clear the
2129 * saved flags to avoid getting false values from polling
2130 * routines or the previous session.
2131 */
2132 serial_inp(up, UART_LSR);
2133 serial_inp(up, UART_RX);
2134 serial_inp(up, UART_IIR);
2135 serial_inp(up, UART_MSR);
2136 up->lsr_saved_flags = 0;
2137 up->msr_saved_flags = 0;
2138
1da177e4
LT		 2139 /*
2140 * Finally, enable interrupts. Note: Modem status interrupts
2141 * are set via set_termios(), which will be occurring imminently
2142 * anyway, so we don't enable them here.
2143 */
2144 up->ier = UART_IER_RLSI | UART_IER_RDI;
2145 serial_outp(up, UART_IER, up->ier);
2146
2147 if (up->port.flags & UPF_FOURPORT) {
2148 unsigned int icp;
2149 /*
2150 * Enable interrupts on the AST Fourport board
2151 */
2152 icp = (up->port.iobase & 0xfe0) | 0x01f;
2153 outb_p(0x80, icp);
2154 (void) inb_p(icp);
2155 }
2156
1da177e4
LT		 2157 return 0;
2158}
2159
2160static void serial8250_shutdown(struct uart_port *port)
2161{
2162 struct uart_8250_port *up = (struct uart_8250_port *)port;
2163 unsigned long flags;
2164
2165 /*
2166 * Disable interrupts from this port
2167 */
2168 up->ier = 0;
2169 serial_outp(up, UART_IER, 0);
2170
2171 spin_lock_irqsave(&up->port.lock, flags);
2172 if (up->port.flags & UPF_FOURPORT) {
2173 /* reset interrupts on the AST Fourport board */
2174 inb((up->port.iobase & 0xfe0) | 0x1f);
2175 up->port.mctrl |= TIOCM_OUT1;
2176 } else
2177 up->port.mctrl &= ~TIOCM_OUT2;
2178
2179 serial8250_set_mctrl(&up->port, up->port.mctrl);
2180 spin_unlock_irqrestore(&up->port.lock, flags);
2181
2182 /*
2183 * Disable break condition and FIFOs
2184 */
2185 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2186 serial8250_clear_fifos(up);
2187
2188#ifdef CONFIG_SERIAL_8250_RSA
2189 /*
2190 * Reset the RSA board back to 115kbps compat mode.
2191 */
2192 disable_rsa(up);
2193#endif
2194
2195 /*
2196 * Read data port to reset things, and then unlink from
2197 * the IRQ chain.
2198 */
2199 (void) serial_in(up, UART_RX);
2200
40b36daa
AW		 2201 del_timer_sync(&up->timer);
2202 up->timer.function = serial8250_timeout;
2203 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2204 serial_unlink_irq_chain(up);
2205}
2206
2207static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2208{
2209 unsigned int quot;
2210
2211 /*
2212 * Handle magic divisors for baud rates above baud_base on
2213 * SMSC SuperIO chips.
2214 */
2215 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2216 baud == (port->uartclk/4))
2217 quot = 0x8001;
2218 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2219 baud == (port->uartclk/8))
2220 quot = 0x8002;
2221 else
2222 quot = uart_get_divisor(port, baud);
2223
2224 return quot;
2225}
2226
2227static void
606d099c
AC		 2228serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2229 struct ktermios *old)
1da177e4
LT		 2230{
2231 struct uart_8250_port *up = (struct uart_8250_port *)port;
2232 unsigned char cval, fcr = 0;
2233 unsigned long flags;
2234 unsigned int baud, quot;
2235
2236 switch (termios->c_cflag & CSIZE) {
2237 case CS5:
0a8b80c5 2238 cval = UART_LCR_WLEN5;
1da177e4
LT		 2239 break;
2240 case CS6:
0a8b80c5 2241 cval = UART_LCR_WLEN6;
1da177e4
LT		 2242 break;
2243 case CS7:
0a8b80c5 2244 cval = UART_LCR_WLEN7;
1da177e4
LT		 2245 break;
2246 default:
2247 case CS8:
0a8b80c5 2248 cval = UART_LCR_WLEN8;
1da177e4
LT		 2249 break;
2250 }
2251
2252 if (termios->c_cflag & CSTOPB)
0a8b80c5 2253 cval |= UART_LCR_STOP;
1da177e4
LT		 2254 if (termios->c_cflag & PARENB)
2255 cval |= UART_LCR_PARITY;
2256 if (!(termios->c_cflag & PARODD))
2257 cval |= UART_LCR_EPAR;
2258#ifdef CMSPAR
2259 if (termios->c_cflag & CMSPAR)
2260 cval |= UART_LCR_SPAR;
2261#endif
2262
2263 /*
2264 * Ask the core to calculate the divisor for us.
2265 */
24d481ec
AV		 2266 baud = uart_get_baud_rate(port, termios, old,
2267 port->uartclk / 16 / 0xffff,
2268 port->uartclk / 16);
1da177e4
LT		 2269 quot = serial8250_get_divisor(port, baud);
2270
2271 /*
4ba5e35d 2272 * Oxford Semi 952 rev B workaround
1da177e4 2273 */
4ba5e35d 2274 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2275 quot++;
1da177e4
LT		 2276
2277 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2278 if (baud < 2400)
2279 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2280 else
2281 fcr = uart_config[up->port.type].fcr;
2282 }
2283
2284 /*
2285 * MCR-based auto flow control. When AFE is enabled, RTS will be
2286 * deasserted when the receive FIFO contains more characters than
2287 * the trigger, or the MCR RTS bit is cleared. In the case where
2288 * the remote UART is not using CTS auto flow control, we must
2289 * have sufficient FIFO entries for the latency of the remote
2290 * UART to respond. IOW, at least 32 bytes of FIFO.
2291 */
2292 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2293 up->mcr &= ~UART_MCR_AFE;
2294 if (termios->c_cflag & CRTSCTS)
2295 up->mcr |= UART_MCR_AFE;
2296 }
2297
2298 /*
2299 * Ok, we're now changing the port state. Do it with
2300 * interrupts disabled.
2301 */
2302 spin_lock_irqsave(&up->port.lock, flags);
2303
2304 /*
2305 * Update the per-port timeout.
2306 */
2307 uart_update_timeout(port, termios->c_cflag, baud);
2308
2309 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2310 if (termios->c_iflag & INPCK)
2311 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2312 if (termios->c_iflag & (BRKINT | PARMRK))
2313 up->port.read_status_mask |= UART_LSR_BI;
2314
2315 /*
2316 * Characteres to ignore
2317 */
2318 up->port.ignore_status_mask = 0;
2319 if (termios->c_iflag & IGNPAR)
2320 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2321 if (termios->c_iflag & IGNBRK) {
2322 up->port.ignore_status_mask |= UART_LSR_BI;
2323 /*
2324 * If we're ignoring parity and break indicators,
2325 * ignore overruns too (for real raw support).
2326 */
2327 if (termios->c_iflag & IGNPAR)
2328 up->port.ignore_status_mask |= UART_LSR_OE;
2329 }
2330
2331 /*
2332 * ignore all characters if CREAD is not set
2333 */
2334 if ((termios->c_cflag & CREAD) == 0)
2335 up->port.ignore_status_mask |= UART_LSR_DR;
2336
2337 /*
2338 * CTS flow control flag and modem status interrupts
2339 */
2340 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2341 if (!(up->bugs & UART_BUG_NOMSR) &&
2342 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2343 up->ier |= UART_IER_MSI;
2344 if (up->capabilities & UART_CAP_UUE)
2345 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2346
2347 serial_out(up, UART_IER, up->ier);
2348
2349 if (up->capabilities & UART_CAP_EFR) {
2350 unsigned char efr = 0;
2351 /*
2352 * TI16C752/Startech hardware flow control. FIXME:
2353 * - TI16C752 requires control thresholds to be set.
2354 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2355 */
2356 if (termios->c_cflag & CRTSCTS)
2357 efr |= UART_EFR_CTS;
2358
2359 serial_outp(up, UART_LCR, 0xBF);
2360 serial_outp(up, UART_EFR, efr);
2361 }
2362
f2eda27d 2363#ifdef CONFIG_ARCH_OMAP
255341c6 2364 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2365 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2366 if (baud == 115200) {
2367 quot = 1;
2368 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2369 } else
2370 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2371 }
2372#endif
2373
1da177e4
LT		 2374 if (up->capabilities & UART_NATSEMI) {
2375 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2376 serial_outp(up, UART_LCR, 0xe0);
2377 } else {
2378 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2379 }
2380
b32b19b8 2381 serial_dl_write(up, quot);
1da177e4
LT		 2382
2383 /*
2384 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2385 * is written without DLAB set, this mode will be disabled.
2386 */
2387 if (up->port.type == PORT_16750)
2388 serial_outp(up, UART_FCR, fcr);
2389
2390 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2391 up->lcr = cval; /* Save LCR */
2392 if (up->port.type != PORT_16750) {
2393 if (fcr & UART_FCR_ENABLE_FIFO) {
2394 /* emulated UARTs (Lucent Venus 167x) need two steps */
2395 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2396 }
2397 serial_outp(up, UART_FCR, fcr); /* set fcr */
2398 }
2399 serial8250_set_mctrl(&up->port, up->port.mctrl);
2400 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2401 /* Don't rewrite B0 */
2402 if (tty_termios_baud_rate(termios))
2403 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2404}
2405
dc77f161
RG		 2406static void
2407serial8250_set_ldisc(struct uart_port *port)
2408{
2409 int line = port->line;
2410
2411 if (line >= port->state->port.tty->driver->num)
2412 return;
2413
2414 if (port->state->port.tty->ldisc->ops->num == N_PPS) {
2415 port->flags |= UPF_HARDPPS_CD;
2416 serial8250_enable_ms(port);
2417 } else
2418 port->flags &= ~UPF_HARDPPS_CD;
2419}
2420
1da177e4
LT		 2421static void
2422serial8250_pm(struct uart_port *port, unsigned int state,
2423 unsigned int oldstate)
2424{
2425 struct uart_8250_port *p = (struct uart_8250_port *)port;
2426
2427 serial8250_set_sleep(p, state != 0);
2428
2429 if (p->pm)
2430 p->pm(port, state, oldstate);
2431}
2432
f2eda27d
RK		 2433static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2434{
2435 if (pt->port.iotype == UPIO_AU)
b2b13cdf 2436 return 0x1000;
f2eda27d
RK		 2437#ifdef CONFIG_ARCH_OMAP
2438 if (is_omap_port(pt))
2439 return 0x16 << pt->port.regshift;
2440#endif
2441 return 8 << pt->port.regshift;
2442}
2443
1da177e4
LT		 2444/*
2445 * Resource handling.
2446 */
2447static int serial8250_request_std_resource(struct uart_8250_port *up)
2448{
f2eda27d 2449 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2450 int ret = 0;
2451
2452 switch (up->port.iotype) {
85835f44 2453 case UPIO_AU:
0b30d668
SS		 2454 case UPIO_TSI:
2455 case UPIO_MEM32:
1da177e4 2456 case UPIO_MEM:
beab697a 2457 case UPIO_DWAPB:
1da177e4
LT		 2458 if (!up->port.mapbase)
2459 break;
2460
2461 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2462 ret = -EBUSY;
2463 break;
2464 }
2465
2466 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2467 up->port.membase = ioremap_nocache(up->port.mapbase,
2468 size);
1da177e4
LT		 2469 if (!up->port.membase) {
2470 release_mem_region(up->port.mapbase, size);
2471 ret = -ENOMEM;
2472 }
2473 }
2474 break;
2475
2476 case UPIO_HUB6:
2477 case UPIO_PORT:
2478 if (!request_region(up->port.iobase, size, "serial"))
2479 ret = -EBUSY;
2480 break;
2481 }
2482 return ret;
2483}
2484
2485static void serial8250_release_std_resource(struct uart_8250_port *up)
2486{
f2eda27d 2487 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2488
2489 switch (up->port.iotype) {
85835f44 2490 case UPIO_AU:
0b30d668
SS		 2491 case UPIO_TSI:
2492 case UPIO_MEM32:
1da177e4 2493 case UPIO_MEM:
beab697a 2494 case UPIO_DWAPB:
1da177e4
LT		 2495 if (!up->port.mapbase)
2496 break;
2497
2498 if (up->port.flags & UPF_IOREMAP) {
2499 iounmap(up->port.membase);
2500 up->port.membase = NULL;
2501 }
2502
2503 release_mem_region(up->port.mapbase, size);
2504 break;
2505
2506 case UPIO_HUB6:
2507 case UPIO_PORT:
2508 release_region(up->port.iobase, size);
2509 break;
2510 }
2511}
2512
2513static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2514{
2515 unsigned long start = UART_RSA_BASE << up->port.regshift;
2516 unsigned int size = 8 << up->port.regshift;
0b30d668 2517 int ret = -EINVAL;
1da177e4
LT		 2518
2519 switch (up->port.iotype) {
1da177e4
LT		 2520 case UPIO_HUB6:
2521 case UPIO_PORT:
2522 start += up->port.iobase;
0b30d668
SS		 2523 if (request_region(start, size, "serial-rsa"))
2524 ret = 0;
2525 else
1da177e4
LT		 2526 ret = -EBUSY;
2527 break;
2528 }
2529
2530 return ret;
2531}
2532
2533static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2534{
2535 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2536 unsigned int size = 8 << up->port.regshift;
2537
2538 switch (up->port.iotype) {
1da177e4
LT		 2539 case UPIO_HUB6:
2540 case UPIO_PORT:
2541 release_region(up->port.iobase + offset, size);
2542 break;
2543 }
2544}
2545
2546static void serial8250_release_port(struct uart_port *port)
2547{
2548 struct uart_8250_port *up = (struct uart_8250_port *)port;
2549
2550 serial8250_release_std_resource(up);
2551 if (up->port.type == PORT_RSA)
2552 serial8250_release_rsa_resource(up);
2553}
2554
2555static int serial8250_request_port(struct uart_port *port)
2556{
2557 struct uart_8250_port *up = (struct uart_8250_port *)port;
2558 int ret = 0;
2559
2560 ret = serial8250_request_std_resource(up);
2561 if (ret == 0 && up->port.type == PORT_RSA) {
2562 ret = serial8250_request_rsa_resource(up);
2563 if (ret < 0)
2564 serial8250_release_std_resource(up);
2565 }
2566
2567 return ret;
2568}
2569
2570static void serial8250_config_port(struct uart_port *port, int flags)
2571{
2572 struct uart_8250_port *up = (struct uart_8250_port *)port;
2573 int probeflags = PROBE_ANY;
2574 int ret;
2575
1da177e4
LT		 2576 /*
2577 * Find the region that we can probe for. This in turn
2578 * tells us whether we can probe for the type of port.
2579 */
2580 ret = serial8250_request_std_resource(up);
2581 if (ret < 0)
2582 return;
2583
2584 ret = serial8250_request_rsa_resource(up);
2585 if (ret < 0)
2586 probeflags &= ~PROBE_RSA;
2587
b8e7e40a
AC		 2588 if (up->port.iotype != up->cur_iotype)
2589 set_io_from_upio(port);
2590
1da177e4
LT		 2591 if (flags & UART_CONFIG_TYPE)
2592 autoconfig(up, probeflags);
b2b13cdf 2593
b2b13cdf
ML		 2594 /* if access method is AU, it is a 16550 with a quirk */
2595 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2596 up->bugs |= UART_BUG_NOMSR;
b2b13cdf 2597
1da177e4
LT		 2598 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2599 autoconfig_irq(up);
2600
2601 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2602 serial8250_release_rsa_resource(up);
2603 if (up->port.type == PORT_UNKNOWN)
2604 serial8250_release_std_resource(up);
2605}
2606
2607static int
2608serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2609{
a62c4133 2610 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2611 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2612 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2613 ser->type == PORT_STARTECH)
2614 return -EINVAL;
2615 return 0;
2616}
2617
2618static const char *
2619serial8250_type(struct uart_port *port)
2620{
2621 int type = port->type;
2622
2623 if (type >= ARRAY_SIZE(uart_config))
2624 type = 0;
2625 return uart_config[type].name;
2626}
2627
2628static struct uart_ops serial8250_pops = {
2629 .tx_empty = serial8250_tx_empty,
2630 .set_mctrl = serial8250_set_mctrl,
2631 .get_mctrl = serial8250_get_mctrl,
2632 .stop_tx = serial8250_stop_tx,
2633 .start_tx = serial8250_start_tx,
2634 .stop_rx = serial8250_stop_rx,
2635 .enable_ms = serial8250_enable_ms,
2636 .break_ctl = serial8250_break_ctl,
2637 .startup = serial8250_startup,
2638 .shutdown = serial8250_shutdown,
2639 .set_termios = serial8250_set_termios,
dc77f161 2640 .set_ldisc = serial8250_set_ldisc,
1da177e4
LT		 2641 .pm = serial8250_pm,
2642 .type = serial8250_type,
2643 .release_port = serial8250_release_port,
2644 .request_port = serial8250_request_port,
2645 .config_port = serial8250_config_port,
2646 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2647#ifdef CONFIG_CONSOLE_POLL
2648 .poll_get_char = serial8250_get_poll_char,
2649 .poll_put_char = serial8250_put_poll_char,
2650#endif
1da177e4
LT		 2651};
2652
2653static struct uart_8250_port serial8250_ports[UART_NR];
2654
2655static void __init serial8250_isa_init_ports(void)
2656{
2657 struct uart_8250_port *up;
2658 static int first = 1;
4c0ebb80 2659 int i, irqflag = 0;
1da177e4
LT		 2660
2661 if (!first)
2662 return;
2663 first = 0;
2664
a61c2d78 2665 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2666 struct uart_8250_port *up = &serial8250_ports[i];
2667
2668 up->port.line = i;
2669 spin_lock_init(&up->port.lock);
2670
2671 init_timer(&up->timer);
2672 up->timer.function = serial8250_timeout;
2673
2674 /*
2675 * ALPHA_KLUDGE_MCR needs to be killed.
2676 */
2677 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2678 up->mcr_force = ALPHA_KLUDGE_MCR;
2679
2680 up->port.ops = &serial8250_pops;
2681 }
2682
4c0ebb80
AGR		 2683 if (share_irqs)
2684 irqflag = IRQF_SHARED;
2685
44454bcd 2686 for (i = 0, up = serial8250_ports;
a61c2d78 2687 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2688 i++, up++) {
2689 up->port.iobase = old_serial_port[i].port;
2690 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2691 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2692 up->port.uartclk = old_serial_port[i].baud_base * 16;
2693 up->port.flags = old_serial_port[i].flags;
2694 up->port.hub6 = old_serial_port[i].hub6;
2695 up->port.membase = old_serial_port[i].iomem_base;
2696 up->port.iotype = old_serial_port[i].io_type;
2697 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2698 set_io_from_upio(&up->port);
4c0ebb80 2699 up->port.irqflags |= irqflag;
1da177e4
LT		 2700 }
2701}
2702
b5d228cc
SL		 2703static void
2704serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2705{
2706 up->port.type = type;
2707 up->port.fifosize = uart_config[type].fifo_size;
2708 up->capabilities = uart_config[type].flags;
2709 up->tx_loadsz = uart_config[type].tx_loadsz;
2710}
2711
1da177e4
LT		 2712static void __init
2713serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2714{
2715 int i;
2716
b8e7e40a
AC		 2717 for (i = 0; i < nr_uarts; i++) {
2718 struct uart_8250_port *up = &serial8250_ports[i];
2719 up->cur_iotype = 0xFF;
2720 }
2721
1da177e4
LT		 2722 serial8250_isa_init_ports();
2723
a61c2d78 2724 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2725 struct uart_8250_port *up = &serial8250_ports[i];
2726
2727 up->port.dev = dev;
b5d228cc
SL		 2728
2729 if (up->port.flags & UPF_FIXED_TYPE)
2730 serial8250_init_fixed_type_port(up, up->port.type);
2731
1da177e4
LT		 2732 uart_add_one_port(drv, &up->port);
2733 }
2734}
2735
2736#ifdef CONFIG_SERIAL_8250_CONSOLE
2737
d358788f
RK		 2738static void serial8250_console_putchar(struct uart_port *port, int ch)
2739{
2740 struct uart_8250_port *up = (struct uart_8250_port *)port;
2741
2742 wait_for_xmitr(up, UART_LSR_THRE);
2743 serial_out(up, UART_TX, ch);
2744}
2745
1da177e4
LT		 2746/*
2747 * Print a string to the serial port trying not to disturb
2748 * any possible real use of the port...
2749 *
2750 * The console_lock must be held when we get here.
2751 */
2752static void
2753serial8250_console_write(struct console *co, const char *s, unsigned int count)
2754{
2755 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2756 unsigned long flags;
1da177e4 2757 unsigned int ier;
d8a5a8d7 2758 int locked = 1;
1da177e4 2759
78512ece
AM		 2760 touch_nmi_watchdog();
2761
68aa2c0d
AM		 2762 local_irq_save(flags);
2763 if (up->port.sysrq) {
2764 /* serial8250_handle_port() already took the lock */
2765 locked = 0;
2766 } else if (oops_in_progress) {
2767 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2768 } else
68aa2c0d 2769 spin_lock(&up->port.lock);
d8a5a8d7 2770
1da177e4 2771 /*
dc7bf130 2772 * First save the IER then disable the interrupts
1da177e4
LT		 2773 */
2774 ier = serial_in(up, UART_IER);
2775
2776 if (up->capabilities & UART_CAP_UUE)
2777 serial_out(up, UART_IER, UART_IER_UUE);
2778 else
2779 serial_out(up, UART_IER, 0);
2780
d358788f 2781 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2782
2783 /*
2784 * Finally, wait for transmitter to become empty
2785 * and restore the IER
2786 */
f91a3715 2787 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2788 serial_out(up, UART_IER, ier);
d8a5a8d7 2789
ad4c2aa6
CM		 2790 /*
2791 * The receive handling will happen properly because the
2792 * receive ready bit will still be set; it is not cleared
2793 * on read. However, modem control will not, we must
2794 * call it if we have saved something in the saved flags
2795 * while processing with interrupts off.
2796 */
2797 if (up->msr_saved_flags)
2798 check_modem_status(up);
2799
d8a5a8d7 2800 if (locked)
68aa2c0d
AM		 2801 spin_unlock(&up->port.lock);
2802 local_irq_restore(flags);
1da177e4
LT		 2803}
2804
118c0ace 2805static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2806{
2807 struct uart_port *port;
2808 int baud = 9600;
2809 int bits = 8;
2810 int parity = 'n';
2811 int flow = 'n';
2812
2813 /*
2814 * Check whether an invalid uart number has been specified, and
2815 * if so, search for the first available port that does have
2816 * console support.
2817 */
a61c2d78 2818 if (co->index >= nr_uarts)
1da177e4
LT		 2819 co->index = 0;
2820 port = &serial8250_ports[co->index].port;
2821 if (!port->iobase && !port->membase)
2822 return -ENODEV;
2823
2824 if (options)
2825 uart_parse_options(options, &baud, &parity, &bits, &flow);
2826
2827 return uart_set_options(port, co, baud, parity, bits, flow);
2828}
2829
b6b1d877 2830static int serial8250_console_early_setup(void)
18a8bd94
YL		 2831{
2832 return serial8250_find_port_for_earlycon();
2833}
2834
1da177e4
LT		 2835static struct console serial8250_console = {
2836 .name = "ttyS",
2837 .write = serial8250_console_write,
2838 .device = uart_console_device,
2839 .setup = serial8250_console_setup,
18a8bd94 2840 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2841 .flags = CON_PRINTBUFFER,
2842 .index = -1,
2843 .data = &serial8250_reg,
2844};
2845
2846static int __init serial8250_console_init(void)
2847{
05d81d22
EB		 2848 if (nr_uarts > UART_NR)
2849 nr_uarts = UART_NR;
2850
1da177e4
LT		 2851 serial8250_isa_init_ports();
2852 register_console(&serial8250_console);
2853 return 0;
2854}
2855console_initcall(serial8250_console_init);
2856
18a8bd94 2857int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2858{
2859 int line;
2860 struct uart_port *port;
2861
a61c2d78 2862 for (line = 0; line < nr_uarts; line++) {
1da177e4 2863 port = &serial8250_ports[line].port;
50aec3b5 2864 if (uart_match_port(p, port))
1da177e4
LT		 2865 return line;
2866 }
2867 return -ENODEV;
2868}
2869
1da177e4
LT		 2870#define SERIAL8250_CONSOLE &serial8250_console
2871#else
2872#define SERIAL8250_CONSOLE NULL
2873#endif
2874
2875static struct uart_driver serial8250_reg = {
2876 .owner = THIS_MODULE,
2877 .driver_name = "serial",
1da177e4
LT		 2878 .dev_name = "ttyS",
2879 .major = TTY_MAJOR,
2880 .minor = 64,
1da177e4
LT		 2881 .cons = SERIAL8250_CONSOLE,
2882};
2883
d856c666
RK		 2884/*
2885 * early_serial_setup - early registration for 8250 ports
2886 *
2887 * Setup an 8250 port structure prior to console initialisation. Use
2888 * after console initialisation will cause undefined behaviour.
2889 */
1da177e4
LT		 2890int __init early_serial_setup(struct uart_port *port)
2891{
b430428a
DD		 2892 struct uart_port *p;
2893
1da177e4
LT		 2894 if (port->line >= ARRAY_SIZE(serial8250_ports))
2895 return -ENODEV;
2896
2897 serial8250_isa_init_ports();
b430428a
DD		 2898 p = &serial8250_ports[port->line].port;
2899 p->iobase = port->iobase;
2900 p->membase = port->membase;
2901 p->irq = port->irq;
1c2f0493 2902 p->irqflags = port->irqflags;
b430428a
DD		 2903 p->uartclk = port->uartclk;
2904 p->fifosize = port->fifosize;
2905 p->regshift = port->regshift;
2906 p->iotype = port->iotype;
2907 p->flags = port->flags;
2908 p->mapbase = port->mapbase;
2909 p->private_data = port->private_data;
125c97d8
HD		 2910 p->type = port->type;
2911 p->line = port->line;
7d6a07d1
DD		 2912
2913 set_io_from_upio(p);
2914 if (port->serial_in)
2915 p->serial_in = port->serial_in;
2916 if (port->serial_out)
2917 p->serial_out = port->serial_out;
2918
1da177e4
LT		 2919 return 0;
2920}
2921
2922/**
2923 * serial8250_suspend_port - suspend one serial port
2924 * @line: serial line number
1da177e4
LT		 2925 *
2926 * Suspend one serial port.
2927 */
2928void serial8250_suspend_port(int line)
2929{
2930 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2931}
2932
2933/**
2934 * serial8250_resume_port - resume one serial port
2935 * @line: serial line number
1da177e4
LT		 2936 *
2937 * Resume one serial port.
2938 */
2939void serial8250_resume_port(int line)
2940{
b5b82df6
DW		 2941 struct uart_8250_port *up = &serial8250_ports[line];
2942
2943 if (up->capabilities & UART_NATSEMI) {
2944 unsigned char tmp;
2945
2946 /* Ensure it's still in high speed mode */
2947 serial_outp(up, UART_LCR, 0xE0);
2948
2949 tmp = serial_in(up, 0x04); /* EXCR2 */
2950 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2951 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2952 serial_outp(up, 0x04, tmp);
2953
2954 serial_outp(up, UART_LCR, 0);
2955 }
2956 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2957}
2958
2959/*
2960 * Register a set of serial devices attached to a platform device. The
2961 * list is terminated with a zero flags entry, which means we expect
2962 * all entries to have at least UPF_BOOT_AUTOCONF set.
2963 */
3ae5eaec 2964static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2965{
3ae5eaec 2966 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2967 struct uart_port port;
4c0ebb80 2968 int ret, i, irqflag = 0;
1da177e4
LT		 2969
2970 memset(&port, 0, sizeof(struct uart_port));
2971
4c0ebb80
AGR		 2972 if (share_irqs)
2973 irqflag = IRQF_SHARED;
2974
ec9f47cd 2975 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2976 port.iobase = p->iobase;
2977 port.membase = p->membase;
2978 port.irq = p->irq;
1c2f0493 2979 port.irqflags = p->irqflags;
74a19741
WN		 2980 port.uartclk = p->uartclk;
2981 port.regshift = p->regshift;
2982 port.iotype = p->iotype;
2983 port.flags = p->flags;
2984 port.mapbase = p->mapbase;
2985 port.hub6 = p->hub6;
2986 port.private_data = p->private_data;
8e23fcc8 2987 port.type = p->type;
7d6a07d1
DD		 2988 port.serial_in = p->serial_in;
2989 port.serial_out = p->serial_out;
74a19741 2990 port.dev = &dev->dev;
4c0ebb80 2991 port.irqflags |= irqflag;
ec9f47cd
RK		 2992 ret = serial8250_register_port(&port);
2993 if (ret < 0) {
3ae5eaec 2994 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2995 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2996 p->iobase, (unsigned long long)p->mapbase,
2997 p->irq, ret);
ec9f47cd 2998 }
1da177e4
LT		 2999 }
3000 return 0;
3001}
3002
3003/*
3004 * Remove serial ports registered against a platform device.
3005 */
3ae5eaec 3006static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 3007{
3008 int i;
3009
a61c2d78 3010 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 3011 struct uart_8250_port *up = &serial8250_ports[i];
3012
3ae5eaec 3013 if (up->port.dev == &dev->dev)
1da177e4
LT		 3014 serial8250_unregister_port(i);
3015 }
3016 return 0;
3017}
3018
3ae5eaec 3019static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 3020{
3021 int i;
3022
1da177e4
LT		 3023 for (i = 0; i < UART_NR; i++) {
3024 struct uart_8250_port *up = &serial8250_ports[i];
3025
3ae5eaec 3026 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3027 uart_suspend_port(&serial8250_reg, &up->port);
3028 }
3029
3030 return 0;
3031}
3032
3ae5eaec 3033static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3034{
3035 int i;
3036
1da177e4
LT		 3037 for (i = 0; i < UART_NR; i++) {
3038 struct uart_8250_port *up = &serial8250_ports[i];
3039
3ae5eaec 3040 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3041 serial8250_resume_port(i);
1da177e4
LT		 3042 }
3043
3044 return 0;
3045}
3046
3ae5eaec 3047static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3048 .probe = serial8250_probe,
3049 .remove = __devexit_p(serial8250_remove),
3050 .suspend = serial8250_suspend,
3051 .resume = serial8250_resume,
3ae5eaec
RK		 3052 .driver = {
3053 .name = "serial8250",
7493a314 3054 .owner = THIS_MODULE,
3ae5eaec 3055 },
1da177e4
LT		 3056};
3057
3058/*
3059 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3060 * in the table in include/asm/serial.h
3061 */
3062static struct platform_device *serial8250_isa_devs;
3063
3064/*
3065 * serial8250_register_port and serial8250_unregister_port allows for
3066 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3067 * modems and PCI multiport cards.
3068 */
f392ecfa 3069static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3070
3071static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3072{
3073 int i;
3074
3075 /*
3076 * First, find a port entry which matches.
3077 */
a61c2d78 3078 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3079 if (uart_match_port(&serial8250_ports[i].port, port))
3080 return &serial8250_ports[i];
3081
3082 /*
3083 * We didn't find a matching entry, so look for the first
3084 * free entry. We look for one which hasn't been previously
3085 * used (indicated by zero iobase).
3086 */
a61c2d78 3087 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3088 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3089 serial8250_ports[i].port.iobase == 0)
3090 return &serial8250_ports[i];
3091
3092 /*
3093 * That also failed. Last resort is to find any entry which
3094 * doesn't have a real port associated with it.
3095 */
a61c2d78 3096 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3097 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3098 return &serial8250_ports[i];
3099
3100 return NULL;
3101}
3102
3103/**
3104 * serial8250_register_port - register a serial port
3105 * @port: serial port template
3106 *
3107 * Configure the serial port specified by the request. If the
3108 * port exists and is in use, it is hung up and unregistered
3109 * first.
3110 *
3111 * The port is then probed and if necessary the IRQ is autodetected
3112 * If this fails an error is returned.
3113 *
3114 * On success the port is ready to use and the line number is returned.
3115 */
3116int serial8250_register_port(struct uart_port *port)
3117{
3118 struct uart_8250_port *uart;
3119 int ret = -ENOSPC;
3120
3121 if (port->uartclk == 0)
3122 return -EINVAL;
3123
f392ecfa 3124 mutex_lock(&serial_mutex);
1da177e4
LT		 3125
3126 uart = serial8250_find_match_or_unused(port);
3127 if (uart) {
3128 uart_remove_one_port(&serial8250_reg, &uart->port);
3129
74a19741
WN		 3130 uart->port.iobase = port->iobase;
3131 uart->port.membase = port->membase;
3132 uart->port.irq = port->irq;
1c2f0493 3133 uart->port.irqflags = port->irqflags;
74a19741
WN		 3134 uart->port.uartclk = port->uartclk;
3135 uart->port.fifosize = port->fifosize;
3136 uart->port.regshift = port->regshift;
3137 uart->port.iotype = port->iotype;
3138 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3139 uart->port.mapbase = port->mapbase;
3140 uart->port.private_data = port->private_data;
1da177e4
LT		 3141 if (port->dev)
3142 uart->port.dev = port->dev;
8e23fcc8 3143
b5d228cc
SL		 3144 if (port->flags & UPF_FIXED_TYPE)
3145 serial8250_init_fixed_type_port(uart, port->type);
8e23fcc8 3146
7d6a07d1
DD		 3147 set_io_from_upio(&uart->port);
3148 /* Possibly override default I/O functions. */
3149 if (port->serial_in)
3150 uart->port.serial_in = port->serial_in;
3151 if (port->serial_out)
3152 uart->port.serial_out = port->serial_out;
1da177e4
LT		 3153
3154 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3155 if (ret == 0)
3156 ret = uart->port.line;
3157 }
f392ecfa 3158 mutex_unlock(&serial_mutex);
1da177e4
LT		 3159
3160 return ret;
3161}
3162EXPORT_SYMBOL(serial8250_register_port);
3163
3164/**
3165 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3166 * @line: serial line number
3167 *
3168 * Remove one serial port. This may not be called from interrupt
3169 * context. We hand the port back to the our control.
3170 */
3171void serial8250_unregister_port(int line)
3172{
3173 struct uart_8250_port *uart = &serial8250_ports[line];
3174
f392ecfa 3175 mutex_lock(&serial_mutex);
1da177e4
LT		 3176 uart_remove_one_port(&serial8250_reg, &uart->port);
3177 if (serial8250_isa_devs) {
3178 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3179 uart->port.type = PORT_UNKNOWN;
3180 uart->port.dev = &serial8250_isa_devs->dev;
3181 uart_add_one_port(&serial8250_reg, &uart->port);
3182 } else {
3183 uart->port.dev = NULL;
3184 }
f392ecfa 3185 mutex_unlock(&serial_mutex);
1da177e4
LT		 3186}
3187EXPORT_SYMBOL(serial8250_unregister_port);
3188
3189static int __init serial8250_init(void)
3190{
25db8ad5 3191 int ret;
1da177e4 3192
a61c2d78
DJ		 3193 if (nr_uarts > UART_NR)
3194 nr_uarts = UART_NR;
3195
f1fb9bb8 3196 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3197 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3198 share_irqs ? "en" : "dis");
3199
b70ac771
DM		 3200#ifdef CONFIG_SPARC
3201 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3202#else
3203 serial8250_reg.nr = UART_NR;
1da177e4 3204 ret = uart_register_driver(&serial8250_reg);
b70ac771 3205#endif
1da177e4
LT		 3206 if (ret)
3207 goto out;
3208
7493a314
DT		 3209 serial8250_isa_devs = platform_device_alloc("serial8250",
3210 PLAT8250_DEV_LEGACY);
3211 if (!serial8250_isa_devs) {
3212 ret = -ENOMEM;
bc965a7f 3213 goto unreg_uart_drv;
1da177e4
LT		 3214 }
3215
7493a314
DT		 3216 ret = platform_device_add(serial8250_isa_devs);
3217 if (ret)
3218 goto put_dev;
3219
1da177e4
LT		 3220 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3221
bc965a7f
RK		 3222 ret = platform_driver_register(&serial8250_isa_driver);
3223 if (ret == 0)
3224 goto out;
1da177e4 3225
bc965a7f 3226 platform_device_del(serial8250_isa_devs);
25db8ad5 3227put_dev:
7493a314 3228 platform_device_put(serial8250_isa_devs);
25db8ad5 3229unreg_uart_drv:
b70ac771
DM		 3230#ifdef CONFIG_SPARC
3231 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3232#else
1da177e4 3233 uart_unregister_driver(&serial8250_reg);
b70ac771 3234#endif
25db8ad5 3235out:
1da177e4
LT		 3236 return ret;
3237}
3238
3239static void __exit serial8250_exit(void)
3240{
3241 struct platform_device *isa_dev = serial8250_isa_devs;
3242
3243 /*
3244 * This tells serial8250_unregister_port() not to re-register
3245 * the ports (thereby making serial8250_isa_driver permanently
3246 * in use.)
3247 */
3248 serial8250_isa_devs = NULL;
3249
3ae5eaec 3250 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3251 platform_device_unregister(isa_dev);
3252
b70ac771
DM		 3253#ifdef CONFIG_SPARC
3254 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3255#else
1da177e4 3256 uart_unregister_driver(&serial8250_reg);
b70ac771 3257#endif
1da177e4
LT		 3258}
3259
3260module_init(serial8250_init);
3261module_exit(serial8250_exit);
3262
3263EXPORT_SYMBOL(serial8250_suspend_port);
3264EXPORT_SYMBOL(serial8250_resume_port);
3265
3266MODULE_LICENSE("GPL");
d87a6d95 3267MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3268
3269module_param(share_irqs, uint, 0644);
3270MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3271 " (unsafe)");
3272
a61c2d78
DJ		 3273module_param(nr_uarts, uint, 0644);
3274MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3275
d41a4b51
CE		 3276module_param(skip_txen_test, uint, 0644);
3277MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3278
1da177e4
LT		 3279#ifdef CONFIG_SERIAL_8250_RSA
3280module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3281MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3282#endif
3283MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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