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[SERIAL] IP22: fix serial console hangs
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
1da177e4
LT		 22
23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
1da177e4 33#include <linux/delay.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4
LT		 35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_reg.h>
38#include <linux/serial_core.h>
39#include <linux/serial.h>
40#include <linux/serial_8250.h>
78512ece 41#include <linux/nmi.h>
f392ecfa 42#include <linux/mutex.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
40663cc7 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 55
a61c2d78
DJ		 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
1da177e4
LT		 58/*
59 * Debugging.
60 */
61#if 0
62#define DEBUG_AUTOCONF(fmt...) printk(fmt)
63#else
64#define DEBUG_AUTOCONF(fmt...) do { } while (0)
65#endif
66
67#if 0
68#define DEBUG_INTR(fmt...) printk(fmt)
69#else
70#define DEBUG_INTR(fmt...) do { } while (0)
71#endif
72
73#define PASS_LIMIT 256
74
75/*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80#define is_real_interrupt(irq) ((irq) != 0)
81
1da177e4
LT		 82#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83#define CONFIG_SERIAL_DETECT_IRQ 1
84#endif
1da177e4
LT		 85#ifdef CONFIG_SERIAL_8250_MANY_PORTS
86#define CONFIG_SERIAL_MANY_PORTS 1
87#endif
88
89/*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93#define CONFIG_HUB6 1
94
95#include <asm/serial.h>
96
97/*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102#ifndef SERIAL_PORT_DFNS
103#define SERIAL_PORT_DFNS
104#endif
105
cb3592be 106static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108};
109
026d02a2 110#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 111
112#ifdef CONFIG_SERIAL_8250_RSA
113
114#define PORT_RSA_MAX 4
115static unsigned long probe_rsa[PORT_RSA_MAX];
116static unsigned int probe_rsa_count;
117#endif /* CONFIG_SERIAL_8250_RSA */
118
119struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
1da177e4 125 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
133
134 /*
135 * We provide a per-port pm hook.
136 */
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
139};
140
141struct irq_info {
142 spinlock_t lock;
143 struct list_head *head;
144};
145
146static struct irq_info irq_lists[NR_IRQS];
147
148/*
149 * Here we define the default xmit fifo size used for each type of UART.
150 */
151static const struct serial8250_config uart_config[] = {
152 [PORT_UNKNOWN] = {
153 .name = "unknown",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_8250] = {
158 .name = "8250",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16450] = {
163 .name = "16450",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550] = {
168 .name = "16550",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16550A] = {
173 .name = "16550A",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
178 },
179 [PORT_CIRRUS] = {
180 .name = "Cirrus",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16650] = {
185 .name = "ST16650",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 },
190 [PORT_16650V2] = {
191 .name = "ST16650V2",
192 .fifo_size = 32,
193 .tx_loadsz = 16,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_00,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16750] = {
199 .name = "TI16750",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
203 UART_FCR7_64BYTE,
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
205 },
206 [PORT_STARTECH] = {
207 .name = "Startech",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16C950] = {
212 .name = "16C950/954",
213 .fifo_size = 128,
214 .tx_loadsz = 128,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
217 },
218 [PORT_16654] = {
219 .name = "ST16654",
220 .fifo_size = 64,
221 .tx_loadsz = 32,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16850] = {
227 .name = "XR16850",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
232 },
233 [PORT_RSA] = {
234 .name = "RSA",
235 .fifo_size = 2048,
236 .tx_loadsz = 2048,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_NS16550A] = {
241 .name = "NS16550A",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
246 },
247 [PORT_XSCALE] = {
248 .name = "XScale",
249 .fifo_size = 32,
250 .tx_loadsz = 32,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
253 },
254};
255
21c614a7
PA		 256#ifdef CONFIG_SERIAL_8250_AU1X00
257
258/* Au1x00 UART hardware has a weird register layout */
259static const u8 au_io_in_map[] = {
260 [UART_RX] = 0,
261 [UART_IER] = 2,
262 [UART_IIR] = 3,
263 [UART_LCR] = 5,
264 [UART_MCR] = 6,
265 [UART_LSR] = 7,
266 [UART_MSR] = 8,
267};
268
269static const u8 au_io_out_map[] = {
270 [UART_TX] = 1,
271 [UART_IER] = 2,
272 [UART_FCR] = 4,
273 [UART_LCR] = 5,
274 [UART_MCR] = 6,
275};
276
277/* sane hardware needs no mapping */
278static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
279{
280 if (up->port.iotype != UPIO_AU)
281 return offset;
282 return au_io_in_map[offset];
283}
284
285static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
286{
287 if (up->port.iotype != UPIO_AU)
288 return offset;
289 return au_io_out_map[offset];
290}
291
292#else
293
294/* sane hardware needs no mapping */
295#define map_8250_in_reg(up, offset) (offset)
296#define map_8250_out_reg(up, offset) (offset)
297
298#endif
299
ea8874dc 300static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 301{
21c614a7 302 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 303
304 switch (up->port.iotype) {
305 case UPIO_HUB6:
306 outb(up->port.hub6 - 1 + offset, up->port.iobase);
307 return inb(up->port.iobase + 1);
308
309 case UPIO_MEM:
310 return readb(up->port.membase + offset);
311
312 case UPIO_MEM32:
313 return readl(up->port.membase + offset);
314
21c614a7
PA		 315#ifdef CONFIG_SERIAL_8250_AU1X00
316 case UPIO_AU:
317 return __raw_readl(up->port.membase + offset);
318#endif
319
1da177e4
LT		 320 default:
321 return inb(up->port.iobase + offset);
322 }
323}
324
ea8874dc 325static void
1da177e4
LT		 326serial_out(struct uart_8250_port *up, int offset, int value)
327{
21c614a7 328 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 329
330 switch (up->port.iotype) {
331 case UPIO_HUB6:
332 outb(up->port.hub6 - 1 + offset, up->port.iobase);
333 outb(value, up->port.iobase + 1);
334 break;
335
336 case UPIO_MEM:
337 writeb(value, up->port.membase + offset);
338 break;
339
340 case UPIO_MEM32:
341 writel(value, up->port.membase + offset);
342 break;
343
21c614a7
PA		 344#ifdef CONFIG_SERIAL_8250_AU1X00
345 case UPIO_AU:
346 __raw_writel(value, up->port.membase + offset);
347 break;
348#endif
349
1da177e4
LT		 350 default:
351 outb(value, up->port.iobase + offset);
352 }
353}
354
355/*
356 * We used to support using pause I/O for certain machines. We
357 * haven't supported this for a while, but just in case it's badly
358 * needed for certain old 386 machines, I've left these #define's
359 * in....
360 */
361#define serial_inp(up, offset) serial_in(up, offset)
362#define serial_outp(up, offset, value) serial_out(up, offset, value)
363
b32b19b8
JAH		 364/* Uart divisor latch read */
365static inline int _serial_dl_read(struct uart_8250_port *up)
366{
367 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
368}
369
370/* Uart divisor latch write */
371static inline void _serial_dl_write(struct uart_8250_port *up, int value)
372{
373 serial_outp(up, UART_DLL, value & 0xff);
374 serial_outp(up, UART_DLM, value >> 8 & 0xff);
375}
376
377#ifdef CONFIG_SERIAL_8250_AU1X00
378/* Au1x00 haven't got a standard divisor latch */
379static int serial_dl_read(struct uart_8250_port *up)
380{
381 if (up->port.iotype == UPIO_AU)
382 return __raw_readl(up->port.membase + 0x28);
383 else
384 return _serial_dl_read(up);
385}
386
387static void serial_dl_write(struct uart_8250_port *up, int value)
388{
389 if (up->port.iotype == UPIO_AU)
390 __raw_writel(value, up->port.membase + 0x28);
391 else
392 _serial_dl_write(up, value);
393}
394#else
395#define serial_dl_read(up) _serial_dl_read(up)
396#define serial_dl_write(up, value) _serial_dl_write(up, value)
397#endif
1da177e4
LT		 398
399/*
400 * For the 16C950
401 */
402static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
403{
404 serial_out(up, UART_SCR, offset);
405 serial_out(up, UART_ICR, value);
406}
407
408static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
409{
410 unsigned int value;
411
412 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
413 serial_out(up, UART_SCR, offset);
414 value = serial_in(up, UART_ICR);
415 serial_icr_write(up, UART_ACR, up->acr);
416
417 return value;
418}
419
420/*
421 * FIFO support.
422 */
423static inline void serial8250_clear_fifos(struct uart_8250_port *p)
424{
425 if (p->capabilities & UART_CAP_FIFO) {
426 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
427 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
428 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
429 serial_outp(p, UART_FCR, 0);
430 }
431}
432
433/*
434 * IER sleep support. UARTs which have EFRs need the "extended
435 * capability" bit enabled. Note that on XR16C850s, we need to
436 * reset LCR to write to IER.
437 */
438static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
439{
440 if (p->capabilities & UART_CAP_SLEEP) {
441 if (p->capabilities & UART_CAP_EFR) {
442 serial_outp(p, UART_LCR, 0xBF);
443 serial_outp(p, UART_EFR, UART_EFR_ECB);
444 serial_outp(p, UART_LCR, 0);
445 }
446 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
447 if (p->capabilities & UART_CAP_EFR) {
448 serial_outp(p, UART_LCR, 0xBF);
449 serial_outp(p, UART_EFR, 0);
450 serial_outp(p, UART_LCR, 0);
451 }
452 }
453}
454
455#ifdef CONFIG_SERIAL_8250_RSA
456/*
457 * Attempts to turn on the RSA FIFO. Returns zero on failure.
458 * We set the port uart clock rate if we succeed.
459 */
460static int __enable_rsa(struct uart_8250_port *up)
461{
462 unsigned char mode;
463 int result;
464
465 mode = serial_inp(up, UART_RSA_MSR);
466 result = mode & UART_RSA_MSR_FIFO;
467
468 if (!result) {
469 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
470 mode = serial_inp(up, UART_RSA_MSR);
471 result = mode & UART_RSA_MSR_FIFO;
472 }
473
474 if (result)
475 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
476
477 return result;
478}
479
480static void enable_rsa(struct uart_8250_port *up)
481{
482 if (up->port.type == PORT_RSA) {
483 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
484 spin_lock_irq(&up->port.lock);
485 __enable_rsa(up);
486 spin_unlock_irq(&up->port.lock);
487 }
488 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
489 serial_outp(up, UART_RSA_FRR, 0);
490 }
491}
492
493/*
494 * Attempts to turn off the RSA FIFO. Returns zero on failure.
495 * It is unknown why interrupts were disabled in here. However,
496 * the caller is expected to preserve this behaviour by grabbing
497 * the spinlock before calling this function.
498 */
499static void disable_rsa(struct uart_8250_port *up)
500{
501 unsigned char mode;
502 int result;
503
504 if (up->port.type == PORT_RSA &&
505 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
506 spin_lock_irq(&up->port.lock);
507
508 mode = serial_inp(up, UART_RSA_MSR);
509 result = !(mode & UART_RSA_MSR_FIFO);
510
511 if (!result) {
512 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
513 mode = serial_inp(up, UART_RSA_MSR);
514 result = !(mode & UART_RSA_MSR_FIFO);
515 }
516
517 if (result)
518 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
519 spin_unlock_irq(&up->port.lock);
520 }
521}
522#endif /* CONFIG_SERIAL_8250_RSA */
523
524/*
525 * This is a quickie test to see how big the FIFO is.
526 * It doesn't work at all the time, more's the pity.
527 */
528static int size_fifo(struct uart_8250_port *up)
529{
b32b19b8
JAH		 530 unsigned char old_fcr, old_mcr, old_lcr;
531 unsigned short old_dl;
1da177e4
LT		 532 int count;
533
534 old_lcr = serial_inp(up, UART_LCR);
535 serial_outp(up, UART_LCR, 0);
536 old_fcr = serial_inp(up, UART_FCR);
537 old_mcr = serial_inp(up, UART_MCR);
538 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
539 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
540 serial_outp(up, UART_MCR, UART_MCR_LOOP);
541 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 542 old_dl = serial_dl_read(up);
543 serial_dl_write(up, 0x0001);
1da177e4
LT		 544 serial_outp(up, UART_LCR, 0x03);
545 for (count = 0; count < 256; count++)
546 serial_outp(up, UART_TX, count);
547 mdelay(20);/* FIXME - schedule_timeout */
548 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
549 (count < 256); count++)
550 serial_inp(up, UART_RX);
551 serial_outp(up, UART_FCR, old_fcr);
552 serial_outp(up, UART_MCR, old_mcr);
553 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 554 serial_dl_write(up, old_dl);
1da177e4
LT		 555 serial_outp(up, UART_LCR, old_lcr);
556
557 return count;
558}
559
560/*
561 * Read UART ID using the divisor method - set DLL and DLM to zero
562 * and the revision will be in DLL and device type in DLM. We
563 * preserve the device state across this.
564 */
565static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
566{
567 unsigned char old_dll, old_dlm, old_lcr;
568 unsigned int id;
569
570 old_lcr = serial_inp(p, UART_LCR);
571 serial_outp(p, UART_LCR, UART_LCR_DLAB);
572
573 old_dll = serial_inp(p, UART_DLL);
574 old_dlm = serial_inp(p, UART_DLM);
575
576 serial_outp(p, UART_DLL, 0);
577 serial_outp(p, UART_DLM, 0);
578
579 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
580
581 serial_outp(p, UART_DLL, old_dll);
582 serial_outp(p, UART_DLM, old_dlm);
583 serial_outp(p, UART_LCR, old_lcr);
584
585 return id;
586}
587
588/*
589 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
590 * When this function is called we know it is at least a StarTech
591 * 16650 V2, but it might be one of several StarTech UARTs, or one of
592 * its clones. (We treat the broken original StarTech 16650 V1 as a
593 * 16550, and why not? Startech doesn't seem to even acknowledge its
594 * existence.)
595 *
596 * What evil have men's minds wrought...
597 */
598static void autoconfig_has_efr(struct uart_8250_port *up)
599{
600 unsigned int id1, id2, id3, rev;
601
602 /*
603 * Everything with an EFR has SLEEP
604 */
605 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
606
607 /*
608 * First we check to see if it's an Oxford Semiconductor UART.
609 *
610 * If we have to do this here because some non-National
611 * Semiconductor clone chips lock up if you try writing to the
612 * LSR register (which serial_icr_read does)
613 */
614
615 /*
616 * Check for Oxford Semiconductor 16C950.
617 *
618 * EFR [4] must be set else this test fails.
619 *
620 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
621 * claims that it's needed for 952 dual UART's (which are not
622 * recommended for new designs).
623 */
624 up->acr = 0;
625 serial_out(up, UART_LCR, 0xBF);
626 serial_out(up, UART_EFR, UART_EFR_ECB);
627 serial_out(up, UART_LCR, 0x00);
628 id1 = serial_icr_read(up, UART_ID1);
629 id2 = serial_icr_read(up, UART_ID2);
630 id3 = serial_icr_read(up, UART_ID3);
631 rev = serial_icr_read(up, UART_REV);
632
633 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
634
635 if (id1 == 0x16 && id2 == 0xC9 &&
636 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
637 up->port.type = PORT_16C950;
4ba5e35d
RK		 638
639 /*
640 * Enable work around for the Oxford Semiconductor 952 rev B
641 * chip which causes it to seriously miscalculate baud rates
642 * when DLL is 0.
643 */
644 if (id3 == 0x52 && rev == 0x01)
645 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 646 return;
647 }
648
649 /*
650 * We check for a XR16C850 by setting DLL and DLM to 0, and then
651 * reading back DLL and DLM. The chip type depends on the DLM
652 * value read back:
653 * 0x10 - XR16C850 and the DLL contains the chip revision.
654 * 0x12 - XR16C2850.
655 * 0x14 - XR16C854.
656 */
657 id1 = autoconfig_read_divisor_id(up);
658 DEBUG_AUTOCONF("850id=%04x ", id1);
659
660 id2 = id1 >> 8;
661 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 662 up->port.type = PORT_16850;
663 return;
664 }
665
666 /*
667 * It wasn't an XR16C850.
668 *
669 * We distinguish between the '654 and the '650 by counting
670 * how many bytes are in the FIFO. I'm using this for now,
671 * since that's the technique that was sent to me in the
672 * serial driver update, but I'm not convinced this works.
673 * I've had problems doing this in the past. -TYT
674 */
675 if (size_fifo(up) == 64)
676 up->port.type = PORT_16654;
677 else
678 up->port.type = PORT_16650V2;
679}
680
681/*
682 * We detected a chip without a FIFO. Only two fall into
683 * this category - the original 8250 and the 16450. The
684 * 16450 has a scratch register (accessible with LCR=0)
685 */
686static void autoconfig_8250(struct uart_8250_port *up)
687{
688 unsigned char scratch, status1, status2;
689
690 up->port.type = PORT_8250;
691
692 scratch = serial_in(up, UART_SCR);
693 serial_outp(up, UART_SCR, 0xa5);
694 status1 = serial_in(up, UART_SCR);
695 serial_outp(up, UART_SCR, 0x5a);
696 status2 = serial_in(up, UART_SCR);
697 serial_outp(up, UART_SCR, scratch);
698
699 if (status1 == 0xa5 && status2 == 0x5a)
700 up->port.type = PORT_16450;
701}
702
703static int broken_efr(struct uart_8250_port *up)
704{
705 /*
706 * Exar ST16C2550 "A2" devices incorrectly detect as
707 * having an EFR, and report an ID of 0x0201. See
708 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
709 */
710 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
711 return 1;
712
713 return 0;
714}
715
716/*
717 * We know that the chip has FIFOs. Does it have an EFR? The
718 * EFR is located in the same register position as the IIR and
719 * we know the top two bits of the IIR are currently set. The
720 * EFR should contain zero. Try to read the EFR.
721 */
722static void autoconfig_16550a(struct uart_8250_port *up)
723{
724 unsigned char status1, status2;
725 unsigned int iersave;
726
727 up->port.type = PORT_16550A;
728 up->capabilities |= UART_CAP_FIFO;
729
730 /*
731 * Check for presence of the EFR when DLAB is set.
732 * Only ST16C650V1 UARTs pass this test.
733 */
734 serial_outp(up, UART_LCR, UART_LCR_DLAB);
735 if (serial_in(up, UART_EFR) == 0) {
736 serial_outp(up, UART_EFR, 0xA8);
737 if (serial_in(up, UART_EFR) != 0) {
738 DEBUG_AUTOCONF("EFRv1 ");
739 up->port.type = PORT_16650;
740 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
741 } else {
742 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
743 }
744 serial_outp(up, UART_EFR, 0);
745 return;
746 }
747
748 /*
749 * Maybe it requires 0xbf to be written to the LCR.
750 * (other ST16C650V2 UARTs, TI16C752A, etc)
751 */
752 serial_outp(up, UART_LCR, 0xBF);
753 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
754 DEBUG_AUTOCONF("EFRv2 ");
755 autoconfig_has_efr(up);
756 return;
757 }
758
759 /*
760 * Check for a National Semiconductor SuperIO chip.
761 * Attempt to switch to bank 2, read the value of the LOOP bit
762 * from EXCR1. Switch back to bank 0, change it in MCR. Then
763 * switch back to bank 2, read it from EXCR1 again and check
764 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 765 */
766 serial_outp(up, UART_LCR, 0);
767 status1 = serial_in(up, UART_MCR);
768 serial_outp(up, UART_LCR, 0xE0);
769 status2 = serial_in(up, 0x02); /* EXCR1 */
770
771 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
772 serial_outp(up, UART_LCR, 0);
773 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
774 serial_outp(up, UART_LCR, 0xE0);
775 status2 = serial_in(up, 0x02); /* EXCR1 */
776 serial_outp(up, UART_LCR, 0);
777 serial_outp(up, UART_MCR, status1);
778
779 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 780 unsigned short quot;
781
1da177e4 782 serial_outp(up, UART_LCR, 0xE0);
857dde2e 783
b32b19b8 784 quot = serial_dl_read(up);
857dde2e
DW		 785 quot <<= 3;
786
1da177e4
LT		 787 status1 = serial_in(up, 0x04); /* EXCR1 */
788 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
789 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
790 serial_outp(up, 0x04, status1);
857dde2e 791
b32b19b8 792 serial_dl_write(up, quot);
857dde2e 793
1da177e4 794 serial_outp(up, UART_LCR, 0);
1da177e4 795
857dde2e 796 up->port.uartclk = 921600*16;
1da177e4
LT		 797 up->port.type = PORT_NS16550A;
798 up->capabilities |= UART_NATSEMI;
799 return;
800 }
801 }
802
803 /*
804 * No EFR. Try to detect a TI16750, which only sets bit 5 of
805 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
806 * Try setting it with and without DLAB set. Cheap clones
807 * set bit 5 without DLAB set.
808 */
809 serial_outp(up, UART_LCR, 0);
810 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
811 status1 = serial_in(up, UART_IIR) >> 5;
812 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
813 serial_outp(up, UART_LCR, UART_LCR_DLAB);
814 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
815 status2 = serial_in(up, UART_IIR) >> 5;
816 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
817 serial_outp(up, UART_LCR, 0);
818
819 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
820
821 if (status1 == 6 && status2 == 7) {
822 up->port.type = PORT_16750;
823 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
824 return;
825 }
826
827 /*
828 * Try writing and reading the UART_IER_UUE bit (b6).
829 * If it works, this is probably one of the Xscale platform's
830 * internal UARTs.
831 * We're going to explicitly set the UUE bit to 0 before
832 * trying to write and read a 1 just to make sure it's not
833 * already a 1 and maybe locked there before we even start start.
834 */
835 iersave = serial_in(up, UART_IER);
836 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
837 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
838 /*
839 * OK it's in a known zero state, try writing and reading
840 * without disturbing the current state of the other bits.
841 */
842 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
843 if (serial_in(up, UART_IER) & UART_IER_UUE) {
844 /*
845 * It's an Xscale.
846 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
847 */
848 DEBUG_AUTOCONF("Xscale ");
849 up->port.type = PORT_XSCALE;
850 up->capabilities |= UART_CAP_UUE;
851 return;
852 }
853 } else {
854 /*
855 * If we got here we couldn't force the IER_UUE bit to 0.
856 * Log it and continue.
857 */
858 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
859 }
860 serial_outp(up, UART_IER, iersave);
861}
862
863/*
864 * This routine is called by rs_init() to initialize a specific serial
865 * port. It determines what type of UART chip this serial port is
866 * using: 8250, 16450, 16550, 16550A. The important question is
867 * whether or not this UART is a 16550A or not, since this will
868 * determine whether or not we can use its FIFO features or not.
869 */
870static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
871{
872 unsigned char status1, scratch, scratch2, scratch3;
873 unsigned char save_lcr, save_mcr;
874 unsigned long flags;
875
876 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
877 return;
878
879 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
880 up->port.line, up->port.iobase, up->port.membase);
881
882 /*
883 * We really do need global IRQs disabled here - we're going to
884 * be frobbing the chips IRQ enable register to see if it exists.
885 */
886 spin_lock_irqsave(&up->port.lock, flags);
887// save_flags(flags); cli();
888
889 up->capabilities = 0;
4ba5e35d 890 up->bugs = 0;
1da177e4
LT		 891
892 if (!(up->port.flags & UPF_BUGGY_UART)) {
893 /*
894 * Do a simple existence test first; if we fail this,
895 * there's no point trying anything else.
896 *
897 * 0x80 is used as a nonsense port to prevent against
898 * false positives due to ISA bus float. The
899 * assumption is that 0x80 is a non-existent port;
900 * which should be safe since include/asm/io.h also
901 * makes this assumption.
902 *
903 * Note: this is safe as long as MCR bit 4 is clear
904 * and the device is in "PC" mode.
905 */
906 scratch = serial_inp(up, UART_IER);
907 serial_outp(up, UART_IER, 0);
908#ifdef __i386__
909 outb(0xff, 0x080);
910#endif
911 scratch2 = serial_inp(up, UART_IER);
912 serial_outp(up, UART_IER, 0x0F);
913#ifdef __i386__
914 outb(0, 0x080);
915#endif
916 scratch3 = serial_inp(up, UART_IER);
917 serial_outp(up, UART_IER, scratch);
918 if (scratch2 != 0 || scratch3 != 0x0F) {
919 /*
920 * We failed; there's nothing here
921 */
922 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
923 scratch2, scratch3);
924 goto out;
925 }
926 }
927
928 save_mcr = serial_in(up, UART_MCR);
929 save_lcr = serial_in(up, UART_LCR);
930
931 /*
932 * Check to see if a UART is really there. Certain broken
933 * internal modems based on the Rockwell chipset fail this
934 * test, because they apparently don't implement the loopback
935 * test mode. So this test is skipped on the COM 1 through
936 * COM 4 ports. This *should* be safe, since no board
937 * manufacturer would be stupid enough to design a board
938 * that conflicts with COM 1-4 --- we hope!
939 */
940 if (!(up->port.flags & UPF_SKIP_TEST)) {
941 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
942 status1 = serial_inp(up, UART_MSR) & 0xF0;
943 serial_outp(up, UART_MCR, save_mcr);
944 if (status1 != 0x90) {
945 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
946 status1);
947 goto out;
948 }
949 }
950
951 /*
952 * We're pretty sure there's a port here. Lets find out what
953 * type of port it is. The IIR top two bits allows us to find
6f0d618f 954 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 955 * determines what we test for next.
956 *
957 * We also initialise the EFR (if any) to zero for later. The
958 * EFR occupies the same register location as the FCR and IIR.
959 */
960 serial_outp(up, UART_LCR, 0xBF);
961 serial_outp(up, UART_EFR, 0);
962 serial_outp(up, UART_LCR, 0);
963
964 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
965 scratch = serial_in(up, UART_IIR) >> 6;
966
967 DEBUG_AUTOCONF("iir=%d ", scratch);
968
969 switch (scratch) {
970 case 0:
971 autoconfig_8250(up);
972 break;
973 case 1:
974 up->port.type = PORT_UNKNOWN;
975 break;
976 case 2:
977 up->port.type = PORT_16550;
978 break;
979 case 3:
980 autoconfig_16550a(up);
981 break;
982 }
983
984#ifdef CONFIG_SERIAL_8250_RSA
985 /*
986 * Only probe for RSA ports if we got the region.
987 */
988 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
989 int i;
990
991 for (i = 0 ; i < probe_rsa_count; ++i) {
992 if (probe_rsa[i] == up->port.iobase &&
993 __enable_rsa(up)) {
994 up->port.type = PORT_RSA;
995 break;
996 }
997 }
998 }
999#endif
21c614a7
PA		 1000
1001#ifdef CONFIG_SERIAL_8250_AU1X00
1002 /* if access method is AU, it is a 16550 with a quirk */
1003 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1004 up->bugs |= UART_BUG_NOMSR;
1005#endif
1006
1da177e4
LT		 1007 serial_outp(up, UART_LCR, save_lcr);
1008
1009 if (up->capabilities != uart_config[up->port.type].flags) {
1010 printk(KERN_WARNING
1011 "ttyS%d: detected caps %08x should be %08x\n",
1012 up->port.line, up->capabilities,
1013 uart_config[up->port.type].flags);
1014 }
1015
1016 up->port.fifosize = uart_config[up->port.type].fifo_size;
1017 up->capabilities = uart_config[up->port.type].flags;
1018 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1019
1020 if (up->port.type == PORT_UNKNOWN)
1021 goto out;
1022
1023 /*
1024 * Reset the UART.
1025 */
1026#ifdef CONFIG_SERIAL_8250_RSA
1027 if (up->port.type == PORT_RSA)
1028 serial_outp(up, UART_RSA_FRR, 0);
1029#endif
1030 serial_outp(up, UART_MCR, save_mcr);
1031 serial8250_clear_fifos(up);
1032 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1033 if (up->capabilities & UART_CAP_UUE)
1034 serial_outp(up, UART_IER, UART_IER_UUE);
1035 else
1036 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1037
1038 out:
1039 spin_unlock_irqrestore(&up->port.lock, flags);
1040// restore_flags(flags);
1041 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1042}
1043
1044static void autoconfig_irq(struct uart_8250_port *up)
1045{
1046 unsigned char save_mcr, save_ier;
1047 unsigned char save_ICP = 0;
1048 unsigned int ICP = 0;
1049 unsigned long irqs;
1050 int irq;
1051
1052 if (up->port.flags & UPF_FOURPORT) {
1053 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1054 save_ICP = inb_p(ICP);
1055 outb_p(0x80, ICP);
1056 (void) inb_p(ICP);
1057 }
1058
1059 /* forget possible initially masked and pending IRQ */
1060 probe_irq_off(probe_irq_on());
1061 save_mcr = serial_inp(up, UART_MCR);
1062 save_ier = serial_inp(up, UART_IER);
1063 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1064
1065 irqs = probe_irq_on();
1066 serial_outp(up, UART_MCR, 0);
1067 udelay (10);
1068 if (up->port.flags & UPF_FOURPORT) {
1069 serial_outp(up, UART_MCR,
1070 UART_MCR_DTR | UART_MCR_RTS);
1071 } else {
1072 serial_outp(up, UART_MCR,
1073 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1074 }
1075 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1076 (void)serial_inp(up, UART_LSR);
1077 (void)serial_inp(up, UART_RX);
1078 (void)serial_inp(up, UART_IIR);
1079 (void)serial_inp(up, UART_MSR);
1080 serial_outp(up, UART_TX, 0xFF);
1081 udelay (20);
1082 irq = probe_irq_off(irqs);
1083
1084 serial_outp(up, UART_MCR, save_mcr);
1085 serial_outp(up, UART_IER, save_ier);
1086
1087 if (up->port.flags & UPF_FOURPORT)
1088 outb_p(save_ICP, ICP);
1089
1090 up->port.irq = (irq > 0) ? irq : 0;
1091}
1092
e763b90c
RK		 1093static inline void __stop_tx(struct uart_8250_port *p)
1094{
1095 if (p->ier & UART_IER_THRI) {
1096 p->ier &= ~UART_IER_THRI;
1097 serial_out(p, UART_IER, p->ier);
1098 }
1099}
1100
b129a8cc 1101static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1102{
1103 struct uart_8250_port *up = (struct uart_8250_port *)port;
1104
e763b90c 1105 __stop_tx(up);
1da177e4
LT		 1106
1107 /*
e763b90c 1108 * We really want to stop the transmitter from sending.
1da177e4 1109 */
e763b90c 1110 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1111 up->acr |= UART_ACR_TXDIS;
1112 serial_icr_write(up, UART_ACR, up->acr);
1113 }
1114}
1115
55d3b282
RK		 1116static void transmit_chars(struct uart_8250_port *up);
1117
b129a8cc 1118static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1119{
1120 struct uart_8250_port *up = (struct uart_8250_port *)port;
1121
1122 if (!(up->ier & UART_IER_THRI)) {
1123 up->ier |= UART_IER_THRI;
1124 serial_out(up, UART_IER, up->ier);
55d3b282 1125
67f7654e 1126 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1127 unsigned char lsr, iir;
1128 lsr = serial_in(up, UART_LSR);
1129 iir = serial_in(up, UART_IIR);
1130 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1131 transmit_chars(up);
1132 }
1da177e4 1133 }
e763b90c 1134
1da177e4 1135 /*
e763b90c 1136 * Re-enable the transmitter if we disabled it.
1da177e4 1137 */
e763b90c 1138 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1139 up->acr &= ~UART_ACR_TXDIS;
1140 serial_icr_write(up, UART_ACR, up->acr);
1141 }
1142}
1143
1144static void serial8250_stop_rx(struct uart_port *port)
1145{
1146 struct uart_8250_port *up = (struct uart_8250_port *)port;
1147
1148 up->ier &= ~UART_IER_RLSI;
1149 up->port.read_status_mask &= ~UART_LSR_DR;
1150 serial_out(up, UART_IER, up->ier);
1151}
1152
1153static void serial8250_enable_ms(struct uart_port *port)
1154{
1155 struct uart_8250_port *up = (struct uart_8250_port *)port;
1156
21c614a7
PA		 1157 /* no MSR capabilities */
1158 if (up->bugs & UART_BUG_NOMSR)
1159 return;
1160
1da177e4
LT		 1161 up->ier |= UART_IER_MSI;
1162 serial_out(up, UART_IER, up->ier);
1163}
1164
ea8874dc 1165static void
1da177e4
LT		 1166receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1167{
1168 struct tty_struct *tty = up->port.info->tty;
1169 unsigned char ch, lsr = *status;
1170 int max_count = 256;
1171 char flag;
1172
1173 do {
1da177e4
LT		 1174 ch = serial_inp(up, UART_RX);
1175 flag = TTY_NORMAL;
1176 up->port.icount.rx++;
1177
1178#ifdef CONFIG_SERIAL_8250_CONSOLE
1179 /*
1180 * Recover the break flag from console xmit
1181 */
1182 if (up->port.line == up->port.cons->index) {
1183 lsr |= up->lsr_break_flag;
1184 up->lsr_break_flag = 0;
1185 }
1186#endif
1187
1188 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1189 UART_LSR_FE | UART_LSR_OE))) {
1190 /*
1191 * For statistics only
1192 */
1193 if (lsr & UART_LSR_BI) {
1194 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1195 up->port.icount.brk++;
1196 /*
1197 * We do the SysRQ and SAK checking
1198 * here because otherwise the break
1199 * may get masked by ignore_status_mask
1200 * or read_status_mask.
1201 */
1202 if (uart_handle_break(&up->port))
1203 goto ignore_char;
1204 } else if (lsr & UART_LSR_PE)
1205 up->port.icount.parity++;
1206 else if (lsr & UART_LSR_FE)
1207 up->port.icount.frame++;
1208 if (lsr & UART_LSR_OE)
1209 up->port.icount.overrun++;
1210
1211 /*
23907eb8 1212 * Mask off conditions which should be ignored.
1da177e4
LT		 1213 */
1214 lsr &= up->port.read_status_mask;
1215
1216 if (lsr & UART_LSR_BI) {
1217 DEBUG_INTR("handling break....");
1218 flag = TTY_BREAK;
1219 } else if (lsr & UART_LSR_PE)
1220 flag = TTY_PARITY;
1221 else if (lsr & UART_LSR_FE)
1222 flag = TTY_FRAME;
1223 }
1224 if (uart_handle_sysrq_char(&up->port, ch, regs))
1225 goto ignore_char;
05ab3014
RK		 1226
1227 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1228
1da177e4
LT		 1229 ignore_char:
1230 lsr = serial_inp(up, UART_LSR);
1231 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1232 spin_unlock(&up->port.lock);
1233 tty_flip_buffer_push(tty);
1234 spin_lock(&up->port.lock);
1235 *status = lsr;
1236}
1237
ea8874dc 1238static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1239{
1240 struct circ_buf *xmit = &up->port.info->xmit;
1241 int count;
1242
1243 if (up->port.x_char) {
1244 serial_outp(up, UART_TX, up->port.x_char);
1245 up->port.icount.tx++;
1246 up->port.x_char = 0;
1247 return;
1248 }
b129a8cc
RK		 1249 if (uart_tx_stopped(&up->port)) {
1250 serial8250_stop_tx(&up->port);
1251 return;
1252 }
1253 if (uart_circ_empty(xmit)) {
e763b90c 1254 __stop_tx(up);
1da177e4
LT		 1255 return;
1256 }
1257
1258 count = up->tx_loadsz;
1259 do {
1260 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1261 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1262 up->port.icount.tx++;
1263 if (uart_circ_empty(xmit))
1264 break;
1265 } while (--count > 0);
1266
1267 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1268 uart_write_wakeup(&up->port);
1269
1270 DEBUG_INTR("THRE...");
1271
1272 if (uart_circ_empty(xmit))
e763b90c 1273 __stop_tx(up);
1da177e4
LT		 1274}
1275
2af7cd68 1276static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1277{
2af7cd68
RK		 1278 unsigned int status = serial_in(up, UART_MSR);
1279
1280 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1281 if (status & UART_MSR_TERI)
1282 up->port.icount.rng++;
1283 if (status & UART_MSR_DDSR)
1284 up->port.icount.dsr++;
1285 if (status & UART_MSR_DDCD)
1286 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1287 if (status & UART_MSR_DCTS)
1288 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1289
1290 wake_up_interruptible(&up->port.info->delta_msr_wait);
1291 }
1da177e4 1292
2af7cd68 1293 return status;
1da177e4
LT		 1294}
1295
1296/*
1297 * This handles the interrupt from one port.
1298 */
1299static inline void
1300serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1301{
45e24601
RK		 1302 unsigned int status;
1303
1304 spin_lock(&up->port.lock);
1305
1306 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1307
1308 DEBUG_INTR("status = %x...", status);
1309
1310 if (status & UART_LSR_DR)
1311 receive_chars(up, &status, regs);
1312 check_modem_status(up);
1313 if (status & UART_LSR_THRE)
1314 transmit_chars(up);
45e24601
RK		 1315
1316 spin_unlock(&up->port.lock);
1da177e4
LT		 1317}
1318
1319/*
1320 * This is the serial driver's interrupt routine.
1321 *
1322 * Arjan thinks the old way was overly complex, so it got simplified.
1323 * Alan disagrees, saying that need the complexity to handle the weird
1324 * nature of ISA shared interrupts. (This is a special exception.)
1325 *
1326 * In order to handle ISA shared interrupts properly, we need to check
1327 * that all ports have been serviced, and therefore the ISA interrupt
1328 * line has been de-asserted.
1329 *
1330 * This means we need to loop through all ports. checking that they
1331 * don't have an interrupt pending.
1332 */
1333static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1334{
1335 struct irq_info *i = dev_id;
1336 struct list_head *l, *end = NULL;
1337 int pass_counter = 0, handled = 0;
1338
1339 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1340
1341 spin_lock(&i->lock);
1342
1343 l = i->head;
1344 do {
1345 struct uart_8250_port *up;
1346 unsigned int iir;
1347
1348 up = list_entry(l, struct uart_8250_port, list);
1349
1350 iir = serial_in(up, UART_IIR);
1351 if (!(iir & UART_IIR_NO_INT)) {
1da177e4 1352 serial8250_handle_port(up, regs);
1da177e4
LT		 1353
1354 handled = 1;
1355
1356 end = NULL;
1357 } else if (end == NULL)
1358 end = l;
1359
1360 l = l->next;
1361
1362 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1363 /* If we hit this, we're dead. */
1364 printk(KERN_ERR "serial8250: too much work for "
1365 "irq%d\n", irq);
1366 break;
1367 }
1368 } while (l != end);
1369
1370 spin_unlock(&i->lock);
1371
1372 DEBUG_INTR("end.\n");
1373
1374 return IRQ_RETVAL(handled);
1375}
1376
1377/*
1378 * To support ISA shared interrupts, we need to have one interrupt
1379 * handler that ensures that the IRQ line has been deasserted
1380 * before returning. Failing to do this will result in the IRQ
1381 * line being stuck active, and, since ISA irqs are edge triggered,
1382 * no more IRQs will be seen.
1383 */
1384static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1385{
1386 spin_lock_irq(&i->lock);
1387
1388 if (!list_empty(i->head)) {
1389 if (i->head == &up->list)
1390 i->head = i->head->next;
1391 list_del(&up->list);
1392 } else {
1393 BUG_ON(i->head != &up->list);
1394 i->head = NULL;
1395 }
1396
1397 spin_unlock_irq(&i->lock);
1398}
1399
1400static int serial_link_irq_chain(struct uart_8250_port *up)
1401{
1402 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1403 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1404
1405 spin_lock_irq(&i->lock);
1406
1407 if (i->head) {
1408 list_add(&up->list, i->head);
1409 spin_unlock_irq(&i->lock);
1410
1411 ret = 0;
1412 } else {
1413 INIT_LIST_HEAD(&up->list);
1414 i->head = &up->list;
1415 spin_unlock_irq(&i->lock);
1416
1417 ret = request_irq(up->port.irq, serial8250_interrupt,
1418 irq_flags, "serial", i);
1419 if (ret < 0)
1420 serial_do_unlink(i, up);
1421 }
1422
1423 return ret;
1424}
1425
1426static void serial_unlink_irq_chain(struct uart_8250_port *up)
1427{
1428 struct irq_info *i = irq_lists + up->port.irq;
1429
1430 BUG_ON(i->head == NULL);
1431
1432 if (list_empty(i->head))
1433 free_irq(up->port.irq, i);
1434
1435 serial_do_unlink(i, up);
1436}
1437
1438/*
1439 * This function is used to handle ports that do not have an
1440 * interrupt. This doesn't work very well for 16450's, but gives
1441 * barely passable results for a 16550A. (Although at the expense
1442 * of much CPU overhead).
1443 */
1444static void serial8250_timeout(unsigned long data)
1445{
1446 struct uart_8250_port *up = (struct uart_8250_port *)data;
1447 unsigned int timeout;
1448 unsigned int iir;
1449
1450 iir = serial_in(up, UART_IIR);
45e24601 1451 if (!(iir & UART_IIR_NO_INT))
1da177e4 1452 serial8250_handle_port(up, NULL);
1da177e4
LT		 1453
1454 timeout = up->port.timeout;
1455 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1456 mod_timer(&up->timer, jiffies + timeout);
1457}
1458
1459static unsigned int serial8250_tx_empty(struct uart_port *port)
1460{
1461 struct uart_8250_port *up = (struct uart_8250_port *)port;
1462 unsigned long flags;
1463 unsigned int ret;
1464
1465 spin_lock_irqsave(&up->port.lock, flags);
1466 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1467 spin_unlock_irqrestore(&up->port.lock, flags);
1468
1469 return ret;
1470}
1471
1472static unsigned int serial8250_get_mctrl(struct uart_port *port)
1473{
1474 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1475 unsigned int status;
1da177e4
LT		 1476 unsigned int ret;
1477
2af7cd68 1478 status = check_modem_status(up);
1da177e4
LT		 1479
1480 ret = 0;
1481 if (status & UART_MSR_DCD)
1482 ret |= TIOCM_CAR;
1483 if (status & UART_MSR_RI)
1484 ret |= TIOCM_RNG;
1485 if (status & UART_MSR_DSR)
1486 ret |= TIOCM_DSR;
1487 if (status & UART_MSR_CTS)
1488 ret |= TIOCM_CTS;
1489 return ret;
1490}
1491
1492static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1493{
1494 struct uart_8250_port *up = (struct uart_8250_port *)port;
1495 unsigned char mcr = 0;
1496
1497 if (mctrl & TIOCM_RTS)
1498 mcr |= UART_MCR_RTS;
1499 if (mctrl & TIOCM_DTR)
1500 mcr |= UART_MCR_DTR;
1501 if (mctrl & TIOCM_OUT1)
1502 mcr |= UART_MCR_OUT1;
1503 if (mctrl & TIOCM_OUT2)
1504 mcr |= UART_MCR_OUT2;
1505 if (mctrl & TIOCM_LOOP)
1506 mcr |= UART_MCR_LOOP;
1507
1508 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1509
1510 serial_out(up, UART_MCR, mcr);
1511}
1512
1513static void serial8250_break_ctl(struct uart_port *port, int break_state)
1514{
1515 struct uart_8250_port *up = (struct uart_8250_port *)port;
1516 unsigned long flags;
1517
1518 spin_lock_irqsave(&up->port.lock, flags);
1519 if (break_state == -1)
1520 up->lcr |= UART_LCR_SBC;
1521 else
1522 up->lcr &= ~UART_LCR_SBC;
1523 serial_out(up, UART_LCR, up->lcr);
1524 spin_unlock_irqrestore(&up->port.lock, flags);
1525}
1526
1527static int serial8250_startup(struct uart_port *port)
1528{
1529 struct uart_8250_port *up = (struct uart_8250_port *)port;
1530 unsigned long flags;
55d3b282 1531 unsigned char lsr, iir;
1da177e4
LT		 1532 int retval;
1533
1534 up->capabilities = uart_config[up->port.type].flags;
1535 up->mcr = 0;
1536
1537 if (up->port.type == PORT_16C950) {
1538 /* Wake up and initialize UART */
1539 up->acr = 0;
1540 serial_outp(up, UART_LCR, 0xBF);
1541 serial_outp(up, UART_EFR, UART_EFR_ECB);
1542 serial_outp(up, UART_IER, 0);
1543 serial_outp(up, UART_LCR, 0);
1544 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1545 serial_outp(up, UART_LCR, 0xBF);
1546 serial_outp(up, UART_EFR, UART_EFR_ECB);
1547 serial_outp(up, UART_LCR, 0);
1548 }
1549
1550#ifdef CONFIG_SERIAL_8250_RSA
1551 /*
1552 * If this is an RSA port, see if we can kick it up to the
1553 * higher speed clock.
1554 */
1555 enable_rsa(up);
1556#endif
1557
1558 /*
1559 * Clear the FIFO buffers and disable them.
7f927fcc 1560 * (they will be reenabled in set_termios())
1da177e4
LT		 1561 */
1562 serial8250_clear_fifos(up);
1563
1564 /*
1565 * Clear the interrupt registers.
1566 */
1567 (void) serial_inp(up, UART_LSR);
1568 (void) serial_inp(up, UART_RX);
1569 (void) serial_inp(up, UART_IIR);
1570 (void) serial_inp(up, UART_MSR);
1571
1572 /*
1573 * At this point, there's no way the LSR could still be 0xff;
1574 * if it is, then bail out, because there's likely no UART
1575 * here.
1576 */
1577 if (!(up->port.flags & UPF_BUGGY_UART) &&
1578 (serial_inp(up, UART_LSR) == 0xff)) {
1579 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1580 return -ENODEV;
1581 }
1582
1583 /*
1584 * For a XR16C850, we need to set the trigger levels
1585 */
1586 if (up->port.type == PORT_16850) {
1587 unsigned char fctr;
1588
1589 serial_outp(up, UART_LCR, 0xbf);
1590
1591 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1592 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1593 serial_outp(up, UART_TRG, UART_TRG_96);
1594 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1595 serial_outp(up, UART_TRG, UART_TRG_96);
1596
1597 serial_outp(up, UART_LCR, 0);
1598 }
1599
1600 /*
1601 * If the "interrupt" for this port doesn't correspond with any
1602 * hardware interrupt, we use a timer-based system. The original
1603 * driver used to do this with IRQ0.
1604 */
1605 if (!is_real_interrupt(up->port.irq)) {
1606 unsigned int timeout = up->port.timeout;
1607
1608 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1609
1610 up->timer.data = (unsigned long)up;
1611 mod_timer(&up->timer, jiffies + timeout);
1612 } else {
1613 retval = serial_link_irq_chain(up);
1614 if (retval)
1615 return retval;
1616 }
1617
1618 /*
1619 * Now, initialize the UART
1620 */
1621 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1622
1623 spin_lock_irqsave(&up->port.lock, flags);
1624 if (up->port.flags & UPF_FOURPORT) {
1625 if (!is_real_interrupt(up->port.irq))
1626 up->port.mctrl |= TIOCM_OUT1;
1627 } else
1628 /*
1629 * Most PC uarts need OUT2 raised to enable interrupts.
1630 */
1631 if (is_real_interrupt(up->port.irq))
1632 up->port.mctrl |= TIOCM_OUT2;
1633
1634 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1635
1636 /*
1637 * Do a quick test to see if we receive an
1638 * interrupt when we enable the TX irq.
1639 */
1640 serial_outp(up, UART_IER, UART_IER_THRI);
1641 lsr = serial_in(up, UART_LSR);
1642 iir = serial_in(up, UART_IIR);
1643 serial_outp(up, UART_IER, 0);
1644
1645 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1646 if (!(up->bugs & UART_BUG_TXEN)) {
1647 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1648 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1649 port->line);
1650 }
1651 } else {
67f7654e 1652 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1653 }
1654
1da177e4
LT		 1655 spin_unlock_irqrestore(&up->port.lock, flags);
1656
1657 /*
1658 * Finally, enable interrupts. Note: Modem status interrupts
1659 * are set via set_termios(), which will be occurring imminently
1660 * anyway, so we don't enable them here.
1661 */
1662 up->ier = UART_IER_RLSI | UART_IER_RDI;
1663 serial_outp(up, UART_IER, up->ier);
1664
1665 if (up->port.flags & UPF_FOURPORT) {
1666 unsigned int icp;
1667 /*
1668 * Enable interrupts on the AST Fourport board
1669 */
1670 icp = (up->port.iobase & 0xfe0) | 0x01f;
1671 outb_p(0x80, icp);
1672 (void) inb_p(icp);
1673 }
1674
1675 /*
1676 * And clear the interrupt registers again for luck.
1677 */
1678 (void) serial_inp(up, UART_LSR);
1679 (void) serial_inp(up, UART_RX);
1680 (void) serial_inp(up, UART_IIR);
1681 (void) serial_inp(up, UART_MSR);
1682
1683 return 0;
1684}
1685
1686static void serial8250_shutdown(struct uart_port *port)
1687{
1688 struct uart_8250_port *up = (struct uart_8250_port *)port;
1689 unsigned long flags;
1690
1691 /*
1692 * Disable interrupts from this port
1693 */
1694 up->ier = 0;
1695 serial_outp(up, UART_IER, 0);
1696
1697 spin_lock_irqsave(&up->port.lock, flags);
1698 if (up->port.flags & UPF_FOURPORT) {
1699 /* reset interrupts on the AST Fourport board */
1700 inb((up->port.iobase & 0xfe0) | 0x1f);
1701 up->port.mctrl |= TIOCM_OUT1;
1702 } else
1703 up->port.mctrl &= ~TIOCM_OUT2;
1704
1705 serial8250_set_mctrl(&up->port, up->port.mctrl);
1706 spin_unlock_irqrestore(&up->port.lock, flags);
1707
1708 /*
1709 * Disable break condition and FIFOs
1710 */
1711 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1712 serial8250_clear_fifos(up);
1713
1714#ifdef CONFIG_SERIAL_8250_RSA
1715 /*
1716 * Reset the RSA board back to 115kbps compat mode.
1717 */
1718 disable_rsa(up);
1719#endif
1720
1721 /*
1722 * Read data port to reset things, and then unlink from
1723 * the IRQ chain.
1724 */
1725 (void) serial_in(up, UART_RX);
1726
1727 if (!is_real_interrupt(up->port.irq))
1728 del_timer_sync(&up->timer);
1729 else
1730 serial_unlink_irq_chain(up);
1731}
1732
1733static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1734{
1735 unsigned int quot;
1736
1737 /*
1738 * Handle magic divisors for baud rates above baud_base on
1739 * SMSC SuperIO chips.
1740 */
1741 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1742 baud == (port->uartclk/4))
1743 quot = 0x8001;
1744 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1745 baud == (port->uartclk/8))
1746 quot = 0x8002;
1747 else
1748 quot = uart_get_divisor(port, baud);
1749
1750 return quot;
1751}
1752
1753static void
1754serial8250_set_termios(struct uart_port *port, struct termios *termios,
1755 struct termios *old)
1756{
1757 struct uart_8250_port *up = (struct uart_8250_port *)port;
1758 unsigned char cval, fcr = 0;
1759 unsigned long flags;
1760 unsigned int baud, quot;
1761
1762 switch (termios->c_cflag & CSIZE) {
1763 case CS5:
0a8b80c5 1764 cval = UART_LCR_WLEN5;
1da177e4
LT		 1765 break;
1766 case CS6:
0a8b80c5 1767 cval = UART_LCR_WLEN6;
1da177e4
LT		 1768 break;
1769 case CS7:
0a8b80c5 1770 cval = UART_LCR_WLEN7;
1da177e4
LT		 1771 break;
1772 default:
1773 case CS8:
0a8b80c5 1774 cval = UART_LCR_WLEN8;
1da177e4
LT		 1775 break;
1776 }
1777
1778 if (termios->c_cflag & CSTOPB)
0a8b80c5 1779 cval |= UART_LCR_STOP;
1da177e4
LT		 1780 if (termios->c_cflag & PARENB)
1781 cval |= UART_LCR_PARITY;
1782 if (!(termios->c_cflag & PARODD))
1783 cval |= UART_LCR_EPAR;
1784#ifdef CMSPAR
1785 if (termios->c_cflag & CMSPAR)
1786 cval |= UART_LCR_SPAR;
1787#endif
1788
1789 /*
1790 * Ask the core to calculate the divisor for us.
1791 */
1792 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1793 quot = serial8250_get_divisor(port, baud);
1794
1795 /*
4ba5e35d 1796 * Oxford Semi 952 rev B workaround
1da177e4 1797 */
4ba5e35d 1798 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1799 quot ++;
1800
1801 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1802 if (baud < 2400)
1803 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1804 else
1805 fcr = uart_config[up->port.type].fcr;
1806 }
1807
1808 /*
1809 * MCR-based auto flow control. When AFE is enabled, RTS will be
1810 * deasserted when the receive FIFO contains more characters than
1811 * the trigger, or the MCR RTS bit is cleared. In the case where
1812 * the remote UART is not using CTS auto flow control, we must
1813 * have sufficient FIFO entries for the latency of the remote
1814 * UART to respond. IOW, at least 32 bytes of FIFO.
1815 */
1816 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1817 up->mcr &= ~UART_MCR_AFE;
1818 if (termios->c_cflag & CRTSCTS)
1819 up->mcr |= UART_MCR_AFE;
1820 }
1821
1822 /*
1823 * Ok, we're now changing the port state. Do it with
1824 * interrupts disabled.
1825 */
1826 spin_lock_irqsave(&up->port.lock, flags);
1827
1828 /*
1829 * Update the per-port timeout.
1830 */
1831 uart_update_timeout(port, termios->c_cflag, baud);
1832
1833 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1834 if (termios->c_iflag & INPCK)
1835 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1836 if (termios->c_iflag & (BRKINT | PARMRK))
1837 up->port.read_status_mask |= UART_LSR_BI;
1838
1839 /*
1840 * Characteres to ignore
1841 */
1842 up->port.ignore_status_mask = 0;
1843 if (termios->c_iflag & IGNPAR)
1844 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1845 if (termios->c_iflag & IGNBRK) {
1846 up->port.ignore_status_mask |= UART_LSR_BI;
1847 /*
1848 * If we're ignoring parity and break indicators,
1849 * ignore overruns too (for real raw support).
1850 */
1851 if (termios->c_iflag & IGNPAR)
1852 up->port.ignore_status_mask |= UART_LSR_OE;
1853 }
1854
1855 /*
1856 * ignore all characters if CREAD is not set
1857 */
1858 if ((termios->c_cflag & CREAD) == 0)
1859 up->port.ignore_status_mask |= UART_LSR_DR;
1860
1861 /*
1862 * CTS flow control flag and modem status interrupts
1863 */
1864 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1865 if (!(up->bugs & UART_BUG_NOMSR) &&
1866 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1867 up->ier |= UART_IER_MSI;
1868 if (up->capabilities & UART_CAP_UUE)
1869 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1870
1871 serial_out(up, UART_IER, up->ier);
1872
1873 if (up->capabilities & UART_CAP_EFR) {
1874 unsigned char efr = 0;
1875 /*
1876 * TI16C752/Startech hardware flow control. FIXME:
1877 * - TI16C752 requires control thresholds to be set.
1878 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1879 */
1880 if (termios->c_cflag & CRTSCTS)
1881 efr |= UART_EFR_CTS;
1882
1883 serial_outp(up, UART_LCR, 0xBF);
1884 serial_outp(up, UART_EFR, efr);
1885 }
1886
1887 if (up->capabilities & UART_NATSEMI) {
1888 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1889 serial_outp(up, UART_LCR, 0xe0);
1890 } else {
1891 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1892 }
1893
b32b19b8 1894 serial_dl_write(up, quot);
1da177e4
LT		 1895
1896 /*
1897 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1898 * is written without DLAB set, this mode will be disabled.
1899 */
1900 if (up->port.type == PORT_16750)
1901 serial_outp(up, UART_FCR, fcr);
1902
1903 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1904 up->lcr = cval; /* Save LCR */
1905 if (up->port.type != PORT_16750) {
1906 if (fcr & UART_FCR_ENABLE_FIFO) {
1907 /* emulated UARTs (Lucent Venus 167x) need two steps */
1908 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1909 }
1910 serial_outp(up, UART_FCR, fcr); /* set fcr */
1911 }
1912 serial8250_set_mctrl(&up->port, up->port.mctrl);
1913 spin_unlock_irqrestore(&up->port.lock, flags);
1914}
1915
1916static void
1917serial8250_pm(struct uart_port *port, unsigned int state,
1918 unsigned int oldstate)
1919{
1920 struct uart_8250_port *p = (struct uart_8250_port *)port;
1921
1922 serial8250_set_sleep(p, state != 0);
1923
1924 if (p->pm)
1925 p->pm(port, state, oldstate);
1926}
1927
1928/*
1929 * Resource handling.
1930 */
1931static int serial8250_request_std_resource(struct uart_8250_port *up)
1932{
1933 unsigned int size = 8 << up->port.regshift;
1934 int ret = 0;
1935
1936 switch (up->port.iotype) {
85835f44
SS		 1937 case UPIO_AU:
1938 size = 0x100000;
1939 /* fall thru */
1da177e4
LT		 1940 case UPIO_MEM:
1941 if (!up->port.mapbase)
1942 break;
1943
1944 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1945 ret = -EBUSY;
1946 break;
1947 }
1948
1949 if (up->port.flags & UPF_IOREMAP) {
1950 up->port.membase = ioremap(up->port.mapbase, size);
1951 if (!up->port.membase) {
1952 release_mem_region(up->port.mapbase, size);
1953 ret = -ENOMEM;
1954 }
1955 }
1956 break;
1957
1958 case UPIO_HUB6:
1959 case UPIO_PORT:
1960 if (!request_region(up->port.iobase, size, "serial"))
1961 ret = -EBUSY;
1962 break;
1963 }
1964 return ret;
1965}
1966
1967static void serial8250_release_std_resource(struct uart_8250_port *up)
1968{
1969 unsigned int size = 8 << up->port.regshift;
1970
1971 switch (up->port.iotype) {
85835f44
SS		 1972 case UPIO_AU:
1973 size = 0x100000;
1974 /* fall thru */
1da177e4
LT		 1975 case UPIO_MEM:
1976 if (!up->port.mapbase)
1977 break;
1978
1979 if (up->port.flags & UPF_IOREMAP) {
1980 iounmap(up->port.membase);
1981 up->port.membase = NULL;
1982 }
1983
1984 release_mem_region(up->port.mapbase, size);
1985 break;
1986
1987 case UPIO_HUB6:
1988 case UPIO_PORT:
1989 release_region(up->port.iobase, size);
1990 break;
1991 }
1992}
1993
1994static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1995{
1996 unsigned long start = UART_RSA_BASE << up->port.regshift;
1997 unsigned int size = 8 << up->port.regshift;
1998 int ret = 0;
1999
2000 switch (up->port.iotype) {
2001 case UPIO_MEM:
2002 ret = -EINVAL;
2003 break;
2004
2005 case UPIO_HUB6:
2006 case UPIO_PORT:
2007 start += up->port.iobase;
2008 if (!request_region(start, size, "serial-rsa"))
2009 ret = -EBUSY;
2010 break;
2011 }
2012
2013 return ret;
2014}
2015
2016static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2017{
2018 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2019 unsigned int size = 8 << up->port.regshift;
2020
2021 switch (up->port.iotype) {
2022 case UPIO_MEM:
2023 break;
2024
2025 case UPIO_HUB6:
2026 case UPIO_PORT:
2027 release_region(up->port.iobase + offset, size);
2028 break;
2029 }
2030}
2031
2032static void serial8250_release_port(struct uart_port *port)
2033{
2034 struct uart_8250_port *up = (struct uart_8250_port *)port;
2035
2036 serial8250_release_std_resource(up);
2037 if (up->port.type == PORT_RSA)
2038 serial8250_release_rsa_resource(up);
2039}
2040
2041static int serial8250_request_port(struct uart_port *port)
2042{
2043 struct uart_8250_port *up = (struct uart_8250_port *)port;
2044 int ret = 0;
2045
2046 ret = serial8250_request_std_resource(up);
2047 if (ret == 0 && up->port.type == PORT_RSA) {
2048 ret = serial8250_request_rsa_resource(up);
2049 if (ret < 0)
2050 serial8250_release_std_resource(up);
2051 }
2052
2053 return ret;
2054}
2055
2056static void serial8250_config_port(struct uart_port *port, int flags)
2057{
2058 struct uart_8250_port *up = (struct uart_8250_port *)port;
2059 int probeflags = PROBE_ANY;
2060 int ret;
2061
1da177e4
LT		 2062 /*
2063 * Find the region that we can probe for. This in turn
2064 * tells us whether we can probe for the type of port.
2065 */
2066 ret = serial8250_request_std_resource(up);
2067 if (ret < 0)
2068 return;
2069
2070 ret = serial8250_request_rsa_resource(up);
2071 if (ret < 0)
2072 probeflags &= ~PROBE_RSA;
2073
2074 if (flags & UART_CONFIG_TYPE)
2075 autoconfig(up, probeflags);
2076 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2077 autoconfig_irq(up);
2078
2079 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2080 serial8250_release_rsa_resource(up);
2081 if (up->port.type == PORT_UNKNOWN)
2082 serial8250_release_std_resource(up);
2083}
2084
2085static int
2086serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2087{
2088 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2089 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2090 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2091 ser->type == PORT_STARTECH)
2092 return -EINVAL;
2093 return 0;
2094}
2095
2096static const char *
2097serial8250_type(struct uart_port *port)
2098{
2099 int type = port->type;
2100
2101 if (type >= ARRAY_SIZE(uart_config))
2102 type = 0;
2103 return uart_config[type].name;
2104}
2105
2106static struct uart_ops serial8250_pops = {
2107 .tx_empty = serial8250_tx_empty,
2108 .set_mctrl = serial8250_set_mctrl,
2109 .get_mctrl = serial8250_get_mctrl,
2110 .stop_tx = serial8250_stop_tx,
2111 .start_tx = serial8250_start_tx,
2112 .stop_rx = serial8250_stop_rx,
2113 .enable_ms = serial8250_enable_ms,
2114 .break_ctl = serial8250_break_ctl,
2115 .startup = serial8250_startup,
2116 .shutdown = serial8250_shutdown,
2117 .set_termios = serial8250_set_termios,
2118 .pm = serial8250_pm,
2119 .type = serial8250_type,
2120 .release_port = serial8250_release_port,
2121 .request_port = serial8250_request_port,
2122 .config_port = serial8250_config_port,
2123 .verify_port = serial8250_verify_port,
2124};
2125
2126static struct uart_8250_port serial8250_ports[UART_NR];
2127
2128static void __init serial8250_isa_init_ports(void)
2129{
2130 struct uart_8250_port *up;
2131 static int first = 1;
2132 int i;
2133
2134 if (!first)
2135 return;
2136 first = 0;
2137
a61c2d78 2138 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2139 struct uart_8250_port *up = &serial8250_ports[i];
2140
2141 up->port.line = i;
2142 spin_lock_init(&up->port.lock);
2143
2144 init_timer(&up->timer);
2145 up->timer.function = serial8250_timeout;
2146
2147 /*
2148 * ALPHA_KLUDGE_MCR needs to be killed.
2149 */
2150 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2151 up->mcr_force = ALPHA_KLUDGE_MCR;
2152
2153 up->port.ops = &serial8250_pops;
2154 }
2155
44454bcd 2156 for (i = 0, up = serial8250_ports;
a61c2d78 2157 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2158 i++, up++) {
2159 up->port.iobase = old_serial_port[i].port;
2160 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2161 up->port.uartclk = old_serial_port[i].baud_base * 16;
2162 up->port.flags = old_serial_port[i].flags;
2163 up->port.hub6 = old_serial_port[i].hub6;
2164 up->port.membase = old_serial_port[i].iomem_base;
2165 up->port.iotype = old_serial_port[i].io_type;
2166 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2167 if (share_irqs)
2168 up->port.flags |= UPF_SHARE_IRQ;
2169 }
2170}
2171
2172static void __init
2173serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2174{
2175 int i;
2176
2177 serial8250_isa_init_ports();
2178
a61c2d78 2179 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2180 struct uart_8250_port *up = &serial8250_ports[i];
2181
2182 up->port.dev = dev;
2183 uart_add_one_port(drv, &up->port);
2184 }
2185}
2186
2187#ifdef CONFIG_SERIAL_8250_CONSOLE
2188
2189#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2190
2191/*
2192 * Wait for transmitter & holding register to empty
2193 */
f91a3715 2194static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1da177e4
LT		 2195{
2196 unsigned int status, tmout = 10000;
2197
2198 /* Wait up to 10ms for the character(s) to be sent. */
2199 do {
2200 status = serial_in(up, UART_LSR);
2201
2202 if (status & UART_LSR_BI)
2203 up->lsr_break_flag = UART_LSR_BI;
2204
2205 if (--tmout == 0)
2206 break;
2207 udelay(1);
f91a3715 2208 } while ((status & bits) != bits);
1da177e4
LT		 2209
2210 /* Wait up to 1s for flow control if necessary */
2211 if (up->port.flags & UPF_CONS_FLOW) {
2212 tmout = 1000000;
2213 while (--tmout &&
2214 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2215 udelay(1);
2216 }
2217}
2218
d358788f
RK		 2219static void serial8250_console_putchar(struct uart_port *port, int ch)
2220{
2221 struct uart_8250_port *up = (struct uart_8250_port *)port;
2222
2223 wait_for_xmitr(up, UART_LSR_THRE);
2224 serial_out(up, UART_TX, ch);
2225}
2226
1da177e4
LT		 2227/*
2228 * Print a string to the serial port trying not to disturb
2229 * any possible real use of the port...
2230 *
2231 * The console_lock must be held when we get here.
2232 */
2233static void
2234serial8250_console_write(struct console *co, const char *s, unsigned int count)
2235{
2236 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2237 unsigned long flags;
1da177e4 2238 unsigned int ier;
d8a5a8d7 2239 int locked = 1;
1da177e4 2240
78512ece
AM		 2241 touch_nmi_watchdog();
2242
d8a5a8d7
RK		 2243 if (oops_in_progress) {
2244 locked = spin_trylock_irqsave(&up->port.lock, flags);
2245 } else
2246 spin_lock_irqsave(&up->port.lock, flags);
2247
1da177e4 2248 /*
dc7bf130 2249 * First save the IER then disable the interrupts
1da177e4
LT		 2250 */
2251 ier = serial_in(up, UART_IER);
2252
2253 if (up->capabilities & UART_CAP_UUE)
2254 serial_out(up, UART_IER, UART_IER_UUE);
2255 else
2256 serial_out(up, UART_IER, 0);
2257
d358788f 2258 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2259
2260 /*
2261 * Finally, wait for transmitter to become empty
2262 * and restore the IER
2263 */
f91a3715 2264 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2265 serial_out(up, UART_IER, ier);
d8a5a8d7
RK		 2266
2267 if (locked)
2268 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 2269}
2270
2271static int serial8250_console_setup(struct console *co, char *options)
2272{
2273 struct uart_port *port;
2274 int baud = 9600;
2275 int bits = 8;
2276 int parity = 'n';
2277 int flow = 'n';
2278
2279 /*
2280 * Check whether an invalid uart number has been specified, and
2281 * if so, search for the first available port that does have
2282 * console support.
2283 */
a61c2d78 2284 if (co->index >= nr_uarts)
1da177e4
LT		 2285 co->index = 0;
2286 port = &serial8250_ports[co->index].port;
2287 if (!port->iobase && !port->membase)
2288 return -ENODEV;
2289
2290 if (options)
2291 uart_parse_options(options, &baud, &parity, &bits, &flow);
2292
2293 return uart_set_options(port, co, baud, parity, bits, flow);
2294}
2295
2296static struct uart_driver serial8250_reg;
2297static struct console serial8250_console = {
2298 .name = "ttyS",
2299 .write = serial8250_console_write,
2300 .device = uart_console_device,
2301 .setup = serial8250_console_setup,
2302 .flags = CON_PRINTBUFFER,
2303 .index = -1,
2304 .data = &serial8250_reg,
2305};
2306
2307static int __init serial8250_console_init(void)
2308{
2309 serial8250_isa_init_ports();
2310 register_console(&serial8250_console);
2311 return 0;
2312}
2313console_initcall(serial8250_console_init);
2314
2315static int __init find_port(struct uart_port *p)
2316{
2317 int line;
2318 struct uart_port *port;
2319
a61c2d78 2320 for (line = 0; line < nr_uarts; line++) {
1da177e4 2321 port = &serial8250_ports[line].port;
50aec3b5 2322 if (uart_match_port(p, port))
1da177e4
LT		 2323 return line;
2324 }
2325 return -ENODEV;
2326}
2327
2328int __init serial8250_start_console(struct uart_port *port, char *options)
2329{
2330 int line;
2331
2332 line = find_port(port);
2333 if (line < 0)
2334 return -ENODEV;
2335
2336 add_preferred_console("ttyS", line, options);
2337 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2338 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2339 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2340 (unsigned long) port->iobase, options);
2341 if (!(serial8250_console.flags & CON_ENABLED)) {
2342 serial8250_console.flags &= ~CON_PRINTBUFFER;
2343 register_console(&serial8250_console);
2344 }
2345 return line;
2346}
2347
2348#define SERIAL8250_CONSOLE &serial8250_console
2349#else
2350#define SERIAL8250_CONSOLE NULL
2351#endif
2352
2353static struct uart_driver serial8250_reg = {
2354 .owner = THIS_MODULE,
2355 .driver_name = "serial",
1da177e4
LT		 2356 .dev_name = "ttyS",
2357 .major = TTY_MAJOR,
2358 .minor = 64,
2359 .nr = UART_NR,
2360 .cons = SERIAL8250_CONSOLE,
2361};
2362
d856c666
RK		 2363/*
2364 * early_serial_setup - early registration for 8250 ports
2365 *
2366 * Setup an 8250 port structure prior to console initialisation. Use
2367 * after console initialisation will cause undefined behaviour.
2368 */
1da177e4
LT		 2369int __init early_serial_setup(struct uart_port *port)
2370{
2371 if (port->line >= ARRAY_SIZE(serial8250_ports))
2372 return -ENODEV;
2373
2374 serial8250_isa_init_ports();
2375 serial8250_ports[port->line].port = *port;
2376 serial8250_ports[port->line].port.ops = &serial8250_pops;
2377 return 0;
2378}
2379
2380/**
2381 * serial8250_suspend_port - suspend one serial port
2382 * @line: serial line number
2383 * @level: the level of port suspension, as per uart_suspend_port
2384 *
2385 * Suspend one serial port.
2386 */
2387void serial8250_suspend_port(int line)
2388{
2389 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2390}
2391
2392/**
2393 * serial8250_resume_port - resume one serial port
2394 * @line: serial line number
2395 * @level: the level of port resumption, as per uart_resume_port
2396 *
2397 * Resume one serial port.
2398 */
2399void serial8250_resume_port(int line)
2400{
2401 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2402}
2403
2404/*
2405 * Register a set of serial devices attached to a platform device. The
2406 * list is terminated with a zero flags entry, which means we expect
2407 * all entries to have at least UPF_BOOT_AUTOCONF set.
2408 */
3ae5eaec 2409static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2410{
3ae5eaec 2411 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2412 struct uart_port port;
ec9f47cd 2413 int ret, i;
1da177e4
LT		 2414
2415 memset(&port, 0, sizeof(struct uart_port));
2416
ec9f47cd 2417 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2418 port.iobase = p->iobase;
2419 port.membase = p->membase;
2420 port.irq = p->irq;
2421 port.uartclk = p->uartclk;
2422 port.regshift = p->regshift;
2423 port.iotype = p->iotype;
2424 port.flags = p->flags;
2425 port.mapbase = p->mapbase;
ec9f47cd 2426 port.hub6 = p->hub6;
3ae5eaec 2427 port.dev = &dev->dev;
1da177e4
LT		 2428 if (share_irqs)
2429 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2430 ret = serial8250_register_port(&port);
2431 if (ret < 0) {
3ae5eaec 2432 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2433 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2434 p->iobase, p->mapbase, p->irq, ret);
2435 }
1da177e4
LT		 2436 }
2437 return 0;
2438}
2439
2440/*
2441 * Remove serial ports registered against a platform device.
2442 */
3ae5eaec 2443static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2444{
2445 int i;
2446
a61c2d78 2447 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2448 struct uart_8250_port *up = &serial8250_ports[i];
2449
3ae5eaec 2450 if (up->port.dev == &dev->dev)
1da177e4
LT		 2451 serial8250_unregister_port(i);
2452 }
2453 return 0;
2454}
2455
3ae5eaec 2456static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2457{
2458 int i;
2459
1da177e4
LT		 2460 for (i = 0; i < UART_NR; i++) {
2461 struct uart_8250_port *up = &serial8250_ports[i];
2462
3ae5eaec 2463 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2464 uart_suspend_port(&serial8250_reg, &up->port);
2465 }
2466
2467 return 0;
2468}
2469
3ae5eaec 2470static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2471{
2472 int i;
2473
1da177e4
LT		 2474 for (i = 0; i < UART_NR; i++) {
2475 struct uart_8250_port *up = &serial8250_ports[i];
2476
3ae5eaec 2477 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2478 uart_resume_port(&serial8250_reg, &up->port);
2479 }
2480
2481 return 0;
2482}
2483
3ae5eaec 2484static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2485 .probe = serial8250_probe,
2486 .remove = __devexit_p(serial8250_remove),
2487 .suspend = serial8250_suspend,
2488 .resume = serial8250_resume,
3ae5eaec
RK		 2489 .driver = {
2490 .name = "serial8250",
7493a314 2491 .owner = THIS_MODULE,
3ae5eaec 2492 },
1da177e4
LT		 2493};
2494
2495/*
2496 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2497 * in the table in include/asm/serial.h
2498 */
2499static struct platform_device *serial8250_isa_devs;
2500
2501/*
2502 * serial8250_register_port and serial8250_unregister_port allows for
2503 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2504 * modems and PCI multiport cards.
2505 */
f392ecfa 2506static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2507
2508static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2509{
2510 int i;
2511
2512 /*
2513 * First, find a port entry which matches.
2514 */
a61c2d78 2515 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2516 if (uart_match_port(&serial8250_ports[i].port, port))
2517 return &serial8250_ports[i];
2518
2519 /*
2520 * We didn't find a matching entry, so look for the first
2521 * free entry. We look for one which hasn't been previously
2522 * used (indicated by zero iobase).
2523 */
a61c2d78 2524 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2525 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2526 serial8250_ports[i].port.iobase == 0)
2527 return &serial8250_ports[i];
2528
2529 /*
2530 * That also failed. Last resort is to find any entry which
2531 * doesn't have a real port associated with it.
2532 */
a61c2d78 2533 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2534 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2535 return &serial8250_ports[i];
2536
2537 return NULL;
2538}
2539
2540/**
2541 * serial8250_register_port - register a serial port
2542 * @port: serial port template
2543 *
2544 * Configure the serial port specified by the request. If the
2545 * port exists and is in use, it is hung up and unregistered
2546 * first.
2547 *
2548 * The port is then probed and if necessary the IRQ is autodetected
2549 * If this fails an error is returned.
2550 *
2551 * On success the port is ready to use and the line number is returned.
2552 */
2553int serial8250_register_port(struct uart_port *port)
2554{
2555 struct uart_8250_port *uart;
2556 int ret = -ENOSPC;
2557
2558 if (port->uartclk == 0)
2559 return -EINVAL;
2560
f392ecfa 2561 mutex_lock(&serial_mutex);
1da177e4
LT		 2562
2563 uart = serial8250_find_match_or_unused(port);
2564 if (uart) {
2565 uart_remove_one_port(&serial8250_reg, &uart->port);
2566
2567 uart->port.iobase = port->iobase;
2568 uart->port.membase = port->membase;
2569 uart->port.irq = port->irq;
2570 uart->port.uartclk = port->uartclk;
2571 uart->port.fifosize = port->fifosize;
2572 uart->port.regshift = port->regshift;
2573 uart->port.iotype = port->iotype;
2574 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2575 uart->port.mapbase = port->mapbase;
2576 if (port->dev)
2577 uart->port.dev = port->dev;
2578
2579 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2580 if (ret == 0)
2581 ret = uart->port.line;
2582 }
f392ecfa 2583 mutex_unlock(&serial_mutex);
1da177e4
LT		 2584
2585 return ret;
2586}
2587EXPORT_SYMBOL(serial8250_register_port);
2588
2589/**
2590 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2591 * @line: serial line number
2592 *
2593 * Remove one serial port. This may not be called from interrupt
2594 * context. We hand the port back to the our control.
2595 */
2596void serial8250_unregister_port(int line)
2597{
2598 struct uart_8250_port *uart = &serial8250_ports[line];
2599
f392ecfa 2600 mutex_lock(&serial_mutex);
1da177e4
LT		 2601 uart_remove_one_port(&serial8250_reg, &uart->port);
2602 if (serial8250_isa_devs) {
2603 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2604 uart->port.type = PORT_UNKNOWN;
2605 uart->port.dev = &serial8250_isa_devs->dev;
2606 uart_add_one_port(&serial8250_reg, &uart->port);
2607 } else {
2608 uart->port.dev = NULL;
2609 }
f392ecfa 2610 mutex_unlock(&serial_mutex);
1da177e4
LT		 2611}
2612EXPORT_SYMBOL(serial8250_unregister_port);
2613
2614static int __init serial8250_init(void)
2615{
2616 int ret, i;
2617
a61c2d78
DJ		 2618 if (nr_uarts > UART_NR)
2619 nr_uarts = UART_NR;
2620
1da177e4 2621 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2622 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2623 share_irqs ? "en" : "dis");
2624
2625 for (i = 0; i < NR_IRQS; i++)
2626 spin_lock_init(&irq_lists[i].lock);
2627
2628 ret = uart_register_driver(&serial8250_reg);
2629 if (ret)
2630 goto out;
2631
7493a314
DT		 2632 serial8250_isa_devs = platform_device_alloc("serial8250",
2633 PLAT8250_DEV_LEGACY);
2634 if (!serial8250_isa_devs) {
2635 ret = -ENOMEM;
bc965a7f 2636 goto unreg_uart_drv;
1da177e4
LT		 2637 }
2638
7493a314
DT		 2639 ret = platform_device_add(serial8250_isa_devs);
2640 if (ret)
2641 goto put_dev;
2642
1da177e4
LT		 2643 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2644
bc965a7f
RK		 2645 ret = platform_driver_register(&serial8250_isa_driver);
2646 if (ret == 0)
2647 goto out;
1da177e4 2648
bc965a7f 2649 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2650 put_dev:
2651 platform_device_put(serial8250_isa_devs);
7493a314 2652 unreg_uart_drv:
1da177e4
LT		 2653 uart_unregister_driver(&serial8250_reg);
2654 out:
2655 return ret;
2656}
2657
2658static void __exit serial8250_exit(void)
2659{
2660 struct platform_device *isa_dev = serial8250_isa_devs;
2661
2662 /*
2663 * This tells serial8250_unregister_port() not to re-register
2664 * the ports (thereby making serial8250_isa_driver permanently
2665 * in use.)
2666 */
2667 serial8250_isa_devs = NULL;
2668
3ae5eaec 2669 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2670 platform_device_unregister(isa_dev);
2671
2672 uart_unregister_driver(&serial8250_reg);
2673}
2674
2675module_init(serial8250_init);
2676module_exit(serial8250_exit);
2677
2678EXPORT_SYMBOL(serial8250_suspend_port);
2679EXPORT_SYMBOL(serial8250_resume_port);
2680
2681MODULE_LICENSE("GPL");
2682MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2683
2684module_param(share_irqs, uint, 0644);
2685MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2686 " (unsafe)");
2687
a61c2d78
DJ		 2688module_param(nr_uarts, uint, 0644);
2689MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2690
1da177e4
LT		 2691#ifdef CONFIG_SERIAL_8250_RSA
2692module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2693MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2694#endif
2695MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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