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[PATCH] Documentation: remove super-{nr, max} to reflect fs/super.c
[net-next-2.6.git] / drivers / serial / 8250.c
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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
51 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
54unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
80/*
81 * This converts from our new CONFIG_ symbols to the symbols
82 * that asm/serial.h expects. You _NEED_ to comment out the
83 * linux/config.h include contained inside asm/serial.h for
84 * this to work.
85 */
86#undef CONFIG_SERIAL_MANY_PORTS
87#undef CONFIG_SERIAL_DETECT_IRQ
88#undef CONFIG_SERIAL_MULTIPORT
89#undef CONFIG_HUB6
90
91#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92#define CONFIG_SERIAL_DETECT_IRQ 1
93#endif
94#ifdef CONFIG_SERIAL_8250_MULTIPORT
95#define CONFIG_SERIAL_MULTIPORT 1
96#endif
97#ifdef CONFIG_SERIAL_8250_MANY_PORTS
98#define CONFIG_SERIAL_MANY_PORTS 1
99#endif
100
101/*
102 * HUB6 is always on. This will be removed once the header
103 * files have been cleaned.
104 */
105#define CONFIG_HUB6 1
106
107#include <asm/serial.h>
108
109/*
110 * SERIAL_PORT_DFNS tells us about built-in ports that have no
111 * standard enumeration mechanism. Platforms that can find all
112 * serial ports via mechanisms like ACPI or PCI need not supply it.
113 */
114#ifndef SERIAL_PORT_DFNS
115#define SERIAL_PORT_DFNS
116#endif
117
118static struct old_serial_port old_serial_port[] = {
119 SERIAL_PORT_DFNS /* defined in asm/serial.h */
120};
121
122#define UART_NR (ARRAY_SIZE(old_serial_port) + CONFIG_SERIAL_8250_NR_UARTS)
123
124#ifdef CONFIG_SERIAL_8250_RSA
125
126#define PORT_RSA_MAX 4
127static unsigned long probe_rsa[PORT_RSA_MAX];
128static unsigned int probe_rsa_count;
129#endif /* CONFIG_SERIAL_8250_RSA */
130
131struct uart_8250_port {
132 struct uart_port port;
133 struct timer_list timer; /* "no irq" timer */
134 struct list_head list; /* ports on this IRQ */
135 unsigned int capabilities; /* port capabilities */
136 unsigned int tx_loadsz; /* transmit fifo load size */
137 unsigned short rev;
138 unsigned char acr;
139 unsigned char ier;
140 unsigned char lcr;
141 unsigned char mcr;
142 unsigned char mcr_mask; /* mask of user bits */
143 unsigned char mcr_force; /* mask of forced bits */
144 unsigned char lsr_break_flag;
145
146 /*
147 * We provide a per-port pm hook.
148 */
149 void (*pm)(struct uart_port *port,
150 unsigned int state, unsigned int old);
151};
152
153struct irq_info {
154 spinlock_t lock;
155 struct list_head *head;
156};
157
158static struct irq_info irq_lists[NR_IRQS];
159
160/*
161 * Here we define the default xmit fifo size used for each type of UART.
162 */
163static const struct serial8250_config uart_config[] = {
164 [PORT_UNKNOWN] = {
165 .name = "unknown",
166 .fifo_size = 1,
167 .tx_loadsz = 1,
168 },
169 [PORT_8250] = {
170 .name = "8250",
171 .fifo_size = 1,
172 .tx_loadsz = 1,
173 },
174 [PORT_16450] = {
175 .name = "16450",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16550] = {
180 .name = "16550",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16550A] = {
185 .name = "16550A",
186 .fifo_size = 16,
187 .tx_loadsz = 16,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
189 .flags = UART_CAP_FIFO,
190 },
191 [PORT_CIRRUS] = {
192 .name = "Cirrus",
193 .fifo_size = 1,
194 .tx_loadsz = 1,
195 },
196 [PORT_16650] = {
197 .name = "ST16650",
198 .fifo_size = 1,
199 .tx_loadsz = 1,
200 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
201 },
202 [PORT_16650V2] = {
203 .name = "ST16650V2",
204 .fifo_size = 32,
205 .tx_loadsz = 16,
206 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
207 UART_FCR_T_TRIG_00,
208 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
209 },
210 [PORT_16750] = {
211 .name = "TI16750",
212 .fifo_size = 64,
213 .tx_loadsz = 64,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
215 UART_FCR7_64BYTE,
216 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
217 },
218 [PORT_STARTECH] = {
219 .name = "Startech",
220 .fifo_size = 1,
221 .tx_loadsz = 1,
222 },
223 [PORT_16C950] = {
224 .name = "16C950/954",
225 .fifo_size = 128,
226 .tx_loadsz = 128,
227 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
228 .flags = UART_CAP_FIFO,
229 },
230 [PORT_16654] = {
231 .name = "ST16654",
232 .fifo_size = 64,
233 .tx_loadsz = 32,
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
235 UART_FCR_T_TRIG_10,
236 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
237 },
238 [PORT_16850] = {
239 .name = "XR16850",
240 .fifo_size = 128,
241 .tx_loadsz = 128,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
244 },
245 [PORT_RSA] = {
246 .name = "RSA",
247 .fifo_size = 2048,
248 .tx_loadsz = 2048,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
250 .flags = UART_CAP_FIFO,
251 },
252 [PORT_NS16550A] = {
253 .name = "NS16550A",
254 .fifo_size = 16,
255 .tx_loadsz = 16,
256 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .flags = UART_CAP_FIFO | UART_NATSEMI,
258 },
259 [PORT_XSCALE] = {
260 .name = "XScale",
261 .fifo_size = 32,
262 .tx_loadsz = 32,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264 .flags = UART_CAP_FIFO | UART_CAP_UUE,
265 },
266};
267
268static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
269{
270 offset <<= up->port.regshift;
271
272 switch (up->port.iotype) {
273 case UPIO_HUB6:
274 outb(up->port.hub6 - 1 + offset, up->port.iobase);
275 return inb(up->port.iobase + 1);
276
277 case UPIO_MEM:
278 return readb(up->port.membase + offset);
279
280 case UPIO_MEM32:
281 return readl(up->port.membase + offset);
282
283 default:
284 return inb(up->port.iobase + offset);
285 }
286}
287
288static _INLINE_ void
289serial_out(struct uart_8250_port *up, int offset, int value)
290{
291 offset <<= up->port.regshift;
292
293 switch (up->port.iotype) {
294 case UPIO_HUB6:
295 outb(up->port.hub6 - 1 + offset, up->port.iobase);
296 outb(value, up->port.iobase + 1);
297 break;
298
299 case UPIO_MEM:
300 writeb(value, up->port.membase + offset);
301 break;
302
303 case UPIO_MEM32:
304 writel(value, up->port.membase + offset);
305 break;
306
307 default:
308 outb(value, up->port.iobase + offset);
309 }
310}
311
312/*
313 * We used to support using pause I/O for certain machines. We
314 * haven't supported this for a while, but just in case it's badly
315 * needed for certain old 386 machines, I've left these #define's
316 * in....
317 */
318#define serial_inp(up, offset) serial_in(up, offset)
319#define serial_outp(up, offset, value) serial_out(up, offset, value)
320
321
322/*
323 * For the 16C950
324 */
325static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
326{
327 serial_out(up, UART_SCR, offset);
328 serial_out(up, UART_ICR, value);
329}
330
331static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
332{
333 unsigned int value;
334
335 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
336 serial_out(up, UART_SCR, offset);
337 value = serial_in(up, UART_ICR);
338 serial_icr_write(up, UART_ACR, up->acr);
339
340 return value;
341}
342
343/*
344 * FIFO support.
345 */
346static inline void serial8250_clear_fifos(struct uart_8250_port *p)
347{
348 if (p->capabilities & UART_CAP_FIFO) {
349 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
350 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
351 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
352 serial_outp(p, UART_FCR, 0);
353 }
354}
355
356/*
357 * IER sleep support. UARTs which have EFRs need the "extended
358 * capability" bit enabled. Note that on XR16C850s, we need to
359 * reset LCR to write to IER.
360 */
361static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
362{
363 if (p->capabilities & UART_CAP_SLEEP) {
364 if (p->capabilities & UART_CAP_EFR) {
365 serial_outp(p, UART_LCR, 0xBF);
366 serial_outp(p, UART_EFR, UART_EFR_ECB);
367 serial_outp(p, UART_LCR, 0);
368 }
369 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
370 if (p->capabilities & UART_CAP_EFR) {
371 serial_outp(p, UART_LCR, 0xBF);
372 serial_outp(p, UART_EFR, 0);
373 serial_outp(p, UART_LCR, 0);
374 }
375 }
376}
377
378#ifdef CONFIG_SERIAL_8250_RSA
379/*
380 * Attempts to turn on the RSA FIFO. Returns zero on failure.
381 * We set the port uart clock rate if we succeed.
382 */
383static int __enable_rsa(struct uart_8250_port *up)
384{
385 unsigned char mode;
386 int result;
387
388 mode = serial_inp(up, UART_RSA_MSR);
389 result = mode & UART_RSA_MSR_FIFO;
390
391 if (!result) {
392 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
393 mode = serial_inp(up, UART_RSA_MSR);
394 result = mode & UART_RSA_MSR_FIFO;
395 }
396
397 if (result)
398 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
399
400 return result;
401}
402
403static void enable_rsa(struct uart_8250_port *up)
404{
405 if (up->port.type == PORT_RSA) {
406 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
407 spin_lock_irq(&up->port.lock);
408 __enable_rsa(up);
409 spin_unlock_irq(&up->port.lock);
410 }
411 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
412 serial_outp(up, UART_RSA_FRR, 0);
413 }
414}
415
416/*
417 * Attempts to turn off the RSA FIFO. Returns zero on failure.
418 * It is unknown why interrupts were disabled in here. However,
419 * the caller is expected to preserve this behaviour by grabbing
420 * the spinlock before calling this function.
421 */
422static void disable_rsa(struct uart_8250_port *up)
423{
424 unsigned char mode;
425 int result;
426
427 if (up->port.type == PORT_RSA &&
428 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
429 spin_lock_irq(&up->port.lock);
430
431 mode = serial_inp(up, UART_RSA_MSR);
432 result = !(mode & UART_RSA_MSR_FIFO);
433
434 if (!result) {
435 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
436 mode = serial_inp(up, UART_RSA_MSR);
437 result = !(mode & UART_RSA_MSR_FIFO);
438 }
439
440 if (result)
441 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
442 spin_unlock_irq(&up->port.lock);
443 }
444}
445#endif /* CONFIG_SERIAL_8250_RSA */
446
447/*
448 * This is a quickie test to see how big the FIFO is.
449 * It doesn't work at all the time, more's the pity.
450 */
451static int size_fifo(struct uart_8250_port *up)
452{
453 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
454 int count;
455
456 old_lcr = serial_inp(up, UART_LCR);
457 serial_outp(up, UART_LCR, 0);
458 old_fcr = serial_inp(up, UART_FCR);
459 old_mcr = serial_inp(up, UART_MCR);
460 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
461 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
462 serial_outp(up, UART_MCR, UART_MCR_LOOP);
463 serial_outp(up, UART_LCR, UART_LCR_DLAB);
464 old_dll = serial_inp(up, UART_DLL);
465 old_dlm = serial_inp(up, UART_DLM);
466 serial_outp(up, UART_DLL, 0x01);
467 serial_outp(up, UART_DLM, 0x00);
468 serial_outp(up, UART_LCR, 0x03);
469 for (count = 0; count < 256; count++)
470 serial_outp(up, UART_TX, count);
471 mdelay(20);/* FIXME - schedule_timeout */
472 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
473 (count < 256); count++)
474 serial_inp(up, UART_RX);
475 serial_outp(up, UART_FCR, old_fcr);
476 serial_outp(up, UART_MCR, old_mcr);
477 serial_outp(up, UART_LCR, UART_LCR_DLAB);
478 serial_outp(up, UART_DLL, old_dll);
479 serial_outp(up, UART_DLM, old_dlm);
480 serial_outp(up, UART_LCR, old_lcr);
481
482 return count;
483}
484
485/*
486 * Read UART ID using the divisor method - set DLL and DLM to zero
487 * and the revision will be in DLL and device type in DLM. We
488 * preserve the device state across this.
489 */
490static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
491{
492 unsigned char old_dll, old_dlm, old_lcr;
493 unsigned int id;
494
495 old_lcr = serial_inp(p, UART_LCR);
496 serial_outp(p, UART_LCR, UART_LCR_DLAB);
497
498 old_dll = serial_inp(p, UART_DLL);
499 old_dlm = serial_inp(p, UART_DLM);
500
501 serial_outp(p, UART_DLL, 0);
502 serial_outp(p, UART_DLM, 0);
503
504 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
505
506 serial_outp(p, UART_DLL, old_dll);
507 serial_outp(p, UART_DLM, old_dlm);
508 serial_outp(p, UART_LCR, old_lcr);
509
510 return id;
511}
512
513/*
514 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
515 * When this function is called we know it is at least a StarTech
516 * 16650 V2, but it might be one of several StarTech UARTs, or one of
517 * its clones. (We treat the broken original StarTech 16650 V1 as a
518 * 16550, and why not? Startech doesn't seem to even acknowledge its
519 * existence.)
520 *
521 * What evil have men's minds wrought...
522 */
523static void autoconfig_has_efr(struct uart_8250_port *up)
524{
525 unsigned int id1, id2, id3, rev;
526
527 /*
528 * Everything with an EFR has SLEEP
529 */
530 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
531
532 /*
533 * First we check to see if it's an Oxford Semiconductor UART.
534 *
535 * If we have to do this here because some non-National
536 * Semiconductor clone chips lock up if you try writing to the
537 * LSR register (which serial_icr_read does)
538 */
539
540 /*
541 * Check for Oxford Semiconductor 16C950.
542 *
543 * EFR [4] must be set else this test fails.
544 *
545 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
546 * claims that it's needed for 952 dual UART's (which are not
547 * recommended for new designs).
548 */
549 up->acr = 0;
550 serial_out(up, UART_LCR, 0xBF);
551 serial_out(up, UART_EFR, UART_EFR_ECB);
552 serial_out(up, UART_LCR, 0x00);
553 id1 = serial_icr_read(up, UART_ID1);
554 id2 = serial_icr_read(up, UART_ID2);
555 id3 = serial_icr_read(up, UART_ID3);
556 rev = serial_icr_read(up, UART_REV);
557
558 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
559
560 if (id1 == 0x16 && id2 == 0xC9 &&
561 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
562 up->port.type = PORT_16C950;
563 up->rev = rev | (id3 << 8);
564 return;
565 }
566
567 /*
568 * We check for a XR16C850 by setting DLL and DLM to 0, and then
569 * reading back DLL and DLM. The chip type depends on the DLM
570 * value read back:
571 * 0x10 - XR16C850 and the DLL contains the chip revision.
572 * 0x12 - XR16C2850.
573 * 0x14 - XR16C854.
574 */
575 id1 = autoconfig_read_divisor_id(up);
576 DEBUG_AUTOCONF("850id=%04x ", id1);
577
578 id2 = id1 >> 8;
579 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
580 if (id2 == 0x10)
581 up->rev = id1 & 255;
582 up->port.type = PORT_16850;
583 return;
584 }
585
586 /*
587 * It wasn't an XR16C850.
588 *
589 * We distinguish between the '654 and the '650 by counting
590 * how many bytes are in the FIFO. I'm using this for now,
591 * since that's the technique that was sent to me in the
592 * serial driver update, but I'm not convinced this works.
593 * I've had problems doing this in the past. -TYT
594 */
595 if (size_fifo(up) == 64)
596 up->port.type = PORT_16654;
597 else
598 up->port.type = PORT_16650V2;
599}
600
601/*
602 * We detected a chip without a FIFO. Only two fall into
603 * this category - the original 8250 and the 16450. The
604 * 16450 has a scratch register (accessible with LCR=0)
605 */
606static void autoconfig_8250(struct uart_8250_port *up)
607{
608 unsigned char scratch, status1, status2;
609
610 up->port.type = PORT_8250;
611
612 scratch = serial_in(up, UART_SCR);
613 serial_outp(up, UART_SCR, 0xa5);
614 status1 = serial_in(up, UART_SCR);
615 serial_outp(up, UART_SCR, 0x5a);
616 status2 = serial_in(up, UART_SCR);
617 serial_outp(up, UART_SCR, scratch);
618
619 if (status1 == 0xa5 && status2 == 0x5a)
620 up->port.type = PORT_16450;
621}
622
623static int broken_efr(struct uart_8250_port *up)
624{
625 /*
626 * Exar ST16C2550 "A2" devices incorrectly detect as
627 * having an EFR, and report an ID of 0x0201. See
628 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
629 */
630 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
631 return 1;
632
633 return 0;
634}
635
636/*
637 * We know that the chip has FIFOs. Does it have an EFR? The
638 * EFR is located in the same register position as the IIR and
639 * we know the top two bits of the IIR are currently set. The
640 * EFR should contain zero. Try to read the EFR.
641 */
642static void autoconfig_16550a(struct uart_8250_port *up)
643{
644 unsigned char status1, status2;
645 unsigned int iersave;
646
647 up->port.type = PORT_16550A;
648 up->capabilities |= UART_CAP_FIFO;
649
650 /*
651 * Check for presence of the EFR when DLAB is set.
652 * Only ST16C650V1 UARTs pass this test.
653 */
654 serial_outp(up, UART_LCR, UART_LCR_DLAB);
655 if (serial_in(up, UART_EFR) == 0) {
656 serial_outp(up, UART_EFR, 0xA8);
657 if (serial_in(up, UART_EFR) != 0) {
658 DEBUG_AUTOCONF("EFRv1 ");
659 up->port.type = PORT_16650;
660 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
661 } else {
662 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
663 }
664 serial_outp(up, UART_EFR, 0);
665 return;
666 }
667
668 /*
669 * Maybe it requires 0xbf to be written to the LCR.
670 * (other ST16C650V2 UARTs, TI16C752A, etc)
671 */
672 serial_outp(up, UART_LCR, 0xBF);
673 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
674 DEBUG_AUTOCONF("EFRv2 ");
675 autoconfig_has_efr(up);
676 return;
677 }
678
679 /*
680 * Check for a National Semiconductor SuperIO chip.
681 * Attempt to switch to bank 2, read the value of the LOOP bit
682 * from EXCR1. Switch back to bank 0, change it in MCR. Then
683 * switch back to bank 2, read it from EXCR1 again and check
684 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
685 * On PowerPC we don't want to change baud_base, as we have
686 * a number of different divisors. -- Tom Rini
687 */
688 serial_outp(up, UART_LCR, 0);
689 status1 = serial_in(up, UART_MCR);
690 serial_outp(up, UART_LCR, 0xE0);
691 status2 = serial_in(up, 0x02); /* EXCR1 */
692
693 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
694 serial_outp(up, UART_LCR, 0);
695 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
696 serial_outp(up, UART_LCR, 0xE0);
697 status2 = serial_in(up, 0x02); /* EXCR1 */
698 serial_outp(up, UART_LCR, 0);
699 serial_outp(up, UART_MCR, status1);
700
701 if ((status2 ^ status1) & UART_MCR_LOOP) {
702#ifndef CONFIG_PPC
703 serial_outp(up, UART_LCR, 0xE0);
704 status1 = serial_in(up, 0x04); /* EXCR1 */
705 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
706 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
707 serial_outp(up, 0x04, status1);
708 serial_outp(up, UART_LCR, 0);
709 up->port.uartclk = 921600*16;
710#endif
711
712 up->port.type = PORT_NS16550A;
713 up->capabilities |= UART_NATSEMI;
714 return;
715 }
716 }
717
718 /*
719 * No EFR. Try to detect a TI16750, which only sets bit 5 of
720 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
721 * Try setting it with and without DLAB set. Cheap clones
722 * set bit 5 without DLAB set.
723 */
724 serial_outp(up, UART_LCR, 0);
725 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
726 status1 = serial_in(up, UART_IIR) >> 5;
727 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
728 serial_outp(up, UART_LCR, UART_LCR_DLAB);
729 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
730 status2 = serial_in(up, UART_IIR) >> 5;
731 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
732 serial_outp(up, UART_LCR, 0);
733
734 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
735
736 if (status1 == 6 && status2 == 7) {
737 up->port.type = PORT_16750;
738 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
739 return;
740 }
741
742 /*
743 * Try writing and reading the UART_IER_UUE bit (b6).
744 * If it works, this is probably one of the Xscale platform's
745 * internal UARTs.
746 * We're going to explicitly set the UUE bit to 0 before
747 * trying to write and read a 1 just to make sure it's not
748 * already a 1 and maybe locked there before we even start start.
749 */
750 iersave = serial_in(up, UART_IER);
751 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
752 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
753 /*
754 * OK it's in a known zero state, try writing and reading
755 * without disturbing the current state of the other bits.
756 */
757 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
758 if (serial_in(up, UART_IER) & UART_IER_UUE) {
759 /*
760 * It's an Xscale.
761 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
762 */
763 DEBUG_AUTOCONF("Xscale ");
764 up->port.type = PORT_XSCALE;
765 up->capabilities |= UART_CAP_UUE;
766 return;
767 }
768 } else {
769 /*
770 * If we got here we couldn't force the IER_UUE bit to 0.
771 * Log it and continue.
772 */
773 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
774 }
775 serial_outp(up, UART_IER, iersave);
776}
777
778/*
779 * This routine is called by rs_init() to initialize a specific serial
780 * port. It determines what type of UART chip this serial port is
781 * using: 8250, 16450, 16550, 16550A. The important question is
782 * whether or not this UART is a 16550A or not, since this will
783 * determine whether or not we can use its FIFO features or not.
784 */
785static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
786{
787 unsigned char status1, scratch, scratch2, scratch3;
788 unsigned char save_lcr, save_mcr;
789 unsigned long flags;
790
791 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
792 return;
793
794 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
795 up->port.line, up->port.iobase, up->port.membase);
796
797 /*
798 * We really do need global IRQs disabled here - we're going to
799 * be frobbing the chips IRQ enable register to see if it exists.
800 */
801 spin_lock_irqsave(&up->port.lock, flags);
802// save_flags(flags); cli();
803
804 up->capabilities = 0;
805
806 if (!(up->port.flags & UPF_BUGGY_UART)) {
807 /*
808 * Do a simple existence test first; if we fail this,
809 * there's no point trying anything else.
810 *
811 * 0x80 is used as a nonsense port to prevent against
812 * false positives due to ISA bus float. The
813 * assumption is that 0x80 is a non-existent port;
814 * which should be safe since include/asm/io.h also
815 * makes this assumption.
816 *
817 * Note: this is safe as long as MCR bit 4 is clear
818 * and the device is in "PC" mode.
819 */
820 scratch = serial_inp(up, UART_IER);
821 serial_outp(up, UART_IER, 0);
822#ifdef __i386__
823 outb(0xff, 0x080);
824#endif
825 scratch2 = serial_inp(up, UART_IER);
826 serial_outp(up, UART_IER, 0x0F);
827#ifdef __i386__
828 outb(0, 0x080);
829#endif
830 scratch3 = serial_inp(up, UART_IER);
831 serial_outp(up, UART_IER, scratch);
832 if (scratch2 != 0 || scratch3 != 0x0F) {
833 /*
834 * We failed; there's nothing here
835 */
836 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
837 scratch2, scratch3);
838 goto out;
839 }
840 }
841
842 save_mcr = serial_in(up, UART_MCR);
843 save_lcr = serial_in(up, UART_LCR);
844
845 /*
846 * Check to see if a UART is really there. Certain broken
847 * internal modems based on the Rockwell chipset fail this
848 * test, because they apparently don't implement the loopback
849 * test mode. So this test is skipped on the COM 1 through
850 * COM 4 ports. This *should* be safe, since no board
851 * manufacturer would be stupid enough to design a board
852 * that conflicts with COM 1-4 --- we hope!
853 */
854 if (!(up->port.flags & UPF_SKIP_TEST)) {
855 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
856 status1 = serial_inp(up, UART_MSR) & 0xF0;
857 serial_outp(up, UART_MCR, save_mcr);
858 if (status1 != 0x90) {
859 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
860 status1);
861 goto out;
862 }
863 }
864
865 /*
866 * We're pretty sure there's a port here. Lets find out what
867 * type of port it is. The IIR top two bits allows us to find
868 * out if its 8250 or 16450, 16550, 16550A or later. This
869 * determines what we test for next.
870 *
871 * We also initialise the EFR (if any) to zero for later. The
872 * EFR occupies the same register location as the FCR and IIR.
873 */
874 serial_outp(up, UART_LCR, 0xBF);
875 serial_outp(up, UART_EFR, 0);
876 serial_outp(up, UART_LCR, 0);
877
878 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
879 scratch = serial_in(up, UART_IIR) >> 6;
880
881 DEBUG_AUTOCONF("iir=%d ", scratch);
882
883 switch (scratch) {
884 case 0:
885 autoconfig_8250(up);
886 break;
887 case 1:
888 up->port.type = PORT_UNKNOWN;
889 break;
890 case 2:
891 up->port.type = PORT_16550;
892 break;
893 case 3:
894 autoconfig_16550a(up);
895 break;
896 }
897
898#ifdef CONFIG_SERIAL_8250_RSA
899 /*
900 * Only probe for RSA ports if we got the region.
901 */
902 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
903 int i;
904
905 for (i = 0 ; i < probe_rsa_count; ++i) {
906 if (probe_rsa[i] == up->port.iobase &&
907 __enable_rsa(up)) {
908 up->port.type = PORT_RSA;
909 break;
910 }
911 }
912 }
913#endif
914 serial_outp(up, UART_LCR, save_lcr);
915
916 if (up->capabilities != uart_config[up->port.type].flags) {
917 printk(KERN_WARNING
918 "ttyS%d: detected caps %08x should be %08x\n",
919 up->port.line, up->capabilities,
920 uart_config[up->port.type].flags);
921 }
922
923 up->port.fifosize = uart_config[up->port.type].fifo_size;
924 up->capabilities = uart_config[up->port.type].flags;
925 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
926
927 if (up->port.type == PORT_UNKNOWN)
928 goto out;
929
930 /*
931 * Reset the UART.
932 */
933#ifdef CONFIG_SERIAL_8250_RSA
934 if (up->port.type == PORT_RSA)
935 serial_outp(up, UART_RSA_FRR, 0);
936#endif
937 serial_outp(up, UART_MCR, save_mcr);
938 serial8250_clear_fifos(up);
939 (void)serial_in(up, UART_RX);
940 serial_outp(up, UART_IER, 0);
941
942 out:
943 spin_unlock_irqrestore(&up->port.lock, flags);
944// restore_flags(flags);
945 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
946}
947
948static void autoconfig_irq(struct uart_8250_port *up)
949{
950 unsigned char save_mcr, save_ier;
951 unsigned char save_ICP = 0;
952 unsigned int ICP = 0;
953 unsigned long irqs;
954 int irq;
955
956 if (up->port.flags & UPF_FOURPORT) {
957 ICP = (up->port.iobase & 0xfe0) | 0x1f;
958 save_ICP = inb_p(ICP);
959 outb_p(0x80, ICP);
960 (void) inb_p(ICP);
961 }
962
963 /* forget possible initially masked and pending IRQ */
964 probe_irq_off(probe_irq_on());
965 save_mcr = serial_inp(up, UART_MCR);
966 save_ier = serial_inp(up, UART_IER);
967 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
968
969 irqs = probe_irq_on();
970 serial_outp(up, UART_MCR, 0);
971 udelay (10);
972 if (up->port.flags & UPF_FOURPORT) {
973 serial_outp(up, UART_MCR,
974 UART_MCR_DTR | UART_MCR_RTS);
975 } else {
976 serial_outp(up, UART_MCR,
977 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
978 }
979 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
980 (void)serial_inp(up, UART_LSR);
981 (void)serial_inp(up, UART_RX);
982 (void)serial_inp(up, UART_IIR);
983 (void)serial_inp(up, UART_MSR);
984 serial_outp(up, UART_TX, 0xFF);
985 udelay (20);
986 irq = probe_irq_off(irqs);
987
988 serial_outp(up, UART_MCR, save_mcr);
989 serial_outp(up, UART_IER, save_ier);
990
991 if (up->port.flags & UPF_FOURPORT)
992 outb_p(save_ICP, ICP);
993
994 up->port.irq = (irq > 0) ? irq : 0;
995}
996
997static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop)
998{
999 struct uart_8250_port *up = (struct uart_8250_port *)port;
1000
1001 if (up->ier & UART_IER_THRI) {
1002 up->ier &= ~UART_IER_THRI;
1003 serial_out(up, UART_IER, up->ier);
1004 }
1005
1006 /*
1007 * We only do this from uart_stop - if we run out of
1008 * characters to send, we don't want to prevent the
1009 * FIFO from emptying.
1010 */
1011 if (up->port.type == PORT_16C950 && tty_stop) {
1012 up->acr |= UART_ACR_TXDIS;
1013 serial_icr_write(up, UART_ACR, up->acr);
1014 }
1015}
1016
1017static void serial8250_start_tx(struct uart_port *port, unsigned int tty_start)
1018{
1019 struct uart_8250_port *up = (struct uart_8250_port *)port;
1020
1021 if (!(up->ier & UART_IER_THRI)) {
1022 up->ier |= UART_IER_THRI;
1023 serial_out(up, UART_IER, up->ier);
1024 }
1025 /*
1026 * We only do this from uart_start
1027 */
1028 if (tty_start && up->port.type == PORT_16C950) {
1029 up->acr &= ~UART_ACR_TXDIS;
1030 serial_icr_write(up, UART_ACR, up->acr);
1031 }
1032}
1033
1034static void serial8250_stop_rx(struct uart_port *port)
1035{
1036 struct uart_8250_port *up = (struct uart_8250_port *)port;
1037
1038 up->ier &= ~UART_IER_RLSI;
1039 up->port.read_status_mask &= ~UART_LSR_DR;
1040 serial_out(up, UART_IER, up->ier);
1041}
1042
1043static void serial8250_enable_ms(struct uart_port *port)
1044{
1045 struct uart_8250_port *up = (struct uart_8250_port *)port;
1046
1047 up->ier |= UART_IER_MSI;
1048 serial_out(up, UART_IER, up->ier);
1049}
1050
1051static _INLINE_ void
1052receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1053{
1054 struct tty_struct *tty = up->port.info->tty;
1055 unsigned char ch, lsr = *status;
1056 int max_count = 256;
1057 char flag;
1058
1059 do {
1060 /* The following is not allowed by the tty layer and
1061 unsafe. It should be fixed ASAP */
1062 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1063 if (tty->low_latency) {
1064 spin_unlock(&up->port.lock);
1065 tty_flip_buffer_push(tty);
1066 spin_lock(&up->port.lock);
1067 }
23907eb8
RK		 1068 /*
1069 * If this failed then we will throw away the
1070 * bytes but must do so to clear interrupts
1071 */
1da177e4
LT		 1072 }
1073 ch = serial_inp(up, UART_RX);
1074 flag = TTY_NORMAL;
1075 up->port.icount.rx++;
1076
1077#ifdef CONFIG_SERIAL_8250_CONSOLE
1078 /*
1079 * Recover the break flag from console xmit
1080 */
1081 if (up->port.line == up->port.cons->index) {
1082 lsr |= up->lsr_break_flag;
1083 up->lsr_break_flag = 0;
1084 }
1085#endif
1086
1087 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1088 UART_LSR_FE | UART_LSR_OE))) {
1089 /*
1090 * For statistics only
1091 */
1092 if (lsr & UART_LSR_BI) {
1093 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1094 up->port.icount.brk++;
1095 /*
1096 * We do the SysRQ and SAK checking
1097 * here because otherwise the break
1098 * may get masked by ignore_status_mask
1099 * or read_status_mask.
1100 */
1101 if (uart_handle_break(&up->port))
1102 goto ignore_char;
1103 } else if (lsr & UART_LSR_PE)
1104 up->port.icount.parity++;
1105 else if (lsr & UART_LSR_FE)
1106 up->port.icount.frame++;
1107 if (lsr & UART_LSR_OE)
1108 up->port.icount.overrun++;
1109
1110 /*
23907eb8 1111 * Mask off conditions which should be ignored.
1da177e4
LT		 1112 */
1113 lsr &= up->port.read_status_mask;
1114
1115 if (lsr & UART_LSR_BI) {
1116 DEBUG_INTR("handling break....");
1117 flag = TTY_BREAK;
1118 } else if (lsr & UART_LSR_PE)
1119 flag = TTY_PARITY;
1120 else if (lsr & UART_LSR_FE)
1121 flag = TTY_FRAME;
1122 }
1123 if (uart_handle_sysrq_char(&up->port, ch, regs))
1124 goto ignore_char;
1125 if ((lsr & up->port.ignore_status_mask) == 0) {
1126 tty_insert_flip_char(tty, ch, flag);
1127 }
1128 if ((lsr & UART_LSR_OE) &&
1129 tty->flip.count < TTY_FLIPBUF_SIZE) {
1130 /*
1131 * Overrun is special, since it's reported
1132 * immediately, and doesn't affect the current
1133 * character.
1134 */
1135 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
1136 }
1137 ignore_char:
1138 lsr = serial_inp(up, UART_LSR);
1139 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1140 spin_unlock(&up->port.lock);
1141 tty_flip_buffer_push(tty);
1142 spin_lock(&up->port.lock);
1143 *status = lsr;
1144}
1145
1146static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1147{
1148 struct circ_buf *xmit = &up->port.info->xmit;
1149 int count;
1150
1151 if (up->port.x_char) {
1152 serial_outp(up, UART_TX, up->port.x_char);
1153 up->port.icount.tx++;
1154 up->port.x_char = 0;
1155 return;
1156 }
1157 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
1158 serial8250_stop_tx(&up->port, 0);
1159 return;
1160 }
1161
1162 count = up->tx_loadsz;
1163 do {
1164 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1165 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1166 up->port.icount.tx++;
1167 if (uart_circ_empty(xmit))
1168 break;
1169 } while (--count > 0);
1170
1171 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1172 uart_write_wakeup(&up->port);
1173
1174 DEBUG_INTR("THRE...");
1175
1176 if (uart_circ_empty(xmit))
1177 serial8250_stop_tx(&up->port, 0);
1178}
1179
1180static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1181{
1182 int status;
1183
1184 status = serial_in(up, UART_MSR);
1185
1186 if ((status & UART_MSR_ANY_DELTA) == 0)
1187 return;
1188
1189 if (status & UART_MSR_TERI)
1190 up->port.icount.rng++;
1191 if (status & UART_MSR_DDSR)
1192 up->port.icount.dsr++;
1193 if (status & UART_MSR_DDCD)
1194 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1195 if (status & UART_MSR_DCTS)
1196 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1197
1198 wake_up_interruptible(&up->port.info->delta_msr_wait);
1199}
1200
1201/*
1202 * This handles the interrupt from one port.
1203 */
1204static inline void
1205serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1206{
1207 unsigned int status = serial_inp(up, UART_LSR);
1208
1209 DEBUG_INTR("status = %x...", status);
1210
1211 if (status & UART_LSR_DR)
1212 receive_chars(up, &status, regs);
1213 check_modem_status(up);
1214 if (status & UART_LSR_THRE)
1215 transmit_chars(up);
1216}
1217
1218/*
1219 * This is the serial driver's interrupt routine.
1220 *
1221 * Arjan thinks the old way was overly complex, so it got simplified.
1222 * Alan disagrees, saying that need the complexity to handle the weird
1223 * nature of ISA shared interrupts. (This is a special exception.)
1224 *
1225 * In order to handle ISA shared interrupts properly, we need to check
1226 * that all ports have been serviced, and therefore the ISA interrupt
1227 * line has been de-asserted.
1228 *
1229 * This means we need to loop through all ports. checking that they
1230 * don't have an interrupt pending.
1231 */
1232static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1233{
1234 struct irq_info *i = dev_id;
1235 struct list_head *l, *end = NULL;
1236 int pass_counter = 0, handled = 0;
1237
1238 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1239
1240 spin_lock(&i->lock);
1241
1242 l = i->head;
1243 do {
1244 struct uart_8250_port *up;
1245 unsigned int iir;
1246
1247 up = list_entry(l, struct uart_8250_port, list);
1248
1249 iir = serial_in(up, UART_IIR);
1250 if (!(iir & UART_IIR_NO_INT)) {
1251 spin_lock(&up->port.lock);
1252 serial8250_handle_port(up, regs);
1253 spin_unlock(&up->port.lock);
1254
1255 handled = 1;
1256
1257 end = NULL;
1258 } else if (end == NULL)
1259 end = l;
1260
1261 l = l->next;
1262
1263 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1264 /* If we hit this, we're dead. */
1265 printk(KERN_ERR "serial8250: too much work for "
1266 "irq%d\n", irq);
1267 break;
1268 }
1269 } while (l != end);
1270
1271 spin_unlock(&i->lock);
1272
1273 DEBUG_INTR("end.\n");
1274
1275 return IRQ_RETVAL(handled);
1276}
1277
1278/*
1279 * To support ISA shared interrupts, we need to have one interrupt
1280 * handler that ensures that the IRQ line has been deasserted
1281 * before returning. Failing to do this will result in the IRQ
1282 * line being stuck active, and, since ISA irqs are edge triggered,
1283 * no more IRQs will be seen.
1284 */
1285static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1286{
1287 spin_lock_irq(&i->lock);
1288
1289 if (!list_empty(i->head)) {
1290 if (i->head == &up->list)
1291 i->head = i->head->next;
1292 list_del(&up->list);
1293 } else {
1294 BUG_ON(i->head != &up->list);
1295 i->head = NULL;
1296 }
1297
1298 spin_unlock_irq(&i->lock);
1299}
1300
1301static int serial_link_irq_chain(struct uart_8250_port *up)
1302{
1303 struct irq_info *i = irq_lists + up->port.irq;
1304 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1305
1306 spin_lock_irq(&i->lock);
1307
1308 if (i->head) {
1309 list_add(&up->list, i->head);
1310 spin_unlock_irq(&i->lock);
1311
1312 ret = 0;
1313 } else {
1314 INIT_LIST_HEAD(&up->list);
1315 i->head = &up->list;
1316 spin_unlock_irq(&i->lock);
1317
1318 ret = request_irq(up->port.irq, serial8250_interrupt,
1319 irq_flags, "serial", i);
1320 if (ret < 0)
1321 serial_do_unlink(i, up);
1322 }
1323
1324 return ret;
1325}
1326
1327static void serial_unlink_irq_chain(struct uart_8250_port *up)
1328{
1329 struct irq_info *i = irq_lists + up->port.irq;
1330
1331 BUG_ON(i->head == NULL);
1332
1333 if (list_empty(i->head))
1334 free_irq(up->port.irq, i);
1335
1336 serial_do_unlink(i, up);
1337}
1338
1339/*
1340 * This function is used to handle ports that do not have an
1341 * interrupt. This doesn't work very well for 16450's, but gives
1342 * barely passable results for a 16550A. (Although at the expense
1343 * of much CPU overhead).
1344 */
1345static void serial8250_timeout(unsigned long data)
1346{
1347 struct uart_8250_port *up = (struct uart_8250_port *)data;
1348 unsigned int timeout;
1349 unsigned int iir;
1350
1351 iir = serial_in(up, UART_IIR);
1352 if (!(iir & UART_IIR_NO_INT)) {
1353 spin_lock(&up->port.lock);
1354 serial8250_handle_port(up, NULL);
1355 spin_unlock(&up->port.lock);
1356 }
1357
1358 timeout = up->port.timeout;
1359 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1360 mod_timer(&up->timer, jiffies + timeout);
1361}
1362
1363static unsigned int serial8250_tx_empty(struct uart_port *port)
1364{
1365 struct uart_8250_port *up = (struct uart_8250_port *)port;
1366 unsigned long flags;
1367 unsigned int ret;
1368
1369 spin_lock_irqsave(&up->port.lock, flags);
1370 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1371 spin_unlock_irqrestore(&up->port.lock, flags);
1372
1373 return ret;
1374}
1375
1376static unsigned int serial8250_get_mctrl(struct uart_port *port)
1377{
1378 struct uart_8250_port *up = (struct uart_8250_port *)port;
1379 unsigned long flags;
1380 unsigned char status;
1381 unsigned int ret;
1382
1383 spin_lock_irqsave(&up->port.lock, flags);
1384 status = serial_in(up, UART_MSR);
1385 spin_unlock_irqrestore(&up->port.lock, flags);
1386
1387 ret = 0;
1388 if (status & UART_MSR_DCD)
1389 ret |= TIOCM_CAR;
1390 if (status & UART_MSR_RI)
1391 ret |= TIOCM_RNG;
1392 if (status & UART_MSR_DSR)
1393 ret |= TIOCM_DSR;
1394 if (status & UART_MSR_CTS)
1395 ret |= TIOCM_CTS;
1396 return ret;
1397}
1398
1399static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1400{
1401 struct uart_8250_port *up = (struct uart_8250_port *)port;
1402 unsigned char mcr = 0;
1403
1404 if (mctrl & TIOCM_RTS)
1405 mcr |= UART_MCR_RTS;
1406 if (mctrl & TIOCM_DTR)
1407 mcr |= UART_MCR_DTR;
1408 if (mctrl & TIOCM_OUT1)
1409 mcr |= UART_MCR_OUT1;
1410 if (mctrl & TIOCM_OUT2)
1411 mcr |= UART_MCR_OUT2;
1412 if (mctrl & TIOCM_LOOP)
1413 mcr |= UART_MCR_LOOP;
1414
1415 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1416
1417 serial_out(up, UART_MCR, mcr);
1418}
1419
1420static void serial8250_break_ctl(struct uart_port *port, int break_state)
1421{
1422 struct uart_8250_port *up = (struct uart_8250_port *)port;
1423 unsigned long flags;
1424
1425 spin_lock_irqsave(&up->port.lock, flags);
1426 if (break_state == -1)
1427 up->lcr |= UART_LCR_SBC;
1428 else
1429 up->lcr &= ~UART_LCR_SBC;
1430 serial_out(up, UART_LCR, up->lcr);
1431 spin_unlock_irqrestore(&up->port.lock, flags);
1432}
1433
1434static int serial8250_startup(struct uart_port *port)
1435{
1436 struct uart_8250_port *up = (struct uart_8250_port *)port;
1437 unsigned long flags;
1438 int retval;
1439
1440 up->capabilities = uart_config[up->port.type].flags;
1441 up->mcr = 0;
1442
1443 if (up->port.type == PORT_16C950) {
1444 /* Wake up and initialize UART */
1445 up->acr = 0;
1446 serial_outp(up, UART_LCR, 0xBF);
1447 serial_outp(up, UART_EFR, UART_EFR_ECB);
1448 serial_outp(up, UART_IER, 0);
1449 serial_outp(up, UART_LCR, 0);
1450 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1451 serial_outp(up, UART_LCR, 0xBF);
1452 serial_outp(up, UART_EFR, UART_EFR_ECB);
1453 serial_outp(up, UART_LCR, 0);
1454 }
1455
1456#ifdef CONFIG_SERIAL_8250_RSA
1457 /*
1458 * If this is an RSA port, see if we can kick it up to the
1459 * higher speed clock.
1460 */
1461 enable_rsa(up);
1462#endif
1463
1464 /*
1465 * Clear the FIFO buffers and disable them.
1466 * (they will be reeanbled in set_termios())
1467 */
1468 serial8250_clear_fifos(up);
1469
1470 /*
1471 * Clear the interrupt registers.
1472 */
1473 (void) serial_inp(up, UART_LSR);
1474 (void) serial_inp(up, UART_RX);
1475 (void) serial_inp(up, UART_IIR);
1476 (void) serial_inp(up, UART_MSR);
1477
1478 /*
1479 * At this point, there's no way the LSR could still be 0xff;
1480 * if it is, then bail out, because there's likely no UART
1481 * here.
1482 */
1483 if (!(up->port.flags & UPF_BUGGY_UART) &&
1484 (serial_inp(up, UART_LSR) == 0xff)) {
1485 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1486 return -ENODEV;
1487 }
1488
1489 /*
1490 * For a XR16C850, we need to set the trigger levels
1491 */
1492 if (up->port.type == PORT_16850) {
1493 unsigned char fctr;
1494
1495 serial_outp(up, UART_LCR, 0xbf);
1496
1497 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1498 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1499 serial_outp(up, UART_TRG, UART_TRG_96);
1500 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1501 serial_outp(up, UART_TRG, UART_TRG_96);
1502
1503 serial_outp(up, UART_LCR, 0);
1504 }
1505
1506 /*
1507 * If the "interrupt" for this port doesn't correspond with any
1508 * hardware interrupt, we use a timer-based system. The original
1509 * driver used to do this with IRQ0.
1510 */
1511 if (!is_real_interrupt(up->port.irq)) {
1512 unsigned int timeout = up->port.timeout;
1513
1514 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1515
1516 up->timer.data = (unsigned long)up;
1517 mod_timer(&up->timer, jiffies + timeout);
1518 } else {
1519 retval = serial_link_irq_chain(up);
1520 if (retval)
1521 return retval;
1522 }
1523
1524 /*
1525 * Now, initialize the UART
1526 */
1527 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1528
1529 spin_lock_irqsave(&up->port.lock, flags);
1530 if (up->port.flags & UPF_FOURPORT) {
1531 if (!is_real_interrupt(up->port.irq))
1532 up->port.mctrl |= TIOCM_OUT1;
1533 } else
1534 /*
1535 * Most PC uarts need OUT2 raised to enable interrupts.
1536 */
1537 if (is_real_interrupt(up->port.irq))
1538 up->port.mctrl |= TIOCM_OUT2;
1539
1540 serial8250_set_mctrl(&up->port, up->port.mctrl);
1541 spin_unlock_irqrestore(&up->port.lock, flags);
1542
1543 /*
1544 * Finally, enable interrupts. Note: Modem status interrupts
1545 * are set via set_termios(), which will be occurring imminently
1546 * anyway, so we don't enable them here.
1547 */
1548 up->ier = UART_IER_RLSI | UART_IER_RDI;
1549 serial_outp(up, UART_IER, up->ier);
1550
1551 if (up->port.flags & UPF_FOURPORT) {
1552 unsigned int icp;
1553 /*
1554 * Enable interrupts on the AST Fourport board
1555 */
1556 icp = (up->port.iobase & 0xfe0) | 0x01f;
1557 outb_p(0x80, icp);
1558 (void) inb_p(icp);
1559 }
1560
1561 /*
1562 * And clear the interrupt registers again for luck.
1563 */
1564 (void) serial_inp(up, UART_LSR);
1565 (void) serial_inp(up, UART_RX);
1566 (void) serial_inp(up, UART_IIR);
1567 (void) serial_inp(up, UART_MSR);
1568
1569 return 0;
1570}
1571
1572static void serial8250_shutdown(struct uart_port *port)
1573{
1574 struct uart_8250_port *up = (struct uart_8250_port *)port;
1575 unsigned long flags;
1576
1577 /*
1578 * Disable interrupts from this port
1579 */
1580 up->ier = 0;
1581 serial_outp(up, UART_IER, 0);
1582
1583 spin_lock_irqsave(&up->port.lock, flags);
1584 if (up->port.flags & UPF_FOURPORT) {
1585 /* reset interrupts on the AST Fourport board */
1586 inb((up->port.iobase & 0xfe0) | 0x1f);
1587 up->port.mctrl |= TIOCM_OUT1;
1588 } else
1589 up->port.mctrl &= ~TIOCM_OUT2;
1590
1591 serial8250_set_mctrl(&up->port, up->port.mctrl);
1592 spin_unlock_irqrestore(&up->port.lock, flags);
1593
1594 /*
1595 * Disable break condition and FIFOs
1596 */
1597 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1598 serial8250_clear_fifos(up);
1599
1600#ifdef CONFIG_SERIAL_8250_RSA
1601 /*
1602 * Reset the RSA board back to 115kbps compat mode.
1603 */
1604 disable_rsa(up);
1605#endif
1606
1607 /*
1608 * Read data port to reset things, and then unlink from
1609 * the IRQ chain.
1610 */
1611 (void) serial_in(up, UART_RX);
1612
1613 if (!is_real_interrupt(up->port.irq))
1614 del_timer_sync(&up->timer);
1615 else
1616 serial_unlink_irq_chain(up);
1617}
1618
1619static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1620{
1621 unsigned int quot;
1622
1623 /*
1624 * Handle magic divisors for baud rates above baud_base on
1625 * SMSC SuperIO chips.
1626 */
1627 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1628 baud == (port->uartclk/4))
1629 quot = 0x8001;
1630 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1631 baud == (port->uartclk/8))
1632 quot = 0x8002;
1633 else
1634 quot = uart_get_divisor(port, baud);
1635
1636 return quot;
1637}
1638
1639static void
1640serial8250_set_termios(struct uart_port *port, struct termios *termios,
1641 struct termios *old)
1642{
1643 struct uart_8250_port *up = (struct uart_8250_port *)port;
1644 unsigned char cval, fcr = 0;
1645 unsigned long flags;
1646 unsigned int baud, quot;
1647
1648 switch (termios->c_cflag & CSIZE) {
1649 case CS5:
1650 cval = 0x00;
1651 break;
1652 case CS6:
1653 cval = 0x01;
1654 break;
1655 case CS7:
1656 cval = 0x02;
1657 break;
1658 default:
1659 case CS8:
1660 cval = 0x03;
1661 break;
1662 }
1663
1664 if (termios->c_cflag & CSTOPB)
1665 cval |= 0x04;
1666 if (termios->c_cflag & PARENB)
1667 cval |= UART_LCR_PARITY;
1668 if (!(termios->c_cflag & PARODD))
1669 cval |= UART_LCR_EPAR;
1670#ifdef CMSPAR
1671 if (termios->c_cflag & CMSPAR)
1672 cval |= UART_LCR_SPAR;
1673#endif
1674
1675 /*
1676 * Ask the core to calculate the divisor for us.
1677 */
1678 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1679 quot = serial8250_get_divisor(port, baud);
1680
1681 /*
1682 * Work around a bug in the Oxford Semiconductor 952 rev B
1683 * chip which causes it to seriously miscalculate baud rates
1684 * when DLL is 0.
1685 */
1686 if ((quot & 0xff) == 0 && up->port.type == PORT_16C950 &&
1687 up->rev == 0x5201)
1688 quot ++;
1689
1690 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1691 if (baud < 2400)
1692 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1693 else
1694 fcr = uart_config[up->port.type].fcr;
1695 }
1696
1697 /*
1698 * MCR-based auto flow control. When AFE is enabled, RTS will be
1699 * deasserted when the receive FIFO contains more characters than
1700 * the trigger, or the MCR RTS bit is cleared. In the case where
1701 * the remote UART is not using CTS auto flow control, we must
1702 * have sufficient FIFO entries for the latency of the remote
1703 * UART to respond. IOW, at least 32 bytes of FIFO.
1704 */
1705 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1706 up->mcr &= ~UART_MCR_AFE;
1707 if (termios->c_cflag & CRTSCTS)
1708 up->mcr |= UART_MCR_AFE;
1709 }
1710
1711 /*
1712 * Ok, we're now changing the port state. Do it with
1713 * interrupts disabled.
1714 */
1715 spin_lock_irqsave(&up->port.lock, flags);
1716
1717 /*
1718 * Update the per-port timeout.
1719 */
1720 uart_update_timeout(port, termios->c_cflag, baud);
1721
1722 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1723 if (termios->c_iflag & INPCK)
1724 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1725 if (termios->c_iflag & (BRKINT | PARMRK))
1726 up->port.read_status_mask |= UART_LSR_BI;
1727
1728 /*
1729 * Characteres to ignore
1730 */
1731 up->port.ignore_status_mask = 0;
1732 if (termios->c_iflag & IGNPAR)
1733 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1734 if (termios->c_iflag & IGNBRK) {
1735 up->port.ignore_status_mask |= UART_LSR_BI;
1736 /*
1737 * If we're ignoring parity and break indicators,
1738 * ignore overruns too (for real raw support).
1739 */
1740 if (termios->c_iflag & IGNPAR)
1741 up->port.ignore_status_mask |= UART_LSR_OE;
1742 }
1743
1744 /*
1745 * ignore all characters if CREAD is not set
1746 */
1747 if ((termios->c_cflag & CREAD) == 0)
1748 up->port.ignore_status_mask |= UART_LSR_DR;
1749
1750 /*
1751 * CTS flow control flag and modem status interrupts
1752 */
1753 up->ier &= ~UART_IER_MSI;
1754 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1755 up->ier |= UART_IER_MSI;
1756 if (up->capabilities & UART_CAP_UUE)
1757 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1758
1759 serial_out(up, UART_IER, up->ier);
1760
1761 if (up->capabilities & UART_CAP_EFR) {
1762 unsigned char efr = 0;
1763 /*
1764 * TI16C752/Startech hardware flow control. FIXME:
1765 * - TI16C752 requires control thresholds to be set.
1766 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1767 */
1768 if (termios->c_cflag & CRTSCTS)
1769 efr |= UART_EFR_CTS;
1770
1771 serial_outp(up, UART_LCR, 0xBF);
1772 serial_outp(up, UART_EFR, efr);
1773 }
1774
1775 if (up->capabilities & UART_NATSEMI) {
1776 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1777 serial_outp(up, UART_LCR, 0xe0);
1778 } else {
1779 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1780 }
1781
1782 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1783 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1784
1785 /*
1786 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1787 * is written without DLAB set, this mode will be disabled.
1788 */
1789 if (up->port.type == PORT_16750)
1790 serial_outp(up, UART_FCR, fcr);
1791
1792 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1793 up->lcr = cval; /* Save LCR */
1794 if (up->port.type != PORT_16750) {
1795 if (fcr & UART_FCR_ENABLE_FIFO) {
1796 /* emulated UARTs (Lucent Venus 167x) need two steps */
1797 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1798 }
1799 serial_outp(up, UART_FCR, fcr); /* set fcr */
1800 }
1801 serial8250_set_mctrl(&up->port, up->port.mctrl);
1802 spin_unlock_irqrestore(&up->port.lock, flags);
1803}
1804
1805static void
1806serial8250_pm(struct uart_port *port, unsigned int state,
1807 unsigned int oldstate)
1808{
1809 struct uart_8250_port *p = (struct uart_8250_port *)port;
1810
1811 serial8250_set_sleep(p, state != 0);
1812
1813 if (p->pm)
1814 p->pm(port, state, oldstate);
1815}
1816
1817/*
1818 * Resource handling.
1819 */
1820static int serial8250_request_std_resource(struct uart_8250_port *up)
1821{
1822 unsigned int size = 8 << up->port.regshift;
1823 int ret = 0;
1824
1825 switch (up->port.iotype) {
1826 case UPIO_MEM:
1827 if (!up->port.mapbase)
1828 break;
1829
1830 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1831 ret = -EBUSY;
1832 break;
1833 }
1834
1835 if (up->port.flags & UPF_IOREMAP) {
1836 up->port.membase = ioremap(up->port.mapbase, size);
1837 if (!up->port.membase) {
1838 release_mem_region(up->port.mapbase, size);
1839 ret = -ENOMEM;
1840 }
1841 }
1842 break;
1843
1844 case UPIO_HUB6:
1845 case UPIO_PORT:
1846 if (!request_region(up->port.iobase, size, "serial"))
1847 ret = -EBUSY;
1848 break;
1849 }
1850 return ret;
1851}
1852
1853static void serial8250_release_std_resource(struct uart_8250_port *up)
1854{
1855 unsigned int size = 8 << up->port.regshift;
1856
1857 switch (up->port.iotype) {
1858 case UPIO_MEM:
1859 if (!up->port.mapbase)
1860 break;
1861
1862 if (up->port.flags & UPF_IOREMAP) {
1863 iounmap(up->port.membase);
1864 up->port.membase = NULL;
1865 }
1866
1867 release_mem_region(up->port.mapbase, size);
1868 break;
1869
1870 case UPIO_HUB6:
1871 case UPIO_PORT:
1872 release_region(up->port.iobase, size);
1873 break;
1874 }
1875}
1876
1877static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1878{
1879 unsigned long start = UART_RSA_BASE << up->port.regshift;
1880 unsigned int size = 8 << up->port.regshift;
1881 int ret = 0;
1882
1883 switch (up->port.iotype) {
1884 case UPIO_MEM:
1885 ret = -EINVAL;
1886 break;
1887
1888 case UPIO_HUB6:
1889 case UPIO_PORT:
1890 start += up->port.iobase;
1891 if (!request_region(start, size, "serial-rsa"))
1892 ret = -EBUSY;
1893 break;
1894 }
1895
1896 return ret;
1897}
1898
1899static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1900{
1901 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1902 unsigned int size = 8 << up->port.regshift;
1903
1904 switch (up->port.iotype) {
1905 case UPIO_MEM:
1906 break;
1907
1908 case UPIO_HUB6:
1909 case UPIO_PORT:
1910 release_region(up->port.iobase + offset, size);
1911 break;
1912 }
1913}
1914
1915static void serial8250_release_port(struct uart_port *port)
1916{
1917 struct uart_8250_port *up = (struct uart_8250_port *)port;
1918
1919 serial8250_release_std_resource(up);
1920 if (up->port.type == PORT_RSA)
1921 serial8250_release_rsa_resource(up);
1922}
1923
1924static int serial8250_request_port(struct uart_port *port)
1925{
1926 struct uart_8250_port *up = (struct uart_8250_port *)port;
1927 int ret = 0;
1928
1929 ret = serial8250_request_std_resource(up);
1930 if (ret == 0 && up->port.type == PORT_RSA) {
1931 ret = serial8250_request_rsa_resource(up);
1932 if (ret < 0)
1933 serial8250_release_std_resource(up);
1934 }
1935
1936 return ret;
1937}
1938
1939static void serial8250_config_port(struct uart_port *port, int flags)
1940{
1941 struct uart_8250_port *up = (struct uart_8250_port *)port;
1942 int probeflags = PROBE_ANY;
1943 int ret;
1944
1945 /*
1946 * Don't probe for MCA ports on non-MCA machines.
1947 */
1948 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
1949 return;
1950
1951 /*
1952 * Find the region that we can probe for. This in turn
1953 * tells us whether we can probe for the type of port.
1954 */
1955 ret = serial8250_request_std_resource(up);
1956 if (ret < 0)
1957 return;
1958
1959 ret = serial8250_request_rsa_resource(up);
1960 if (ret < 0)
1961 probeflags &= ~PROBE_RSA;
1962
1963 if (flags & UART_CONFIG_TYPE)
1964 autoconfig(up, probeflags);
1965 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1966 autoconfig_irq(up);
1967
1968 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
1969 serial8250_release_rsa_resource(up);
1970 if (up->port.type == PORT_UNKNOWN)
1971 serial8250_release_std_resource(up);
1972}
1973
1974static int
1975serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
1976{
1977 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
1978 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
1979 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
1980 ser->type == PORT_STARTECH)
1981 return -EINVAL;
1982 return 0;
1983}
1984
1985static const char *
1986serial8250_type(struct uart_port *port)
1987{
1988 int type = port->type;
1989
1990 if (type >= ARRAY_SIZE(uart_config))
1991 type = 0;
1992 return uart_config[type].name;
1993}
1994
1995static struct uart_ops serial8250_pops = {
1996 .tx_empty = serial8250_tx_empty,
1997 .set_mctrl = serial8250_set_mctrl,
1998 .get_mctrl = serial8250_get_mctrl,
1999 .stop_tx = serial8250_stop_tx,
2000 .start_tx = serial8250_start_tx,
2001 .stop_rx = serial8250_stop_rx,
2002 .enable_ms = serial8250_enable_ms,
2003 .break_ctl = serial8250_break_ctl,
2004 .startup = serial8250_startup,
2005 .shutdown = serial8250_shutdown,
2006 .set_termios = serial8250_set_termios,
2007 .pm = serial8250_pm,
2008 .type = serial8250_type,
2009 .release_port = serial8250_release_port,
2010 .request_port = serial8250_request_port,
2011 .config_port = serial8250_config_port,
2012 .verify_port = serial8250_verify_port,
2013};
2014
2015static struct uart_8250_port serial8250_ports[UART_NR];
2016
2017static void __init serial8250_isa_init_ports(void)
2018{
2019 struct uart_8250_port *up;
2020 static int first = 1;
2021 int i;
2022
2023 if (!first)
2024 return;
2025 first = 0;
2026
2027 for (i = 0; i < UART_NR; i++) {
2028 struct uart_8250_port *up = &serial8250_ports[i];
2029
2030 up->port.line = i;
2031 spin_lock_init(&up->port.lock);
2032
2033 init_timer(&up->timer);
2034 up->timer.function = serial8250_timeout;
2035
2036 /*
2037 * ALPHA_KLUDGE_MCR needs to be killed.
2038 */
2039 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2040 up->mcr_force = ALPHA_KLUDGE_MCR;
2041
2042 up->port.ops = &serial8250_pops;
2043 }
2044
2045 for (i = 0, up = serial8250_ports; i < ARRAY_SIZE(old_serial_port);
2046 i++, up++) {
2047 up->port.iobase = old_serial_port[i].port;
2048 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2049 up->port.uartclk = old_serial_port[i].baud_base * 16;
2050 up->port.flags = old_serial_port[i].flags;
2051 up->port.hub6 = old_serial_port[i].hub6;
2052 up->port.membase = old_serial_port[i].iomem_base;
2053 up->port.iotype = old_serial_port[i].io_type;
2054 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2055 if (share_irqs)
2056 up->port.flags |= UPF_SHARE_IRQ;
2057 }
2058}
2059
2060static void __init
2061serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2062{
2063 int i;
2064
2065 serial8250_isa_init_ports();
2066
2067 for (i = 0; i < UART_NR; i++) {
2068 struct uart_8250_port *up = &serial8250_ports[i];
2069
2070 up->port.dev = dev;
2071 uart_add_one_port(drv, &up->port);
2072 }
2073}
2074
2075#ifdef CONFIG_SERIAL_8250_CONSOLE
2076
2077#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2078
2079/*
2080 * Wait for transmitter & holding register to empty
2081 */
2082static inline void wait_for_xmitr(struct uart_8250_port *up)
2083{
2084 unsigned int status, tmout = 10000;
2085
2086 /* Wait up to 10ms for the character(s) to be sent. */
2087 do {
2088 status = serial_in(up, UART_LSR);
2089
2090 if (status & UART_LSR_BI)
2091 up->lsr_break_flag = UART_LSR_BI;
2092
2093 if (--tmout == 0)
2094 break;
2095 udelay(1);
2096 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2097
2098 /* Wait up to 1s for flow control if necessary */
2099 if (up->port.flags & UPF_CONS_FLOW) {
2100 tmout = 1000000;
2101 while (--tmout &&
2102 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2103 udelay(1);
2104 }
2105}
2106
2107/*
2108 * Print a string to the serial port trying not to disturb
2109 * any possible real use of the port...
2110 *
2111 * The console_lock must be held when we get here.
2112 */
2113static void
2114serial8250_console_write(struct console *co, const char *s, unsigned int count)
2115{
2116 struct uart_8250_port *up = &serial8250_ports[co->index];
2117 unsigned int ier;
2118 int i;
2119
2120 /*
2121 * First save the UER then disable the interrupts
2122 */
2123 ier = serial_in(up, UART_IER);
2124
2125 if (up->capabilities & UART_CAP_UUE)
2126 serial_out(up, UART_IER, UART_IER_UUE);
2127 else
2128 serial_out(up, UART_IER, 0);
2129
2130 /*
2131 * Now, do each character
2132 */
2133 for (i = 0; i < count; i++, s++) {
2134 wait_for_xmitr(up);
2135
2136 /*
2137 * Send the character out.
2138 * If a LF, also do CR...
2139 */
2140 serial_out(up, UART_TX, *s);
2141 if (*s == 10) {
2142 wait_for_xmitr(up);
2143 serial_out(up, UART_TX, 13);
2144 }
2145 }
2146
2147 /*
2148 * Finally, wait for transmitter to become empty
2149 * and restore the IER
2150 */
2151 wait_for_xmitr(up);
2152 serial_out(up, UART_IER, ier);
2153}
2154
2155static int serial8250_console_setup(struct console *co, char *options)
2156{
2157 struct uart_port *port;
2158 int baud = 9600;
2159 int bits = 8;
2160 int parity = 'n';
2161 int flow = 'n';
2162
2163 /*
2164 * Check whether an invalid uart number has been specified, and
2165 * if so, search for the first available port that does have
2166 * console support.
2167 */
2168 if (co->index >= UART_NR)
2169 co->index = 0;
2170 port = &serial8250_ports[co->index].port;
2171 if (!port->iobase && !port->membase)
2172 return -ENODEV;
2173
2174 if (options)
2175 uart_parse_options(options, &baud, &parity, &bits, &flow);
2176
2177 return uart_set_options(port, co, baud, parity, bits, flow);
2178}
2179
2180static struct uart_driver serial8250_reg;
2181static struct console serial8250_console = {
2182 .name = "ttyS",
2183 .write = serial8250_console_write,
2184 .device = uart_console_device,
2185 .setup = serial8250_console_setup,
2186 .flags = CON_PRINTBUFFER,
2187 .index = -1,
2188 .data = &serial8250_reg,
2189};
2190
2191static int __init serial8250_console_init(void)
2192{
2193 serial8250_isa_init_ports();
2194 register_console(&serial8250_console);
2195 return 0;
2196}
2197console_initcall(serial8250_console_init);
2198
2199static int __init find_port(struct uart_port *p)
2200{
2201 int line;
2202 struct uart_port *port;
2203
2204 for (line = 0; line < UART_NR; line++) {
2205 port = &serial8250_ports[line].port;
2206 if (p->iotype == port->iotype &&
2207 p->iobase == port->iobase &&
2208 p->membase == port->membase)
2209 return line;
2210 }
2211 return -ENODEV;
2212}
2213
2214int __init serial8250_start_console(struct uart_port *port, char *options)
2215{
2216 int line;
2217
2218 line = find_port(port);
2219 if (line < 0)
2220 return -ENODEV;
2221
2222 add_preferred_console("ttyS", line, options);
2223 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2224 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2225 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2226 (unsigned long) port->iobase, options);
2227 if (!(serial8250_console.flags & CON_ENABLED)) {
2228 serial8250_console.flags &= ~CON_PRINTBUFFER;
2229 register_console(&serial8250_console);
2230 }
2231 return line;
2232}
2233
2234#define SERIAL8250_CONSOLE &serial8250_console
2235#else
2236#define SERIAL8250_CONSOLE NULL
2237#endif
2238
2239static struct uart_driver serial8250_reg = {
2240 .owner = THIS_MODULE,
2241 .driver_name = "serial",
2242 .devfs_name = "tts/",
2243 .dev_name = "ttyS",
2244 .major = TTY_MAJOR,
2245 .minor = 64,
2246 .nr = UART_NR,
2247 .cons = SERIAL8250_CONSOLE,
2248};
2249
2250int __init early_serial_setup(struct uart_port *port)
2251{
2252 if (port->line >= ARRAY_SIZE(serial8250_ports))
2253 return -ENODEV;
2254
2255 serial8250_isa_init_ports();
2256 serial8250_ports[port->line].port = *port;
2257 serial8250_ports[port->line].port.ops = &serial8250_pops;
2258 return 0;
2259}
2260
2261/**
2262 * serial8250_suspend_port - suspend one serial port
2263 * @line: serial line number
2264 * @level: the level of port suspension, as per uart_suspend_port
2265 *
2266 * Suspend one serial port.
2267 */
2268void serial8250_suspend_port(int line)
2269{
2270 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2271}
2272
2273/**
2274 * serial8250_resume_port - resume one serial port
2275 * @line: serial line number
2276 * @level: the level of port resumption, as per uart_resume_port
2277 *
2278 * Resume one serial port.
2279 */
2280void serial8250_resume_port(int line)
2281{
2282 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2283}
2284
2285/*
2286 * Register a set of serial devices attached to a platform device. The
2287 * list is terminated with a zero flags entry, which means we expect
2288 * all entries to have at least UPF_BOOT_AUTOCONF set.
2289 */
2290static int __devinit serial8250_probe(struct device *dev)
2291{
2292 struct plat_serial8250_port *p = dev->platform_data;
2293 struct uart_port port;
2294
2295 memset(&port, 0, sizeof(struct uart_port));
2296
2297 for (; p && p->flags != 0; p++) {
2298 port.iobase = p->iobase;
2299 port.membase = p->membase;
2300 port.irq = p->irq;
2301 port.uartclk = p->uartclk;
2302 port.regshift = p->regshift;
2303 port.iotype = p->iotype;
2304 port.flags = p->flags;
2305 port.mapbase = p->mapbase;
2306 port.dev = dev;
2307 if (share_irqs)
2308 port.flags |= UPF_SHARE_IRQ;
2309 serial8250_register_port(&port);
2310 }
2311 return 0;
2312}
2313
2314/*
2315 * Remove serial ports registered against a platform device.
2316 */
2317static int __devexit serial8250_remove(struct device *dev)
2318{
2319 int i;
2320
2321 for (i = 0; i < UART_NR; i++) {
2322 struct uart_8250_port *up = &serial8250_ports[i];
2323
2324 if (up->port.dev == dev)
2325 serial8250_unregister_port(i);
2326 }
2327 return 0;
2328}
2329
2330static int serial8250_suspend(struct device *dev, pm_message_t state, u32 level)
2331{
2332 int i;
2333
2334 if (level != SUSPEND_DISABLE)
2335 return 0;
2336
2337 for (i = 0; i < UART_NR; i++) {
2338 struct uart_8250_port *up = &serial8250_ports[i];
2339
2340 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2341 uart_suspend_port(&serial8250_reg, &up->port);
2342 }
2343
2344 return 0;
2345}
2346
2347static int serial8250_resume(struct device *dev, u32 level)
2348{
2349 int i;
2350
2351 if (level != RESUME_ENABLE)
2352 return 0;
2353
2354 for (i = 0; i < UART_NR; i++) {
2355 struct uart_8250_port *up = &serial8250_ports[i];
2356
2357 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2358 uart_resume_port(&serial8250_reg, &up->port);
2359 }
2360
2361 return 0;
2362}
2363
2364static struct device_driver serial8250_isa_driver = {
2365 .name = "serial8250",
2366 .bus = &platform_bus_type,
2367 .probe = serial8250_probe,
2368 .remove = __devexit_p(serial8250_remove),
2369 .suspend = serial8250_suspend,
2370 .resume = serial8250_resume,
2371};
2372
2373/*
2374 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2375 * in the table in include/asm/serial.h
2376 */
2377static struct platform_device *serial8250_isa_devs;
2378
2379/*
2380 * serial8250_register_port and serial8250_unregister_port allows for
2381 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2382 * modems and PCI multiport cards.
2383 */
2384static DECLARE_MUTEX(serial_sem);
2385
2386static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2387{
2388 int i;
2389
2390 /*
2391 * First, find a port entry which matches.
2392 */
2393 for (i = 0; i < UART_NR; i++)
2394 if (uart_match_port(&serial8250_ports[i].port, port))
2395 return &serial8250_ports[i];
2396
2397 /*
2398 * We didn't find a matching entry, so look for the first
2399 * free entry. We look for one which hasn't been previously
2400 * used (indicated by zero iobase).
2401 */
2402 for (i = 0; i < UART_NR; i++)
2403 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2404 serial8250_ports[i].port.iobase == 0)
2405 return &serial8250_ports[i];
2406
2407 /*
2408 * That also failed. Last resort is to find any entry which
2409 * doesn't have a real port associated with it.
2410 */
2411 for (i = 0; i < UART_NR; i++)
2412 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2413 return &serial8250_ports[i];
2414
2415 return NULL;
2416}
2417
2418/**
2419 * serial8250_register_port - register a serial port
2420 * @port: serial port template
2421 *
2422 * Configure the serial port specified by the request. If the
2423 * port exists and is in use, it is hung up and unregistered
2424 * first.
2425 *
2426 * The port is then probed and if necessary the IRQ is autodetected
2427 * If this fails an error is returned.
2428 *
2429 * On success the port is ready to use and the line number is returned.
2430 */
2431int serial8250_register_port(struct uart_port *port)
2432{
2433 struct uart_8250_port *uart;
2434 int ret = -ENOSPC;
2435
2436 if (port->uartclk == 0)
2437 return -EINVAL;
2438
2439 down(&serial_sem);
2440
2441 uart = serial8250_find_match_or_unused(port);
2442 if (uart) {
2443 uart_remove_one_port(&serial8250_reg, &uart->port);
2444
2445 uart->port.iobase = port->iobase;
2446 uart->port.membase = port->membase;
2447 uart->port.irq = port->irq;
2448 uart->port.uartclk = port->uartclk;
2449 uart->port.fifosize = port->fifosize;
2450 uart->port.regshift = port->regshift;
2451 uart->port.iotype = port->iotype;
2452 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2453 uart->port.mapbase = port->mapbase;
2454 if (port->dev)
2455 uart->port.dev = port->dev;
2456
2457 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2458 if (ret == 0)
2459 ret = uart->port.line;
2460 }
2461 up(&serial_sem);
2462
2463 return ret;
2464}
2465EXPORT_SYMBOL(serial8250_register_port);
2466
2467/**
2468 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2469 * @line: serial line number
2470 *
2471 * Remove one serial port. This may not be called from interrupt
2472 * context. We hand the port back to the our control.
2473 */
2474void serial8250_unregister_port(int line)
2475{
2476 struct uart_8250_port *uart = &serial8250_ports[line];
2477
2478 down(&serial_sem);
2479 uart_remove_one_port(&serial8250_reg, &uart->port);
2480 if (serial8250_isa_devs) {
2481 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2482 uart->port.type = PORT_UNKNOWN;
2483 uart->port.dev = &serial8250_isa_devs->dev;
2484 uart_add_one_port(&serial8250_reg, &uart->port);
2485 } else {
2486 uart->port.dev = NULL;
2487 }
2488 up(&serial_sem);
2489}
2490EXPORT_SYMBOL(serial8250_unregister_port);
2491
2492static int __init serial8250_init(void)
2493{
2494 int ret, i;
2495
2496 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2497 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2498 share_irqs ? "en" : "dis");
2499
2500 for (i = 0; i < NR_IRQS; i++)
2501 spin_lock_init(&irq_lists[i].lock);
2502
2503 ret = uart_register_driver(&serial8250_reg);
2504 if (ret)
2505 goto out;
2506
2507 serial8250_isa_devs = platform_device_register_simple("serial8250",
2508 -1, NULL, 0);
2509 if (IS_ERR(serial8250_isa_devs)) {
2510 ret = PTR_ERR(serial8250_isa_devs);
2511 goto unreg;
2512 }
2513
2514 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2515
2516 ret = driver_register(&serial8250_isa_driver);
2517 if (ret == 0)
2518 goto out;
2519
2520 platform_device_unregister(serial8250_isa_devs);
2521 unreg:
2522 uart_unregister_driver(&serial8250_reg);
2523 out:
2524 return ret;
2525}
2526
2527static void __exit serial8250_exit(void)
2528{
2529 struct platform_device *isa_dev = serial8250_isa_devs;
2530
2531 /*
2532 * This tells serial8250_unregister_port() not to re-register
2533 * the ports (thereby making serial8250_isa_driver permanently
2534 * in use.)
2535 */
2536 serial8250_isa_devs = NULL;
2537
2538 driver_unregister(&serial8250_isa_driver);
2539 platform_device_unregister(isa_dev);
2540
2541 uart_unregister_driver(&serial8250_reg);
2542}
2543
2544module_init(serial8250_init);
2545module_exit(serial8250_exit);
2546
2547EXPORT_SYMBOL(serial8250_suspend_port);
2548EXPORT_SYMBOL(serial8250_resume_port);
2549
2550MODULE_LICENSE("GPL");
2551MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2552
2553module_param(share_irqs, uint, 0644);
2554MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2555 " (unsafe)");
2556
2557#ifdef CONFIG_SERIAL_8250_RSA
2558module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2559MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2560#endif
2561MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
2562
2563/**
2564 * register_serial - configure a 16x50 serial port at runtime
2565 * @req: request structure
2566 *
2567 * Configure the serial port specified by the request. If the
2568 * port exists and is in use an error is returned. If the port
2569 * is not currently in the table it is added.
2570 *
2571 * The port is then probed and if necessary the IRQ is autodetected
2572 * If this fails an error is returned.
2573 *
2574 * On success the port is ready to use and the line number is returned.
23907eb8
RK		 2575 *
2576 * Note: this function is deprecated - use serial8250_register_port
2577 * instead.
1da177e4
LT		 2578 */
2579int register_serial(struct serial_struct *req)
2580{
2581 struct uart_port port;
2582
2583 port.iobase = req->port;
2584 port.membase = req->iomem_base;
2585 port.irq = req->irq;
2586 port.uartclk = req->baud_base * 16;
2587 port.fifosize = req->xmit_fifo_size;
2588 port.regshift = req->iomem_reg_shift;
2589 port.iotype = req->io_type;
2590 port.flags = req->flags | UPF_BOOT_AUTOCONF;
2591 port.mapbase = req->iomap_base;
2592 port.dev = NULL;
2593
2594 if (share_irqs)
2595 port.flags |= UPF_SHARE_IRQ;
2596
2597 if (HIGH_BITS_OFFSET)
2598 port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET;
2599
2600 /*
2601 * If a clock rate wasn't specified by the low level driver, then
2602 * default to the standard clock rate. This should be 115200 (*16)
2603 * and should not depend on the architecture's BASE_BAUD definition.
2604 * However, since this API will be deprecated, it's probably a
2605 * better idea to convert the drivers to use the new API
2606 * (serial8250_register_port and serial8250_unregister_port).
2607 */
2608 if (port.uartclk == 0) {
2609 printk(KERN_WARNING
2610 "Serial: registering port at [%08x,%08lx,%p] irq %d with zero baud_base\n",
2611 port.iobase, port.mapbase, port.membase, port.irq);
2612 printk(KERN_WARNING "Serial: see %s:%d for more information\n",
2613 __FILE__, __LINE__);
2614 dump_stack();
2615
2616 /*
2617 * Fix it up for now, but this is only a temporary measure.
2618 */
2619 port.uartclk = BASE_BAUD * 16;
2620 }
2621
2622 return serial8250_register_port(&port);
2623}
2624EXPORT_SYMBOL(register_serial);
2625
2626/**
2627 * unregister_serial - remove a 16x50 serial port at runtime
2628 * @line: serial line number
2629 *
2630 * Remove one serial port. This may not be called from interrupt
2631 * context. We hand the port back to our local PM control.
23907eb8
RK		 2632 *
2633 * Note: this function is deprecated - use serial8250_unregister_port
2634 * instead.
1da177e4
LT		 2635 */
2636void unregister_serial(int line)
2637{
2638 serial8250_unregister_port(line);
2639}
2640EXPORT_SYMBOL(unregister_serial);
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