]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/serial/8250.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] Typo fixes
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
1da177e4 34#include <linux/delay.h>
d052d1be 35#include <linux/platform_device.h>
1da177e4
LT		 36#include <linux/tty.h>
37#include <linux/tty_flip.h>
38#include <linux/serial_reg.h>
39#include <linux/serial_core.h>
40#include <linux/serial.h>
41#include <linux/serial_8250.h>
78512ece 42#include <linux/nmi.h>
f392ecfa 43#include <linux/mutex.h>
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
52 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 56
a61c2d78
DJ		 57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
1da177e4
LT		 59/*
60 * Debugging.
61 */
62#if 0
63#define DEBUG_AUTOCONF(fmt...) printk(fmt)
64#else
65#define DEBUG_AUTOCONF(fmt...) do { } while (0)
66#endif
67
68#if 0
69#define DEBUG_INTR(fmt...) printk(fmt)
70#else
71#define DEBUG_INTR(fmt...) do { } while (0)
72#endif
73
74#define PASS_LIMIT 256
75
76/*
77 * We default to IRQ0 for the "no irq" hack. Some
78 * machine types want others as well - they're free
79 * to redefine this in their header file.
80 */
81#define is_real_interrupt(irq) ((irq) != 0)
82
1da177e4
LT		 83#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
84#define CONFIG_SERIAL_DETECT_IRQ 1
85#endif
1da177e4
LT		 86#ifdef CONFIG_SERIAL_8250_MANY_PORTS
87#define CONFIG_SERIAL_MANY_PORTS 1
88#endif
89
90/*
91 * HUB6 is always on. This will be removed once the header
92 * files have been cleaned.
93 */
94#define CONFIG_HUB6 1
95
96#include <asm/serial.h>
97
98/*
99 * SERIAL_PORT_DFNS tells us about built-in ports that have no
100 * standard enumeration mechanism. Platforms that can find all
101 * serial ports via mechanisms like ACPI or PCI need not supply it.
102 */
103#ifndef SERIAL_PORT_DFNS
104#define SERIAL_PORT_DFNS
105#endif
106
cb3592be 107static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 108 SERIAL_PORT_DFNS /* defined in asm/serial.h */
109};
110
026d02a2 111#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 112
113#ifdef CONFIG_SERIAL_8250_RSA
114
115#define PORT_RSA_MAX 4
116static unsigned long probe_rsa[PORT_RSA_MAX];
117static unsigned int probe_rsa_count;
118#endif /* CONFIG_SERIAL_8250_RSA */
119
120struct uart_8250_port {
121 struct uart_port port;
122 struct timer_list timer; /* "no irq" timer */
123 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 124 unsigned short capabilities; /* port capabilities */
125 unsigned short bugs; /* port bugs */
1da177e4 126 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 127 unsigned char acr;
128 unsigned char ier;
129 unsigned char lcr;
130 unsigned char mcr;
131 unsigned char mcr_mask; /* mask of user bits */
132 unsigned char mcr_force; /* mask of forced bits */
133 unsigned char lsr_break_flag;
134
135 /*
136 * We provide a per-port pm hook.
137 */
138 void (*pm)(struct uart_port *port,
139 unsigned int state, unsigned int old);
140};
141
142struct irq_info {
143 spinlock_t lock;
144 struct list_head *head;
145};
146
147static struct irq_info irq_lists[NR_IRQS];
148
149/*
150 * Here we define the default xmit fifo size used for each type of UART.
151 */
152static const struct serial8250_config uart_config[] = {
153 [PORT_UNKNOWN] = {
154 .name = "unknown",
155 .fifo_size = 1,
156 .tx_loadsz = 1,
157 },
158 [PORT_8250] = {
159 .name = "8250",
160 .fifo_size = 1,
161 .tx_loadsz = 1,
162 },
163 [PORT_16450] = {
164 .name = "16450",
165 .fifo_size = 1,
166 .tx_loadsz = 1,
167 },
168 [PORT_16550] = {
169 .name = "16550",
170 .fifo_size = 1,
171 .tx_loadsz = 1,
172 },
173 [PORT_16550A] = {
174 .name = "16550A",
175 .fifo_size = 16,
176 .tx_loadsz = 16,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
178 .flags = UART_CAP_FIFO,
179 },
180 [PORT_CIRRUS] = {
181 .name = "Cirrus",
182 .fifo_size = 1,
183 .tx_loadsz = 1,
184 },
185 [PORT_16650] = {
186 .name = "ST16650",
187 .fifo_size = 1,
188 .tx_loadsz = 1,
189 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
190 },
191 [PORT_16650V2] = {
192 .name = "ST16650V2",
193 .fifo_size = 32,
194 .tx_loadsz = 16,
195 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
196 UART_FCR_T_TRIG_00,
197 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
198 },
199 [PORT_16750] = {
200 .name = "TI16750",
201 .fifo_size = 64,
202 .tx_loadsz = 64,
203 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
204 UART_FCR7_64BYTE,
205 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
206 },
207 [PORT_STARTECH] = {
208 .name = "Startech",
209 .fifo_size = 1,
210 .tx_loadsz = 1,
211 },
212 [PORT_16C950] = {
213 .name = "16C950/954",
214 .fifo_size = 128,
215 .tx_loadsz = 128,
216 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
217 .flags = UART_CAP_FIFO,
218 },
219 [PORT_16654] = {
220 .name = "ST16654",
221 .fifo_size = 64,
222 .tx_loadsz = 32,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
224 UART_FCR_T_TRIG_10,
225 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
226 },
227 [PORT_16850] = {
228 .name = "XR16850",
229 .fifo_size = 128,
230 .tx_loadsz = 128,
231 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
232 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
233 },
234 [PORT_RSA] = {
235 .name = "RSA",
236 .fifo_size = 2048,
237 .tx_loadsz = 2048,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
239 .flags = UART_CAP_FIFO,
240 },
241 [PORT_NS16550A] = {
242 .name = "NS16550A",
243 .fifo_size = 16,
244 .tx_loadsz = 16,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
246 .flags = UART_CAP_FIFO | UART_NATSEMI,
247 },
248 [PORT_XSCALE] = {
249 .name = "XScale",
250 .fifo_size = 32,
251 .tx_loadsz = 32,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_CAP_UUE,
254 },
255};
256
21c614a7
PA		 257#ifdef CONFIG_SERIAL_8250_AU1X00
258
259/* Au1x00 UART hardware has a weird register layout */
260static const u8 au_io_in_map[] = {
261 [UART_RX] = 0,
262 [UART_IER] = 2,
263 [UART_IIR] = 3,
264 [UART_LCR] = 5,
265 [UART_MCR] = 6,
266 [UART_LSR] = 7,
267 [UART_MSR] = 8,
268};
269
270static const u8 au_io_out_map[] = {
271 [UART_TX] = 1,
272 [UART_IER] = 2,
273 [UART_FCR] = 4,
274 [UART_LCR] = 5,
275 [UART_MCR] = 6,
276};
277
278/* sane hardware needs no mapping */
279static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
280{
281 if (up->port.iotype != UPIO_AU)
282 return offset;
283 return au_io_in_map[offset];
284}
285
286static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
287{
288 if (up->port.iotype != UPIO_AU)
289 return offset;
290 return au_io_out_map[offset];
291}
292
293#else
294
295/* sane hardware needs no mapping */
296#define map_8250_in_reg(up, offset) (offset)
297#define map_8250_out_reg(up, offset) (offset)
298
299#endif
300
ea8874dc 301static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 302{
21c614a7 303 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 304
305 switch (up->port.iotype) {
306 case UPIO_HUB6:
307 outb(up->port.hub6 - 1 + offset, up->port.iobase);
308 return inb(up->port.iobase + 1);
309
310 case UPIO_MEM:
311 return readb(up->port.membase + offset);
312
313 case UPIO_MEM32:
314 return readl(up->port.membase + offset);
315
21c614a7
PA		 316#ifdef CONFIG_SERIAL_8250_AU1X00
317 case UPIO_AU:
318 return __raw_readl(up->port.membase + offset);
319#endif
320
1da177e4
LT		 321 default:
322 return inb(up->port.iobase + offset);
323 }
324}
325
ea8874dc 326static void
1da177e4
LT		 327serial_out(struct uart_8250_port *up, int offset, int value)
328{
21c614a7 329 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 330
331 switch (up->port.iotype) {
332 case UPIO_HUB6:
333 outb(up->port.hub6 - 1 + offset, up->port.iobase);
334 outb(value, up->port.iobase + 1);
335 break;
336
337 case UPIO_MEM:
338 writeb(value, up->port.membase + offset);
339 break;
340
341 case UPIO_MEM32:
342 writel(value, up->port.membase + offset);
343 break;
344
21c614a7
PA		 345#ifdef CONFIG_SERIAL_8250_AU1X00
346 case UPIO_AU:
347 __raw_writel(value, up->port.membase + offset);
348 break;
349#endif
350
1da177e4
LT		 351 default:
352 outb(value, up->port.iobase + offset);
353 }
354}
355
356/*
357 * We used to support using pause I/O for certain machines. We
358 * haven't supported this for a while, but just in case it's badly
359 * needed for certain old 386 machines, I've left these #define's
360 * in....
361 */
362#define serial_inp(up, offset) serial_in(up, offset)
363#define serial_outp(up, offset, value) serial_out(up, offset, value)
364
365
366/*
367 * For the 16C950
368 */
369static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
370{
371 serial_out(up, UART_SCR, offset);
372 serial_out(up, UART_ICR, value);
373}
374
375static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
376{
377 unsigned int value;
378
379 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
380 serial_out(up, UART_SCR, offset);
381 value = serial_in(up, UART_ICR);
382 serial_icr_write(up, UART_ACR, up->acr);
383
384 return value;
385}
386
387/*
388 * FIFO support.
389 */
390static inline void serial8250_clear_fifos(struct uart_8250_port *p)
391{
392 if (p->capabilities & UART_CAP_FIFO) {
393 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
394 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
395 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
396 serial_outp(p, UART_FCR, 0);
397 }
398}
399
400/*
401 * IER sleep support. UARTs which have EFRs need the "extended
402 * capability" bit enabled. Note that on XR16C850s, we need to
403 * reset LCR to write to IER.
404 */
405static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
406{
407 if (p->capabilities & UART_CAP_SLEEP) {
408 if (p->capabilities & UART_CAP_EFR) {
409 serial_outp(p, UART_LCR, 0xBF);
410 serial_outp(p, UART_EFR, UART_EFR_ECB);
411 serial_outp(p, UART_LCR, 0);
412 }
413 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
414 if (p->capabilities & UART_CAP_EFR) {
415 serial_outp(p, UART_LCR, 0xBF);
416 serial_outp(p, UART_EFR, 0);
417 serial_outp(p, UART_LCR, 0);
418 }
419 }
420}
421
422#ifdef CONFIG_SERIAL_8250_RSA
423/*
424 * Attempts to turn on the RSA FIFO. Returns zero on failure.
425 * We set the port uart clock rate if we succeed.
426 */
427static int __enable_rsa(struct uart_8250_port *up)
428{
429 unsigned char mode;
430 int result;
431
432 mode = serial_inp(up, UART_RSA_MSR);
433 result = mode & UART_RSA_MSR_FIFO;
434
435 if (!result) {
436 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
437 mode = serial_inp(up, UART_RSA_MSR);
438 result = mode & UART_RSA_MSR_FIFO;
439 }
440
441 if (result)
442 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
443
444 return result;
445}
446
447static void enable_rsa(struct uart_8250_port *up)
448{
449 if (up->port.type == PORT_RSA) {
450 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
451 spin_lock_irq(&up->port.lock);
452 __enable_rsa(up);
453 spin_unlock_irq(&up->port.lock);
454 }
455 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
456 serial_outp(up, UART_RSA_FRR, 0);
457 }
458}
459
460/*
461 * Attempts to turn off the RSA FIFO. Returns zero on failure.
462 * It is unknown why interrupts were disabled in here. However,
463 * the caller is expected to preserve this behaviour by grabbing
464 * the spinlock before calling this function.
465 */
466static void disable_rsa(struct uart_8250_port *up)
467{
468 unsigned char mode;
469 int result;
470
471 if (up->port.type == PORT_RSA &&
472 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
473 spin_lock_irq(&up->port.lock);
474
475 mode = serial_inp(up, UART_RSA_MSR);
476 result = !(mode & UART_RSA_MSR_FIFO);
477
478 if (!result) {
479 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
480 mode = serial_inp(up, UART_RSA_MSR);
481 result = !(mode & UART_RSA_MSR_FIFO);
482 }
483
484 if (result)
485 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
486 spin_unlock_irq(&up->port.lock);
487 }
488}
489#endif /* CONFIG_SERIAL_8250_RSA */
490
491/*
492 * This is a quickie test to see how big the FIFO is.
493 * It doesn't work at all the time, more's the pity.
494 */
495static int size_fifo(struct uart_8250_port *up)
496{
497 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
498 int count;
499
500 old_lcr = serial_inp(up, UART_LCR);
501 serial_outp(up, UART_LCR, 0);
502 old_fcr = serial_inp(up, UART_FCR);
503 old_mcr = serial_inp(up, UART_MCR);
504 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
505 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
506 serial_outp(up, UART_MCR, UART_MCR_LOOP);
507 serial_outp(up, UART_LCR, UART_LCR_DLAB);
508 old_dll = serial_inp(up, UART_DLL);
509 old_dlm = serial_inp(up, UART_DLM);
510 serial_outp(up, UART_DLL, 0x01);
511 serial_outp(up, UART_DLM, 0x00);
512 serial_outp(up, UART_LCR, 0x03);
513 for (count = 0; count < 256; count++)
514 serial_outp(up, UART_TX, count);
515 mdelay(20);/* FIXME - schedule_timeout */
516 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
517 (count < 256); count++)
518 serial_inp(up, UART_RX);
519 serial_outp(up, UART_FCR, old_fcr);
520 serial_outp(up, UART_MCR, old_mcr);
521 serial_outp(up, UART_LCR, UART_LCR_DLAB);
522 serial_outp(up, UART_DLL, old_dll);
523 serial_outp(up, UART_DLM, old_dlm);
524 serial_outp(up, UART_LCR, old_lcr);
525
526 return count;
527}
528
529/*
530 * Read UART ID using the divisor method - set DLL and DLM to zero
531 * and the revision will be in DLL and device type in DLM. We
532 * preserve the device state across this.
533 */
534static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
535{
536 unsigned char old_dll, old_dlm, old_lcr;
537 unsigned int id;
538
539 old_lcr = serial_inp(p, UART_LCR);
540 serial_outp(p, UART_LCR, UART_LCR_DLAB);
541
542 old_dll = serial_inp(p, UART_DLL);
543 old_dlm = serial_inp(p, UART_DLM);
544
545 serial_outp(p, UART_DLL, 0);
546 serial_outp(p, UART_DLM, 0);
547
548 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
549
550 serial_outp(p, UART_DLL, old_dll);
551 serial_outp(p, UART_DLM, old_dlm);
552 serial_outp(p, UART_LCR, old_lcr);
553
554 return id;
555}
556
557/*
558 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
559 * When this function is called we know it is at least a StarTech
560 * 16650 V2, but it might be one of several StarTech UARTs, or one of
561 * its clones. (We treat the broken original StarTech 16650 V1 as a
562 * 16550, and why not? Startech doesn't seem to even acknowledge its
563 * existence.)
564 *
565 * What evil have men's minds wrought...
566 */
567static void autoconfig_has_efr(struct uart_8250_port *up)
568{
569 unsigned int id1, id2, id3, rev;
570
571 /*
572 * Everything with an EFR has SLEEP
573 */
574 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
575
576 /*
577 * First we check to see if it's an Oxford Semiconductor UART.
578 *
579 * If we have to do this here because some non-National
580 * Semiconductor clone chips lock up if you try writing to the
581 * LSR register (which serial_icr_read does)
582 */
583
584 /*
585 * Check for Oxford Semiconductor 16C950.
586 *
587 * EFR [4] must be set else this test fails.
588 *
589 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
590 * claims that it's needed for 952 dual UART's (which are not
591 * recommended for new designs).
592 */
593 up->acr = 0;
594 serial_out(up, UART_LCR, 0xBF);
595 serial_out(up, UART_EFR, UART_EFR_ECB);
596 serial_out(up, UART_LCR, 0x00);
597 id1 = serial_icr_read(up, UART_ID1);
598 id2 = serial_icr_read(up, UART_ID2);
599 id3 = serial_icr_read(up, UART_ID3);
600 rev = serial_icr_read(up, UART_REV);
601
602 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
603
604 if (id1 == 0x16 && id2 == 0xC9 &&
605 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
606 up->port.type = PORT_16C950;
4ba5e35d
RK		 607
608 /*
609 * Enable work around for the Oxford Semiconductor 952 rev B
610 * chip which causes it to seriously miscalculate baud rates
611 * when DLL is 0.
612 */
613 if (id3 == 0x52 && rev == 0x01)
614 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 615 return;
616 }
617
618 /*
619 * We check for a XR16C850 by setting DLL and DLM to 0, and then
620 * reading back DLL and DLM. The chip type depends on the DLM
621 * value read back:
622 * 0x10 - XR16C850 and the DLL contains the chip revision.
623 * 0x12 - XR16C2850.
624 * 0x14 - XR16C854.
625 */
626 id1 = autoconfig_read_divisor_id(up);
627 DEBUG_AUTOCONF("850id=%04x ", id1);
628
629 id2 = id1 >> 8;
630 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 631 up->port.type = PORT_16850;
632 return;
633 }
634
635 /*
636 * It wasn't an XR16C850.
637 *
638 * We distinguish between the '654 and the '650 by counting
639 * how many bytes are in the FIFO. I'm using this for now,
640 * since that's the technique that was sent to me in the
641 * serial driver update, but I'm not convinced this works.
642 * I've had problems doing this in the past. -TYT
643 */
644 if (size_fifo(up) == 64)
645 up->port.type = PORT_16654;
646 else
647 up->port.type = PORT_16650V2;
648}
649
650/*
651 * We detected a chip without a FIFO. Only two fall into
652 * this category - the original 8250 and the 16450. The
653 * 16450 has a scratch register (accessible with LCR=0)
654 */
655static void autoconfig_8250(struct uart_8250_port *up)
656{
657 unsigned char scratch, status1, status2;
658
659 up->port.type = PORT_8250;
660
661 scratch = serial_in(up, UART_SCR);
662 serial_outp(up, UART_SCR, 0xa5);
663 status1 = serial_in(up, UART_SCR);
664 serial_outp(up, UART_SCR, 0x5a);
665 status2 = serial_in(up, UART_SCR);
666 serial_outp(up, UART_SCR, scratch);
667
668 if (status1 == 0xa5 && status2 == 0x5a)
669 up->port.type = PORT_16450;
670}
671
672static int broken_efr(struct uart_8250_port *up)
673{
674 /*
675 * Exar ST16C2550 "A2" devices incorrectly detect as
676 * having an EFR, and report an ID of 0x0201. See
677 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
678 */
679 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
680 return 1;
681
682 return 0;
683}
684
685/*
686 * We know that the chip has FIFOs. Does it have an EFR? The
687 * EFR is located in the same register position as the IIR and
688 * we know the top two bits of the IIR are currently set. The
689 * EFR should contain zero. Try to read the EFR.
690 */
691static void autoconfig_16550a(struct uart_8250_port *up)
692{
693 unsigned char status1, status2;
694 unsigned int iersave;
695
696 up->port.type = PORT_16550A;
697 up->capabilities |= UART_CAP_FIFO;
698
699 /*
700 * Check for presence of the EFR when DLAB is set.
701 * Only ST16C650V1 UARTs pass this test.
702 */
703 serial_outp(up, UART_LCR, UART_LCR_DLAB);
704 if (serial_in(up, UART_EFR) == 0) {
705 serial_outp(up, UART_EFR, 0xA8);
706 if (serial_in(up, UART_EFR) != 0) {
707 DEBUG_AUTOCONF("EFRv1 ");
708 up->port.type = PORT_16650;
709 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
710 } else {
711 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
712 }
713 serial_outp(up, UART_EFR, 0);
714 return;
715 }
716
717 /*
718 * Maybe it requires 0xbf to be written to the LCR.
719 * (other ST16C650V2 UARTs, TI16C752A, etc)
720 */
721 serial_outp(up, UART_LCR, 0xBF);
722 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
723 DEBUG_AUTOCONF("EFRv2 ");
724 autoconfig_has_efr(up);
725 return;
726 }
727
728 /*
729 * Check for a National Semiconductor SuperIO chip.
730 * Attempt to switch to bank 2, read the value of the LOOP bit
731 * from EXCR1. Switch back to bank 0, change it in MCR. Then
732 * switch back to bank 2, read it from EXCR1 again and check
733 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 734 */
735 serial_outp(up, UART_LCR, 0);
736 status1 = serial_in(up, UART_MCR);
737 serial_outp(up, UART_LCR, 0xE0);
738 status2 = serial_in(up, 0x02); /* EXCR1 */
739
740 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
741 serial_outp(up, UART_LCR, 0);
742 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
743 serial_outp(up, UART_LCR, 0xE0);
744 status2 = serial_in(up, 0x02); /* EXCR1 */
745 serial_outp(up, UART_LCR, 0);
746 serial_outp(up, UART_MCR, status1);
747
748 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 749 unsigned short quot;
750
1da177e4 751 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 752
753 quot = serial_inp(up, UART_DLM) << 8;
754 quot += serial_inp(up, UART_DLL);
755 quot <<= 3;
756
1da177e4
LT		 757 status1 = serial_in(up, 0x04); /* EXCR1 */
758 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
759 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
760 serial_outp(up, 0x04, status1);
857dde2e
DW		 761
762 serial_outp(up, UART_DLL, quot & 0xff);
763 serial_outp(up, UART_DLM, quot >> 8);
764
1da177e4 765 serial_outp(up, UART_LCR, 0);
1da177e4 766
857dde2e 767 up->port.uartclk = 921600*16;
1da177e4
LT		 768 up->port.type = PORT_NS16550A;
769 up->capabilities |= UART_NATSEMI;
770 return;
771 }
772 }
773
774 /*
775 * No EFR. Try to detect a TI16750, which only sets bit 5 of
776 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
777 * Try setting it with and without DLAB set. Cheap clones
778 * set bit 5 without DLAB set.
779 */
780 serial_outp(up, UART_LCR, 0);
781 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
782 status1 = serial_in(up, UART_IIR) >> 5;
783 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
784 serial_outp(up, UART_LCR, UART_LCR_DLAB);
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
786 status2 = serial_in(up, UART_IIR) >> 5;
787 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
788 serial_outp(up, UART_LCR, 0);
789
790 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
791
792 if (status1 == 6 && status2 == 7) {
793 up->port.type = PORT_16750;
794 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
795 return;
796 }
797
798 /*
799 * Try writing and reading the UART_IER_UUE bit (b6).
800 * If it works, this is probably one of the Xscale platform's
801 * internal UARTs.
802 * We're going to explicitly set the UUE bit to 0 before
803 * trying to write and read a 1 just to make sure it's not
804 * already a 1 and maybe locked there before we even start start.
805 */
806 iersave = serial_in(up, UART_IER);
807 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
808 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
809 /*
810 * OK it's in a known zero state, try writing and reading
811 * without disturbing the current state of the other bits.
812 */
813 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
814 if (serial_in(up, UART_IER) & UART_IER_UUE) {
815 /*
816 * It's an Xscale.
817 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
818 */
819 DEBUG_AUTOCONF("Xscale ");
820 up->port.type = PORT_XSCALE;
821 up->capabilities |= UART_CAP_UUE;
822 return;
823 }
824 } else {
825 /*
826 * If we got here we couldn't force the IER_UUE bit to 0.
827 * Log it and continue.
828 */
829 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
830 }
831 serial_outp(up, UART_IER, iersave);
832}
833
834/*
835 * This routine is called by rs_init() to initialize a specific serial
836 * port. It determines what type of UART chip this serial port is
837 * using: 8250, 16450, 16550, 16550A. The important question is
838 * whether or not this UART is a 16550A or not, since this will
839 * determine whether or not we can use its FIFO features or not.
840 */
841static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
842{
843 unsigned char status1, scratch, scratch2, scratch3;
844 unsigned char save_lcr, save_mcr;
845 unsigned long flags;
846
847 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
848 return;
849
850 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
851 up->port.line, up->port.iobase, up->port.membase);
852
853 /*
854 * We really do need global IRQs disabled here - we're going to
855 * be frobbing the chips IRQ enable register to see if it exists.
856 */
857 spin_lock_irqsave(&up->port.lock, flags);
858// save_flags(flags); cli();
859
860 up->capabilities = 0;
4ba5e35d 861 up->bugs = 0;
1da177e4
LT		 862
863 if (!(up->port.flags & UPF_BUGGY_UART)) {
864 /*
865 * Do a simple existence test first; if we fail this,
866 * there's no point trying anything else.
867 *
868 * 0x80 is used as a nonsense port to prevent against
869 * false positives due to ISA bus float. The
870 * assumption is that 0x80 is a non-existent port;
871 * which should be safe since include/asm/io.h also
872 * makes this assumption.
873 *
874 * Note: this is safe as long as MCR bit 4 is clear
875 * and the device is in "PC" mode.
876 */
877 scratch = serial_inp(up, UART_IER);
878 serial_outp(up, UART_IER, 0);
879#ifdef __i386__
880 outb(0xff, 0x080);
881#endif
882 scratch2 = serial_inp(up, UART_IER);
883 serial_outp(up, UART_IER, 0x0F);
884#ifdef __i386__
885 outb(0, 0x080);
886#endif
887 scratch3 = serial_inp(up, UART_IER);
888 serial_outp(up, UART_IER, scratch);
889 if (scratch2 != 0 || scratch3 != 0x0F) {
890 /*
891 * We failed; there's nothing here
892 */
893 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
894 scratch2, scratch3);
895 goto out;
896 }
897 }
898
899 save_mcr = serial_in(up, UART_MCR);
900 save_lcr = serial_in(up, UART_LCR);
901
902 /*
903 * Check to see if a UART is really there. Certain broken
904 * internal modems based on the Rockwell chipset fail this
905 * test, because they apparently don't implement the loopback
906 * test mode. So this test is skipped on the COM 1 through
907 * COM 4 ports. This *should* be safe, since no board
908 * manufacturer would be stupid enough to design a board
909 * that conflicts with COM 1-4 --- we hope!
910 */
911 if (!(up->port.flags & UPF_SKIP_TEST)) {
912 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
913 status1 = serial_inp(up, UART_MSR) & 0xF0;
914 serial_outp(up, UART_MCR, save_mcr);
915 if (status1 != 0x90) {
916 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
917 status1);
918 goto out;
919 }
920 }
921
922 /*
923 * We're pretty sure there's a port here. Lets find out what
924 * type of port it is. The IIR top two bits allows us to find
6f0d618f 925 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 926 * determines what we test for next.
927 *
928 * We also initialise the EFR (if any) to zero for later. The
929 * EFR occupies the same register location as the FCR and IIR.
930 */
931 serial_outp(up, UART_LCR, 0xBF);
932 serial_outp(up, UART_EFR, 0);
933 serial_outp(up, UART_LCR, 0);
934
935 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
936 scratch = serial_in(up, UART_IIR) >> 6;
937
938 DEBUG_AUTOCONF("iir=%d ", scratch);
939
940 switch (scratch) {
941 case 0:
942 autoconfig_8250(up);
943 break;
944 case 1:
945 up->port.type = PORT_UNKNOWN;
946 break;
947 case 2:
948 up->port.type = PORT_16550;
949 break;
950 case 3:
951 autoconfig_16550a(up);
952 break;
953 }
954
955#ifdef CONFIG_SERIAL_8250_RSA
956 /*
957 * Only probe for RSA ports if we got the region.
958 */
959 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
960 int i;
961
962 for (i = 0 ; i < probe_rsa_count; ++i) {
963 if (probe_rsa[i] == up->port.iobase &&
964 __enable_rsa(up)) {
965 up->port.type = PORT_RSA;
966 break;
967 }
968 }
969 }
970#endif
21c614a7
PA		 971
972#ifdef CONFIG_SERIAL_8250_AU1X00
973 /* if access method is AU, it is a 16550 with a quirk */
974 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
975 up->bugs |= UART_BUG_NOMSR;
976#endif
977
1da177e4
LT		 978 serial_outp(up, UART_LCR, save_lcr);
979
980 if (up->capabilities != uart_config[up->port.type].flags) {
981 printk(KERN_WARNING
982 "ttyS%d: detected caps %08x should be %08x\n",
983 up->port.line, up->capabilities,
984 uart_config[up->port.type].flags);
985 }
986
987 up->port.fifosize = uart_config[up->port.type].fifo_size;
988 up->capabilities = uart_config[up->port.type].flags;
989 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
990
991 if (up->port.type == PORT_UNKNOWN)
992 goto out;
993
994 /*
995 * Reset the UART.
996 */
997#ifdef CONFIG_SERIAL_8250_RSA
998 if (up->port.type == PORT_RSA)
999 serial_outp(up, UART_RSA_FRR, 0);
1000#endif
1001 serial_outp(up, UART_MCR, save_mcr);
1002 serial8250_clear_fifos(up);
1003 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1004 if (up->capabilities & UART_CAP_UUE)
1005 serial_outp(up, UART_IER, UART_IER_UUE);
1006 else
1007 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1008
1009 out:
1010 spin_unlock_irqrestore(&up->port.lock, flags);
1011// restore_flags(flags);
1012 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1013}
1014
1015static void autoconfig_irq(struct uart_8250_port *up)
1016{
1017 unsigned char save_mcr, save_ier;
1018 unsigned char save_ICP = 0;
1019 unsigned int ICP = 0;
1020 unsigned long irqs;
1021 int irq;
1022
1023 if (up->port.flags & UPF_FOURPORT) {
1024 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1025 save_ICP = inb_p(ICP);
1026 outb_p(0x80, ICP);
1027 (void) inb_p(ICP);
1028 }
1029
1030 /* forget possible initially masked and pending IRQ */
1031 probe_irq_off(probe_irq_on());
1032 save_mcr = serial_inp(up, UART_MCR);
1033 save_ier = serial_inp(up, UART_IER);
1034 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1035
1036 irqs = probe_irq_on();
1037 serial_outp(up, UART_MCR, 0);
1038 udelay (10);
1039 if (up->port.flags & UPF_FOURPORT) {
1040 serial_outp(up, UART_MCR,
1041 UART_MCR_DTR | UART_MCR_RTS);
1042 } else {
1043 serial_outp(up, UART_MCR,
1044 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1045 }
1046 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1047 (void)serial_inp(up, UART_LSR);
1048 (void)serial_inp(up, UART_RX);
1049 (void)serial_inp(up, UART_IIR);
1050 (void)serial_inp(up, UART_MSR);
1051 serial_outp(up, UART_TX, 0xFF);
1052 udelay (20);
1053 irq = probe_irq_off(irqs);
1054
1055 serial_outp(up, UART_MCR, save_mcr);
1056 serial_outp(up, UART_IER, save_ier);
1057
1058 if (up->port.flags & UPF_FOURPORT)
1059 outb_p(save_ICP, ICP);
1060
1061 up->port.irq = (irq > 0) ? irq : 0;
1062}
1063
e763b90c
RK		 1064static inline void __stop_tx(struct uart_8250_port *p)
1065{
1066 if (p->ier & UART_IER_THRI) {
1067 p->ier &= ~UART_IER_THRI;
1068 serial_out(p, UART_IER, p->ier);
1069 }
1070}
1071
b129a8cc 1072static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1073{
1074 struct uart_8250_port *up = (struct uart_8250_port *)port;
1075
e763b90c 1076 __stop_tx(up);
1da177e4
LT		 1077
1078 /*
e763b90c 1079 * We really want to stop the transmitter from sending.
1da177e4 1080 */
e763b90c 1081 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1082 up->acr |= UART_ACR_TXDIS;
1083 serial_icr_write(up, UART_ACR, up->acr);
1084 }
1085}
1086
55d3b282
RK		 1087static void transmit_chars(struct uart_8250_port *up);
1088
b129a8cc 1089static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1090{
1091 struct uart_8250_port *up = (struct uart_8250_port *)port;
1092
1093 if (!(up->ier & UART_IER_THRI)) {
1094 up->ier |= UART_IER_THRI;
1095 serial_out(up, UART_IER, up->ier);
55d3b282 1096
67f7654e 1097 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1098 unsigned char lsr, iir;
1099 lsr = serial_in(up, UART_LSR);
1100 iir = serial_in(up, UART_IIR);
1101 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1102 transmit_chars(up);
1103 }
1da177e4 1104 }
e763b90c 1105
1da177e4 1106 /*
e763b90c 1107 * Re-enable the transmitter if we disabled it.
1da177e4 1108 */
e763b90c 1109 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1110 up->acr &= ~UART_ACR_TXDIS;
1111 serial_icr_write(up, UART_ACR, up->acr);
1112 }
1113}
1114
1115static void serial8250_stop_rx(struct uart_port *port)
1116{
1117 struct uart_8250_port *up = (struct uart_8250_port *)port;
1118
1119 up->ier &= ~UART_IER_RLSI;
1120 up->port.read_status_mask &= ~UART_LSR_DR;
1121 serial_out(up, UART_IER, up->ier);
1122}
1123
1124static void serial8250_enable_ms(struct uart_port *port)
1125{
1126 struct uart_8250_port *up = (struct uart_8250_port *)port;
1127
21c614a7
PA		 1128 /* no MSR capabilities */
1129 if (up->bugs & UART_BUG_NOMSR)
1130 return;
1131
1da177e4
LT		 1132 up->ier |= UART_IER_MSI;
1133 serial_out(up, UART_IER, up->ier);
1134}
1135
ea8874dc 1136static void
1da177e4
LT		 1137receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1138{
1139 struct tty_struct *tty = up->port.info->tty;
1140 unsigned char ch, lsr = *status;
1141 int max_count = 256;
1142 char flag;
1143
1144 do {
1da177e4
LT		 1145 ch = serial_inp(up, UART_RX);
1146 flag = TTY_NORMAL;
1147 up->port.icount.rx++;
1148
1149#ifdef CONFIG_SERIAL_8250_CONSOLE
1150 /*
1151 * Recover the break flag from console xmit
1152 */
1153 if (up->port.line == up->port.cons->index) {
1154 lsr |= up->lsr_break_flag;
1155 up->lsr_break_flag = 0;
1156 }
1157#endif
1158
1159 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1160 UART_LSR_FE | UART_LSR_OE))) {
1161 /*
1162 * For statistics only
1163 */
1164 if (lsr & UART_LSR_BI) {
1165 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1166 up->port.icount.brk++;
1167 /*
1168 * We do the SysRQ and SAK checking
1169 * here because otherwise the break
1170 * may get masked by ignore_status_mask
1171 * or read_status_mask.
1172 */
1173 if (uart_handle_break(&up->port))
1174 goto ignore_char;
1175 } else if (lsr & UART_LSR_PE)
1176 up->port.icount.parity++;
1177 else if (lsr & UART_LSR_FE)
1178 up->port.icount.frame++;
1179 if (lsr & UART_LSR_OE)
1180 up->port.icount.overrun++;
1181
1182 /*
23907eb8 1183 * Mask off conditions which should be ignored.
1da177e4
LT		 1184 */
1185 lsr &= up->port.read_status_mask;
1186
1187 if (lsr & UART_LSR_BI) {
1188 DEBUG_INTR("handling break....");
1189 flag = TTY_BREAK;
1190 } else if (lsr & UART_LSR_PE)
1191 flag = TTY_PARITY;
1192 else if (lsr & UART_LSR_FE)
1193 flag = TTY_FRAME;
1194 }
1195 if (uart_handle_sysrq_char(&up->port, ch, regs))
1196 goto ignore_char;
05ab3014
RK		 1197
1198 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1199
1da177e4
LT		 1200 ignore_char:
1201 lsr = serial_inp(up, UART_LSR);
1202 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1203 spin_unlock(&up->port.lock);
1204 tty_flip_buffer_push(tty);
1205 spin_lock(&up->port.lock);
1206 *status = lsr;
1207}
1208
ea8874dc 1209static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1210{
1211 struct circ_buf *xmit = &up->port.info->xmit;
1212 int count;
1213
1214 if (up->port.x_char) {
1215 serial_outp(up, UART_TX, up->port.x_char);
1216 up->port.icount.tx++;
1217 up->port.x_char = 0;
1218 return;
1219 }
b129a8cc
RK		 1220 if (uart_tx_stopped(&up->port)) {
1221 serial8250_stop_tx(&up->port);
1222 return;
1223 }
1224 if (uart_circ_empty(xmit)) {
e763b90c 1225 __stop_tx(up);
1da177e4
LT		 1226 return;
1227 }
1228
1229 count = up->tx_loadsz;
1230 do {
1231 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1232 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1233 up->port.icount.tx++;
1234 if (uart_circ_empty(xmit))
1235 break;
1236 } while (--count > 0);
1237
1238 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1239 uart_write_wakeup(&up->port);
1240
1241 DEBUG_INTR("THRE...");
1242
1243 if (uart_circ_empty(xmit))
e763b90c 1244 __stop_tx(up);
1da177e4
LT		 1245}
1246
2af7cd68 1247static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1248{
2af7cd68
RK		 1249 unsigned int status = serial_in(up, UART_MSR);
1250
1251 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1252 if (status & UART_MSR_TERI)
1253 up->port.icount.rng++;
1254 if (status & UART_MSR_DDSR)
1255 up->port.icount.dsr++;
1256 if (status & UART_MSR_DDCD)
1257 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1258 if (status & UART_MSR_DCTS)
1259 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1260
1261 wake_up_interruptible(&up->port.info->delta_msr_wait);
1262 }
1da177e4 1263
2af7cd68 1264 return status;
1da177e4
LT		 1265}
1266
1267/*
1268 * This handles the interrupt from one port.
1269 */
1270static inline void
1271serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1272{
45e24601
RK		 1273 unsigned int status;
1274
1275 spin_lock(&up->port.lock);
1276
1277 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1278
1279 DEBUG_INTR("status = %x...", status);
1280
1281 if (status & UART_LSR_DR)
1282 receive_chars(up, &status, regs);
1283 check_modem_status(up);
1284 if (status & UART_LSR_THRE)
1285 transmit_chars(up);
45e24601
RK		 1286
1287 spin_unlock(&up->port.lock);
1da177e4
LT		 1288}
1289
1290/*
1291 * This is the serial driver's interrupt routine.
1292 *
1293 * Arjan thinks the old way was overly complex, so it got simplified.
1294 * Alan disagrees, saying that need the complexity to handle the weird
1295 * nature of ISA shared interrupts. (This is a special exception.)
1296 *
1297 * In order to handle ISA shared interrupts properly, we need to check
1298 * that all ports have been serviced, and therefore the ISA interrupt
1299 * line has been de-asserted.
1300 *
1301 * This means we need to loop through all ports. checking that they
1302 * don't have an interrupt pending.
1303 */
1304static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1305{
1306 struct irq_info *i = dev_id;
1307 struct list_head *l, *end = NULL;
1308 int pass_counter = 0, handled = 0;
1309
1310 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1311
1312 spin_lock(&i->lock);
1313
1314 l = i->head;
1315 do {
1316 struct uart_8250_port *up;
1317 unsigned int iir;
1318
1319 up = list_entry(l, struct uart_8250_port, list);
1320
1321 iir = serial_in(up, UART_IIR);
1322 if (!(iir & UART_IIR_NO_INT)) {
1da177e4 1323 serial8250_handle_port(up, regs);
1da177e4
LT		 1324
1325 handled = 1;
1326
1327 end = NULL;
1328 } else if (end == NULL)
1329 end = l;
1330
1331 l = l->next;
1332
1333 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1334 /* If we hit this, we're dead. */
1335 printk(KERN_ERR "serial8250: too much work for "
1336 "irq%d\n", irq);
1337 break;
1338 }
1339 } while (l != end);
1340
1341 spin_unlock(&i->lock);
1342
1343 DEBUG_INTR("end.\n");
1344
1345 return IRQ_RETVAL(handled);
1346}
1347
1348/*
1349 * To support ISA shared interrupts, we need to have one interrupt
1350 * handler that ensures that the IRQ line has been deasserted
1351 * before returning. Failing to do this will result in the IRQ
1352 * line being stuck active, and, since ISA irqs are edge triggered,
1353 * no more IRQs will be seen.
1354 */
1355static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1356{
1357 spin_lock_irq(&i->lock);
1358
1359 if (!list_empty(i->head)) {
1360 if (i->head == &up->list)
1361 i->head = i->head->next;
1362 list_del(&up->list);
1363 } else {
1364 BUG_ON(i->head != &up->list);
1365 i->head = NULL;
1366 }
1367
1368 spin_unlock_irq(&i->lock);
1369}
1370
1371static int serial_link_irq_chain(struct uart_8250_port *up)
1372{
1373 struct irq_info *i = irq_lists + up->port.irq;
1374 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1375
1376 spin_lock_irq(&i->lock);
1377
1378 if (i->head) {
1379 list_add(&up->list, i->head);
1380 spin_unlock_irq(&i->lock);
1381
1382 ret = 0;
1383 } else {
1384 INIT_LIST_HEAD(&up->list);
1385 i->head = &up->list;
1386 spin_unlock_irq(&i->lock);
1387
1388 ret = request_irq(up->port.irq, serial8250_interrupt,
1389 irq_flags, "serial", i);
1390 if (ret < 0)
1391 serial_do_unlink(i, up);
1392 }
1393
1394 return ret;
1395}
1396
1397static void serial_unlink_irq_chain(struct uart_8250_port *up)
1398{
1399 struct irq_info *i = irq_lists + up->port.irq;
1400
1401 BUG_ON(i->head == NULL);
1402
1403 if (list_empty(i->head))
1404 free_irq(up->port.irq, i);
1405
1406 serial_do_unlink(i, up);
1407}
1408
1409/*
1410 * This function is used to handle ports that do not have an
1411 * interrupt. This doesn't work very well for 16450's, but gives
1412 * barely passable results for a 16550A. (Although at the expense
1413 * of much CPU overhead).
1414 */
1415static void serial8250_timeout(unsigned long data)
1416{
1417 struct uart_8250_port *up = (struct uart_8250_port *)data;
1418 unsigned int timeout;
1419 unsigned int iir;
1420
1421 iir = serial_in(up, UART_IIR);
45e24601 1422 if (!(iir & UART_IIR_NO_INT))
1da177e4 1423 serial8250_handle_port(up, NULL);
1da177e4
LT		 1424
1425 timeout = up->port.timeout;
1426 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1427 mod_timer(&up->timer, jiffies + timeout);
1428}
1429
1430static unsigned int serial8250_tx_empty(struct uart_port *port)
1431{
1432 struct uart_8250_port *up = (struct uart_8250_port *)port;
1433 unsigned long flags;
1434 unsigned int ret;
1435
1436 spin_lock_irqsave(&up->port.lock, flags);
1437 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1438 spin_unlock_irqrestore(&up->port.lock, flags);
1439
1440 return ret;
1441}
1442
1443static unsigned int serial8250_get_mctrl(struct uart_port *port)
1444{
1445 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1446 unsigned int status;
1da177e4
LT		 1447 unsigned int ret;
1448
2af7cd68 1449 status = check_modem_status(up);
1da177e4
LT		 1450
1451 ret = 0;
1452 if (status & UART_MSR_DCD)
1453 ret |= TIOCM_CAR;
1454 if (status & UART_MSR_RI)
1455 ret |= TIOCM_RNG;
1456 if (status & UART_MSR_DSR)
1457 ret |= TIOCM_DSR;
1458 if (status & UART_MSR_CTS)
1459 ret |= TIOCM_CTS;
1460 return ret;
1461}
1462
1463static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1464{
1465 struct uart_8250_port *up = (struct uart_8250_port *)port;
1466 unsigned char mcr = 0;
1467
1468 if (mctrl & TIOCM_RTS)
1469 mcr |= UART_MCR_RTS;
1470 if (mctrl & TIOCM_DTR)
1471 mcr |= UART_MCR_DTR;
1472 if (mctrl & TIOCM_OUT1)
1473 mcr |= UART_MCR_OUT1;
1474 if (mctrl & TIOCM_OUT2)
1475 mcr |= UART_MCR_OUT2;
1476 if (mctrl & TIOCM_LOOP)
1477 mcr |= UART_MCR_LOOP;
1478
1479 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1480
1481 serial_out(up, UART_MCR, mcr);
1482}
1483
1484static void serial8250_break_ctl(struct uart_port *port, int break_state)
1485{
1486 struct uart_8250_port *up = (struct uart_8250_port *)port;
1487 unsigned long flags;
1488
1489 spin_lock_irqsave(&up->port.lock, flags);
1490 if (break_state == -1)
1491 up->lcr |= UART_LCR_SBC;
1492 else
1493 up->lcr &= ~UART_LCR_SBC;
1494 serial_out(up, UART_LCR, up->lcr);
1495 spin_unlock_irqrestore(&up->port.lock, flags);
1496}
1497
1498static int serial8250_startup(struct uart_port *port)
1499{
1500 struct uart_8250_port *up = (struct uart_8250_port *)port;
1501 unsigned long flags;
55d3b282 1502 unsigned char lsr, iir;
1da177e4
LT		 1503 int retval;
1504
1505 up->capabilities = uart_config[up->port.type].flags;
1506 up->mcr = 0;
1507
1508 if (up->port.type == PORT_16C950) {
1509 /* Wake up and initialize UART */
1510 up->acr = 0;
1511 serial_outp(up, UART_LCR, 0xBF);
1512 serial_outp(up, UART_EFR, UART_EFR_ECB);
1513 serial_outp(up, UART_IER, 0);
1514 serial_outp(up, UART_LCR, 0);
1515 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1516 serial_outp(up, UART_LCR, 0xBF);
1517 serial_outp(up, UART_EFR, UART_EFR_ECB);
1518 serial_outp(up, UART_LCR, 0);
1519 }
1520
1521#ifdef CONFIG_SERIAL_8250_RSA
1522 /*
1523 * If this is an RSA port, see if we can kick it up to the
1524 * higher speed clock.
1525 */
1526 enable_rsa(up);
1527#endif
1528
1529 /*
1530 * Clear the FIFO buffers and disable them.
7f927fcc 1531 * (they will be reenabled in set_termios())
1da177e4
LT		 1532 */
1533 serial8250_clear_fifos(up);
1534
1535 /*
1536 * Clear the interrupt registers.
1537 */
1538 (void) serial_inp(up, UART_LSR);
1539 (void) serial_inp(up, UART_RX);
1540 (void) serial_inp(up, UART_IIR);
1541 (void) serial_inp(up, UART_MSR);
1542
1543 /*
1544 * At this point, there's no way the LSR could still be 0xff;
1545 * if it is, then bail out, because there's likely no UART
1546 * here.
1547 */
1548 if (!(up->port.flags & UPF_BUGGY_UART) &&
1549 (serial_inp(up, UART_LSR) == 0xff)) {
1550 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1551 return -ENODEV;
1552 }
1553
1554 /*
1555 * For a XR16C850, we need to set the trigger levels
1556 */
1557 if (up->port.type == PORT_16850) {
1558 unsigned char fctr;
1559
1560 serial_outp(up, UART_LCR, 0xbf);
1561
1562 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1563 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1564 serial_outp(up, UART_TRG, UART_TRG_96);
1565 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1566 serial_outp(up, UART_TRG, UART_TRG_96);
1567
1568 serial_outp(up, UART_LCR, 0);
1569 }
1570
1571 /*
1572 * If the "interrupt" for this port doesn't correspond with any
1573 * hardware interrupt, we use a timer-based system. The original
1574 * driver used to do this with IRQ0.
1575 */
1576 if (!is_real_interrupt(up->port.irq)) {
1577 unsigned int timeout = up->port.timeout;
1578
1579 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1580
1581 up->timer.data = (unsigned long)up;
1582 mod_timer(&up->timer, jiffies + timeout);
1583 } else {
1584 retval = serial_link_irq_chain(up);
1585 if (retval)
1586 return retval;
1587 }
1588
1589 /*
1590 * Now, initialize the UART
1591 */
1592 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1593
1594 spin_lock_irqsave(&up->port.lock, flags);
1595 if (up->port.flags & UPF_FOURPORT) {
1596 if (!is_real_interrupt(up->port.irq))
1597 up->port.mctrl |= TIOCM_OUT1;
1598 } else
1599 /*
1600 * Most PC uarts need OUT2 raised to enable interrupts.
1601 */
1602 if (is_real_interrupt(up->port.irq))
1603 up->port.mctrl |= TIOCM_OUT2;
1604
1605 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1606
1607 /*
1608 * Do a quick test to see if we receive an
1609 * interrupt when we enable the TX irq.
1610 */
1611 serial_outp(up, UART_IER, UART_IER_THRI);
1612 lsr = serial_in(up, UART_LSR);
1613 iir = serial_in(up, UART_IIR);
1614 serial_outp(up, UART_IER, 0);
1615
1616 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1617 if (!(up->bugs & UART_BUG_TXEN)) {
1618 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1619 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1620 port->line);
1621 }
1622 } else {
67f7654e 1623 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1624 }
1625
1da177e4
LT		 1626 spin_unlock_irqrestore(&up->port.lock, flags);
1627
1628 /*
1629 * Finally, enable interrupts. Note: Modem status interrupts
1630 * are set via set_termios(), which will be occurring imminently
1631 * anyway, so we don't enable them here.
1632 */
1633 up->ier = UART_IER_RLSI | UART_IER_RDI;
1634 serial_outp(up, UART_IER, up->ier);
1635
1636 if (up->port.flags & UPF_FOURPORT) {
1637 unsigned int icp;
1638 /*
1639 * Enable interrupts on the AST Fourport board
1640 */
1641 icp = (up->port.iobase & 0xfe0) | 0x01f;
1642 outb_p(0x80, icp);
1643 (void) inb_p(icp);
1644 }
1645
1646 /*
1647 * And clear the interrupt registers again for luck.
1648 */
1649 (void) serial_inp(up, UART_LSR);
1650 (void) serial_inp(up, UART_RX);
1651 (void) serial_inp(up, UART_IIR);
1652 (void) serial_inp(up, UART_MSR);
1653
1654 return 0;
1655}
1656
1657static void serial8250_shutdown(struct uart_port *port)
1658{
1659 struct uart_8250_port *up = (struct uart_8250_port *)port;
1660 unsigned long flags;
1661
1662 /*
1663 * Disable interrupts from this port
1664 */
1665 up->ier = 0;
1666 serial_outp(up, UART_IER, 0);
1667
1668 spin_lock_irqsave(&up->port.lock, flags);
1669 if (up->port.flags & UPF_FOURPORT) {
1670 /* reset interrupts on the AST Fourport board */
1671 inb((up->port.iobase & 0xfe0) | 0x1f);
1672 up->port.mctrl |= TIOCM_OUT1;
1673 } else
1674 up->port.mctrl &= ~TIOCM_OUT2;
1675
1676 serial8250_set_mctrl(&up->port, up->port.mctrl);
1677 spin_unlock_irqrestore(&up->port.lock, flags);
1678
1679 /*
1680 * Disable break condition and FIFOs
1681 */
1682 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1683 serial8250_clear_fifos(up);
1684
1685#ifdef CONFIG_SERIAL_8250_RSA
1686 /*
1687 * Reset the RSA board back to 115kbps compat mode.
1688 */
1689 disable_rsa(up);
1690#endif
1691
1692 /*
1693 * Read data port to reset things, and then unlink from
1694 * the IRQ chain.
1695 */
1696 (void) serial_in(up, UART_RX);
1697
1698 if (!is_real_interrupt(up->port.irq))
1699 del_timer_sync(&up->timer);
1700 else
1701 serial_unlink_irq_chain(up);
1702}
1703
1704static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1705{
1706 unsigned int quot;
1707
1708 /*
1709 * Handle magic divisors for baud rates above baud_base on
1710 * SMSC SuperIO chips.
1711 */
1712 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1713 baud == (port->uartclk/4))
1714 quot = 0x8001;
1715 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1716 baud == (port->uartclk/8))
1717 quot = 0x8002;
1718 else
1719 quot = uart_get_divisor(port, baud);
1720
1721 return quot;
1722}
1723
1724static void
1725serial8250_set_termios(struct uart_port *port, struct termios *termios,
1726 struct termios *old)
1727{
1728 struct uart_8250_port *up = (struct uart_8250_port *)port;
1729 unsigned char cval, fcr = 0;
1730 unsigned long flags;
1731 unsigned int baud, quot;
1732
1733 switch (termios->c_cflag & CSIZE) {
1734 case CS5:
0a8b80c5 1735 cval = UART_LCR_WLEN5;
1da177e4
LT		 1736 break;
1737 case CS6:
0a8b80c5 1738 cval = UART_LCR_WLEN6;
1da177e4
LT		 1739 break;
1740 case CS7:
0a8b80c5 1741 cval = UART_LCR_WLEN7;
1da177e4
LT		 1742 break;
1743 default:
1744 case CS8:
0a8b80c5 1745 cval = UART_LCR_WLEN8;
1da177e4
LT		 1746 break;
1747 }
1748
1749 if (termios->c_cflag & CSTOPB)
0a8b80c5 1750 cval |= UART_LCR_STOP;
1da177e4
LT		 1751 if (termios->c_cflag & PARENB)
1752 cval |= UART_LCR_PARITY;
1753 if (!(termios->c_cflag & PARODD))
1754 cval |= UART_LCR_EPAR;
1755#ifdef CMSPAR
1756 if (termios->c_cflag & CMSPAR)
1757 cval |= UART_LCR_SPAR;
1758#endif
1759
1760 /*
1761 * Ask the core to calculate the divisor for us.
1762 */
1763 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1764 quot = serial8250_get_divisor(port, baud);
1765
1766 /*
4ba5e35d 1767 * Oxford Semi 952 rev B workaround
1da177e4 1768 */
4ba5e35d 1769 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1770 quot ++;
1771
1772 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1773 if (baud < 2400)
1774 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1775 else
1776 fcr = uart_config[up->port.type].fcr;
1777 }
1778
1779 /*
1780 * MCR-based auto flow control. When AFE is enabled, RTS will be
1781 * deasserted when the receive FIFO contains more characters than
1782 * the trigger, or the MCR RTS bit is cleared. In the case where
1783 * the remote UART is not using CTS auto flow control, we must
1784 * have sufficient FIFO entries for the latency of the remote
1785 * UART to respond. IOW, at least 32 bytes of FIFO.
1786 */
1787 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1788 up->mcr &= ~UART_MCR_AFE;
1789 if (termios->c_cflag & CRTSCTS)
1790 up->mcr |= UART_MCR_AFE;
1791 }
1792
1793 /*
1794 * Ok, we're now changing the port state. Do it with
1795 * interrupts disabled.
1796 */
1797 spin_lock_irqsave(&up->port.lock, flags);
1798
1799 /*
1800 * Update the per-port timeout.
1801 */
1802 uart_update_timeout(port, termios->c_cflag, baud);
1803
1804 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1805 if (termios->c_iflag & INPCK)
1806 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1807 if (termios->c_iflag & (BRKINT | PARMRK))
1808 up->port.read_status_mask |= UART_LSR_BI;
1809
1810 /*
1811 * Characteres to ignore
1812 */
1813 up->port.ignore_status_mask = 0;
1814 if (termios->c_iflag & IGNPAR)
1815 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1816 if (termios->c_iflag & IGNBRK) {
1817 up->port.ignore_status_mask |= UART_LSR_BI;
1818 /*
1819 * If we're ignoring parity and break indicators,
1820 * ignore overruns too (for real raw support).
1821 */
1822 if (termios->c_iflag & IGNPAR)
1823 up->port.ignore_status_mask |= UART_LSR_OE;
1824 }
1825
1826 /*
1827 * ignore all characters if CREAD is not set
1828 */
1829 if ((termios->c_cflag & CREAD) == 0)
1830 up->port.ignore_status_mask |= UART_LSR_DR;
1831
1832 /*
1833 * CTS flow control flag and modem status interrupts
1834 */
1835 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1836 if (!(up->bugs & UART_BUG_NOMSR) &&
1837 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1838 up->ier |= UART_IER_MSI;
1839 if (up->capabilities & UART_CAP_UUE)
1840 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1841
1842 serial_out(up, UART_IER, up->ier);
1843
1844 if (up->capabilities & UART_CAP_EFR) {
1845 unsigned char efr = 0;
1846 /*
1847 * TI16C752/Startech hardware flow control. FIXME:
1848 * - TI16C752 requires control thresholds to be set.
1849 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1850 */
1851 if (termios->c_cflag & CRTSCTS)
1852 efr |= UART_EFR_CTS;
1853
1854 serial_outp(up, UART_LCR, 0xBF);
1855 serial_outp(up, UART_EFR, efr);
1856 }
1857
1858 if (up->capabilities & UART_NATSEMI) {
1859 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1860 serial_outp(up, UART_LCR, 0xe0);
1861 } else {
1862 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1863 }
1864
1865 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1866 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1867
1868 /*
1869 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1870 * is written without DLAB set, this mode will be disabled.
1871 */
1872 if (up->port.type == PORT_16750)
1873 serial_outp(up, UART_FCR, fcr);
1874
1875 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1876 up->lcr = cval; /* Save LCR */
1877 if (up->port.type != PORT_16750) {
1878 if (fcr & UART_FCR_ENABLE_FIFO) {
1879 /* emulated UARTs (Lucent Venus 167x) need two steps */
1880 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1881 }
1882 serial_outp(up, UART_FCR, fcr); /* set fcr */
1883 }
1884 serial8250_set_mctrl(&up->port, up->port.mctrl);
1885 spin_unlock_irqrestore(&up->port.lock, flags);
1886}
1887
1888static void
1889serial8250_pm(struct uart_port *port, unsigned int state,
1890 unsigned int oldstate)
1891{
1892 struct uart_8250_port *p = (struct uart_8250_port *)port;
1893
1894 serial8250_set_sleep(p, state != 0);
1895
1896 if (p->pm)
1897 p->pm(port, state, oldstate);
1898}
1899
1900/*
1901 * Resource handling.
1902 */
1903static int serial8250_request_std_resource(struct uart_8250_port *up)
1904{
1905 unsigned int size = 8 << up->port.regshift;
1906 int ret = 0;
1907
1908 switch (up->port.iotype) {
1909 case UPIO_MEM:
1910 if (!up->port.mapbase)
1911 break;
1912
1913 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1914 ret = -EBUSY;
1915 break;
1916 }
1917
1918 if (up->port.flags & UPF_IOREMAP) {
1919 up->port.membase = ioremap(up->port.mapbase, size);
1920 if (!up->port.membase) {
1921 release_mem_region(up->port.mapbase, size);
1922 ret = -ENOMEM;
1923 }
1924 }
1925 break;
1926
1927 case UPIO_HUB6:
1928 case UPIO_PORT:
1929 if (!request_region(up->port.iobase, size, "serial"))
1930 ret = -EBUSY;
1931 break;
1932 }
1933 return ret;
1934}
1935
1936static void serial8250_release_std_resource(struct uart_8250_port *up)
1937{
1938 unsigned int size = 8 << up->port.regshift;
1939
1940 switch (up->port.iotype) {
1941 case UPIO_MEM:
1942 if (!up->port.mapbase)
1943 break;
1944
1945 if (up->port.flags & UPF_IOREMAP) {
1946 iounmap(up->port.membase);
1947 up->port.membase = NULL;
1948 }
1949
1950 release_mem_region(up->port.mapbase, size);
1951 break;
1952
1953 case UPIO_HUB6:
1954 case UPIO_PORT:
1955 release_region(up->port.iobase, size);
1956 break;
1957 }
1958}
1959
1960static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1961{
1962 unsigned long start = UART_RSA_BASE << up->port.regshift;
1963 unsigned int size = 8 << up->port.regshift;
1964 int ret = 0;
1965
1966 switch (up->port.iotype) {
1967 case UPIO_MEM:
1968 ret = -EINVAL;
1969 break;
1970
1971 case UPIO_HUB6:
1972 case UPIO_PORT:
1973 start += up->port.iobase;
1974 if (!request_region(start, size, "serial-rsa"))
1975 ret = -EBUSY;
1976 break;
1977 }
1978
1979 return ret;
1980}
1981
1982static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1983{
1984 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1985 unsigned int size = 8 << up->port.regshift;
1986
1987 switch (up->port.iotype) {
1988 case UPIO_MEM:
1989 break;
1990
1991 case UPIO_HUB6:
1992 case UPIO_PORT:
1993 release_region(up->port.iobase + offset, size);
1994 break;
1995 }
1996}
1997
1998static void serial8250_release_port(struct uart_port *port)
1999{
2000 struct uart_8250_port *up = (struct uart_8250_port *)port;
2001
2002 serial8250_release_std_resource(up);
2003 if (up->port.type == PORT_RSA)
2004 serial8250_release_rsa_resource(up);
2005}
2006
2007static int serial8250_request_port(struct uart_port *port)
2008{
2009 struct uart_8250_port *up = (struct uart_8250_port *)port;
2010 int ret = 0;
2011
2012 ret = serial8250_request_std_resource(up);
2013 if (ret == 0 && up->port.type == PORT_RSA) {
2014 ret = serial8250_request_rsa_resource(up);
2015 if (ret < 0)
2016 serial8250_release_std_resource(up);
2017 }
2018
2019 return ret;
2020}
2021
2022static void serial8250_config_port(struct uart_port *port, int flags)
2023{
2024 struct uart_8250_port *up = (struct uart_8250_port *)port;
2025 int probeflags = PROBE_ANY;
2026 int ret;
2027
1da177e4
LT		 2028 /*
2029 * Find the region that we can probe for. This in turn
2030 * tells us whether we can probe for the type of port.
2031 */
2032 ret = serial8250_request_std_resource(up);
2033 if (ret < 0)
2034 return;
2035
2036 ret = serial8250_request_rsa_resource(up);
2037 if (ret < 0)
2038 probeflags &= ~PROBE_RSA;
2039
2040 if (flags & UART_CONFIG_TYPE)
2041 autoconfig(up, probeflags);
2042 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2043 autoconfig_irq(up);
2044
2045 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2046 serial8250_release_rsa_resource(up);
2047 if (up->port.type == PORT_UNKNOWN)
2048 serial8250_release_std_resource(up);
2049}
2050
2051static int
2052serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2053{
2054 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2055 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2056 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2057 ser->type == PORT_STARTECH)
2058 return -EINVAL;
2059 return 0;
2060}
2061
2062static const char *
2063serial8250_type(struct uart_port *port)
2064{
2065 int type = port->type;
2066
2067 if (type >= ARRAY_SIZE(uart_config))
2068 type = 0;
2069 return uart_config[type].name;
2070}
2071
2072static struct uart_ops serial8250_pops = {
2073 .tx_empty = serial8250_tx_empty,
2074 .set_mctrl = serial8250_set_mctrl,
2075 .get_mctrl = serial8250_get_mctrl,
2076 .stop_tx = serial8250_stop_tx,
2077 .start_tx = serial8250_start_tx,
2078 .stop_rx = serial8250_stop_rx,
2079 .enable_ms = serial8250_enable_ms,
2080 .break_ctl = serial8250_break_ctl,
2081 .startup = serial8250_startup,
2082 .shutdown = serial8250_shutdown,
2083 .set_termios = serial8250_set_termios,
2084 .pm = serial8250_pm,
2085 .type = serial8250_type,
2086 .release_port = serial8250_release_port,
2087 .request_port = serial8250_request_port,
2088 .config_port = serial8250_config_port,
2089 .verify_port = serial8250_verify_port,
2090};
2091
2092static struct uart_8250_port serial8250_ports[UART_NR];
2093
2094static void __init serial8250_isa_init_ports(void)
2095{
2096 struct uart_8250_port *up;
2097 static int first = 1;
2098 int i;
2099
2100 if (!first)
2101 return;
2102 first = 0;
2103
a61c2d78 2104 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2105 struct uart_8250_port *up = &serial8250_ports[i];
2106
2107 up->port.line = i;
2108 spin_lock_init(&up->port.lock);
2109
2110 init_timer(&up->timer);
2111 up->timer.function = serial8250_timeout;
2112
2113 /*
2114 * ALPHA_KLUDGE_MCR needs to be killed.
2115 */
2116 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2117 up->mcr_force = ALPHA_KLUDGE_MCR;
2118
2119 up->port.ops = &serial8250_pops;
2120 }
2121
44454bcd 2122 for (i = 0, up = serial8250_ports;
a61c2d78 2123 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2124 i++, up++) {
2125 up->port.iobase = old_serial_port[i].port;
2126 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2127 up->port.uartclk = old_serial_port[i].baud_base * 16;
2128 up->port.flags = old_serial_port[i].flags;
2129 up->port.hub6 = old_serial_port[i].hub6;
2130 up->port.membase = old_serial_port[i].iomem_base;
2131 up->port.iotype = old_serial_port[i].io_type;
2132 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2133 if (share_irqs)
2134 up->port.flags |= UPF_SHARE_IRQ;
2135 }
2136}
2137
2138static void __init
2139serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2140{
2141 int i;
2142
2143 serial8250_isa_init_ports();
2144
a61c2d78 2145 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2146 struct uart_8250_port *up = &serial8250_ports[i];
2147
2148 up->port.dev = dev;
2149 uart_add_one_port(drv, &up->port);
2150 }
2151}
2152
2153#ifdef CONFIG_SERIAL_8250_CONSOLE
2154
2155#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2156
2157/*
2158 * Wait for transmitter & holding register to empty
2159 */
f91a3715 2160static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1da177e4
LT		 2161{
2162 unsigned int status, tmout = 10000;
2163
2164 /* Wait up to 10ms for the character(s) to be sent. */
2165 do {
2166 status = serial_in(up, UART_LSR);
2167
2168 if (status & UART_LSR_BI)
2169 up->lsr_break_flag = UART_LSR_BI;
2170
2171 if (--tmout == 0)
2172 break;
2173 udelay(1);
f91a3715 2174 } while ((status & bits) != bits);
1da177e4
LT		 2175
2176 /* Wait up to 1s for flow control if necessary */
2177 if (up->port.flags & UPF_CONS_FLOW) {
2178 tmout = 1000000;
2179 while (--tmout &&
2180 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2181 udelay(1);
2182 }
2183}
2184
d358788f
RK		 2185static void serial8250_console_putchar(struct uart_port *port, int ch)
2186{
2187 struct uart_8250_port *up = (struct uart_8250_port *)port;
2188
2189 wait_for_xmitr(up, UART_LSR_THRE);
2190 serial_out(up, UART_TX, ch);
2191}
2192
1da177e4
LT		 2193/*
2194 * Print a string to the serial port trying not to disturb
2195 * any possible real use of the port...
2196 *
2197 * The console_lock must be held when we get here.
2198 */
2199static void
2200serial8250_console_write(struct console *co, const char *s, unsigned int count)
2201{
2202 struct uart_8250_port *up = &serial8250_ports[co->index];
2203 unsigned int ier;
1da177e4 2204
78512ece
AM		 2205 touch_nmi_watchdog();
2206
1da177e4 2207 /*
dc7bf130 2208 * First save the IER then disable the interrupts
1da177e4
LT		 2209 */
2210 ier = serial_in(up, UART_IER);
2211
2212 if (up->capabilities & UART_CAP_UUE)
2213 serial_out(up, UART_IER, UART_IER_UUE);
2214 else
2215 serial_out(up, UART_IER, 0);
2216
d358788f 2217 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2218
2219 /*
2220 * Finally, wait for transmitter to become empty
2221 * and restore the IER
2222 */
f91a3715 2223 wait_for_xmitr(up, BOTH_EMPTY);
f5968b37 2224 up->ier |= UART_IER_THRI;
f91a3715 2225 serial_out(up, UART_IER, ier | UART_IER_THRI);
1da177e4
LT		 2226}
2227
2228static int serial8250_console_setup(struct console *co, char *options)
2229{
2230 struct uart_port *port;
2231 int baud = 9600;
2232 int bits = 8;
2233 int parity = 'n';
2234 int flow = 'n';
2235
2236 /*
2237 * Check whether an invalid uart number has been specified, and
2238 * if so, search for the first available port that does have
2239 * console support.
2240 */
a61c2d78 2241 if (co->index >= nr_uarts)
1da177e4
LT		 2242 co->index = 0;
2243 port = &serial8250_ports[co->index].port;
2244 if (!port->iobase && !port->membase)
2245 return -ENODEV;
2246
2247 if (options)
2248 uart_parse_options(options, &baud, &parity, &bits, &flow);
2249
2250 return uart_set_options(port, co, baud, parity, bits, flow);
2251}
2252
2253static struct uart_driver serial8250_reg;
2254static struct console serial8250_console = {
2255 .name = "ttyS",
2256 .write = serial8250_console_write,
2257 .device = uart_console_device,
2258 .setup = serial8250_console_setup,
2259 .flags = CON_PRINTBUFFER,
2260 .index = -1,
2261 .data = &serial8250_reg,
2262};
2263
2264static int __init serial8250_console_init(void)
2265{
2266 serial8250_isa_init_ports();
2267 register_console(&serial8250_console);
2268 return 0;
2269}
2270console_initcall(serial8250_console_init);
2271
2272static int __init find_port(struct uart_port *p)
2273{
2274 int line;
2275 struct uart_port *port;
2276
a61c2d78 2277 for (line = 0; line < nr_uarts; line++) {
1da177e4 2278 port = &serial8250_ports[line].port;
50aec3b5 2279 if (uart_match_port(p, port))
1da177e4
LT		 2280 return line;
2281 }
2282 return -ENODEV;
2283}
2284
2285int __init serial8250_start_console(struct uart_port *port, char *options)
2286{
2287 int line;
2288
2289 line = find_port(port);
2290 if (line < 0)
2291 return -ENODEV;
2292
2293 add_preferred_console("ttyS", line, options);
2294 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2295 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2296 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2297 (unsigned long) port->iobase, options);
2298 if (!(serial8250_console.flags & CON_ENABLED)) {
2299 serial8250_console.flags &= ~CON_PRINTBUFFER;
2300 register_console(&serial8250_console);
2301 }
2302 return line;
2303}
2304
2305#define SERIAL8250_CONSOLE &serial8250_console
2306#else
2307#define SERIAL8250_CONSOLE NULL
2308#endif
2309
2310static struct uart_driver serial8250_reg = {
2311 .owner = THIS_MODULE,
2312 .driver_name = "serial",
2313 .devfs_name = "tts/",
2314 .dev_name = "ttyS",
2315 .major = TTY_MAJOR,
2316 .minor = 64,
2317 .nr = UART_NR,
2318 .cons = SERIAL8250_CONSOLE,
2319};
2320
d856c666
RK		 2321/*
2322 * early_serial_setup - early registration for 8250 ports
2323 *
2324 * Setup an 8250 port structure prior to console initialisation. Use
2325 * after console initialisation will cause undefined behaviour.
2326 */
1da177e4
LT		 2327int __init early_serial_setup(struct uart_port *port)
2328{
2329 if (port->line >= ARRAY_SIZE(serial8250_ports))
2330 return -ENODEV;
2331
2332 serial8250_isa_init_ports();
2333 serial8250_ports[port->line].port = *port;
2334 serial8250_ports[port->line].port.ops = &serial8250_pops;
2335 return 0;
2336}
2337
2338/**
2339 * serial8250_suspend_port - suspend one serial port
2340 * @line: serial line number
2341 * @level: the level of port suspension, as per uart_suspend_port
2342 *
2343 * Suspend one serial port.
2344 */
2345void serial8250_suspend_port(int line)
2346{
2347 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2348}
2349
2350/**
2351 * serial8250_resume_port - resume one serial port
2352 * @line: serial line number
2353 * @level: the level of port resumption, as per uart_resume_port
2354 *
2355 * Resume one serial port.
2356 */
2357void serial8250_resume_port(int line)
2358{
2359 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2360}
2361
2362/*
2363 * Register a set of serial devices attached to a platform device. The
2364 * list is terminated with a zero flags entry, which means we expect
2365 * all entries to have at least UPF_BOOT_AUTOCONF set.
2366 */
3ae5eaec 2367static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2368{
3ae5eaec 2369 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2370 struct uart_port port;
ec9f47cd 2371 int ret, i;
1da177e4
LT		 2372
2373 memset(&port, 0, sizeof(struct uart_port));
2374
ec9f47cd 2375 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2376 port.iobase = p->iobase;
2377 port.membase = p->membase;
2378 port.irq = p->irq;
2379 port.uartclk = p->uartclk;
2380 port.regshift = p->regshift;
2381 port.iotype = p->iotype;
2382 port.flags = p->flags;
2383 port.mapbase = p->mapbase;
ec9f47cd 2384 port.hub6 = p->hub6;
3ae5eaec 2385 port.dev = &dev->dev;
1da177e4
LT		 2386 if (share_irqs)
2387 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2388 ret = serial8250_register_port(&port);
2389 if (ret < 0) {
3ae5eaec 2390 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2391 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2392 p->iobase, p->mapbase, p->irq, ret);
2393 }
1da177e4
LT		 2394 }
2395 return 0;
2396}
2397
2398/*
2399 * Remove serial ports registered against a platform device.
2400 */
3ae5eaec 2401static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2402{
2403 int i;
2404
a61c2d78 2405 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2406 struct uart_8250_port *up = &serial8250_ports[i];
2407
3ae5eaec 2408 if (up->port.dev == &dev->dev)
1da177e4
LT		 2409 serial8250_unregister_port(i);
2410 }
2411 return 0;
2412}
2413
3ae5eaec 2414static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2415{
2416 int i;
2417
1da177e4
LT		 2418 for (i = 0; i < UART_NR; i++) {
2419 struct uart_8250_port *up = &serial8250_ports[i];
2420
3ae5eaec 2421 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2422 uart_suspend_port(&serial8250_reg, &up->port);
2423 }
2424
2425 return 0;
2426}
2427
3ae5eaec 2428static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2429{
2430 int i;
2431
1da177e4
LT		 2432 for (i = 0; i < UART_NR; i++) {
2433 struct uart_8250_port *up = &serial8250_ports[i];
2434
3ae5eaec 2435 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2436 uart_resume_port(&serial8250_reg, &up->port);
2437 }
2438
2439 return 0;
2440}
2441
3ae5eaec 2442static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2443 .probe = serial8250_probe,
2444 .remove = __devexit_p(serial8250_remove),
2445 .suspend = serial8250_suspend,
2446 .resume = serial8250_resume,
3ae5eaec
RK		 2447 .driver = {
2448 .name = "serial8250",
7493a314 2449 .owner = THIS_MODULE,
3ae5eaec 2450 },
1da177e4
LT		 2451};
2452
2453/*
2454 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2455 * in the table in include/asm/serial.h
2456 */
2457static struct platform_device *serial8250_isa_devs;
2458
2459/*
2460 * serial8250_register_port and serial8250_unregister_port allows for
2461 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2462 * modems and PCI multiport cards.
2463 */
f392ecfa 2464static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2465
2466static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2467{
2468 int i;
2469
2470 /*
2471 * First, find a port entry which matches.
2472 */
a61c2d78 2473 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2474 if (uart_match_port(&serial8250_ports[i].port, port))
2475 return &serial8250_ports[i];
2476
2477 /*
2478 * We didn't find a matching entry, so look for the first
2479 * free entry. We look for one which hasn't been previously
2480 * used (indicated by zero iobase).
2481 */
a61c2d78 2482 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2483 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2484 serial8250_ports[i].port.iobase == 0)
2485 return &serial8250_ports[i];
2486
2487 /*
2488 * That also failed. Last resort is to find any entry which
2489 * doesn't have a real port associated with it.
2490 */
a61c2d78 2491 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2492 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2493 return &serial8250_ports[i];
2494
2495 return NULL;
2496}
2497
2498/**
2499 * serial8250_register_port - register a serial port
2500 * @port: serial port template
2501 *
2502 * Configure the serial port specified by the request. If the
2503 * port exists and is in use, it is hung up and unregistered
2504 * first.
2505 *
2506 * The port is then probed and if necessary the IRQ is autodetected
2507 * If this fails an error is returned.
2508 *
2509 * On success the port is ready to use and the line number is returned.
2510 */
2511int serial8250_register_port(struct uart_port *port)
2512{
2513 struct uart_8250_port *uart;
2514 int ret = -ENOSPC;
2515
2516 if (port->uartclk == 0)
2517 return -EINVAL;
2518
f392ecfa 2519 mutex_lock(&serial_mutex);
1da177e4
LT		 2520
2521 uart = serial8250_find_match_or_unused(port);
2522 if (uart) {
2523 uart_remove_one_port(&serial8250_reg, &uart->port);
2524
2525 uart->port.iobase = port->iobase;
2526 uart->port.membase = port->membase;
2527 uart->port.irq = port->irq;
2528 uart->port.uartclk = port->uartclk;
2529 uart->port.fifosize = port->fifosize;
2530 uart->port.regshift = port->regshift;
2531 uart->port.iotype = port->iotype;
2532 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2533 uart->port.mapbase = port->mapbase;
2534 if (port->dev)
2535 uart->port.dev = port->dev;
2536
2537 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2538 if (ret == 0)
2539 ret = uart->port.line;
2540 }
f392ecfa 2541 mutex_unlock(&serial_mutex);
1da177e4
LT		 2542
2543 return ret;
2544}
2545EXPORT_SYMBOL(serial8250_register_port);
2546
2547/**
2548 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2549 * @line: serial line number
2550 *
2551 * Remove one serial port. This may not be called from interrupt
2552 * context. We hand the port back to the our control.
2553 */
2554void serial8250_unregister_port(int line)
2555{
2556 struct uart_8250_port *uart = &serial8250_ports[line];
2557
f392ecfa 2558 mutex_lock(&serial_mutex);
1da177e4
LT		 2559 uart_remove_one_port(&serial8250_reg, &uart->port);
2560 if (serial8250_isa_devs) {
2561 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2562 uart->port.type = PORT_UNKNOWN;
2563 uart->port.dev = &serial8250_isa_devs->dev;
2564 uart_add_one_port(&serial8250_reg, &uart->port);
2565 } else {
2566 uart->port.dev = NULL;
2567 }
f392ecfa 2568 mutex_unlock(&serial_mutex);
1da177e4
LT		 2569}
2570EXPORT_SYMBOL(serial8250_unregister_port);
2571
2572static int __init serial8250_init(void)
2573{
2574 int ret, i;
2575
a61c2d78
DJ		 2576 if (nr_uarts > UART_NR)
2577 nr_uarts = UART_NR;
2578
1da177e4 2579 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2580 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2581 share_irqs ? "en" : "dis");
2582
2583 for (i = 0; i < NR_IRQS; i++)
2584 spin_lock_init(&irq_lists[i].lock);
2585
2586 ret = uart_register_driver(&serial8250_reg);
2587 if (ret)
2588 goto out;
2589
7493a314
DT		 2590 serial8250_isa_devs = platform_device_alloc("serial8250",
2591 PLAT8250_DEV_LEGACY);
2592 if (!serial8250_isa_devs) {
2593 ret = -ENOMEM;
bc965a7f 2594 goto unreg_uart_drv;
1da177e4
LT		 2595 }
2596
7493a314
DT		 2597 ret = platform_device_add(serial8250_isa_devs);
2598 if (ret)
2599 goto put_dev;
2600
1da177e4
LT		 2601 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2602
bc965a7f
RK		 2603 ret = platform_driver_register(&serial8250_isa_driver);
2604 if (ret == 0)
2605 goto out;
1da177e4 2606
bc965a7f 2607 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2608 put_dev:
2609 platform_device_put(serial8250_isa_devs);
7493a314 2610 unreg_uart_drv:
1da177e4
LT		 2611 uart_unregister_driver(&serial8250_reg);
2612 out:
2613 return ret;
2614}
2615
2616static void __exit serial8250_exit(void)
2617{
2618 struct platform_device *isa_dev = serial8250_isa_devs;
2619
2620 /*
2621 * This tells serial8250_unregister_port() not to re-register
2622 * the ports (thereby making serial8250_isa_driver permanently
2623 * in use.)
2624 */
2625 serial8250_isa_devs = NULL;
2626
3ae5eaec 2627 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2628 platform_device_unregister(isa_dev);
2629
2630 uart_unregister_driver(&serial8250_reg);
2631}
2632
2633module_init(serial8250_init);
2634module_exit(serial8250_exit);
2635
2636EXPORT_SYMBOL(serial8250_suspend_port);
2637EXPORT_SYMBOL(serial8250_resume_port);
2638
2639MODULE_LICENSE("GPL");
2640MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2641
2642module_param(share_irqs, uint, 0644);
2643MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2644 " (unsafe)");
2645
a61c2d78
DJ		 2646module_param(nr_uarts, uint, 0644);
2647MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2648
1da177e4
LT		 2649#ifdef CONFIG_SERIAL_8250_RSA
2650module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2651MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2652#endif
2653MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Clone of davem's net-next-2.6 tree