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1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
1da177e4
LT		 22
23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
1da177e4 33#include <linux/delay.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4
LT		 35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_reg.h>
38#include <linux/serial_core.h>
39#include <linux/serial.h>
40#include <linux/serial_8250.h>
78512ece 41#include <linux/nmi.h>
f392ecfa 42#include <linux/mutex.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
40663cc7 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 55
a61c2d78
DJ		 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
1da177e4
LT		 58/*
59 * Debugging.
60 */
61#if 0
62#define DEBUG_AUTOCONF(fmt...) printk(fmt)
63#else
64#define DEBUG_AUTOCONF(fmt...) do { } while (0)
65#endif
66
67#if 0
68#define DEBUG_INTR(fmt...) printk(fmt)
69#else
70#define DEBUG_INTR(fmt...) do { } while (0)
71#endif
72
73#define PASS_LIMIT 256
74
75/*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80#define is_real_interrupt(irq) ((irq) != 0)
81
1da177e4
LT		 82#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83#define CONFIG_SERIAL_DETECT_IRQ 1
84#endif
1da177e4
LT		 85#ifdef CONFIG_SERIAL_8250_MANY_PORTS
86#define CONFIG_SERIAL_MANY_PORTS 1
87#endif
88
89/*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93#define CONFIG_HUB6 1
94
a4ed1e41 95#include <asm/serial.h>
1da177e4
LT		 96/*
97 * SERIAL_PORT_DFNS tells us about built-in ports that have no
98 * standard enumeration mechanism. Platforms that can find all
99 * serial ports via mechanisms like ACPI or PCI need not supply it.
100 */
101#ifndef SERIAL_PORT_DFNS
102#define SERIAL_PORT_DFNS
103#endif
104
cb3592be 105static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 106 SERIAL_PORT_DFNS /* defined in asm/serial.h */
107};
108
026d02a2 109#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 110
111#ifdef CONFIG_SERIAL_8250_RSA
112
113#define PORT_RSA_MAX 4
114static unsigned long probe_rsa[PORT_RSA_MAX];
115static unsigned int probe_rsa_count;
116#endif /* CONFIG_SERIAL_8250_RSA */
117
118struct uart_8250_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 122 unsigned short capabilities; /* port capabilities */
123 unsigned short bugs; /* port bugs */
1da177e4 124 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 125 unsigned char acr;
126 unsigned char ier;
127 unsigned char lcr;
128 unsigned char mcr;
129 unsigned char mcr_mask; /* mask of user bits */
130 unsigned char mcr_force; /* mask of forced bits */
ad4c2aa6
CM		 131
132 /*
133 * Some bits in registers are cleared on a read, so they must
134 * be saved whenever the register is read but the bits will not
135 * be immediately processed.
136 */
137#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
138 unsigned char lsr_saved_flags;
139#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
140 unsigned char msr_saved_flags;
1da177e4
LT		 141
142 /*
143 * We provide a per-port pm hook.
144 */
145 void (*pm)(struct uart_port *port,
146 unsigned int state, unsigned int old);
147};
148
149struct irq_info {
150 spinlock_t lock;
151 struct list_head *head;
152};
153
154static struct irq_info irq_lists[NR_IRQS];
155
156/*
157 * Here we define the default xmit fifo size used for each type of UART.
158 */
159static const struct serial8250_config uart_config[] = {
160 [PORT_UNKNOWN] = {
161 .name = "unknown",
162 .fifo_size = 1,
163 .tx_loadsz = 1,
164 },
165 [PORT_8250] = {
166 .name = "8250",
167 .fifo_size = 1,
168 .tx_loadsz = 1,
169 },
170 [PORT_16450] = {
171 .name = "16450",
172 .fifo_size = 1,
173 .tx_loadsz = 1,
174 },
175 [PORT_16550] = {
176 .name = "16550",
177 .fifo_size = 1,
178 .tx_loadsz = 1,
179 },
180 [PORT_16550A] = {
181 .name = "16550A",
182 .fifo_size = 16,
183 .tx_loadsz = 16,
184 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 .flags = UART_CAP_FIFO,
186 },
187 [PORT_CIRRUS] = {
188 .name = "Cirrus",
189 .fifo_size = 1,
190 .tx_loadsz = 1,
191 },
192 [PORT_16650] = {
193 .name = "ST16650",
194 .fifo_size = 1,
195 .tx_loadsz = 1,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16650V2] = {
199 .name = "ST16650V2",
200 .fifo_size = 32,
201 .tx_loadsz = 16,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
203 UART_FCR_T_TRIG_00,
204 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
205 },
206 [PORT_16750] = {
207 .name = "TI16750",
208 .fifo_size = 64,
209 .tx_loadsz = 64,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
211 UART_FCR7_64BYTE,
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
213 },
214 [PORT_STARTECH] = {
215 .name = "Startech",
216 .fifo_size = 1,
217 .tx_loadsz = 1,
218 },
219 [PORT_16C950] = {
220 .name = "16C950/954",
221 .fifo_size = 128,
222 .tx_loadsz = 128,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
224 .flags = UART_CAP_FIFO,
225 },
226 [PORT_16654] = {
227 .name = "ST16654",
228 .fifo_size = 64,
229 .tx_loadsz = 32,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
231 UART_FCR_T_TRIG_10,
232 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
233 },
234 [PORT_16850] = {
235 .name = "XR16850",
236 .fifo_size = 128,
237 .tx_loadsz = 128,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
240 },
241 [PORT_RSA] = {
242 .name = "RSA",
243 .fifo_size = 2048,
244 .tx_loadsz = 2048,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
246 .flags = UART_CAP_FIFO,
247 },
248 [PORT_NS16550A] = {
249 .name = "NS16550A",
250 .fifo_size = 16,
251 .tx_loadsz = 16,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_NATSEMI,
254 },
255 [PORT_XSCALE] = {
256 .name = "XScale",
257 .fifo_size = 32,
258 .tx_loadsz = 32,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
260 .flags = UART_CAP_FIFO | UART_CAP_UUE,
261 },
bd71c182
TK		 262 [PORT_RM9000] = {
263 .name = "RM9000",
264 .fifo_size = 16,
265 .tx_loadsz = 16,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO,
268 },
1da177e4
LT		 269};
270
bd71c182 271#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 272
273/* Au1x00 UART hardware has a weird register layout */
274static const u8 au_io_in_map[] = {
275 [UART_RX] = 0,
276 [UART_IER] = 2,
277 [UART_IIR] = 3,
278 [UART_LCR] = 5,
279 [UART_MCR] = 6,
280 [UART_LSR] = 7,
281 [UART_MSR] = 8,
282};
283
284static const u8 au_io_out_map[] = {
285 [UART_TX] = 1,
286 [UART_IER] = 2,
287 [UART_FCR] = 4,
288 [UART_LCR] = 5,
289 [UART_MCR] = 6,
290};
291
292/* sane hardware needs no mapping */
293static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
294{
295 if (up->port.iotype != UPIO_AU)
296 return offset;
297 return au_io_in_map[offset];
298}
299
300static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
301{
302 if (up->port.iotype != UPIO_AU)
303 return offset;
304 return au_io_out_map[offset];
305}
306
6f803cd0 307#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 308
309static const u8
310 regmap_in[8] = {
311 [UART_RX] = 0x00,
312 [UART_IER] = 0x0c,
313 [UART_IIR] = 0x14,
314 [UART_LCR] = 0x1c,
315 [UART_MCR] = 0x20,
316 [UART_LSR] = 0x24,
317 [UART_MSR] = 0x28,
318 [UART_SCR] = 0x2c
319 },
320 regmap_out[8] = {
321 [UART_TX] = 0x04,
322 [UART_IER] = 0x0c,
323 [UART_FCR] = 0x18,
324 [UART_LCR] = 0x1c,
325 [UART_MCR] = 0x20,
326 [UART_LSR] = 0x24,
327 [UART_MSR] = 0x28,
328 [UART_SCR] = 0x2c
329 };
330
331static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
332{
333 if (up->port.iotype != UPIO_RM9000)
334 return offset;
335 return regmap_in[offset];
336}
337
338static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
339{
340 if (up->port.iotype != UPIO_RM9000)
341 return offset;
342 return regmap_out[offset];
343}
344
21c614a7
PA		 345#else
346
347/* sane hardware needs no mapping */
348#define map_8250_in_reg(up, offset) (offset)
349#define map_8250_out_reg(up, offset) (offset)
350
351#endif
352
ea8874dc 353static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 354{
3be91ec7 355 unsigned int tmp;
21c614a7 356 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 357
358 switch (up->port.iotype) {
359 case UPIO_HUB6:
360 outb(up->port.hub6 - 1 + offset, up->port.iobase);
361 return inb(up->port.iobase + 1);
362
363 case UPIO_MEM:
beab697a 364 case UPIO_DWAPB:
1da177e4
LT		 365 return readb(up->port.membase + offset);
366
bd71c182 367 case UPIO_RM9000:
1da177e4
LT		 368 case UPIO_MEM32:
369 return readl(up->port.membase + offset);
370
21c614a7
PA		 371#ifdef CONFIG_SERIAL_8250_AU1X00
372 case UPIO_AU:
373 return __raw_readl(up->port.membase + offset);
374#endif
375
3be91ec7
ZR		 376 case UPIO_TSI:
377 if (offset == UART_IIR) {
9e84b60e
AV		 378 tmp = readl(up->port.membase + (UART_IIR & ~3));
379 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
3be91ec7
ZR		 380 } else
381 return readb(up->port.membase + offset);
382
1da177e4
LT		 383 default:
384 return inb(up->port.iobase + offset);
385 }
386}
387
ea8874dc 388static void
1da177e4
LT		 389serial_out(struct uart_8250_port *up, int offset, int value)
390{
beab697a
MSJ		 391 /* Save the offset before it's remapped */
392 int save_offset = offset;
21c614a7 393 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 394
395 switch (up->port.iotype) {
396 case UPIO_HUB6:
397 outb(up->port.hub6 - 1 + offset, up->port.iobase);
398 outb(value, up->port.iobase + 1);
399 break;
400
401 case UPIO_MEM:
402 writeb(value, up->port.membase + offset);
403 break;
404
bd71c182 405 case UPIO_RM9000:
1da177e4
LT		 406 case UPIO_MEM32:
407 writel(value, up->port.membase + offset);
408 break;
409
21c614a7
PA		 410#ifdef CONFIG_SERIAL_8250_AU1X00
411 case UPIO_AU:
412 __raw_writel(value, up->port.membase + offset);
413 break;
414#endif
3be91ec7
ZR		 415 case UPIO_TSI:
416 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
417 writeb(value, up->port.membase + offset);
418 break;
21c614a7 419
beab697a
MSJ		 420 case UPIO_DWAPB:
421 /* Save the LCR value so it can be re-written when a
422 * Busy Detect interrupt occurs. */
423 if (save_offset == UART_LCR)
424 up->lcr = value;
425 writeb(value, up->port.membase + offset);
426 /* Read the IER to ensure any interrupt is cleared before
427 * returning from ISR. */
428 if (save_offset == UART_TX || save_offset == UART_IER)
429 value = serial_in(up, UART_IER);
430 break;
431
1da177e4
LT		 432 default:
433 outb(value, up->port.iobase + offset);
434 }
435}
436
40b36daa
AW		 437static void
438serial_out_sync(struct uart_8250_port *up, int offset, int value)
439{
440 switch (up->port.iotype) {
441 case UPIO_MEM:
442 case UPIO_MEM32:
443#ifdef CONFIG_SERIAL_8250_AU1X00
444 case UPIO_AU:
445#endif
beab697a 446 case UPIO_DWAPB:
40b36daa
AW		 447 serial_out(up, offset, value);
448 serial_in(up, UART_LCR); /* safe, no side-effects */
449 break;
450 default:
451 serial_out(up, offset, value);
452 }
453}
454
1da177e4
LT		 455/*
456 * We used to support using pause I/O for certain machines. We
457 * haven't supported this for a while, but just in case it's badly
458 * needed for certain old 386 machines, I've left these #define's
459 * in....
460 */
461#define serial_inp(up, offset) serial_in(up, offset)
462#define serial_outp(up, offset, value) serial_out(up, offset, value)
463
b32b19b8
JAH		 464/* Uart divisor latch read */
465static inline int _serial_dl_read(struct uart_8250_port *up)
466{
467 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
468}
469
470/* Uart divisor latch write */
471static inline void _serial_dl_write(struct uart_8250_port *up, int value)
472{
473 serial_outp(up, UART_DLL, value & 0xff);
474 serial_outp(up, UART_DLM, value >> 8 & 0xff);
475}
476
6f803cd0 477#if defined(CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 478/* Au1x00 haven't got a standard divisor latch */
479static int serial_dl_read(struct uart_8250_port *up)
480{
481 if (up->port.iotype == UPIO_AU)
482 return __raw_readl(up->port.membase + 0x28);
483 else
484 return _serial_dl_read(up);
485}
486
487static void serial_dl_write(struct uart_8250_port *up, int value)
488{
489 if (up->port.iotype == UPIO_AU)
490 __raw_writel(value, up->port.membase + 0x28);
491 else
492 _serial_dl_write(up, value);
493}
6f803cd0 494#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 495static int serial_dl_read(struct uart_8250_port *up)
496{
497 return (up->port.iotype == UPIO_RM9000) ?
498 (((__raw_readl(up->port.membase + 0x10) << 8) |
499 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
500 _serial_dl_read(up);
501}
502
503static void serial_dl_write(struct uart_8250_port *up, int value)
504{
505 if (up->port.iotype == UPIO_RM9000) {
506 __raw_writel(value, up->port.membase + 0x08);
507 __raw_writel(value >> 8, up->port.membase + 0x10);
508 } else {
509 _serial_dl_write(up, value);
510 }
511}
b32b19b8
JAH		 512#else
513#define serial_dl_read(up) _serial_dl_read(up)
514#define serial_dl_write(up, value) _serial_dl_write(up, value)
515#endif
1da177e4
LT		 516
517/*
518 * For the 16C950
519 */
520static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
521{
522 serial_out(up, UART_SCR, offset);
523 serial_out(up, UART_ICR, value);
524}
525
526static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
527{
528 unsigned int value;
529
530 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
531 serial_out(up, UART_SCR, offset);
532 value = serial_in(up, UART_ICR);
533 serial_icr_write(up, UART_ACR, up->acr);
534
535 return value;
536}
537
538/*
539 * FIFO support.
540 */
541static inline void serial8250_clear_fifos(struct uart_8250_port *p)
542{
543 if (p->capabilities & UART_CAP_FIFO) {
544 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
545 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
546 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
547 serial_outp(p, UART_FCR, 0);
548 }
549}
550
551/*
552 * IER sleep support. UARTs which have EFRs need the "extended
553 * capability" bit enabled. Note that on XR16C850s, we need to
554 * reset LCR to write to IER.
555 */
556static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
557{
558 if (p->capabilities & UART_CAP_SLEEP) {
559 if (p->capabilities & UART_CAP_EFR) {
560 serial_outp(p, UART_LCR, 0xBF);
561 serial_outp(p, UART_EFR, UART_EFR_ECB);
562 serial_outp(p, UART_LCR, 0);
563 }
564 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
565 if (p->capabilities & UART_CAP_EFR) {
566 serial_outp(p, UART_LCR, 0xBF);
567 serial_outp(p, UART_EFR, 0);
568 serial_outp(p, UART_LCR, 0);
569 }
570 }
571}
572
573#ifdef CONFIG_SERIAL_8250_RSA
574/*
575 * Attempts to turn on the RSA FIFO. Returns zero on failure.
576 * We set the port uart clock rate if we succeed.
577 */
578static int __enable_rsa(struct uart_8250_port *up)
579{
580 unsigned char mode;
581 int result;
582
583 mode = serial_inp(up, UART_RSA_MSR);
584 result = mode & UART_RSA_MSR_FIFO;
585
586 if (!result) {
587 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
588 mode = serial_inp(up, UART_RSA_MSR);
589 result = mode & UART_RSA_MSR_FIFO;
590 }
591
592 if (result)
593 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
594
595 return result;
596}
597
598static void enable_rsa(struct uart_8250_port *up)
599{
600 if (up->port.type == PORT_RSA) {
601 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
602 spin_lock_irq(&up->port.lock);
603 __enable_rsa(up);
604 spin_unlock_irq(&up->port.lock);
605 }
606 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
607 serial_outp(up, UART_RSA_FRR, 0);
608 }
609}
610
611/*
612 * Attempts to turn off the RSA FIFO. Returns zero on failure.
613 * It is unknown why interrupts were disabled in here. However,
614 * the caller is expected to preserve this behaviour by grabbing
615 * the spinlock before calling this function.
616 */
617static void disable_rsa(struct uart_8250_port *up)
618{
619 unsigned char mode;
620 int result;
621
622 if (up->port.type == PORT_RSA &&
623 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
624 spin_lock_irq(&up->port.lock);
625
626 mode = serial_inp(up, UART_RSA_MSR);
627 result = !(mode & UART_RSA_MSR_FIFO);
628
629 if (!result) {
630 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
631 mode = serial_inp(up, UART_RSA_MSR);
632 result = !(mode & UART_RSA_MSR_FIFO);
633 }
634
635 if (result)
636 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
637 spin_unlock_irq(&up->port.lock);
638 }
639}
640#endif /* CONFIG_SERIAL_8250_RSA */
641
642/*
643 * This is a quickie test to see how big the FIFO is.
644 * It doesn't work at all the time, more's the pity.
645 */
646static int size_fifo(struct uart_8250_port *up)
647{
b32b19b8
JAH		 648 unsigned char old_fcr, old_mcr, old_lcr;
649 unsigned short old_dl;
1da177e4
LT		 650 int count;
651
652 old_lcr = serial_inp(up, UART_LCR);
653 serial_outp(up, UART_LCR, 0);
654 old_fcr = serial_inp(up, UART_FCR);
655 old_mcr = serial_inp(up, UART_MCR);
656 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
657 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
658 serial_outp(up, UART_MCR, UART_MCR_LOOP);
659 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 660 old_dl = serial_dl_read(up);
661 serial_dl_write(up, 0x0001);
1da177e4
LT		 662 serial_outp(up, UART_LCR, 0x03);
663 for (count = 0; count < 256; count++)
664 serial_outp(up, UART_TX, count);
665 mdelay(20);/* FIXME - schedule_timeout */
666 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
667 (count < 256); count++)
668 serial_inp(up, UART_RX);
669 serial_outp(up, UART_FCR, old_fcr);
670 serial_outp(up, UART_MCR, old_mcr);
671 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 672 serial_dl_write(up, old_dl);
1da177e4
LT		 673 serial_outp(up, UART_LCR, old_lcr);
674
675 return count;
676}
677
678/*
679 * Read UART ID using the divisor method - set DLL and DLM to zero
680 * and the revision will be in DLL and device type in DLM. We
681 * preserve the device state across this.
682 */
683static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
684{
685 unsigned char old_dll, old_dlm, old_lcr;
686 unsigned int id;
687
688 old_lcr = serial_inp(p, UART_LCR);
689 serial_outp(p, UART_LCR, UART_LCR_DLAB);
690
691 old_dll = serial_inp(p, UART_DLL);
692 old_dlm = serial_inp(p, UART_DLM);
693
694 serial_outp(p, UART_DLL, 0);
695 serial_outp(p, UART_DLM, 0);
696
697 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
698
699 serial_outp(p, UART_DLL, old_dll);
700 serial_outp(p, UART_DLM, old_dlm);
701 serial_outp(p, UART_LCR, old_lcr);
702
703 return id;
704}
705
706/*
707 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
708 * When this function is called we know it is at least a StarTech
709 * 16650 V2, but it might be one of several StarTech UARTs, or one of
710 * its clones. (We treat the broken original StarTech 16650 V1 as a
711 * 16550, and why not? Startech doesn't seem to even acknowledge its
712 * existence.)
bd71c182 713 *
1da177e4
LT		 714 * What evil have men's minds wrought...
715 */
716static void autoconfig_has_efr(struct uart_8250_port *up)
717{
718 unsigned int id1, id2, id3, rev;
719
720 /*
721 * Everything with an EFR has SLEEP
722 */
723 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
724
725 /*
726 * First we check to see if it's an Oxford Semiconductor UART.
727 *
728 * If we have to do this here because some non-National
729 * Semiconductor clone chips lock up if you try writing to the
730 * LSR register (which serial_icr_read does)
731 */
732
733 /*
734 * Check for Oxford Semiconductor 16C950.
735 *
736 * EFR [4] must be set else this test fails.
737 *
738 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
739 * claims that it's needed for 952 dual UART's (which are not
740 * recommended for new designs).
741 */
742 up->acr = 0;
743 serial_out(up, UART_LCR, 0xBF);
744 serial_out(up, UART_EFR, UART_EFR_ECB);
745 serial_out(up, UART_LCR, 0x00);
746 id1 = serial_icr_read(up, UART_ID1);
747 id2 = serial_icr_read(up, UART_ID2);
748 id3 = serial_icr_read(up, UART_ID3);
749 rev = serial_icr_read(up, UART_REV);
750
751 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
752
753 if (id1 == 0x16 && id2 == 0xC9 &&
754 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
755 up->port.type = PORT_16C950;
4ba5e35d
RK		 756
757 /*
758 * Enable work around for the Oxford Semiconductor 952 rev B
759 * chip which causes it to seriously miscalculate baud rates
760 * when DLL is 0.
761 */
762 if (id3 == 0x52 && rev == 0x01)
763 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 764 return;
765 }
bd71c182 766
1da177e4
LT		 767 /*
768 * We check for a XR16C850 by setting DLL and DLM to 0, and then
769 * reading back DLL and DLM. The chip type depends on the DLM
770 * value read back:
771 * 0x10 - XR16C850 and the DLL contains the chip revision.
772 * 0x12 - XR16C2850.
773 * 0x14 - XR16C854.
774 */
775 id1 = autoconfig_read_divisor_id(up);
776 DEBUG_AUTOCONF("850id=%04x ", id1);
777
778 id2 = id1 >> 8;
779 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 780 up->port.type = PORT_16850;
781 return;
782 }
783
784 /*
785 * It wasn't an XR16C850.
786 *
787 * We distinguish between the '654 and the '650 by counting
788 * how many bytes are in the FIFO. I'm using this for now,
789 * since that's the technique that was sent to me in the
790 * serial driver update, but I'm not convinced this works.
791 * I've had problems doing this in the past. -TYT
792 */
793 if (size_fifo(up) == 64)
794 up->port.type = PORT_16654;
795 else
796 up->port.type = PORT_16650V2;
797}
798
799/*
800 * We detected a chip without a FIFO. Only two fall into
801 * this category - the original 8250 and the 16450. The
802 * 16450 has a scratch register (accessible with LCR=0)
803 */
804static void autoconfig_8250(struct uart_8250_port *up)
805{
806 unsigned char scratch, status1, status2;
807
808 up->port.type = PORT_8250;
809
810 scratch = serial_in(up, UART_SCR);
811 serial_outp(up, UART_SCR, 0xa5);
812 status1 = serial_in(up, UART_SCR);
813 serial_outp(up, UART_SCR, 0x5a);
814 status2 = serial_in(up, UART_SCR);
815 serial_outp(up, UART_SCR, scratch);
816
817 if (status1 == 0xa5 && status2 == 0x5a)
818 up->port.type = PORT_16450;
819}
820
821static int broken_efr(struct uart_8250_port *up)
822{
823 /*
824 * Exar ST16C2550 "A2" devices incorrectly detect as
825 * having an EFR, and report an ID of 0x0201. See
826 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
827 */
828 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
829 return 1;
830
831 return 0;
832}
833
834/*
835 * We know that the chip has FIFOs. Does it have an EFR? The
836 * EFR is located in the same register position as the IIR and
837 * we know the top two bits of the IIR are currently set. The
838 * EFR should contain zero. Try to read the EFR.
839 */
840static void autoconfig_16550a(struct uart_8250_port *up)
841{
842 unsigned char status1, status2;
843 unsigned int iersave;
844
845 up->port.type = PORT_16550A;
846 up->capabilities |= UART_CAP_FIFO;
847
848 /*
849 * Check for presence of the EFR when DLAB is set.
850 * Only ST16C650V1 UARTs pass this test.
851 */
852 serial_outp(up, UART_LCR, UART_LCR_DLAB);
853 if (serial_in(up, UART_EFR) == 0) {
854 serial_outp(up, UART_EFR, 0xA8);
855 if (serial_in(up, UART_EFR) != 0) {
856 DEBUG_AUTOCONF("EFRv1 ");
857 up->port.type = PORT_16650;
858 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
859 } else {
860 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
861 }
862 serial_outp(up, UART_EFR, 0);
863 return;
864 }
865
866 /*
867 * Maybe it requires 0xbf to be written to the LCR.
868 * (other ST16C650V2 UARTs, TI16C752A, etc)
869 */
870 serial_outp(up, UART_LCR, 0xBF);
871 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
872 DEBUG_AUTOCONF("EFRv2 ");
873 autoconfig_has_efr(up);
874 return;
875 }
876
877 /*
878 * Check for a National Semiconductor SuperIO chip.
879 * Attempt to switch to bank 2, read the value of the LOOP bit
880 * from EXCR1. Switch back to bank 0, change it in MCR. Then
881 * switch back to bank 2, read it from EXCR1 again and check
882 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 883 */
884 serial_outp(up, UART_LCR, 0);
885 status1 = serial_in(up, UART_MCR);
886 serial_outp(up, UART_LCR, 0xE0);
887 status2 = serial_in(up, 0x02); /* EXCR1 */
888
889 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
890 serial_outp(up, UART_LCR, 0);
891 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
892 serial_outp(up, UART_LCR, 0xE0);
893 status2 = serial_in(up, 0x02); /* EXCR1 */
894 serial_outp(up, UART_LCR, 0);
895 serial_outp(up, UART_MCR, status1);
896
897 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 898 unsigned short quot;
899
1da177e4 900 serial_outp(up, UART_LCR, 0xE0);
857dde2e 901
b32b19b8 902 quot = serial_dl_read(up);
857dde2e
DW		 903 quot <<= 3;
904
b5b82df6 905 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 906 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
907 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
908 serial_outp(up, 0x04, status1);
bd71c182 909
b32b19b8 910 serial_dl_write(up, quot);
857dde2e 911
1da177e4 912 serial_outp(up, UART_LCR, 0);
1da177e4 913
857dde2e 914 up->port.uartclk = 921600*16;
1da177e4
LT		 915 up->port.type = PORT_NS16550A;
916 up->capabilities |= UART_NATSEMI;
917 return;
918 }
919 }
920
921 /*
922 * No EFR. Try to detect a TI16750, which only sets bit 5 of
923 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
924 * Try setting it with and without DLAB set. Cheap clones
925 * set bit 5 without DLAB set.
926 */
927 serial_outp(up, UART_LCR, 0);
928 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
929 status1 = serial_in(up, UART_IIR) >> 5;
930 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
931 serial_outp(up, UART_LCR, UART_LCR_DLAB);
932 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
933 status2 = serial_in(up, UART_IIR) >> 5;
934 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
935 serial_outp(up, UART_LCR, 0);
936
937 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
938
939 if (status1 == 6 && status2 == 7) {
940 up->port.type = PORT_16750;
941 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
942 return;
943 }
944
945 /*
946 * Try writing and reading the UART_IER_UUE bit (b6).
947 * If it works, this is probably one of the Xscale platform's
948 * internal UARTs.
949 * We're going to explicitly set the UUE bit to 0 before
950 * trying to write and read a 1 just to make sure it's not
951 * already a 1 and maybe locked there before we even start start.
952 */
953 iersave = serial_in(up, UART_IER);
954 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
955 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
956 /*
957 * OK it's in a known zero state, try writing and reading
958 * without disturbing the current state of the other bits.
959 */
960 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
961 if (serial_in(up, UART_IER) & UART_IER_UUE) {
962 /*
963 * It's an Xscale.
964 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
965 */
966 DEBUG_AUTOCONF("Xscale ");
967 up->port.type = PORT_XSCALE;
968 up->capabilities |= UART_CAP_UUE;
969 return;
970 }
971 } else {
972 /*
973 * If we got here we couldn't force the IER_UUE bit to 0.
974 * Log it and continue.
975 */
976 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
977 }
978 serial_outp(up, UART_IER, iersave);
979}
980
981/*
982 * This routine is called by rs_init() to initialize a specific serial
983 * port. It determines what type of UART chip this serial port is
984 * using: 8250, 16450, 16550, 16550A. The important question is
985 * whether or not this UART is a 16550A or not, since this will
986 * determine whether or not we can use its FIFO features or not.
987 */
988static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
989{
990 unsigned char status1, scratch, scratch2, scratch3;
991 unsigned char save_lcr, save_mcr;
992 unsigned long flags;
993
994 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
995 return;
996
997 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
998 up->port.line, up->port.iobase, up->port.membase);
999
1000 /*
1001 * We really do need global IRQs disabled here - we're going to
1002 * be frobbing the chips IRQ enable register to see if it exists.
1003 */
1004 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1005
1006 up->capabilities = 0;
4ba5e35d 1007 up->bugs = 0;
1da177e4
LT		 1008
1009 if (!(up->port.flags & UPF_BUGGY_UART)) {
1010 /*
1011 * Do a simple existence test first; if we fail this,
1012 * there's no point trying anything else.
bd71c182 1013 *
1da177e4
LT		 1014 * 0x80 is used as a nonsense port to prevent against
1015 * false positives due to ISA bus float. The
1016 * assumption is that 0x80 is a non-existent port;
1017 * which should be safe since include/asm/io.h also
1018 * makes this assumption.
1019 *
1020 * Note: this is safe as long as MCR bit 4 is clear
1021 * and the device is in "PC" mode.
1022 */
1023 scratch = serial_inp(up, UART_IER);
1024 serial_outp(up, UART_IER, 0);
1025#ifdef __i386__
1026 outb(0xff, 0x080);
1027#endif
48212008
TH		 1028 /*
1029 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1030 * 16C754B) allow only to modify them if an EFR bit is set.
1031 */
1032 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1033 serial_outp(up, UART_IER, 0x0F);
1034#ifdef __i386__
1035 outb(0, 0x080);
1036#endif
48212008 1037 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1038 serial_outp(up, UART_IER, scratch);
1039 if (scratch2 != 0 || scratch3 != 0x0F) {
1040 /*
1041 * We failed; there's nothing here
1042 */
1043 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1044 scratch2, scratch3);
1045 goto out;
1046 }
1047 }
1048
1049 save_mcr = serial_in(up, UART_MCR);
1050 save_lcr = serial_in(up, UART_LCR);
1051
bd71c182 1052 /*
1da177e4
LT		 1053 * Check to see if a UART is really there. Certain broken
1054 * internal modems based on the Rockwell chipset fail this
1055 * test, because they apparently don't implement the loopback
1056 * test mode. So this test is skipped on the COM 1 through
1057 * COM 4 ports. This *should* be safe, since no board
1058 * manufacturer would be stupid enough to design a board
1059 * that conflicts with COM 1-4 --- we hope!
1060 */
1061 if (!(up->port.flags & UPF_SKIP_TEST)) {
1062 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1063 status1 = serial_inp(up, UART_MSR) & 0xF0;
1064 serial_outp(up, UART_MCR, save_mcr);
1065 if (status1 != 0x90) {
1066 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1067 status1);
1068 goto out;
1069 }
1070 }
1071
1072 /*
1073 * We're pretty sure there's a port here. Lets find out what
1074 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1075 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1076 * determines what we test for next.
1077 *
1078 * We also initialise the EFR (if any) to zero for later. The
1079 * EFR occupies the same register location as the FCR and IIR.
1080 */
1081 serial_outp(up, UART_LCR, 0xBF);
1082 serial_outp(up, UART_EFR, 0);
1083 serial_outp(up, UART_LCR, 0);
1084
1085 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1086 scratch = serial_in(up, UART_IIR) >> 6;
1087
1088 DEBUG_AUTOCONF("iir=%d ", scratch);
1089
1090 switch (scratch) {
1091 case 0:
1092 autoconfig_8250(up);
1093 break;
1094 case 1:
1095 up->port.type = PORT_UNKNOWN;
1096 break;
1097 case 2:
1098 up->port.type = PORT_16550;
1099 break;
1100 case 3:
1101 autoconfig_16550a(up);
1102 break;
1103 }
1104
1105#ifdef CONFIG_SERIAL_8250_RSA
1106 /*
1107 * Only probe for RSA ports if we got the region.
1108 */
1109 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1110 int i;
1111
1112 for (i = 0 ; i < probe_rsa_count; ++i) {
1113 if (probe_rsa[i] == up->port.iobase &&
1114 __enable_rsa(up)) {
1115 up->port.type = PORT_RSA;
1116 break;
1117 }
1118 }
1119 }
1120#endif
21c614a7
PA		 1121
1122#ifdef CONFIG_SERIAL_8250_AU1X00
1123 /* if access method is AU, it is a 16550 with a quirk */
1124 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1125 up->bugs |= UART_BUG_NOMSR;
1126#endif
1127
1da177e4
LT		 1128 serial_outp(up, UART_LCR, save_lcr);
1129
1130 if (up->capabilities != uart_config[up->port.type].flags) {
1131 printk(KERN_WARNING
1132 "ttyS%d: detected caps %08x should be %08x\n",
1133 up->port.line, up->capabilities,
1134 uart_config[up->port.type].flags);
1135 }
1136
1137 up->port.fifosize = uart_config[up->port.type].fifo_size;
1138 up->capabilities = uart_config[up->port.type].flags;
1139 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1140
1141 if (up->port.type == PORT_UNKNOWN)
1142 goto out;
1143
1144 /*
1145 * Reset the UART.
1146 */
1147#ifdef CONFIG_SERIAL_8250_RSA
1148 if (up->port.type == PORT_RSA)
1149 serial_outp(up, UART_RSA_FRR, 0);
1150#endif
1151 serial_outp(up, UART_MCR, save_mcr);
1152 serial8250_clear_fifos(up);
40b36daa 1153 serial_in(up, UART_RX);
5c8c755c
LB		 1154 if (up->capabilities & UART_CAP_UUE)
1155 serial_outp(up, UART_IER, UART_IER_UUE);
1156 else
1157 serial_outp(up, UART_IER, 0);
1da177e4 1158
bd71c182 1159 out:
1da177e4 1160 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1161 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1162}
1163
1164static void autoconfig_irq(struct uart_8250_port *up)
1165{
1166 unsigned char save_mcr, save_ier;
1167 unsigned char save_ICP = 0;
1168 unsigned int ICP = 0;
1169 unsigned long irqs;
1170 int irq;
1171
1172 if (up->port.flags & UPF_FOURPORT) {
1173 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1174 save_ICP = inb_p(ICP);
1175 outb_p(0x80, ICP);
1176 (void) inb_p(ICP);
1177 }
1178
1179 /* forget possible initially masked and pending IRQ */
1180 probe_irq_off(probe_irq_on());
1181 save_mcr = serial_inp(up, UART_MCR);
1182 save_ier = serial_inp(up, UART_IER);
1183 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1184
1da177e4
LT		 1185 irqs = probe_irq_on();
1186 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1187 udelay(10);
1188 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1189 serial_outp(up, UART_MCR,
1190 UART_MCR_DTR | UART_MCR_RTS);
1191 } else {
1192 serial_outp(up, UART_MCR,
1193 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1194 }
1195 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1196 (void)serial_inp(up, UART_LSR);
1197 (void)serial_inp(up, UART_RX);
1198 (void)serial_inp(up, UART_IIR);
1199 (void)serial_inp(up, UART_MSR);
1200 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1201 udelay(20);
1da177e4
LT		 1202 irq = probe_irq_off(irqs);
1203
1204 serial_outp(up, UART_MCR, save_mcr);
1205 serial_outp(up, UART_IER, save_ier);
1206
1207 if (up->port.flags & UPF_FOURPORT)
1208 outb_p(save_ICP, ICP);
1209
1210 up->port.irq = (irq > 0) ? irq : 0;
1211}
1212
e763b90c
RK		 1213static inline void __stop_tx(struct uart_8250_port *p)
1214{
1215 if (p->ier & UART_IER_THRI) {
1216 p->ier &= ~UART_IER_THRI;
1217 serial_out(p, UART_IER, p->ier);
1218 }
1219}
1220
b129a8cc 1221static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1222{
1223 struct uart_8250_port *up = (struct uart_8250_port *)port;
1224
e763b90c 1225 __stop_tx(up);
1da177e4
LT		 1226
1227 /*
e763b90c 1228 * We really want to stop the transmitter from sending.
1da177e4 1229 */
e763b90c 1230 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1231 up->acr |= UART_ACR_TXDIS;
1232 serial_icr_write(up, UART_ACR, up->acr);
1233 }
1234}
1235
55d3b282
RK		 1236static void transmit_chars(struct uart_8250_port *up);
1237
b129a8cc 1238static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1239{
1240 struct uart_8250_port *up = (struct uart_8250_port *)port;
1241
1242 if (!(up->ier & UART_IER_THRI)) {
1243 up->ier |= UART_IER_THRI;
1244 serial_out(up, UART_IER, up->ier);
55d3b282 1245
67f7654e 1246 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1247 unsigned char lsr, iir;
1248 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1249 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182
TK		 1250 iir = serial_in(up, UART_IIR) & 0x0f;
1251 if ((up->port.type == PORT_RM9000) ?
1252 (lsr & UART_LSR_THRE &&
1253 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1254 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
55d3b282
RK		 1255 transmit_chars(up);
1256 }
1da177e4 1257 }
e763b90c 1258
1da177e4 1259 /*
e763b90c 1260 * Re-enable the transmitter if we disabled it.
1da177e4 1261 */
e763b90c 1262 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1263 up->acr &= ~UART_ACR_TXDIS;
1264 serial_icr_write(up, UART_ACR, up->acr);
1265 }
1266}
1267
1268static void serial8250_stop_rx(struct uart_port *port)
1269{
1270 struct uart_8250_port *up = (struct uart_8250_port *)port;
1271
1272 up->ier &= ~UART_IER_RLSI;
1273 up->port.read_status_mask &= ~UART_LSR_DR;
1274 serial_out(up, UART_IER, up->ier);
1275}
1276
1277static void serial8250_enable_ms(struct uart_port *port)
1278{
1279 struct uart_8250_port *up = (struct uart_8250_port *)port;
1280
21c614a7
PA		 1281 /* no MSR capabilities */
1282 if (up->bugs & UART_BUG_NOMSR)
1283 return;
1284
1da177e4
LT		 1285 up->ier |= UART_IER_MSI;
1286 serial_out(up, UART_IER, up->ier);
1287}
1288
ea8874dc 1289static void
cc79aa9d 1290receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4
LT		 1291{
1292 struct tty_struct *tty = up->port.info->tty;
1293 unsigned char ch, lsr = *status;
1294 int max_count = 256;
1295 char flag;
1296
1297 do {
1da177e4
LT		 1298 ch = serial_inp(up, UART_RX);
1299 flag = TTY_NORMAL;
1300 up->port.icount.rx++;
1301
ad4c2aa6
CM		 1302 lsr |= up->lsr_saved_flags;
1303 up->lsr_saved_flags = 0;
1da177e4 1304
ad4c2aa6 1305 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1306 /*
1307 * For statistics only
1308 */
1309 if (lsr & UART_LSR_BI) {
1310 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1311 up->port.icount.brk++;
1312 /*
1313 * We do the SysRQ and SAK checking
1314 * here because otherwise the break
1315 * may get masked by ignore_status_mask
1316 * or read_status_mask.
1317 */
1318 if (uart_handle_break(&up->port))
1319 goto ignore_char;
1320 } else if (lsr & UART_LSR_PE)
1321 up->port.icount.parity++;
1322 else if (lsr & UART_LSR_FE)
1323 up->port.icount.frame++;
1324 if (lsr & UART_LSR_OE)
1325 up->port.icount.overrun++;
1326
1327 /*
23907eb8 1328 * Mask off conditions which should be ignored.
1da177e4
LT		 1329 */
1330 lsr &= up->port.read_status_mask;
1331
1332 if (lsr & UART_LSR_BI) {
1333 DEBUG_INTR("handling break....");
1334 flag = TTY_BREAK;
1335 } else if (lsr & UART_LSR_PE)
1336 flag = TTY_PARITY;
1337 else if (lsr & UART_LSR_FE)
1338 flag = TTY_FRAME;
1339 }
7d12e780 1340 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1341 goto ignore_char;
05ab3014
RK		 1342
1343 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1344
6f803cd0 1345ignore_char:
1da177e4
LT		 1346 lsr = serial_inp(up, UART_LSR);
1347 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1348 spin_unlock(&up->port.lock);
1349 tty_flip_buffer_push(tty);
1350 spin_lock(&up->port.lock);
1351 *status = lsr;
1352}
1353
ea8874dc 1354static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1355{
1356 struct circ_buf *xmit = &up->port.info->xmit;
1357 int count;
1358
1359 if (up->port.x_char) {
1360 serial_outp(up, UART_TX, up->port.x_char);
1361 up->port.icount.tx++;
1362 up->port.x_char = 0;
1363 return;
1364 }
b129a8cc
RK		 1365 if (uart_tx_stopped(&up->port)) {
1366 serial8250_stop_tx(&up->port);
1367 return;
1368 }
1369 if (uart_circ_empty(xmit)) {
e763b90c 1370 __stop_tx(up);
1da177e4
LT		 1371 return;
1372 }
1373
1374 count = up->tx_loadsz;
1375 do {
1376 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1377 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1378 up->port.icount.tx++;
1379 if (uart_circ_empty(xmit))
1380 break;
1381 } while (--count > 0);
1382
1383 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1384 uart_write_wakeup(&up->port);
1385
1386 DEBUG_INTR("THRE...");
1387
1388 if (uart_circ_empty(xmit))
e763b90c 1389 __stop_tx(up);
1da177e4
LT		 1390}
1391
2af7cd68 1392static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1393{
2af7cd68
RK		 1394 unsigned int status = serial_in(up, UART_MSR);
1395
ad4c2aa6
CM		 1396 status |= up->msr_saved_flags;
1397 up->msr_saved_flags = 0;
fdc30b3d
TI		 1398 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1399 up->port.info != NULL) {
2af7cd68
RK		 1400 if (status & UART_MSR_TERI)
1401 up->port.icount.rng++;
1402 if (status & UART_MSR_DDSR)
1403 up->port.icount.dsr++;
1404 if (status & UART_MSR_DDCD)
1405 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1406 if (status & UART_MSR_DCTS)
1407 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1408
1409 wake_up_interruptible(&up->port.info->delta_msr_wait);
1410 }
1da177e4 1411
2af7cd68 1412 return status;
1da177e4
LT		 1413}
1414
1415/*
1416 * This handles the interrupt from one port.
1417 */
1418static inline void
7d12e780 1419serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1420{
45e24601 1421 unsigned int status;
4bf3631c 1422 unsigned long flags;
45e24601 1423
4bf3631c 1424 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1425
1426 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1427
1428 DEBUG_INTR("status = %x...", status);
1429
1430 if (status & UART_LSR_DR)
7d12e780 1431 receive_chars(up, &status);
1da177e4
LT		 1432 check_modem_status(up);
1433 if (status & UART_LSR_THRE)
1434 transmit_chars(up);
45e24601 1435
4bf3631c 1436 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1437}
1438
1439/*
1440 * This is the serial driver's interrupt routine.
1441 *
1442 * Arjan thinks the old way was overly complex, so it got simplified.
1443 * Alan disagrees, saying that need the complexity to handle the weird
1444 * nature of ISA shared interrupts. (This is a special exception.)
1445 *
1446 * In order to handle ISA shared interrupts properly, we need to check
1447 * that all ports have been serviced, and therefore the ISA interrupt
1448 * line has been de-asserted.
1449 *
1450 * This means we need to loop through all ports. checking that they
1451 * don't have an interrupt pending.
1452 */
7d12e780 1453static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1454{
1455 struct irq_info *i = dev_id;
1456 struct list_head *l, *end = NULL;
1457 int pass_counter = 0, handled = 0;
1458
1459 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1460
1461 spin_lock(&i->lock);
1462
1463 l = i->head;
1464 do {
1465 struct uart_8250_port *up;
1466 unsigned int iir;
1467
1468 up = list_entry(l, struct uart_8250_port, list);
1469
1470 iir = serial_in(up, UART_IIR);
1471 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1472 serial8250_handle_port(up);
1da177e4
LT		 1473
1474 handled = 1;
1475
beab697a
MSJ		 1476 end = NULL;
1477 } else if (up->port.iotype == UPIO_DWAPB &&
1478 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1479 /* The DesignWare APB UART has an Busy Detect (0x07)
1480 * interrupt meaning an LCR write attempt occured while the
1481 * UART was busy. The interrupt must be cleared by reading
1482 * the UART status register (USR) and the LCR re-written. */
1483 unsigned int status;
1484 status = *(volatile u32 *)up->port.private_data;
1485 serial_out(up, UART_LCR, up->lcr);
1486
1487 handled = 1;
1488
1da177e4
LT		 1489 end = NULL;
1490 } else if (end == NULL)
1491 end = l;
1492
1493 l = l->next;
1494
1495 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1496 /* If we hit this, we're dead. */
1497 printk(KERN_ERR "serial8250: too much work for "
1498 "irq%d\n", irq);
1499 break;
1500 }
1501 } while (l != end);
1502
1503 spin_unlock(&i->lock);
1504
1505 DEBUG_INTR("end.\n");
1506
1507 return IRQ_RETVAL(handled);
1508}
1509
1510/*
1511 * To support ISA shared interrupts, we need to have one interrupt
1512 * handler that ensures that the IRQ line has been deasserted
1513 * before returning. Failing to do this will result in the IRQ
1514 * line being stuck active, and, since ISA irqs are edge triggered,
1515 * no more IRQs will be seen.
1516 */
1517static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1518{
1519 spin_lock_irq(&i->lock);
1520
1521 if (!list_empty(i->head)) {
1522 if (i->head == &up->list)
1523 i->head = i->head->next;
1524 list_del(&up->list);
1525 } else {
1526 BUG_ON(i->head != &up->list);
1527 i->head = NULL;
1528 }
1529
1530 spin_unlock_irq(&i->lock);
1531}
1532
1533static int serial_link_irq_chain(struct uart_8250_port *up)
1534{
1535 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1536 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1537
1538 spin_lock_irq(&i->lock);
1539
1540 if (i->head) {
1541 list_add(&up->list, i->head);
1542 spin_unlock_irq(&i->lock);
1543
1544 ret = 0;
1545 } else {
1546 INIT_LIST_HEAD(&up->list);
1547 i->head = &up->list;
1548 spin_unlock_irq(&i->lock);
1549
1550 ret = request_irq(up->port.irq, serial8250_interrupt,
1551 irq_flags, "serial", i);
1552 if (ret < 0)
1553 serial_do_unlink(i, up);
1554 }
1555
1556 return ret;
1557}
1558
1559static void serial_unlink_irq_chain(struct uart_8250_port *up)
1560{
1561 struct irq_info *i = irq_lists + up->port.irq;
1562
1563 BUG_ON(i->head == NULL);
1564
1565 if (list_empty(i->head))
1566 free_irq(up->port.irq, i);
1567
1568 serial_do_unlink(i, up);
1569}
1570
40b36daa
AW		 1571/* Base timer interval for polling */
1572static inline int poll_timeout(int timeout)
1573{
1574 return timeout > 6 ? (timeout / 2 - 2) : 1;
1575}
1576
1da177e4
LT		 1577/*
1578 * This function is used to handle ports that do not have an
1579 * interrupt. This doesn't work very well for 16450's, but gives
1580 * barely passable results for a 16550A. (Although at the expense
1581 * of much CPU overhead).
1582 */
1583static void serial8250_timeout(unsigned long data)
1584{
1585 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1586 unsigned int iir;
1587
1588 iir = serial_in(up, UART_IIR);
45e24601 1589 if (!(iir & UART_IIR_NO_INT))
7d12e780 1590 serial8250_handle_port(up);
40b36daa
AW		 1591 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1592}
1593
1594static void serial8250_backup_timeout(unsigned long data)
1595{
1596 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1597 unsigned int iir, ier = 0, lsr;
1598 unsigned long flags;
40b36daa
AW		 1599
1600 /*
1601 * Must disable interrupts or else we risk racing with the interrupt
1602 * based handler.
1603 */
1604 if (is_real_interrupt(up->port.irq)) {
1605 ier = serial_in(up, UART_IER);
1606 serial_out(up, UART_IER, 0);
1607 }
1da177e4 1608
40b36daa
AW		 1609 iir = serial_in(up, UART_IIR);
1610
1611 /*
1612 * This should be a safe test for anyone who doesn't trust the
1613 * IIR bits on their UART, but it's specifically designed for
1614 * the "Diva" UART used on the management processor on many HP
1615 * ia64 and parisc boxes.
1616 */
ad4c2aa6
CM		 1617 spin_lock_irqsave(&up->port.lock, flags);
1618 lsr = serial_in(up, UART_LSR);
1619 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1620 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 1621 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1622 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
ad4c2aa6 1623 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1624 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1625 iir |= UART_IIR_THRI;
1626 }
1627
1628 if (!(iir & UART_IIR_NO_INT))
1629 serial8250_handle_port(up);
1630
1631 if (is_real_interrupt(up->port.irq))
1632 serial_out(up, UART_IER, ier);
1633
1634 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1635 mod_timer(&up->timer,
1636 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1637}
1638
1639static unsigned int serial8250_tx_empty(struct uart_port *port)
1640{
1641 struct uart_8250_port *up = (struct uart_8250_port *)port;
1642 unsigned long flags;
ad4c2aa6 1643 unsigned int lsr;
1da177e4
LT		 1644
1645 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1646 lsr = serial_in(up, UART_LSR);
1647 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1648 spin_unlock_irqrestore(&up->port.lock, flags);
1649
ad4c2aa6 1650 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1da177e4
LT		 1651}
1652
1653static unsigned int serial8250_get_mctrl(struct uart_port *port)
1654{
1655 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1656 unsigned int status;
1da177e4
LT		 1657 unsigned int ret;
1658
2af7cd68 1659 status = check_modem_status(up);
1da177e4
LT		 1660
1661 ret = 0;
1662 if (status & UART_MSR_DCD)
1663 ret |= TIOCM_CAR;
1664 if (status & UART_MSR_RI)
1665 ret |= TIOCM_RNG;
1666 if (status & UART_MSR_DSR)
1667 ret |= TIOCM_DSR;
1668 if (status & UART_MSR_CTS)
1669 ret |= TIOCM_CTS;
1670 return ret;
1671}
1672
1673static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1674{
1675 struct uart_8250_port *up = (struct uart_8250_port *)port;
1676 unsigned char mcr = 0;
1677
1678 if (mctrl & TIOCM_RTS)
1679 mcr |= UART_MCR_RTS;
1680 if (mctrl & TIOCM_DTR)
1681 mcr |= UART_MCR_DTR;
1682 if (mctrl & TIOCM_OUT1)
1683 mcr |= UART_MCR_OUT1;
1684 if (mctrl & TIOCM_OUT2)
1685 mcr |= UART_MCR_OUT2;
1686 if (mctrl & TIOCM_LOOP)
1687 mcr |= UART_MCR_LOOP;
1688
1689 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1690
1691 serial_out(up, UART_MCR, mcr);
1692}
1693
1694static void serial8250_break_ctl(struct uart_port *port, int break_state)
1695{
1696 struct uart_8250_port *up = (struct uart_8250_port *)port;
1697 unsigned long flags;
1698
1699 spin_lock_irqsave(&up->port.lock, flags);
1700 if (break_state == -1)
1701 up->lcr |= UART_LCR_SBC;
1702 else
1703 up->lcr &= ~UART_LCR_SBC;
1704 serial_out(up, UART_LCR, up->lcr);
1705 spin_unlock_irqrestore(&up->port.lock, flags);
1706}
1707
40b36daa
AW		 1708#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1709
1710/*
1711 * Wait for transmitter & holding register to empty
1712 */
1713static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1714{
1715 unsigned int status, tmout = 10000;
1716
1717 /* Wait up to 10ms for the character(s) to be sent. */
1718 do {
1719 status = serial_in(up, UART_LSR);
1720
ad4c2aa6 1721 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1722
1723 if (--tmout == 0)
1724 break;
1725 udelay(1);
1726 } while ((status & bits) != bits);
1727
1728 /* Wait up to 1s for flow control if necessary */
1729 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1730 unsigned int tmout;
1731 for (tmout = 1000000; tmout; tmout--) {
1732 unsigned int msr = serial_in(up, UART_MSR);
1733 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1734 if (msr & UART_MSR_CTS)
1735 break;
40b36daa
AW		 1736 udelay(1);
1737 touch_nmi_watchdog();
1738 }
1739 }
1740}
1741
f2d937f3
JW		 1742#ifdef CONFIG_CONSOLE_POLL
1743/*
1744 * Console polling routines for writing and reading from the uart while
1745 * in an interrupt or debug context.
1746 */
1747
1748static int serial8250_get_poll_char(struct uart_port *port)
1749{
1750 struct uart_8250_port *up = (struct uart_8250_port *)port;
1751 unsigned char lsr = serial_inp(up, UART_LSR);
1752
1753 while (!(lsr & UART_LSR_DR))
1754 lsr = serial_inp(up, UART_LSR);
1755
1756 return serial_inp(up, UART_RX);
1757}
1758
1759
1760static void serial8250_put_poll_char(struct uart_port *port,
1761 unsigned char c)
1762{
1763 unsigned int ier;
1764 struct uart_8250_port *up = (struct uart_8250_port *)port;
1765
1766 /*
1767 * First save the IER then disable the interrupts
1768 */
1769 ier = serial_in(up, UART_IER);
1770 if (up->capabilities & UART_CAP_UUE)
1771 serial_out(up, UART_IER, UART_IER_UUE);
1772 else
1773 serial_out(up, UART_IER, 0);
1774
1775 wait_for_xmitr(up, BOTH_EMPTY);
1776 /*
1777 * Send the character out.
1778 * If a LF, also do CR...
1779 */
1780 serial_out(up, UART_TX, c);
1781 if (c == 10) {
1782 wait_for_xmitr(up, BOTH_EMPTY);
1783 serial_out(up, UART_TX, 13);
1784 }
1785
1786 /*
1787 * Finally, wait for transmitter to become empty
1788 * and restore the IER
1789 */
1790 wait_for_xmitr(up, BOTH_EMPTY);
1791 serial_out(up, UART_IER, ier);
1792}
1793
1794#endif /* CONFIG_CONSOLE_POLL */
1795
1da177e4
LT		 1796static int serial8250_startup(struct uart_port *port)
1797{
1798 struct uart_8250_port *up = (struct uart_8250_port *)port;
1799 unsigned long flags;
55d3b282 1800 unsigned char lsr, iir;
1da177e4
LT		 1801 int retval;
1802
1803 up->capabilities = uart_config[up->port.type].flags;
1804 up->mcr = 0;
1805
1806 if (up->port.type == PORT_16C950) {
1807 /* Wake up and initialize UART */
1808 up->acr = 0;
1809 serial_outp(up, UART_LCR, 0xBF);
1810 serial_outp(up, UART_EFR, UART_EFR_ECB);
1811 serial_outp(up, UART_IER, 0);
1812 serial_outp(up, UART_LCR, 0);
1813 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1814 serial_outp(up, UART_LCR, 0xBF);
1815 serial_outp(up, UART_EFR, UART_EFR_ECB);
1816 serial_outp(up, UART_LCR, 0);
1817 }
1818
1819#ifdef CONFIG_SERIAL_8250_RSA
1820 /*
1821 * If this is an RSA port, see if we can kick it up to the
1822 * higher speed clock.
1823 */
1824 enable_rsa(up);
1825#endif
1826
1827 /*
1828 * Clear the FIFO buffers and disable them.
7f927fcc 1829 * (they will be reenabled in set_termios())
1da177e4
LT		 1830 */
1831 serial8250_clear_fifos(up);
1832
1833 /*
1834 * Clear the interrupt registers.
1835 */
1836 (void) serial_inp(up, UART_LSR);
1837 (void) serial_inp(up, UART_RX);
1838 (void) serial_inp(up, UART_IIR);
1839 (void) serial_inp(up, UART_MSR);
1840
1841 /*
1842 * At this point, there's no way the LSR could still be 0xff;
1843 * if it is, then bail out, because there's likely no UART
1844 * here.
1845 */
1846 if (!(up->port.flags & UPF_BUGGY_UART) &&
1847 (serial_inp(up, UART_LSR) == 0xff)) {
1848 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1849 return -ENODEV;
1850 }
1851
1852 /*
1853 * For a XR16C850, we need to set the trigger levels
1854 */
1855 if (up->port.type == PORT_16850) {
1856 unsigned char fctr;
1857
1858 serial_outp(up, UART_LCR, 0xbf);
1859
1860 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1861 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1862 serial_outp(up, UART_TRG, UART_TRG_96);
1863 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1864 serial_outp(up, UART_TRG, UART_TRG_96);
1865
1866 serial_outp(up, UART_LCR, 0);
1867 }
1868
40b36daa 1869 if (is_real_interrupt(up->port.irq)) {
01c194d9 1870 unsigned char iir1;
40b36daa
AW		 1871 /*
1872 * Test for UARTs that do not reassert THRE when the
1873 * transmitter is idle and the interrupt has already
1874 * been cleared. Real 16550s should always reassert
1875 * this interrupt whenever the transmitter is idle and
1876 * the interrupt is enabled. Delays are necessary to
1877 * allow register changes to become visible.
1878 */
1879 spin_lock_irqsave(&up->port.lock, flags);
1880
1881 wait_for_xmitr(up, UART_LSR_THRE);
1882 serial_out_sync(up, UART_IER, UART_IER_THRI);
1883 udelay(1); /* allow THRE to set */
01c194d9 1884 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 1885 serial_out(up, UART_IER, 0);
1886 serial_out_sync(up, UART_IER, UART_IER_THRI);
1887 udelay(1); /* allow a working UART time to re-assert THRE */
1888 iir = serial_in(up, UART_IIR);
1889 serial_out(up, UART_IER, 0);
1890
1891 spin_unlock_irqrestore(&up->port.lock, flags);
1892
1893 /*
1894 * If the interrupt is not reasserted, setup a timer to
1895 * kick the UART on a regular basis.
1896 */
01c194d9 1897 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
40b36daa
AW		 1898 pr_debug("ttyS%d - using backup timer\n", port->line);
1899 up->timer.function = serial8250_backup_timeout;
1900 up->timer.data = (unsigned long)up;
1901 mod_timer(&up->timer, jiffies +
6f803cd0 1902 poll_timeout(up->port.timeout) + HZ / 5);
40b36daa
AW		 1903 }
1904 }
1905
1da177e4
LT		 1906 /*
1907 * If the "interrupt" for this port doesn't correspond with any
1908 * hardware interrupt, we use a timer-based system. The original
1909 * driver used to do this with IRQ0.
1910 */
1911 if (!is_real_interrupt(up->port.irq)) {
1da177e4 1912 up->timer.data = (unsigned long)up;
40b36daa 1913 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 1914 } else {
1915 retval = serial_link_irq_chain(up);
1916 if (retval)
1917 return retval;
1918 }
1919
1920 /*
1921 * Now, initialize the UART
1922 */
1923 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1924
1925 spin_lock_irqsave(&up->port.lock, flags);
1926 if (up->port.flags & UPF_FOURPORT) {
1927 if (!is_real_interrupt(up->port.irq))
1928 up->port.mctrl |= TIOCM_OUT1;
1929 } else
1930 /*
1931 * Most PC uarts need OUT2 raised to enable interrupts.
1932 */
1933 if (is_real_interrupt(up->port.irq))
1934 up->port.mctrl |= TIOCM_OUT2;
1935
1936 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1937
1938 /*
1939 * Do a quick test to see if we receive an
1940 * interrupt when we enable the TX irq.
1941 */
1942 serial_outp(up, UART_IER, UART_IER_THRI);
1943 lsr = serial_in(up, UART_LSR);
1944 iir = serial_in(up, UART_IIR);
1945 serial_outp(up, UART_IER, 0);
1946
1947 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1948 if (!(up->bugs & UART_BUG_TXEN)) {
1949 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1950 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1951 port->line);
1952 }
1953 } else {
67f7654e 1954 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1955 }
1956
1da177e4
LT		 1957 spin_unlock_irqrestore(&up->port.lock, flags);
1958
ad4c2aa6
CM		 1959 /*
1960 * Clear the interrupt registers again for luck, and clear the
1961 * saved flags to avoid getting false values from polling
1962 * routines or the previous session.
1963 */
1964 serial_inp(up, UART_LSR);
1965 serial_inp(up, UART_RX);
1966 serial_inp(up, UART_IIR);
1967 serial_inp(up, UART_MSR);
1968 up->lsr_saved_flags = 0;
1969 up->msr_saved_flags = 0;
1970
1da177e4
LT		 1971 /*
1972 * Finally, enable interrupts. Note: Modem status interrupts
1973 * are set via set_termios(), which will be occurring imminently
1974 * anyway, so we don't enable them here.
1975 */
1976 up->ier = UART_IER_RLSI | UART_IER_RDI;
1977 serial_outp(up, UART_IER, up->ier);
1978
1979 if (up->port.flags & UPF_FOURPORT) {
1980 unsigned int icp;
1981 /*
1982 * Enable interrupts on the AST Fourport board
1983 */
1984 icp = (up->port.iobase & 0xfe0) | 0x01f;
1985 outb_p(0x80, icp);
1986 (void) inb_p(icp);
1987 }
1988
1da177e4
LT		 1989 return 0;
1990}
1991
1992static void serial8250_shutdown(struct uart_port *port)
1993{
1994 struct uart_8250_port *up = (struct uart_8250_port *)port;
1995 unsigned long flags;
1996
1997 /*
1998 * Disable interrupts from this port
1999 */
2000 up->ier = 0;
2001 serial_outp(up, UART_IER, 0);
2002
2003 spin_lock_irqsave(&up->port.lock, flags);
2004 if (up->port.flags & UPF_FOURPORT) {
2005 /* reset interrupts on the AST Fourport board */
2006 inb((up->port.iobase & 0xfe0) | 0x1f);
2007 up->port.mctrl |= TIOCM_OUT1;
2008 } else
2009 up->port.mctrl &= ~TIOCM_OUT2;
2010
2011 serial8250_set_mctrl(&up->port, up->port.mctrl);
2012 spin_unlock_irqrestore(&up->port.lock, flags);
2013
2014 /*
2015 * Disable break condition and FIFOs
2016 */
2017 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2018 serial8250_clear_fifos(up);
2019
2020#ifdef CONFIG_SERIAL_8250_RSA
2021 /*
2022 * Reset the RSA board back to 115kbps compat mode.
2023 */
2024 disable_rsa(up);
2025#endif
2026
2027 /*
2028 * Read data port to reset things, and then unlink from
2029 * the IRQ chain.
2030 */
2031 (void) serial_in(up, UART_RX);
2032
40b36daa
AW		 2033 del_timer_sync(&up->timer);
2034 up->timer.function = serial8250_timeout;
2035 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2036 serial_unlink_irq_chain(up);
2037}
2038
2039static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2040{
2041 unsigned int quot;
2042
2043 /*
2044 * Handle magic divisors for baud rates above baud_base on
2045 * SMSC SuperIO chips.
2046 */
2047 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2048 baud == (port->uartclk/4))
2049 quot = 0x8001;
2050 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2051 baud == (port->uartclk/8))
2052 quot = 0x8002;
2053 else
2054 quot = uart_get_divisor(port, baud);
2055
2056 return quot;
2057}
2058
2059static void
606d099c
AC		 2060serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2061 struct ktermios *old)
1da177e4
LT		 2062{
2063 struct uart_8250_port *up = (struct uart_8250_port *)port;
2064 unsigned char cval, fcr = 0;
2065 unsigned long flags;
2066 unsigned int baud, quot;
2067
2068 switch (termios->c_cflag & CSIZE) {
2069 case CS5:
0a8b80c5 2070 cval = UART_LCR_WLEN5;
1da177e4
LT		 2071 break;
2072 case CS6:
0a8b80c5 2073 cval = UART_LCR_WLEN6;
1da177e4
LT		 2074 break;
2075 case CS7:
0a8b80c5 2076 cval = UART_LCR_WLEN7;
1da177e4
LT		 2077 break;
2078 default:
2079 case CS8:
0a8b80c5 2080 cval = UART_LCR_WLEN8;
1da177e4
LT		 2081 break;
2082 }
2083
2084 if (termios->c_cflag & CSTOPB)
0a8b80c5 2085 cval |= UART_LCR_STOP;
1da177e4
LT		 2086 if (termios->c_cflag & PARENB)
2087 cval |= UART_LCR_PARITY;
2088 if (!(termios->c_cflag & PARODD))
2089 cval |= UART_LCR_EPAR;
2090#ifdef CMSPAR
2091 if (termios->c_cflag & CMSPAR)
2092 cval |= UART_LCR_SPAR;
2093#endif
2094
2095 /*
2096 * Ask the core to calculate the divisor for us.
2097 */
bd71c182 2098 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1da177e4
LT		 2099 quot = serial8250_get_divisor(port, baud);
2100
2101 /*
4ba5e35d 2102 * Oxford Semi 952 rev B workaround
1da177e4 2103 */
4ba5e35d 2104 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2105 quot++;
1da177e4
LT		 2106
2107 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2108 if (baud < 2400)
2109 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2110 else
2111 fcr = uart_config[up->port.type].fcr;
2112 }
2113
2114 /*
2115 * MCR-based auto flow control. When AFE is enabled, RTS will be
2116 * deasserted when the receive FIFO contains more characters than
2117 * the trigger, or the MCR RTS bit is cleared. In the case where
2118 * the remote UART is not using CTS auto flow control, we must
2119 * have sufficient FIFO entries for the latency of the remote
2120 * UART to respond. IOW, at least 32 bytes of FIFO.
2121 */
2122 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2123 up->mcr &= ~UART_MCR_AFE;
2124 if (termios->c_cflag & CRTSCTS)
2125 up->mcr |= UART_MCR_AFE;
2126 }
2127
2128 /*
2129 * Ok, we're now changing the port state. Do it with
2130 * interrupts disabled.
2131 */
2132 spin_lock_irqsave(&up->port.lock, flags);
2133
2134 /*
2135 * Update the per-port timeout.
2136 */
2137 uart_update_timeout(port, termios->c_cflag, baud);
2138
2139 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2140 if (termios->c_iflag & INPCK)
2141 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2142 if (termios->c_iflag & (BRKINT | PARMRK))
2143 up->port.read_status_mask |= UART_LSR_BI;
2144
2145 /*
2146 * Characteres to ignore
2147 */
2148 up->port.ignore_status_mask = 0;
2149 if (termios->c_iflag & IGNPAR)
2150 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2151 if (termios->c_iflag & IGNBRK) {
2152 up->port.ignore_status_mask |= UART_LSR_BI;
2153 /*
2154 * If we're ignoring parity and break indicators,
2155 * ignore overruns too (for real raw support).
2156 */
2157 if (termios->c_iflag & IGNPAR)
2158 up->port.ignore_status_mask |= UART_LSR_OE;
2159 }
2160
2161 /*
2162 * ignore all characters if CREAD is not set
2163 */
2164 if ((termios->c_cflag & CREAD) == 0)
2165 up->port.ignore_status_mask |= UART_LSR_DR;
2166
2167 /*
2168 * CTS flow control flag and modem status interrupts
2169 */
2170 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2171 if (!(up->bugs & UART_BUG_NOMSR) &&
2172 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2173 up->ier |= UART_IER_MSI;
2174 if (up->capabilities & UART_CAP_UUE)
2175 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2176
2177 serial_out(up, UART_IER, up->ier);
2178
2179 if (up->capabilities & UART_CAP_EFR) {
2180 unsigned char efr = 0;
2181 /*
2182 * TI16C752/Startech hardware flow control. FIXME:
2183 * - TI16C752 requires control thresholds to be set.
2184 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2185 */
2186 if (termios->c_cflag & CRTSCTS)
2187 efr |= UART_EFR_CTS;
2188
2189 serial_outp(up, UART_LCR, 0xBF);
2190 serial_outp(up, UART_EFR, efr);
2191 }
2192
255341c6
JM		 2193#ifdef CONFIG_ARCH_OMAP15XX
2194 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2195 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2196 if (baud == 115200) {
2197 quot = 1;
2198 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2199 } else
2200 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2201 }
2202#endif
2203
1da177e4
LT		 2204 if (up->capabilities & UART_NATSEMI) {
2205 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2206 serial_outp(up, UART_LCR, 0xe0);
2207 } else {
2208 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2209 }
2210
b32b19b8 2211 serial_dl_write(up, quot);
1da177e4
LT		 2212
2213 /*
2214 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2215 * is written without DLAB set, this mode will be disabled.
2216 */
2217 if (up->port.type == PORT_16750)
2218 serial_outp(up, UART_FCR, fcr);
2219
2220 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2221 up->lcr = cval; /* Save LCR */
2222 if (up->port.type != PORT_16750) {
2223 if (fcr & UART_FCR_ENABLE_FIFO) {
2224 /* emulated UARTs (Lucent Venus 167x) need two steps */
2225 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2226 }
2227 serial_outp(up, UART_FCR, fcr); /* set fcr */
2228 }
2229 serial8250_set_mctrl(&up->port, up->port.mctrl);
2230 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2231 /* Don't rewrite B0 */
2232 if (tty_termios_baud_rate(termios))
2233 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2234}
2235
2236static void
2237serial8250_pm(struct uart_port *port, unsigned int state,
2238 unsigned int oldstate)
2239{
2240 struct uart_8250_port *p = (struct uart_8250_port *)port;
2241
2242 serial8250_set_sleep(p, state != 0);
2243
2244 if (p->pm)
2245 p->pm(port, state, oldstate);
2246}
2247
2248/*
2249 * Resource handling.
2250 */
2251static int serial8250_request_std_resource(struct uart_8250_port *up)
2252{
2253 unsigned int size = 8 << up->port.regshift;
2254 int ret = 0;
2255
2256 switch (up->port.iotype) {
85835f44
SS		 2257 case UPIO_AU:
2258 size = 0x100000;
2259 /* fall thru */
0b30d668
SS		 2260 case UPIO_TSI:
2261 case UPIO_MEM32:
1da177e4 2262 case UPIO_MEM:
beab697a 2263 case UPIO_DWAPB:
1da177e4
LT		 2264 if (!up->port.mapbase)
2265 break;
2266
2267 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2268 ret = -EBUSY;
2269 break;
2270 }
2271
2272 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2273 up->port.membase = ioremap_nocache(up->port.mapbase,
2274 size);
1da177e4
LT		 2275 if (!up->port.membase) {
2276 release_mem_region(up->port.mapbase, size);
2277 ret = -ENOMEM;
2278 }
2279 }
2280 break;
2281
2282 case UPIO_HUB6:
2283 case UPIO_PORT:
2284 if (!request_region(up->port.iobase, size, "serial"))
2285 ret = -EBUSY;
2286 break;
2287 }
2288 return ret;
2289}
2290
2291static void serial8250_release_std_resource(struct uart_8250_port *up)
2292{
2293 unsigned int size = 8 << up->port.regshift;
2294
2295 switch (up->port.iotype) {
85835f44
SS		 2296 case UPIO_AU:
2297 size = 0x100000;
2298 /* fall thru */
0b30d668
SS		 2299 case UPIO_TSI:
2300 case UPIO_MEM32:
1da177e4 2301 case UPIO_MEM:
beab697a 2302 case UPIO_DWAPB:
1da177e4
LT		 2303 if (!up->port.mapbase)
2304 break;
2305
2306 if (up->port.flags & UPF_IOREMAP) {
2307 iounmap(up->port.membase);
2308 up->port.membase = NULL;
2309 }
2310
2311 release_mem_region(up->port.mapbase, size);
2312 break;
2313
2314 case UPIO_HUB6:
2315 case UPIO_PORT:
2316 release_region(up->port.iobase, size);
2317 break;
2318 }
2319}
2320
2321static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2322{
2323 unsigned long start = UART_RSA_BASE << up->port.regshift;
2324 unsigned int size = 8 << up->port.regshift;
0b30d668 2325 int ret = -EINVAL;
1da177e4
LT		 2326
2327 switch (up->port.iotype) {
1da177e4
LT		 2328 case UPIO_HUB6:
2329 case UPIO_PORT:
2330 start += up->port.iobase;
0b30d668
SS		 2331 if (request_region(start, size, "serial-rsa"))
2332 ret = 0;
2333 else
1da177e4
LT		 2334 ret = -EBUSY;
2335 break;
2336 }
2337
2338 return ret;
2339}
2340
2341static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2342{
2343 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2344 unsigned int size = 8 << up->port.regshift;
2345
2346 switch (up->port.iotype) {
1da177e4
LT		 2347 case UPIO_HUB6:
2348 case UPIO_PORT:
2349 release_region(up->port.iobase + offset, size);
2350 break;
2351 }
2352}
2353
2354static void serial8250_release_port(struct uart_port *port)
2355{
2356 struct uart_8250_port *up = (struct uart_8250_port *)port;
2357
2358 serial8250_release_std_resource(up);
2359 if (up->port.type == PORT_RSA)
2360 serial8250_release_rsa_resource(up);
2361}
2362
2363static int serial8250_request_port(struct uart_port *port)
2364{
2365 struct uart_8250_port *up = (struct uart_8250_port *)port;
2366 int ret = 0;
2367
2368 ret = serial8250_request_std_resource(up);
2369 if (ret == 0 && up->port.type == PORT_RSA) {
2370 ret = serial8250_request_rsa_resource(up);
2371 if (ret < 0)
2372 serial8250_release_std_resource(up);
2373 }
2374
2375 return ret;
2376}
2377
2378static void serial8250_config_port(struct uart_port *port, int flags)
2379{
2380 struct uart_8250_port *up = (struct uart_8250_port *)port;
2381 int probeflags = PROBE_ANY;
2382 int ret;
2383
1da177e4
LT		 2384 /*
2385 * Find the region that we can probe for. This in turn
2386 * tells us whether we can probe for the type of port.
2387 */
2388 ret = serial8250_request_std_resource(up);
2389 if (ret < 0)
2390 return;
2391
2392 ret = serial8250_request_rsa_resource(up);
2393 if (ret < 0)
2394 probeflags &= ~PROBE_RSA;
2395
2396 if (flags & UART_CONFIG_TYPE)
2397 autoconfig(up, probeflags);
2398 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2399 autoconfig_irq(up);
2400
2401 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2402 serial8250_release_rsa_resource(up);
2403 if (up->port.type == PORT_UNKNOWN)
2404 serial8250_release_std_resource(up);
2405}
2406
2407static int
2408serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2409{
2410 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2411 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2412 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2413 ser->type == PORT_STARTECH)
2414 return -EINVAL;
2415 return 0;
2416}
2417
2418static const char *
2419serial8250_type(struct uart_port *port)
2420{
2421 int type = port->type;
2422
2423 if (type >= ARRAY_SIZE(uart_config))
2424 type = 0;
2425 return uart_config[type].name;
2426}
2427
2428static struct uart_ops serial8250_pops = {
2429 .tx_empty = serial8250_tx_empty,
2430 .set_mctrl = serial8250_set_mctrl,
2431 .get_mctrl = serial8250_get_mctrl,
2432 .stop_tx = serial8250_stop_tx,
2433 .start_tx = serial8250_start_tx,
2434 .stop_rx = serial8250_stop_rx,
2435 .enable_ms = serial8250_enable_ms,
2436 .break_ctl = serial8250_break_ctl,
2437 .startup = serial8250_startup,
2438 .shutdown = serial8250_shutdown,
2439 .set_termios = serial8250_set_termios,
2440 .pm = serial8250_pm,
2441 .type = serial8250_type,
2442 .release_port = serial8250_release_port,
2443 .request_port = serial8250_request_port,
2444 .config_port = serial8250_config_port,
2445 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2446#ifdef CONFIG_CONSOLE_POLL
2447 .poll_get_char = serial8250_get_poll_char,
2448 .poll_put_char = serial8250_put_poll_char,
2449#endif
1da177e4
LT		 2450};
2451
2452static struct uart_8250_port serial8250_ports[UART_NR];
2453
2454static void __init serial8250_isa_init_ports(void)
2455{
2456 struct uart_8250_port *up;
2457 static int first = 1;
2458 int i;
2459
2460 if (!first)
2461 return;
2462 first = 0;
2463
a61c2d78 2464 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2465 struct uart_8250_port *up = &serial8250_ports[i];
2466
2467 up->port.line = i;
2468 spin_lock_init(&up->port.lock);
2469
2470 init_timer(&up->timer);
2471 up->timer.function = serial8250_timeout;
2472
2473 /*
2474 * ALPHA_KLUDGE_MCR needs to be killed.
2475 */
2476 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2477 up->mcr_force = ALPHA_KLUDGE_MCR;
2478
2479 up->port.ops = &serial8250_pops;
2480 }
2481
44454bcd 2482 for (i = 0, up = serial8250_ports;
a61c2d78 2483 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2484 i++, up++) {
2485 up->port.iobase = old_serial_port[i].port;
2486 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2487 up->port.uartclk = old_serial_port[i].baud_base * 16;
2488 up->port.flags = old_serial_port[i].flags;
2489 up->port.hub6 = old_serial_port[i].hub6;
2490 up->port.membase = old_serial_port[i].iomem_base;
2491 up->port.iotype = old_serial_port[i].io_type;
2492 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2493 if (share_irqs)
2494 up->port.flags |= UPF_SHARE_IRQ;
2495 }
2496}
2497
2498static void __init
2499serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2500{
2501 int i;
2502
2503 serial8250_isa_init_ports();
2504
a61c2d78 2505 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2506 struct uart_8250_port *up = &serial8250_ports[i];
2507
2508 up->port.dev = dev;
2509 uart_add_one_port(drv, &up->port);
2510 }
2511}
2512
2513#ifdef CONFIG_SERIAL_8250_CONSOLE
2514
d358788f
RK		 2515static void serial8250_console_putchar(struct uart_port *port, int ch)
2516{
2517 struct uart_8250_port *up = (struct uart_8250_port *)port;
2518
2519 wait_for_xmitr(up, UART_LSR_THRE);
2520 serial_out(up, UART_TX, ch);
2521}
2522
1da177e4
LT		 2523/*
2524 * Print a string to the serial port trying not to disturb
2525 * any possible real use of the port...
2526 *
2527 * The console_lock must be held when we get here.
2528 */
2529static void
2530serial8250_console_write(struct console *co, const char *s, unsigned int count)
2531{
2532 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2533 unsigned long flags;
1da177e4 2534 unsigned int ier;
d8a5a8d7 2535 int locked = 1;
1da177e4 2536
78512ece
AM		 2537 touch_nmi_watchdog();
2538
68aa2c0d
AM		 2539 local_irq_save(flags);
2540 if (up->port.sysrq) {
2541 /* serial8250_handle_port() already took the lock */
2542 locked = 0;
2543 } else if (oops_in_progress) {
2544 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2545 } else
68aa2c0d 2546 spin_lock(&up->port.lock);
d8a5a8d7 2547
1da177e4 2548 /*
dc7bf130 2549 * First save the IER then disable the interrupts
1da177e4
LT		 2550 */
2551 ier = serial_in(up, UART_IER);
2552
2553 if (up->capabilities & UART_CAP_UUE)
2554 serial_out(up, UART_IER, UART_IER_UUE);
2555 else
2556 serial_out(up, UART_IER, 0);
2557
d358788f 2558 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2559
2560 /*
2561 * Finally, wait for transmitter to become empty
2562 * and restore the IER
2563 */
f91a3715 2564 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2565 serial_out(up, UART_IER, ier);
d8a5a8d7 2566
ad4c2aa6
CM		 2567 /*
2568 * The receive handling will happen properly because the
2569 * receive ready bit will still be set; it is not cleared
2570 * on read. However, modem control will not, we must
2571 * call it if we have saved something in the saved flags
2572 * while processing with interrupts off.
2573 */
2574 if (up->msr_saved_flags)
2575 check_modem_status(up);
2576
d8a5a8d7 2577 if (locked)
68aa2c0d
AM		 2578 spin_unlock(&up->port.lock);
2579 local_irq_restore(flags);
1da177e4
LT		 2580}
2581
118c0ace 2582static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2583{
2584 struct uart_port *port;
2585 int baud = 9600;
2586 int bits = 8;
2587 int parity = 'n';
2588 int flow = 'n';
2589
2590 /*
2591 * Check whether an invalid uart number has been specified, and
2592 * if so, search for the first available port that does have
2593 * console support.
2594 */
a61c2d78 2595 if (co->index >= nr_uarts)
1da177e4
LT		 2596 co->index = 0;
2597 port = &serial8250_ports[co->index].port;
2598 if (!port->iobase && !port->membase)
2599 return -ENODEV;
2600
2601 if (options)
2602 uart_parse_options(options, &baud, &parity, &bits, &flow);
2603
2604 return uart_set_options(port, co, baud, parity, bits, flow);
2605}
2606
b6b1d877 2607static int serial8250_console_early_setup(void)
18a8bd94
YL		 2608{
2609 return serial8250_find_port_for_earlycon();
2610}
2611
1da177e4
LT		 2612static struct uart_driver serial8250_reg;
2613static struct console serial8250_console = {
2614 .name = "ttyS",
2615 .write = serial8250_console_write,
2616 .device = uart_console_device,
2617 .setup = serial8250_console_setup,
18a8bd94 2618 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2619 .flags = CON_PRINTBUFFER,
2620 .index = -1,
2621 .data = &serial8250_reg,
2622};
2623
2624static int __init serial8250_console_init(void)
2625{
05d81d22
EB		 2626 if (nr_uarts > UART_NR)
2627 nr_uarts = UART_NR;
2628
1da177e4
LT		 2629 serial8250_isa_init_ports();
2630 register_console(&serial8250_console);
2631 return 0;
2632}
2633console_initcall(serial8250_console_init);
2634
18a8bd94 2635int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2636{
2637 int line;
2638 struct uart_port *port;
2639
a61c2d78 2640 for (line = 0; line < nr_uarts; line++) {
1da177e4 2641 port = &serial8250_ports[line].port;
50aec3b5 2642 if (uart_match_port(p, port))
1da177e4
LT		 2643 return line;
2644 }
2645 return -ENODEV;
2646}
2647
1da177e4
LT		 2648#define SERIAL8250_CONSOLE &serial8250_console
2649#else
2650#define SERIAL8250_CONSOLE NULL
2651#endif
2652
2653static struct uart_driver serial8250_reg = {
2654 .owner = THIS_MODULE,
2655 .driver_name = "serial",
1da177e4
LT		 2656 .dev_name = "ttyS",
2657 .major = TTY_MAJOR,
2658 .minor = 64,
2659 .nr = UART_NR,
2660 .cons = SERIAL8250_CONSOLE,
2661};
2662
d856c666
RK		 2663/*
2664 * early_serial_setup - early registration for 8250 ports
2665 *
2666 * Setup an 8250 port structure prior to console initialisation. Use
2667 * after console initialisation will cause undefined behaviour.
2668 */
1da177e4
LT		 2669int __init early_serial_setup(struct uart_port *port)
2670{
2671 if (port->line >= ARRAY_SIZE(serial8250_ports))
2672 return -ENODEV;
2673
2674 serial8250_isa_init_ports();
2675 serial8250_ports[port->line].port = *port;
2676 serial8250_ports[port->line].port.ops = &serial8250_pops;
2677 return 0;
2678}
2679
2680/**
2681 * serial8250_suspend_port - suspend one serial port
2682 * @line: serial line number
1da177e4
LT		 2683 *
2684 * Suspend one serial port.
2685 */
2686void serial8250_suspend_port(int line)
2687{
2688 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2689}
2690
2691/**
2692 * serial8250_resume_port - resume one serial port
2693 * @line: serial line number
1da177e4
LT		 2694 *
2695 * Resume one serial port.
2696 */
2697void serial8250_resume_port(int line)
2698{
b5b82df6
DW		 2699 struct uart_8250_port *up = &serial8250_ports[line];
2700
2701 if (up->capabilities & UART_NATSEMI) {
2702 unsigned char tmp;
2703
2704 /* Ensure it's still in high speed mode */
2705 serial_outp(up, UART_LCR, 0xE0);
2706
2707 tmp = serial_in(up, 0x04); /* EXCR2 */
2708 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2709 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2710 serial_outp(up, 0x04, tmp);
2711
2712 serial_outp(up, UART_LCR, 0);
2713 }
2714 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2715}
2716
2717/*
2718 * Register a set of serial devices attached to a platform device. The
2719 * list is terminated with a zero flags entry, which means we expect
2720 * all entries to have at least UPF_BOOT_AUTOCONF set.
2721 */
3ae5eaec 2722static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2723{
3ae5eaec 2724 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2725 struct uart_port port;
ec9f47cd 2726 int ret, i;
1da177e4
LT		 2727
2728 memset(&port, 0, sizeof(struct uart_port));
2729
ec9f47cd 2730 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2731 port.iobase = p->iobase;
2732 port.membase = p->membase;
2733 port.irq = p->irq;
2734 port.uartclk = p->uartclk;
2735 port.regshift = p->regshift;
2736 port.iotype = p->iotype;
2737 port.flags = p->flags;
2738 port.mapbase = p->mapbase;
2739 port.hub6 = p->hub6;
2740 port.private_data = p->private_data;
2741 port.dev = &dev->dev;
1da177e4
LT		 2742 if (share_irqs)
2743 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2744 ret = serial8250_register_port(&port);
2745 if (ret < 0) {
3ae5eaec 2746 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2747 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2748 p->iobase, (unsigned long long)p->mapbase,
2749 p->irq, ret);
ec9f47cd 2750 }
1da177e4
LT		 2751 }
2752 return 0;
2753}
2754
2755/*
2756 * Remove serial ports registered against a platform device.
2757 */
3ae5eaec 2758static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2759{
2760 int i;
2761
a61c2d78 2762 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2763 struct uart_8250_port *up = &serial8250_ports[i];
2764
3ae5eaec 2765 if (up->port.dev == &dev->dev)
1da177e4
LT		 2766 serial8250_unregister_port(i);
2767 }
2768 return 0;
2769}
2770
3ae5eaec 2771static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2772{
2773 int i;
2774
1da177e4
LT		 2775 for (i = 0; i < UART_NR; i++) {
2776 struct uart_8250_port *up = &serial8250_ports[i];
2777
3ae5eaec 2778 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2779 uart_suspend_port(&serial8250_reg, &up->port);
2780 }
2781
2782 return 0;
2783}
2784
3ae5eaec 2785static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2786{
2787 int i;
2788
1da177e4
LT		 2789 for (i = 0; i < UART_NR; i++) {
2790 struct uart_8250_port *up = &serial8250_ports[i];
2791
3ae5eaec 2792 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 2793 serial8250_resume_port(i);
1da177e4
LT		 2794 }
2795
2796 return 0;
2797}
2798
3ae5eaec 2799static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2800 .probe = serial8250_probe,
2801 .remove = __devexit_p(serial8250_remove),
2802 .suspend = serial8250_suspend,
2803 .resume = serial8250_resume,
3ae5eaec
RK		 2804 .driver = {
2805 .name = "serial8250",
7493a314 2806 .owner = THIS_MODULE,
3ae5eaec 2807 },
1da177e4
LT		 2808};
2809
2810/*
2811 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2812 * in the table in include/asm/serial.h
2813 */
2814static struct platform_device *serial8250_isa_devs;
2815
2816/*
2817 * serial8250_register_port and serial8250_unregister_port allows for
2818 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2819 * modems and PCI multiport cards.
2820 */
f392ecfa 2821static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2822
2823static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2824{
2825 int i;
2826
2827 /*
2828 * First, find a port entry which matches.
2829 */
a61c2d78 2830 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2831 if (uart_match_port(&serial8250_ports[i].port, port))
2832 return &serial8250_ports[i];
2833
2834 /*
2835 * We didn't find a matching entry, so look for the first
2836 * free entry. We look for one which hasn't been previously
2837 * used (indicated by zero iobase).
2838 */
a61c2d78 2839 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2840 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2841 serial8250_ports[i].port.iobase == 0)
2842 return &serial8250_ports[i];
2843
2844 /*
2845 * That also failed. Last resort is to find any entry which
2846 * doesn't have a real port associated with it.
2847 */
a61c2d78 2848 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2849 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2850 return &serial8250_ports[i];
2851
2852 return NULL;
2853}
2854
2855/**
2856 * serial8250_register_port - register a serial port
2857 * @port: serial port template
2858 *
2859 * Configure the serial port specified by the request. If the
2860 * port exists and is in use, it is hung up and unregistered
2861 * first.
2862 *
2863 * The port is then probed and if necessary the IRQ is autodetected
2864 * If this fails an error is returned.
2865 *
2866 * On success the port is ready to use and the line number is returned.
2867 */
2868int serial8250_register_port(struct uart_port *port)
2869{
2870 struct uart_8250_port *uart;
2871 int ret = -ENOSPC;
2872
2873 if (port->uartclk == 0)
2874 return -EINVAL;
2875
f392ecfa 2876 mutex_lock(&serial_mutex);
1da177e4
LT		 2877
2878 uart = serial8250_find_match_or_unused(port);
2879 if (uart) {
2880 uart_remove_one_port(&serial8250_reg, &uart->port);
2881
74a19741
WN		 2882 uart->port.iobase = port->iobase;
2883 uart->port.membase = port->membase;
2884 uart->port.irq = port->irq;
2885 uart->port.uartclk = port->uartclk;
2886 uart->port.fifosize = port->fifosize;
2887 uart->port.regshift = port->regshift;
2888 uart->port.iotype = port->iotype;
2889 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2890 uart->port.mapbase = port->mapbase;
2891 uart->port.private_data = port->private_data;
1da177e4
LT		 2892 if (port->dev)
2893 uart->port.dev = port->dev;
2894
2895 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2896 if (ret == 0)
2897 ret = uart->port.line;
2898 }
f392ecfa 2899 mutex_unlock(&serial_mutex);
1da177e4
LT		 2900
2901 return ret;
2902}
2903EXPORT_SYMBOL(serial8250_register_port);
2904
2905/**
2906 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2907 * @line: serial line number
2908 *
2909 * Remove one serial port. This may not be called from interrupt
2910 * context. We hand the port back to the our control.
2911 */
2912void serial8250_unregister_port(int line)
2913{
2914 struct uart_8250_port *uart = &serial8250_ports[line];
2915
f392ecfa 2916 mutex_lock(&serial_mutex);
1da177e4
LT		 2917 uart_remove_one_port(&serial8250_reg, &uart->port);
2918 if (serial8250_isa_devs) {
2919 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2920 uart->port.type = PORT_UNKNOWN;
2921 uart->port.dev = &serial8250_isa_devs->dev;
2922 uart_add_one_port(&serial8250_reg, &uart->port);
2923 } else {
2924 uart->port.dev = NULL;
2925 }
f392ecfa 2926 mutex_unlock(&serial_mutex);
1da177e4
LT		 2927}
2928EXPORT_SYMBOL(serial8250_unregister_port);
2929
2930static int __init serial8250_init(void)
2931{
2932 int ret, i;
2933
a61c2d78
DJ		 2934 if (nr_uarts > UART_NR)
2935 nr_uarts = UART_NR;
2936
1da177e4 2937 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2938 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2939 share_irqs ? "en" : "dis");
2940
2941 for (i = 0; i < NR_IRQS; i++)
2942 spin_lock_init(&irq_lists[i].lock);
2943
2944 ret = uart_register_driver(&serial8250_reg);
2945 if (ret)
2946 goto out;
2947
7493a314
DT		 2948 serial8250_isa_devs = platform_device_alloc("serial8250",
2949 PLAT8250_DEV_LEGACY);
2950 if (!serial8250_isa_devs) {
2951 ret = -ENOMEM;
bc965a7f 2952 goto unreg_uart_drv;
1da177e4
LT		 2953 }
2954
7493a314
DT		 2955 ret = platform_device_add(serial8250_isa_devs);
2956 if (ret)
2957 goto put_dev;
2958
1da177e4
LT		 2959 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2960
bc965a7f
RK		 2961 ret = platform_driver_register(&serial8250_isa_driver);
2962 if (ret == 0)
2963 goto out;
1da177e4 2964
bc965a7f 2965 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2966 put_dev:
2967 platform_device_put(serial8250_isa_devs);
7493a314 2968 unreg_uart_drv:
1da177e4
LT		 2969 uart_unregister_driver(&serial8250_reg);
2970 out:
2971 return ret;
2972}
2973
2974static void __exit serial8250_exit(void)
2975{
2976 struct platform_device *isa_dev = serial8250_isa_devs;
2977
2978 /*
2979 * This tells serial8250_unregister_port() not to re-register
2980 * the ports (thereby making serial8250_isa_driver permanently
2981 * in use.)
2982 */
2983 serial8250_isa_devs = NULL;
2984
3ae5eaec 2985 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2986 platform_device_unregister(isa_dev);
2987
2988 uart_unregister_driver(&serial8250_reg);
2989}
2990
2991module_init(serial8250_init);
2992module_exit(serial8250_exit);
2993
2994EXPORT_SYMBOL(serial8250_suspend_port);
2995EXPORT_SYMBOL(serial8250_resume_port);
2996
2997MODULE_LICENSE("GPL");
2998MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2999
3000module_param(share_irqs, uint, 0644);
3001MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3002 " (unsafe)");
3003
a61c2d78
DJ		 3004module_param(nr_uarts, uint, 0644);
3005MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3006
1da177e4
LT		 3007#ifdef CONFIG_SERIAL_8250_RSA
3008module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3009MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3010#endif
3011MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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