]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/serial/8250.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] Serial: Mobility's 16550A ports need a helping hand
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
36#include <linux/device.h>
37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
51 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4
LT		 55
56/*
57 * Debugging.
58 */
59#if 0
60#define DEBUG_AUTOCONF(fmt...) printk(fmt)
61#else
62#define DEBUG_AUTOCONF(fmt...) do { } while (0)
63#endif
64
65#if 0
66#define DEBUG_INTR(fmt...) printk(fmt)
67#else
68#define DEBUG_INTR(fmt...) do { } while (0)
69#endif
70
71#define PASS_LIMIT 256
72
73/*
74 * We default to IRQ0 for the "no irq" hack. Some
75 * machine types want others as well - they're free
76 * to redefine this in their header file.
77 */
78#define is_real_interrupt(irq) ((irq) != 0)
79
80/*
81 * This converts from our new CONFIG_ symbols to the symbols
82 * that asm/serial.h expects. You _NEED_ to comment out the
83 * linux/config.h include contained inside asm/serial.h for
84 * this to work.
85 */
86#undef CONFIG_SERIAL_MANY_PORTS
87#undef CONFIG_SERIAL_DETECT_IRQ
88#undef CONFIG_SERIAL_MULTIPORT
89#undef CONFIG_HUB6
90
91#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92#define CONFIG_SERIAL_DETECT_IRQ 1
93#endif
94#ifdef CONFIG_SERIAL_8250_MULTIPORT
95#define CONFIG_SERIAL_MULTIPORT 1
96#endif
97#ifdef CONFIG_SERIAL_8250_MANY_PORTS
98#define CONFIG_SERIAL_MANY_PORTS 1
99#endif
100
101/*
102 * HUB6 is always on. This will be removed once the header
103 * files have been cleaned.
104 */
105#define CONFIG_HUB6 1
106
107#include <asm/serial.h>
108
109/*
110 * SERIAL_PORT_DFNS tells us about built-in ports that have no
111 * standard enumeration mechanism. Platforms that can find all
112 * serial ports via mechanisms like ACPI or PCI need not supply it.
113 */
114#ifndef SERIAL_PORT_DFNS
115#define SERIAL_PORT_DFNS
116#endif
117
118static struct old_serial_port old_serial_port[] = {
119 SERIAL_PORT_DFNS /* defined in asm/serial.h */
120};
121
122#define UART_NR (ARRAY_SIZE(old_serial_port) + CONFIG_SERIAL_8250_NR_UARTS)
123
124#ifdef CONFIG_SERIAL_8250_RSA
125
126#define PORT_RSA_MAX 4
127static unsigned long probe_rsa[PORT_RSA_MAX];
128static unsigned int probe_rsa_count;
129#endif /* CONFIG_SERIAL_8250_RSA */
130
131struct uart_8250_port {
132 struct uart_port port;
133 struct timer_list timer; /* "no irq" timer */
134 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 135 unsigned short capabilities; /* port capabilities */
136 unsigned short bugs; /* port bugs */
1da177e4 137 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 138 unsigned char acr;
139 unsigned char ier;
140 unsigned char lcr;
141 unsigned char mcr;
142 unsigned char mcr_mask; /* mask of user bits */
143 unsigned char mcr_force; /* mask of forced bits */
144 unsigned char lsr_break_flag;
145
146 /*
147 * We provide a per-port pm hook.
148 */
149 void (*pm)(struct uart_port *port,
150 unsigned int state, unsigned int old);
151};
152
153struct irq_info {
154 spinlock_t lock;
155 struct list_head *head;
156};
157
158static struct irq_info irq_lists[NR_IRQS];
159
160/*
161 * Here we define the default xmit fifo size used for each type of UART.
162 */
163static const struct serial8250_config uart_config[] = {
164 [PORT_UNKNOWN] = {
165 .name = "unknown",
166 .fifo_size = 1,
167 .tx_loadsz = 1,
168 },
169 [PORT_8250] = {
170 .name = "8250",
171 .fifo_size = 1,
172 .tx_loadsz = 1,
173 },
174 [PORT_16450] = {
175 .name = "16450",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16550] = {
180 .name = "16550",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16550A] = {
185 .name = "16550A",
186 .fifo_size = 16,
187 .tx_loadsz = 16,
188 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
189 .flags = UART_CAP_FIFO,
190 },
191 [PORT_CIRRUS] = {
192 .name = "Cirrus",
193 .fifo_size = 1,
194 .tx_loadsz = 1,
195 },
196 [PORT_16650] = {
197 .name = "ST16650",
198 .fifo_size = 1,
199 .tx_loadsz = 1,
200 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
201 },
202 [PORT_16650V2] = {
203 .name = "ST16650V2",
204 .fifo_size = 32,
205 .tx_loadsz = 16,
206 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
207 UART_FCR_T_TRIG_00,
208 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
209 },
210 [PORT_16750] = {
211 .name = "TI16750",
212 .fifo_size = 64,
213 .tx_loadsz = 64,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
215 UART_FCR7_64BYTE,
216 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
217 },
218 [PORT_STARTECH] = {
219 .name = "Startech",
220 .fifo_size = 1,
221 .tx_loadsz = 1,
222 },
223 [PORT_16C950] = {
224 .name = "16C950/954",
225 .fifo_size = 128,
226 .tx_loadsz = 128,
227 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
228 .flags = UART_CAP_FIFO,
229 },
230 [PORT_16654] = {
231 .name = "ST16654",
232 .fifo_size = 64,
233 .tx_loadsz = 32,
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
235 UART_FCR_T_TRIG_10,
236 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
237 },
238 [PORT_16850] = {
239 .name = "XR16850",
240 .fifo_size = 128,
241 .tx_loadsz = 128,
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
244 },
245 [PORT_RSA] = {
246 .name = "RSA",
247 .fifo_size = 2048,
248 .tx_loadsz = 2048,
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
250 .flags = UART_CAP_FIFO,
251 },
252 [PORT_NS16550A] = {
253 .name = "NS16550A",
254 .fifo_size = 16,
255 .tx_loadsz = 16,
256 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
257 .flags = UART_CAP_FIFO | UART_NATSEMI,
258 },
259 [PORT_XSCALE] = {
260 .name = "XScale",
261 .fifo_size = 32,
262 .tx_loadsz = 32,
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
264 .flags = UART_CAP_FIFO | UART_CAP_UUE,
265 },
266};
267
268static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
269{
270 offset <<= up->port.regshift;
271
272 switch (up->port.iotype) {
273 case UPIO_HUB6:
274 outb(up->port.hub6 - 1 + offset, up->port.iobase);
275 return inb(up->port.iobase + 1);
276
277 case UPIO_MEM:
278 return readb(up->port.membase + offset);
279
280 case UPIO_MEM32:
281 return readl(up->port.membase + offset);
282
283 default:
284 return inb(up->port.iobase + offset);
285 }
286}
287
288static _INLINE_ void
289serial_out(struct uart_8250_port *up, int offset, int value)
290{
291 offset <<= up->port.regshift;
292
293 switch (up->port.iotype) {
294 case UPIO_HUB6:
295 outb(up->port.hub6 - 1 + offset, up->port.iobase);
296 outb(value, up->port.iobase + 1);
297 break;
298
299 case UPIO_MEM:
300 writeb(value, up->port.membase + offset);
301 break;
302
303 case UPIO_MEM32:
304 writel(value, up->port.membase + offset);
305 break;
306
307 default:
308 outb(value, up->port.iobase + offset);
309 }
310}
311
312/*
313 * We used to support using pause I/O for certain machines. We
314 * haven't supported this for a while, but just in case it's badly
315 * needed for certain old 386 machines, I've left these #define's
316 * in....
317 */
318#define serial_inp(up, offset) serial_in(up, offset)
319#define serial_outp(up, offset, value) serial_out(up, offset, value)
320
321
322/*
323 * For the 16C950
324 */
325static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
326{
327 serial_out(up, UART_SCR, offset);
328 serial_out(up, UART_ICR, value);
329}
330
331static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
332{
333 unsigned int value;
334
335 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
336 serial_out(up, UART_SCR, offset);
337 value = serial_in(up, UART_ICR);
338 serial_icr_write(up, UART_ACR, up->acr);
339
340 return value;
341}
342
343/*
344 * FIFO support.
345 */
346static inline void serial8250_clear_fifos(struct uart_8250_port *p)
347{
348 if (p->capabilities & UART_CAP_FIFO) {
349 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
350 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
351 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
352 serial_outp(p, UART_FCR, 0);
353 }
354}
355
356/*
357 * IER sleep support. UARTs which have EFRs need the "extended
358 * capability" bit enabled. Note that on XR16C850s, we need to
359 * reset LCR to write to IER.
360 */
361static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
362{
363 if (p->capabilities & UART_CAP_SLEEP) {
364 if (p->capabilities & UART_CAP_EFR) {
365 serial_outp(p, UART_LCR, 0xBF);
366 serial_outp(p, UART_EFR, UART_EFR_ECB);
367 serial_outp(p, UART_LCR, 0);
368 }
369 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
370 if (p->capabilities & UART_CAP_EFR) {
371 serial_outp(p, UART_LCR, 0xBF);
372 serial_outp(p, UART_EFR, 0);
373 serial_outp(p, UART_LCR, 0);
374 }
375 }
376}
377
378#ifdef CONFIG_SERIAL_8250_RSA
379/*
380 * Attempts to turn on the RSA FIFO. Returns zero on failure.
381 * We set the port uart clock rate if we succeed.
382 */
383static int __enable_rsa(struct uart_8250_port *up)
384{
385 unsigned char mode;
386 int result;
387
388 mode = serial_inp(up, UART_RSA_MSR);
389 result = mode & UART_RSA_MSR_FIFO;
390
391 if (!result) {
392 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
393 mode = serial_inp(up, UART_RSA_MSR);
394 result = mode & UART_RSA_MSR_FIFO;
395 }
396
397 if (result)
398 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
399
400 return result;
401}
402
403static void enable_rsa(struct uart_8250_port *up)
404{
405 if (up->port.type == PORT_RSA) {
406 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
407 spin_lock_irq(&up->port.lock);
408 __enable_rsa(up);
409 spin_unlock_irq(&up->port.lock);
410 }
411 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
412 serial_outp(up, UART_RSA_FRR, 0);
413 }
414}
415
416/*
417 * Attempts to turn off the RSA FIFO. Returns zero on failure.
418 * It is unknown why interrupts were disabled in here. However,
419 * the caller is expected to preserve this behaviour by grabbing
420 * the spinlock before calling this function.
421 */
422static void disable_rsa(struct uart_8250_port *up)
423{
424 unsigned char mode;
425 int result;
426
427 if (up->port.type == PORT_RSA &&
428 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
429 spin_lock_irq(&up->port.lock);
430
431 mode = serial_inp(up, UART_RSA_MSR);
432 result = !(mode & UART_RSA_MSR_FIFO);
433
434 if (!result) {
435 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
436 mode = serial_inp(up, UART_RSA_MSR);
437 result = !(mode & UART_RSA_MSR_FIFO);
438 }
439
440 if (result)
441 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
442 spin_unlock_irq(&up->port.lock);
443 }
444}
445#endif /* CONFIG_SERIAL_8250_RSA */
446
447/*
448 * This is a quickie test to see how big the FIFO is.
449 * It doesn't work at all the time, more's the pity.
450 */
451static int size_fifo(struct uart_8250_port *up)
452{
453 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
454 int count;
455
456 old_lcr = serial_inp(up, UART_LCR);
457 serial_outp(up, UART_LCR, 0);
458 old_fcr = serial_inp(up, UART_FCR);
459 old_mcr = serial_inp(up, UART_MCR);
460 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
461 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
462 serial_outp(up, UART_MCR, UART_MCR_LOOP);
463 serial_outp(up, UART_LCR, UART_LCR_DLAB);
464 old_dll = serial_inp(up, UART_DLL);
465 old_dlm = serial_inp(up, UART_DLM);
466 serial_outp(up, UART_DLL, 0x01);
467 serial_outp(up, UART_DLM, 0x00);
468 serial_outp(up, UART_LCR, 0x03);
469 for (count = 0; count < 256; count++)
470 serial_outp(up, UART_TX, count);
471 mdelay(20);/* FIXME - schedule_timeout */
472 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
473 (count < 256); count++)
474 serial_inp(up, UART_RX);
475 serial_outp(up, UART_FCR, old_fcr);
476 serial_outp(up, UART_MCR, old_mcr);
477 serial_outp(up, UART_LCR, UART_LCR_DLAB);
478 serial_outp(up, UART_DLL, old_dll);
479 serial_outp(up, UART_DLM, old_dlm);
480 serial_outp(up, UART_LCR, old_lcr);
481
482 return count;
483}
484
485/*
486 * Read UART ID using the divisor method - set DLL and DLM to zero
487 * and the revision will be in DLL and device type in DLM. We
488 * preserve the device state across this.
489 */
490static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
491{
492 unsigned char old_dll, old_dlm, old_lcr;
493 unsigned int id;
494
495 old_lcr = serial_inp(p, UART_LCR);
496 serial_outp(p, UART_LCR, UART_LCR_DLAB);
497
498 old_dll = serial_inp(p, UART_DLL);
499 old_dlm = serial_inp(p, UART_DLM);
500
501 serial_outp(p, UART_DLL, 0);
502 serial_outp(p, UART_DLM, 0);
503
504 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
505
506 serial_outp(p, UART_DLL, old_dll);
507 serial_outp(p, UART_DLM, old_dlm);
508 serial_outp(p, UART_LCR, old_lcr);
509
510 return id;
511}
512
513/*
514 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
515 * When this function is called we know it is at least a StarTech
516 * 16650 V2, but it might be one of several StarTech UARTs, or one of
517 * its clones. (We treat the broken original StarTech 16650 V1 as a
518 * 16550, and why not? Startech doesn't seem to even acknowledge its
519 * existence.)
520 *
521 * What evil have men's minds wrought...
522 */
523static void autoconfig_has_efr(struct uart_8250_port *up)
524{
525 unsigned int id1, id2, id3, rev;
526
527 /*
528 * Everything with an EFR has SLEEP
529 */
530 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
531
532 /*
533 * First we check to see if it's an Oxford Semiconductor UART.
534 *
535 * If we have to do this here because some non-National
536 * Semiconductor clone chips lock up if you try writing to the
537 * LSR register (which serial_icr_read does)
538 */
539
540 /*
541 * Check for Oxford Semiconductor 16C950.
542 *
543 * EFR [4] must be set else this test fails.
544 *
545 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
546 * claims that it's needed for 952 dual UART's (which are not
547 * recommended for new designs).
548 */
549 up->acr = 0;
550 serial_out(up, UART_LCR, 0xBF);
551 serial_out(up, UART_EFR, UART_EFR_ECB);
552 serial_out(up, UART_LCR, 0x00);
553 id1 = serial_icr_read(up, UART_ID1);
554 id2 = serial_icr_read(up, UART_ID2);
555 id3 = serial_icr_read(up, UART_ID3);
556 rev = serial_icr_read(up, UART_REV);
557
558 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
559
560 if (id1 == 0x16 && id2 == 0xC9 &&
561 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
562 up->port.type = PORT_16C950;
4ba5e35d
RK		 563
564 /*
565 * Enable work around for the Oxford Semiconductor 952 rev B
566 * chip which causes it to seriously miscalculate baud rates
567 * when DLL is 0.
568 */
569 if (id3 == 0x52 && rev == 0x01)
570 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 571 return;
572 }
573
574 /*
575 * We check for a XR16C850 by setting DLL and DLM to 0, and then
576 * reading back DLL and DLM. The chip type depends on the DLM
577 * value read back:
578 * 0x10 - XR16C850 and the DLL contains the chip revision.
579 * 0x12 - XR16C2850.
580 * 0x14 - XR16C854.
581 */
582 id1 = autoconfig_read_divisor_id(up);
583 DEBUG_AUTOCONF("850id=%04x ", id1);
584
585 id2 = id1 >> 8;
586 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 587 up->port.type = PORT_16850;
588 return;
589 }
590
591 /*
592 * It wasn't an XR16C850.
593 *
594 * We distinguish between the '654 and the '650 by counting
595 * how many bytes are in the FIFO. I'm using this for now,
596 * since that's the technique that was sent to me in the
597 * serial driver update, but I'm not convinced this works.
598 * I've had problems doing this in the past. -TYT
599 */
600 if (size_fifo(up) == 64)
601 up->port.type = PORT_16654;
602 else
603 up->port.type = PORT_16650V2;
604}
605
606/*
607 * We detected a chip without a FIFO. Only two fall into
608 * this category - the original 8250 and the 16450. The
609 * 16450 has a scratch register (accessible with LCR=0)
610 */
611static void autoconfig_8250(struct uart_8250_port *up)
612{
613 unsigned char scratch, status1, status2;
614
615 up->port.type = PORT_8250;
616
617 scratch = serial_in(up, UART_SCR);
618 serial_outp(up, UART_SCR, 0xa5);
619 status1 = serial_in(up, UART_SCR);
620 serial_outp(up, UART_SCR, 0x5a);
621 status2 = serial_in(up, UART_SCR);
622 serial_outp(up, UART_SCR, scratch);
623
624 if (status1 == 0xa5 && status2 == 0x5a)
625 up->port.type = PORT_16450;
626}
627
628static int broken_efr(struct uart_8250_port *up)
629{
630 /*
631 * Exar ST16C2550 "A2" devices incorrectly detect as
632 * having an EFR, and report an ID of 0x0201. See
633 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
634 */
635 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
636 return 1;
637
638 return 0;
639}
640
641/*
642 * We know that the chip has FIFOs. Does it have an EFR? The
643 * EFR is located in the same register position as the IIR and
644 * we know the top two bits of the IIR are currently set. The
645 * EFR should contain zero. Try to read the EFR.
646 */
647static void autoconfig_16550a(struct uart_8250_port *up)
648{
649 unsigned char status1, status2;
650 unsigned int iersave;
651
652 up->port.type = PORT_16550A;
653 up->capabilities |= UART_CAP_FIFO;
654
655 /*
656 * Check for presence of the EFR when DLAB is set.
657 * Only ST16C650V1 UARTs pass this test.
658 */
659 serial_outp(up, UART_LCR, UART_LCR_DLAB);
660 if (serial_in(up, UART_EFR) == 0) {
661 serial_outp(up, UART_EFR, 0xA8);
662 if (serial_in(up, UART_EFR) != 0) {
663 DEBUG_AUTOCONF("EFRv1 ");
664 up->port.type = PORT_16650;
665 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
666 } else {
667 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
668 }
669 serial_outp(up, UART_EFR, 0);
670 return;
671 }
672
673 /*
674 * Maybe it requires 0xbf to be written to the LCR.
675 * (other ST16C650V2 UARTs, TI16C752A, etc)
676 */
677 serial_outp(up, UART_LCR, 0xBF);
678 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
679 DEBUG_AUTOCONF("EFRv2 ");
680 autoconfig_has_efr(up);
681 return;
682 }
683
684 /*
685 * Check for a National Semiconductor SuperIO chip.
686 * Attempt to switch to bank 2, read the value of the LOOP bit
687 * from EXCR1. Switch back to bank 0, change it in MCR. Then
688 * switch back to bank 2, read it from EXCR1 again and check
689 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 690 */
691 serial_outp(up, UART_LCR, 0);
692 status1 = serial_in(up, UART_MCR);
693 serial_outp(up, UART_LCR, 0xE0);
694 status2 = serial_in(up, 0x02); /* EXCR1 */
695
696 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
697 serial_outp(up, UART_LCR, 0);
698 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
699 serial_outp(up, UART_LCR, 0xE0);
700 status2 = serial_in(up, 0x02); /* EXCR1 */
701 serial_outp(up, UART_LCR, 0);
702 serial_outp(up, UART_MCR, status1);
703
704 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 705 unsigned short quot;
706
1da177e4 707 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 708
709 quot = serial_inp(up, UART_DLM) << 8;
710 quot += serial_inp(up, UART_DLL);
711 quot <<= 3;
712
1da177e4
LT		 713 status1 = serial_in(up, 0x04); /* EXCR1 */
714 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
715 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
716 serial_outp(up, 0x04, status1);
857dde2e
DW		 717
718 serial_outp(up, UART_DLL, quot & 0xff);
719 serial_outp(up, UART_DLM, quot >> 8);
720
1da177e4 721 serial_outp(up, UART_LCR, 0);
1da177e4 722
857dde2e 723 up->port.uartclk = 921600*16;
1da177e4
LT		 724 up->port.type = PORT_NS16550A;
725 up->capabilities |= UART_NATSEMI;
726 return;
727 }
728 }
729
730 /*
731 * No EFR. Try to detect a TI16750, which only sets bit 5 of
732 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
733 * Try setting it with and without DLAB set. Cheap clones
734 * set bit 5 without DLAB set.
735 */
736 serial_outp(up, UART_LCR, 0);
737 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
738 status1 = serial_in(up, UART_IIR) >> 5;
739 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
740 serial_outp(up, UART_LCR, UART_LCR_DLAB);
741 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
742 status2 = serial_in(up, UART_IIR) >> 5;
743 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
744 serial_outp(up, UART_LCR, 0);
745
746 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
747
748 if (status1 == 6 && status2 == 7) {
749 up->port.type = PORT_16750;
750 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
751 return;
752 }
753
754 /*
755 * Try writing and reading the UART_IER_UUE bit (b6).
756 * If it works, this is probably one of the Xscale platform's
757 * internal UARTs.
758 * We're going to explicitly set the UUE bit to 0 before
759 * trying to write and read a 1 just to make sure it's not
760 * already a 1 and maybe locked there before we even start start.
761 */
762 iersave = serial_in(up, UART_IER);
763 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
764 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
765 /*
766 * OK it's in a known zero state, try writing and reading
767 * without disturbing the current state of the other bits.
768 */
769 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
770 if (serial_in(up, UART_IER) & UART_IER_UUE) {
771 /*
772 * It's an Xscale.
773 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
774 */
775 DEBUG_AUTOCONF("Xscale ");
776 up->port.type = PORT_XSCALE;
777 up->capabilities |= UART_CAP_UUE;
778 return;
779 }
780 } else {
781 /*
782 * If we got here we couldn't force the IER_UUE bit to 0.
783 * Log it and continue.
784 */
785 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
786 }
787 serial_outp(up, UART_IER, iersave);
788}
789
790/*
791 * This routine is called by rs_init() to initialize a specific serial
792 * port. It determines what type of UART chip this serial port is
793 * using: 8250, 16450, 16550, 16550A. The important question is
794 * whether or not this UART is a 16550A or not, since this will
795 * determine whether or not we can use its FIFO features or not.
796 */
797static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
798{
799 unsigned char status1, scratch, scratch2, scratch3;
800 unsigned char save_lcr, save_mcr;
801 unsigned long flags;
802
803 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
804 return;
805
806 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
807 up->port.line, up->port.iobase, up->port.membase);
808
809 /*
810 * We really do need global IRQs disabled here - we're going to
811 * be frobbing the chips IRQ enable register to see if it exists.
812 */
813 spin_lock_irqsave(&up->port.lock, flags);
814// save_flags(flags); cli();
815
816 up->capabilities = 0;
4ba5e35d 817 up->bugs = 0;
1da177e4
LT		 818
819 if (!(up->port.flags & UPF_BUGGY_UART)) {
820 /*
821 * Do a simple existence test first; if we fail this,
822 * there's no point trying anything else.
823 *
824 * 0x80 is used as a nonsense port to prevent against
825 * false positives due to ISA bus float. The
826 * assumption is that 0x80 is a non-existent port;
827 * which should be safe since include/asm/io.h also
828 * makes this assumption.
829 *
830 * Note: this is safe as long as MCR bit 4 is clear
831 * and the device is in "PC" mode.
832 */
833 scratch = serial_inp(up, UART_IER);
834 serial_outp(up, UART_IER, 0);
835#ifdef __i386__
836 outb(0xff, 0x080);
837#endif
838 scratch2 = serial_inp(up, UART_IER);
839 serial_outp(up, UART_IER, 0x0F);
840#ifdef __i386__
841 outb(0, 0x080);
842#endif
843 scratch3 = serial_inp(up, UART_IER);
844 serial_outp(up, UART_IER, scratch);
845 if (scratch2 != 0 || scratch3 != 0x0F) {
846 /*
847 * We failed; there's nothing here
848 */
849 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
850 scratch2, scratch3);
851 goto out;
852 }
853 }
854
855 save_mcr = serial_in(up, UART_MCR);
856 save_lcr = serial_in(up, UART_LCR);
857
858 /*
859 * Check to see if a UART is really there. Certain broken
860 * internal modems based on the Rockwell chipset fail this
861 * test, because they apparently don't implement the loopback
862 * test mode. So this test is skipped on the COM 1 through
863 * COM 4 ports. This *should* be safe, since no board
864 * manufacturer would be stupid enough to design a board
865 * that conflicts with COM 1-4 --- we hope!
866 */
867 if (!(up->port.flags & UPF_SKIP_TEST)) {
868 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
869 status1 = serial_inp(up, UART_MSR) & 0xF0;
870 serial_outp(up, UART_MCR, save_mcr);
871 if (status1 != 0x90) {
872 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
873 status1);
874 goto out;
875 }
876 }
877
878 /*
879 * We're pretty sure there's a port here. Lets find out what
880 * type of port it is. The IIR top two bits allows us to find
881 * out if its 8250 or 16450, 16550, 16550A or later. This
882 * determines what we test for next.
883 *
884 * We also initialise the EFR (if any) to zero for later. The
885 * EFR occupies the same register location as the FCR and IIR.
886 */
887 serial_outp(up, UART_LCR, 0xBF);
888 serial_outp(up, UART_EFR, 0);
889 serial_outp(up, UART_LCR, 0);
890
891 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
892 scratch = serial_in(up, UART_IIR) >> 6;
893
894 DEBUG_AUTOCONF("iir=%d ", scratch);
895
896 switch (scratch) {
897 case 0:
898 autoconfig_8250(up);
899 break;
900 case 1:
901 up->port.type = PORT_UNKNOWN;
902 break;
903 case 2:
904 up->port.type = PORT_16550;
905 break;
906 case 3:
907 autoconfig_16550a(up);
908 break;
909 }
910
911#ifdef CONFIG_SERIAL_8250_RSA
912 /*
913 * Only probe for RSA ports if we got the region.
914 */
915 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
916 int i;
917
918 for (i = 0 ; i < probe_rsa_count; ++i) {
919 if (probe_rsa[i] == up->port.iobase &&
920 __enable_rsa(up)) {
921 up->port.type = PORT_RSA;
922 break;
923 }
924 }
925 }
926#endif
927 serial_outp(up, UART_LCR, save_lcr);
928
929 if (up->capabilities != uart_config[up->port.type].flags) {
930 printk(KERN_WARNING
931 "ttyS%d: detected caps %08x should be %08x\n",
932 up->port.line, up->capabilities,
933 uart_config[up->port.type].flags);
934 }
935
936 up->port.fifosize = uart_config[up->port.type].fifo_size;
937 up->capabilities = uart_config[up->port.type].flags;
938 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
939
940 if (up->port.type == PORT_UNKNOWN)
941 goto out;
942
943 /*
944 * Reset the UART.
945 */
946#ifdef CONFIG_SERIAL_8250_RSA
947 if (up->port.type == PORT_RSA)
948 serial_outp(up, UART_RSA_FRR, 0);
949#endif
950 serial_outp(up, UART_MCR, save_mcr);
951 serial8250_clear_fifos(up);
952 (void)serial_in(up, UART_RX);
953 serial_outp(up, UART_IER, 0);
954
955 out:
956 spin_unlock_irqrestore(&up->port.lock, flags);
957// restore_flags(flags);
958 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
959}
960
961static void autoconfig_irq(struct uart_8250_port *up)
962{
963 unsigned char save_mcr, save_ier;
964 unsigned char save_ICP = 0;
965 unsigned int ICP = 0;
966 unsigned long irqs;
967 int irq;
968
969 if (up->port.flags & UPF_FOURPORT) {
970 ICP = (up->port.iobase & 0xfe0) | 0x1f;
971 save_ICP = inb_p(ICP);
972 outb_p(0x80, ICP);
973 (void) inb_p(ICP);
974 }
975
976 /* forget possible initially masked and pending IRQ */
977 probe_irq_off(probe_irq_on());
978 save_mcr = serial_inp(up, UART_MCR);
979 save_ier = serial_inp(up, UART_IER);
980 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
981
982 irqs = probe_irq_on();
983 serial_outp(up, UART_MCR, 0);
984 udelay (10);
985 if (up->port.flags & UPF_FOURPORT) {
986 serial_outp(up, UART_MCR,
987 UART_MCR_DTR | UART_MCR_RTS);
988 } else {
989 serial_outp(up, UART_MCR,
990 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
991 }
992 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
993 (void)serial_inp(up, UART_LSR);
994 (void)serial_inp(up, UART_RX);
995 (void)serial_inp(up, UART_IIR);
996 (void)serial_inp(up, UART_MSR);
997 serial_outp(up, UART_TX, 0xFF);
998 udelay (20);
999 irq = probe_irq_off(irqs);
1000
1001 serial_outp(up, UART_MCR, save_mcr);
1002 serial_outp(up, UART_IER, save_ier);
1003
1004 if (up->port.flags & UPF_FOURPORT)
1005 outb_p(save_ICP, ICP);
1006
1007 up->port.irq = (irq > 0) ? irq : 0;
1008}
1009
1010static void serial8250_stop_tx(struct uart_port *port, unsigned int tty_stop)
1011{
1012 struct uart_8250_port *up = (struct uart_8250_port *)port;
1013
1014 if (up->ier & UART_IER_THRI) {
1015 up->ier &= ~UART_IER_THRI;
1016 serial_out(up, UART_IER, up->ier);
1017 }
1018
1019 /*
1020 * We only do this from uart_stop - if we run out of
1021 * characters to send, we don't want to prevent the
1022 * FIFO from emptying.
1023 */
1024 if (up->port.type == PORT_16C950 && tty_stop) {
1025 up->acr |= UART_ACR_TXDIS;
1026 serial_icr_write(up, UART_ACR, up->acr);
1027 }
1028}
1029
55d3b282
RK		 1030static void transmit_chars(struct uart_8250_port *up);
1031
1da177e4
LT		 1032static void serial8250_start_tx(struct uart_port *port, unsigned int tty_start)
1033{
1034 struct uart_8250_port *up = (struct uart_8250_port *)port;
1035
1036 if (!(up->ier & UART_IER_THRI)) {
1037 up->ier |= UART_IER_THRI;
1038 serial_out(up, UART_IER, up->ier);
55d3b282
RK		 1039
1040 if (up->capabilities & UART_BUG_TXEN) {
1041 unsigned char lsr, iir;
1042 lsr = serial_in(up, UART_LSR);
1043 iir = serial_in(up, UART_IIR);
1044 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1045 transmit_chars(up);
1046 }
1da177e4
LT		 1047 }
1048 /*
1049 * We only do this from uart_start
1050 */
1051 if (tty_start && up->port.type == PORT_16C950) {
1052 up->acr &= ~UART_ACR_TXDIS;
1053 serial_icr_write(up, UART_ACR, up->acr);
1054 }
1055}
1056
1057static void serial8250_stop_rx(struct uart_port *port)
1058{
1059 struct uart_8250_port *up = (struct uart_8250_port *)port;
1060
1061 up->ier &= ~UART_IER_RLSI;
1062 up->port.read_status_mask &= ~UART_LSR_DR;
1063 serial_out(up, UART_IER, up->ier);
1064}
1065
1066static void serial8250_enable_ms(struct uart_port *port)
1067{
1068 struct uart_8250_port *up = (struct uart_8250_port *)port;
1069
1070 up->ier |= UART_IER_MSI;
1071 serial_out(up, UART_IER, up->ier);
1072}
1073
1074static _INLINE_ void
1075receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1076{
1077 struct tty_struct *tty = up->port.info->tty;
1078 unsigned char ch, lsr = *status;
1079 int max_count = 256;
1080 char flag;
1081
1082 do {
1083 /* The following is not allowed by the tty layer and
1084 unsafe. It should be fixed ASAP */
1085 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1086 if (tty->low_latency) {
1087 spin_unlock(&up->port.lock);
1088 tty_flip_buffer_push(tty);
1089 spin_lock(&up->port.lock);
1090 }
23907eb8
RK		 1091 /*
1092 * If this failed then we will throw away the
1093 * bytes but must do so to clear interrupts
1094 */
1da177e4
LT		 1095 }
1096 ch = serial_inp(up, UART_RX);
1097 flag = TTY_NORMAL;
1098 up->port.icount.rx++;
1099
1100#ifdef CONFIG_SERIAL_8250_CONSOLE
1101 /*
1102 * Recover the break flag from console xmit
1103 */
1104 if (up->port.line == up->port.cons->index) {
1105 lsr |= up->lsr_break_flag;
1106 up->lsr_break_flag = 0;
1107 }
1108#endif
1109
1110 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1111 UART_LSR_FE | UART_LSR_OE))) {
1112 /*
1113 * For statistics only
1114 */
1115 if (lsr & UART_LSR_BI) {
1116 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1117 up->port.icount.brk++;
1118 /*
1119 * We do the SysRQ and SAK checking
1120 * here because otherwise the break
1121 * may get masked by ignore_status_mask
1122 * or read_status_mask.
1123 */
1124 if (uart_handle_break(&up->port))
1125 goto ignore_char;
1126 } else if (lsr & UART_LSR_PE)
1127 up->port.icount.parity++;
1128 else if (lsr & UART_LSR_FE)
1129 up->port.icount.frame++;
1130 if (lsr & UART_LSR_OE)
1131 up->port.icount.overrun++;
1132
1133 /*
23907eb8 1134 * Mask off conditions which should be ignored.
1da177e4
LT		 1135 */
1136 lsr &= up->port.read_status_mask;
1137
1138 if (lsr & UART_LSR_BI) {
1139 DEBUG_INTR("handling break....");
1140 flag = TTY_BREAK;
1141 } else if (lsr & UART_LSR_PE)
1142 flag = TTY_PARITY;
1143 else if (lsr & UART_LSR_FE)
1144 flag = TTY_FRAME;
1145 }
1146 if (uart_handle_sysrq_char(&up->port, ch, regs))
1147 goto ignore_char;
05ab3014
RK		 1148
1149 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1150
1da177e4
LT		 1151 ignore_char:
1152 lsr = serial_inp(up, UART_LSR);
1153 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1154 spin_unlock(&up->port.lock);
1155 tty_flip_buffer_push(tty);
1156 spin_lock(&up->port.lock);
1157 *status = lsr;
1158}
1159
1160static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1161{
1162 struct circ_buf *xmit = &up->port.info->xmit;
1163 int count;
1164
1165 if (up->port.x_char) {
1166 serial_outp(up, UART_TX, up->port.x_char);
1167 up->port.icount.tx++;
1168 up->port.x_char = 0;
1169 return;
1170 }
1171 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
1172 serial8250_stop_tx(&up->port, 0);
1173 return;
1174 }
1175
1176 count = up->tx_loadsz;
1177 do {
1178 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1179 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1180 up->port.icount.tx++;
1181 if (uart_circ_empty(xmit))
1182 break;
1183 } while (--count > 0);
1184
1185 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1186 uart_write_wakeup(&up->port);
1187
1188 DEBUG_INTR("THRE...");
1189
1190 if (uart_circ_empty(xmit))
1191 serial8250_stop_tx(&up->port, 0);
1192}
1193
1194static _INLINE_ void check_modem_status(struct uart_8250_port *up)
1195{
1196 int status;
1197
1198 status = serial_in(up, UART_MSR);
1199
1200 if ((status & UART_MSR_ANY_DELTA) == 0)
1201 return;
1202
1203 if (status & UART_MSR_TERI)
1204 up->port.icount.rng++;
1205 if (status & UART_MSR_DDSR)
1206 up->port.icount.dsr++;
1207 if (status & UART_MSR_DDCD)
1208 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1209 if (status & UART_MSR_DCTS)
1210 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1211
1212 wake_up_interruptible(&up->port.info->delta_msr_wait);
1213}
1214
1215/*
1216 * This handles the interrupt from one port.
1217 */
1218static inline void
1219serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1220{
1221 unsigned int status = serial_inp(up, UART_LSR);
1222
1223 DEBUG_INTR("status = %x...", status);
1224
1225 if (status & UART_LSR_DR)
1226 receive_chars(up, &status, regs);
1227 check_modem_status(up);
1228 if (status & UART_LSR_THRE)
1229 transmit_chars(up);
1230}
1231
1232/*
1233 * This is the serial driver's interrupt routine.
1234 *
1235 * Arjan thinks the old way was overly complex, so it got simplified.
1236 * Alan disagrees, saying that need the complexity to handle the weird
1237 * nature of ISA shared interrupts. (This is a special exception.)
1238 *
1239 * In order to handle ISA shared interrupts properly, we need to check
1240 * that all ports have been serviced, and therefore the ISA interrupt
1241 * line has been de-asserted.
1242 *
1243 * This means we need to loop through all ports. checking that they
1244 * don't have an interrupt pending.
1245 */
1246static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1247{
1248 struct irq_info *i = dev_id;
1249 struct list_head *l, *end = NULL;
1250 int pass_counter = 0, handled = 0;
1251
1252 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1253
1254 spin_lock(&i->lock);
1255
1256 l = i->head;
1257 do {
1258 struct uart_8250_port *up;
1259 unsigned int iir;
1260
1261 up = list_entry(l, struct uart_8250_port, list);
1262
1263 iir = serial_in(up, UART_IIR);
1264 if (!(iir & UART_IIR_NO_INT)) {
1265 spin_lock(&up->port.lock);
1266 serial8250_handle_port(up, regs);
1267 spin_unlock(&up->port.lock);
1268
1269 handled = 1;
1270
1271 end = NULL;
1272 } else if (end == NULL)
1273 end = l;
1274
1275 l = l->next;
1276
1277 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1278 /* If we hit this, we're dead. */
1279 printk(KERN_ERR "serial8250: too much work for "
1280 "irq%d\n", irq);
1281 break;
1282 }
1283 } while (l != end);
1284
1285 spin_unlock(&i->lock);
1286
1287 DEBUG_INTR("end.\n");
1288
1289 return IRQ_RETVAL(handled);
1290}
1291
1292/*
1293 * To support ISA shared interrupts, we need to have one interrupt
1294 * handler that ensures that the IRQ line has been deasserted
1295 * before returning. Failing to do this will result in the IRQ
1296 * line being stuck active, and, since ISA irqs are edge triggered,
1297 * no more IRQs will be seen.
1298 */
1299static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1300{
1301 spin_lock_irq(&i->lock);
1302
1303 if (!list_empty(i->head)) {
1304 if (i->head == &up->list)
1305 i->head = i->head->next;
1306 list_del(&up->list);
1307 } else {
1308 BUG_ON(i->head != &up->list);
1309 i->head = NULL;
1310 }
1311
1312 spin_unlock_irq(&i->lock);
1313}
1314
1315static int serial_link_irq_chain(struct uart_8250_port *up)
1316{
1317 struct irq_info *i = irq_lists + up->port.irq;
1318 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1319
1320 spin_lock_irq(&i->lock);
1321
1322 if (i->head) {
1323 list_add(&up->list, i->head);
1324 spin_unlock_irq(&i->lock);
1325
1326 ret = 0;
1327 } else {
1328 INIT_LIST_HEAD(&up->list);
1329 i->head = &up->list;
1330 spin_unlock_irq(&i->lock);
1331
1332 ret = request_irq(up->port.irq, serial8250_interrupt,
1333 irq_flags, "serial", i);
1334 if (ret < 0)
1335 serial_do_unlink(i, up);
1336 }
1337
1338 return ret;
1339}
1340
1341static void serial_unlink_irq_chain(struct uart_8250_port *up)
1342{
1343 struct irq_info *i = irq_lists + up->port.irq;
1344
1345 BUG_ON(i->head == NULL);
1346
1347 if (list_empty(i->head))
1348 free_irq(up->port.irq, i);
1349
1350 serial_do_unlink(i, up);
1351}
1352
1353/*
1354 * This function is used to handle ports that do not have an
1355 * interrupt. This doesn't work very well for 16450's, but gives
1356 * barely passable results for a 16550A. (Although at the expense
1357 * of much CPU overhead).
1358 */
1359static void serial8250_timeout(unsigned long data)
1360{
1361 struct uart_8250_port *up = (struct uart_8250_port *)data;
1362 unsigned int timeout;
1363 unsigned int iir;
1364
1365 iir = serial_in(up, UART_IIR);
1366 if (!(iir & UART_IIR_NO_INT)) {
1367 spin_lock(&up->port.lock);
1368 serial8250_handle_port(up, NULL);
1369 spin_unlock(&up->port.lock);
1370 }
1371
1372 timeout = up->port.timeout;
1373 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1374 mod_timer(&up->timer, jiffies + timeout);
1375}
1376
1377static unsigned int serial8250_tx_empty(struct uart_port *port)
1378{
1379 struct uart_8250_port *up = (struct uart_8250_port *)port;
1380 unsigned long flags;
1381 unsigned int ret;
1382
1383 spin_lock_irqsave(&up->port.lock, flags);
1384 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1385 spin_unlock_irqrestore(&up->port.lock, flags);
1386
1387 return ret;
1388}
1389
1390static unsigned int serial8250_get_mctrl(struct uart_port *port)
1391{
1392 struct uart_8250_port *up = (struct uart_8250_port *)port;
1393 unsigned long flags;
1394 unsigned char status;
1395 unsigned int ret;
1396
1397 spin_lock_irqsave(&up->port.lock, flags);
1398 status = serial_in(up, UART_MSR);
1399 spin_unlock_irqrestore(&up->port.lock, flags);
1400
1401 ret = 0;
1402 if (status & UART_MSR_DCD)
1403 ret |= TIOCM_CAR;
1404 if (status & UART_MSR_RI)
1405 ret |= TIOCM_RNG;
1406 if (status & UART_MSR_DSR)
1407 ret |= TIOCM_DSR;
1408 if (status & UART_MSR_CTS)
1409 ret |= TIOCM_CTS;
1410 return ret;
1411}
1412
1413static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1414{
1415 struct uart_8250_port *up = (struct uart_8250_port *)port;
1416 unsigned char mcr = 0;
1417
1418 if (mctrl & TIOCM_RTS)
1419 mcr |= UART_MCR_RTS;
1420 if (mctrl & TIOCM_DTR)
1421 mcr |= UART_MCR_DTR;
1422 if (mctrl & TIOCM_OUT1)
1423 mcr |= UART_MCR_OUT1;
1424 if (mctrl & TIOCM_OUT2)
1425 mcr |= UART_MCR_OUT2;
1426 if (mctrl & TIOCM_LOOP)
1427 mcr |= UART_MCR_LOOP;
1428
1429 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1430
1431 serial_out(up, UART_MCR, mcr);
1432}
1433
1434static void serial8250_break_ctl(struct uart_port *port, int break_state)
1435{
1436 struct uart_8250_port *up = (struct uart_8250_port *)port;
1437 unsigned long flags;
1438
1439 spin_lock_irqsave(&up->port.lock, flags);
1440 if (break_state == -1)
1441 up->lcr |= UART_LCR_SBC;
1442 else
1443 up->lcr &= ~UART_LCR_SBC;
1444 serial_out(up, UART_LCR, up->lcr);
1445 spin_unlock_irqrestore(&up->port.lock, flags);
1446}
1447
1448static int serial8250_startup(struct uart_port *port)
1449{
1450 struct uart_8250_port *up = (struct uart_8250_port *)port;
1451 unsigned long flags;
55d3b282 1452 unsigned char lsr, iir;
1da177e4
LT		 1453 int retval;
1454
1455 up->capabilities = uart_config[up->port.type].flags;
1456 up->mcr = 0;
1457
1458 if (up->port.type == PORT_16C950) {
1459 /* Wake up and initialize UART */
1460 up->acr = 0;
1461 serial_outp(up, UART_LCR, 0xBF);
1462 serial_outp(up, UART_EFR, UART_EFR_ECB);
1463 serial_outp(up, UART_IER, 0);
1464 serial_outp(up, UART_LCR, 0);
1465 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1466 serial_outp(up, UART_LCR, 0xBF);
1467 serial_outp(up, UART_EFR, UART_EFR_ECB);
1468 serial_outp(up, UART_LCR, 0);
1469 }
1470
1471#ifdef CONFIG_SERIAL_8250_RSA
1472 /*
1473 * If this is an RSA port, see if we can kick it up to the
1474 * higher speed clock.
1475 */
1476 enable_rsa(up);
1477#endif
1478
1479 /*
1480 * Clear the FIFO buffers and disable them.
1481 * (they will be reeanbled in set_termios())
1482 */
1483 serial8250_clear_fifos(up);
1484
1485 /*
1486 * Clear the interrupt registers.
1487 */
1488 (void) serial_inp(up, UART_LSR);
1489 (void) serial_inp(up, UART_RX);
1490 (void) serial_inp(up, UART_IIR);
1491 (void) serial_inp(up, UART_MSR);
1492
1493 /*
1494 * At this point, there's no way the LSR could still be 0xff;
1495 * if it is, then bail out, because there's likely no UART
1496 * here.
1497 */
1498 if (!(up->port.flags & UPF_BUGGY_UART) &&
1499 (serial_inp(up, UART_LSR) == 0xff)) {
1500 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1501 return -ENODEV;
1502 }
1503
1504 /*
1505 * For a XR16C850, we need to set the trigger levels
1506 */
1507 if (up->port.type == PORT_16850) {
1508 unsigned char fctr;
1509
1510 serial_outp(up, UART_LCR, 0xbf);
1511
1512 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1513 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1514 serial_outp(up, UART_TRG, UART_TRG_96);
1515 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1516 serial_outp(up, UART_TRG, UART_TRG_96);
1517
1518 serial_outp(up, UART_LCR, 0);
1519 }
1520
1521 /*
1522 * If the "interrupt" for this port doesn't correspond with any
1523 * hardware interrupt, we use a timer-based system. The original
1524 * driver used to do this with IRQ0.
1525 */
1526 if (!is_real_interrupt(up->port.irq)) {
1527 unsigned int timeout = up->port.timeout;
1528
1529 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1530
1531 up->timer.data = (unsigned long)up;
1532 mod_timer(&up->timer, jiffies + timeout);
1533 } else {
1534 retval = serial_link_irq_chain(up);
1535 if (retval)
1536 return retval;
1537 }
1538
1539 /*
1540 * Now, initialize the UART
1541 */
1542 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1543
1544 spin_lock_irqsave(&up->port.lock, flags);
1545 if (up->port.flags & UPF_FOURPORT) {
1546 if (!is_real_interrupt(up->port.irq))
1547 up->port.mctrl |= TIOCM_OUT1;
1548 } else
1549 /*
1550 * Most PC uarts need OUT2 raised to enable interrupts.
1551 */
1552 if (is_real_interrupt(up->port.irq))
1553 up->port.mctrl |= TIOCM_OUT2;
1554
1555 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1556
1557 /*
1558 * Do a quick test to see if we receive an
1559 * interrupt when we enable the TX irq.
1560 */
1561 serial_outp(up, UART_IER, UART_IER_THRI);
1562 lsr = serial_in(up, UART_LSR);
1563 iir = serial_in(up, UART_IIR);
1564 serial_outp(up, UART_IER, 0);
1565
1566 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1567 if (!(up->capabilities & UART_BUG_TXEN)) {
1568 up->capabilities |= UART_BUG_TXEN;
1569 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1570 port->line);
1571 }
1572 } else {
1573 up->capabilities &= ~UART_BUG_TXEN;
1574 }
1575
1da177e4
LT		 1576 spin_unlock_irqrestore(&up->port.lock, flags);
1577
1578 /*
1579 * Finally, enable interrupts. Note: Modem status interrupts
1580 * are set via set_termios(), which will be occurring imminently
1581 * anyway, so we don't enable them here.
1582 */
1583 up->ier = UART_IER_RLSI | UART_IER_RDI;
1584 serial_outp(up, UART_IER, up->ier);
1585
1586 if (up->port.flags & UPF_FOURPORT) {
1587 unsigned int icp;
1588 /*
1589 * Enable interrupts on the AST Fourport board
1590 */
1591 icp = (up->port.iobase & 0xfe0) | 0x01f;
1592 outb_p(0x80, icp);
1593 (void) inb_p(icp);
1594 }
1595
1596 /*
1597 * And clear the interrupt registers again for luck.
1598 */
1599 (void) serial_inp(up, UART_LSR);
1600 (void) serial_inp(up, UART_RX);
1601 (void) serial_inp(up, UART_IIR);
1602 (void) serial_inp(up, UART_MSR);
1603
1604 return 0;
1605}
1606
1607static void serial8250_shutdown(struct uart_port *port)
1608{
1609 struct uart_8250_port *up = (struct uart_8250_port *)port;
1610 unsigned long flags;
1611
1612 /*
1613 * Disable interrupts from this port
1614 */
1615 up->ier = 0;
1616 serial_outp(up, UART_IER, 0);
1617
1618 spin_lock_irqsave(&up->port.lock, flags);
1619 if (up->port.flags & UPF_FOURPORT) {
1620 /* reset interrupts on the AST Fourport board */
1621 inb((up->port.iobase & 0xfe0) | 0x1f);
1622 up->port.mctrl |= TIOCM_OUT1;
1623 } else
1624 up->port.mctrl &= ~TIOCM_OUT2;
1625
1626 serial8250_set_mctrl(&up->port, up->port.mctrl);
1627 spin_unlock_irqrestore(&up->port.lock, flags);
1628
1629 /*
1630 * Disable break condition and FIFOs
1631 */
1632 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1633 serial8250_clear_fifos(up);
1634
1635#ifdef CONFIG_SERIAL_8250_RSA
1636 /*
1637 * Reset the RSA board back to 115kbps compat mode.
1638 */
1639 disable_rsa(up);
1640#endif
1641
1642 /*
1643 * Read data port to reset things, and then unlink from
1644 * the IRQ chain.
1645 */
1646 (void) serial_in(up, UART_RX);
1647
1648 if (!is_real_interrupt(up->port.irq))
1649 del_timer_sync(&up->timer);
1650 else
1651 serial_unlink_irq_chain(up);
1652}
1653
1654static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1655{
1656 unsigned int quot;
1657
1658 /*
1659 * Handle magic divisors for baud rates above baud_base on
1660 * SMSC SuperIO chips.
1661 */
1662 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1663 baud == (port->uartclk/4))
1664 quot = 0x8001;
1665 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1666 baud == (port->uartclk/8))
1667 quot = 0x8002;
1668 else
1669 quot = uart_get_divisor(port, baud);
1670
1671 return quot;
1672}
1673
1674static void
1675serial8250_set_termios(struct uart_port *port, struct termios *termios,
1676 struct termios *old)
1677{
1678 struct uart_8250_port *up = (struct uart_8250_port *)port;
1679 unsigned char cval, fcr = 0;
1680 unsigned long flags;
1681 unsigned int baud, quot;
1682
1683 switch (termios->c_cflag & CSIZE) {
1684 case CS5:
1685 cval = 0x00;
1686 break;
1687 case CS6:
1688 cval = 0x01;
1689 break;
1690 case CS7:
1691 cval = 0x02;
1692 break;
1693 default:
1694 case CS8:
1695 cval = 0x03;
1696 break;
1697 }
1698
1699 if (termios->c_cflag & CSTOPB)
1700 cval |= 0x04;
1701 if (termios->c_cflag & PARENB)
1702 cval |= UART_LCR_PARITY;
1703 if (!(termios->c_cflag & PARODD))
1704 cval |= UART_LCR_EPAR;
1705#ifdef CMSPAR
1706 if (termios->c_cflag & CMSPAR)
1707 cval |= UART_LCR_SPAR;
1708#endif
1709
1710 /*
1711 * Ask the core to calculate the divisor for us.
1712 */
1713 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1714 quot = serial8250_get_divisor(port, baud);
1715
1716 /*
4ba5e35d 1717 * Oxford Semi 952 rev B workaround
1da177e4 1718 */
4ba5e35d 1719 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1720 quot ++;
1721
1722 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1723 if (baud < 2400)
1724 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1725 else
1726 fcr = uart_config[up->port.type].fcr;
1727 }
1728
1729 /*
1730 * MCR-based auto flow control. When AFE is enabled, RTS will be
1731 * deasserted when the receive FIFO contains more characters than
1732 * the trigger, or the MCR RTS bit is cleared. In the case where
1733 * the remote UART is not using CTS auto flow control, we must
1734 * have sufficient FIFO entries for the latency of the remote
1735 * UART to respond. IOW, at least 32 bytes of FIFO.
1736 */
1737 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1738 up->mcr &= ~UART_MCR_AFE;
1739 if (termios->c_cflag & CRTSCTS)
1740 up->mcr |= UART_MCR_AFE;
1741 }
1742
1743 /*
1744 * Ok, we're now changing the port state. Do it with
1745 * interrupts disabled.
1746 */
1747 spin_lock_irqsave(&up->port.lock, flags);
1748
1749 /*
1750 * Update the per-port timeout.
1751 */
1752 uart_update_timeout(port, termios->c_cflag, baud);
1753
1754 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1755 if (termios->c_iflag & INPCK)
1756 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1757 if (termios->c_iflag & (BRKINT | PARMRK))
1758 up->port.read_status_mask |= UART_LSR_BI;
1759
1760 /*
1761 * Characteres to ignore
1762 */
1763 up->port.ignore_status_mask = 0;
1764 if (termios->c_iflag & IGNPAR)
1765 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1766 if (termios->c_iflag & IGNBRK) {
1767 up->port.ignore_status_mask |= UART_LSR_BI;
1768 /*
1769 * If we're ignoring parity and break indicators,
1770 * ignore overruns too (for real raw support).
1771 */
1772 if (termios->c_iflag & IGNPAR)
1773 up->port.ignore_status_mask |= UART_LSR_OE;
1774 }
1775
1776 /*
1777 * ignore all characters if CREAD is not set
1778 */
1779 if ((termios->c_cflag & CREAD) == 0)
1780 up->port.ignore_status_mask |= UART_LSR_DR;
1781
1782 /*
1783 * CTS flow control flag and modem status interrupts
1784 */
1785 up->ier &= ~UART_IER_MSI;
1786 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
1787 up->ier |= UART_IER_MSI;
1788 if (up->capabilities & UART_CAP_UUE)
1789 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1790
1791 serial_out(up, UART_IER, up->ier);
1792
1793 if (up->capabilities & UART_CAP_EFR) {
1794 unsigned char efr = 0;
1795 /*
1796 * TI16C752/Startech hardware flow control. FIXME:
1797 * - TI16C752 requires control thresholds to be set.
1798 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1799 */
1800 if (termios->c_cflag & CRTSCTS)
1801 efr |= UART_EFR_CTS;
1802
1803 serial_outp(up, UART_LCR, 0xBF);
1804 serial_outp(up, UART_EFR, efr);
1805 }
1806
1807 if (up->capabilities & UART_NATSEMI) {
1808 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1809 serial_outp(up, UART_LCR, 0xe0);
1810 } else {
1811 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1812 }
1813
1814 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1815 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1816
1817 /*
1818 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1819 * is written without DLAB set, this mode will be disabled.
1820 */
1821 if (up->port.type == PORT_16750)
1822 serial_outp(up, UART_FCR, fcr);
1823
1824 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1825 up->lcr = cval; /* Save LCR */
1826 if (up->port.type != PORT_16750) {
1827 if (fcr & UART_FCR_ENABLE_FIFO) {
1828 /* emulated UARTs (Lucent Venus 167x) need two steps */
1829 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1830 }
1831 serial_outp(up, UART_FCR, fcr); /* set fcr */
1832 }
1833 serial8250_set_mctrl(&up->port, up->port.mctrl);
1834 spin_unlock_irqrestore(&up->port.lock, flags);
1835}
1836
1837static void
1838serial8250_pm(struct uart_port *port, unsigned int state,
1839 unsigned int oldstate)
1840{
1841 struct uart_8250_port *p = (struct uart_8250_port *)port;
1842
1843 serial8250_set_sleep(p, state != 0);
1844
1845 if (p->pm)
1846 p->pm(port, state, oldstate);
1847}
1848
1849/*
1850 * Resource handling.
1851 */
1852static int serial8250_request_std_resource(struct uart_8250_port *up)
1853{
1854 unsigned int size = 8 << up->port.regshift;
1855 int ret = 0;
1856
1857 switch (up->port.iotype) {
1858 case UPIO_MEM:
1859 if (!up->port.mapbase)
1860 break;
1861
1862 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1863 ret = -EBUSY;
1864 break;
1865 }
1866
1867 if (up->port.flags & UPF_IOREMAP) {
1868 up->port.membase = ioremap(up->port.mapbase, size);
1869 if (!up->port.membase) {
1870 release_mem_region(up->port.mapbase, size);
1871 ret = -ENOMEM;
1872 }
1873 }
1874 break;
1875
1876 case UPIO_HUB6:
1877 case UPIO_PORT:
1878 if (!request_region(up->port.iobase, size, "serial"))
1879 ret = -EBUSY;
1880 break;
1881 }
1882 return ret;
1883}
1884
1885static void serial8250_release_std_resource(struct uart_8250_port *up)
1886{
1887 unsigned int size = 8 << up->port.regshift;
1888
1889 switch (up->port.iotype) {
1890 case UPIO_MEM:
1891 if (!up->port.mapbase)
1892 break;
1893
1894 if (up->port.flags & UPF_IOREMAP) {
1895 iounmap(up->port.membase);
1896 up->port.membase = NULL;
1897 }
1898
1899 release_mem_region(up->port.mapbase, size);
1900 break;
1901
1902 case UPIO_HUB6:
1903 case UPIO_PORT:
1904 release_region(up->port.iobase, size);
1905 break;
1906 }
1907}
1908
1909static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1910{
1911 unsigned long start = UART_RSA_BASE << up->port.regshift;
1912 unsigned int size = 8 << up->port.regshift;
1913 int ret = 0;
1914
1915 switch (up->port.iotype) {
1916 case UPIO_MEM:
1917 ret = -EINVAL;
1918 break;
1919
1920 case UPIO_HUB6:
1921 case UPIO_PORT:
1922 start += up->port.iobase;
1923 if (!request_region(start, size, "serial-rsa"))
1924 ret = -EBUSY;
1925 break;
1926 }
1927
1928 return ret;
1929}
1930
1931static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1932{
1933 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1934 unsigned int size = 8 << up->port.regshift;
1935
1936 switch (up->port.iotype) {
1937 case UPIO_MEM:
1938 break;
1939
1940 case UPIO_HUB6:
1941 case UPIO_PORT:
1942 release_region(up->port.iobase + offset, size);
1943 break;
1944 }
1945}
1946
1947static void serial8250_release_port(struct uart_port *port)
1948{
1949 struct uart_8250_port *up = (struct uart_8250_port *)port;
1950
1951 serial8250_release_std_resource(up);
1952 if (up->port.type == PORT_RSA)
1953 serial8250_release_rsa_resource(up);
1954}
1955
1956static int serial8250_request_port(struct uart_port *port)
1957{
1958 struct uart_8250_port *up = (struct uart_8250_port *)port;
1959 int ret = 0;
1960
1961 ret = serial8250_request_std_resource(up);
1962 if (ret == 0 && up->port.type == PORT_RSA) {
1963 ret = serial8250_request_rsa_resource(up);
1964 if (ret < 0)
1965 serial8250_release_std_resource(up);
1966 }
1967
1968 return ret;
1969}
1970
1971static void serial8250_config_port(struct uart_port *port, int flags)
1972{
1973 struct uart_8250_port *up = (struct uart_8250_port *)port;
1974 int probeflags = PROBE_ANY;
1975 int ret;
1976
1977 /*
1978 * Don't probe for MCA ports on non-MCA machines.
1979 */
1980 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
1981 return;
1982
1983 /*
1984 * Find the region that we can probe for. This in turn
1985 * tells us whether we can probe for the type of port.
1986 */
1987 ret = serial8250_request_std_resource(up);
1988 if (ret < 0)
1989 return;
1990
1991 ret = serial8250_request_rsa_resource(up);
1992 if (ret < 0)
1993 probeflags &= ~PROBE_RSA;
1994
1995 if (flags & UART_CONFIG_TYPE)
1996 autoconfig(up, probeflags);
1997 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
1998 autoconfig_irq(up);
1999
2000 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2001 serial8250_release_rsa_resource(up);
2002 if (up->port.type == PORT_UNKNOWN)
2003 serial8250_release_std_resource(up);
2004}
2005
2006static int
2007serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2008{
2009 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2010 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2011 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2012 ser->type == PORT_STARTECH)
2013 return -EINVAL;
2014 return 0;
2015}
2016
2017static const char *
2018serial8250_type(struct uart_port *port)
2019{
2020 int type = port->type;
2021
2022 if (type >= ARRAY_SIZE(uart_config))
2023 type = 0;
2024 return uart_config[type].name;
2025}
2026
2027static struct uart_ops serial8250_pops = {
2028 .tx_empty = serial8250_tx_empty,
2029 .set_mctrl = serial8250_set_mctrl,
2030 .get_mctrl = serial8250_get_mctrl,
2031 .stop_tx = serial8250_stop_tx,
2032 .start_tx = serial8250_start_tx,
2033 .stop_rx = serial8250_stop_rx,
2034 .enable_ms = serial8250_enable_ms,
2035 .break_ctl = serial8250_break_ctl,
2036 .startup = serial8250_startup,
2037 .shutdown = serial8250_shutdown,
2038 .set_termios = serial8250_set_termios,
2039 .pm = serial8250_pm,
2040 .type = serial8250_type,
2041 .release_port = serial8250_release_port,
2042 .request_port = serial8250_request_port,
2043 .config_port = serial8250_config_port,
2044 .verify_port = serial8250_verify_port,
2045};
2046
2047static struct uart_8250_port serial8250_ports[UART_NR];
2048
2049static void __init serial8250_isa_init_ports(void)
2050{
2051 struct uart_8250_port *up;
2052 static int first = 1;
2053 int i;
2054
2055 if (!first)
2056 return;
2057 first = 0;
2058
2059 for (i = 0; i < UART_NR; i++) {
2060 struct uart_8250_port *up = &serial8250_ports[i];
2061
2062 up->port.line = i;
2063 spin_lock_init(&up->port.lock);
2064
2065 init_timer(&up->timer);
2066 up->timer.function = serial8250_timeout;
2067
2068 /*
2069 * ALPHA_KLUDGE_MCR needs to be killed.
2070 */
2071 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2072 up->mcr_force = ALPHA_KLUDGE_MCR;
2073
2074 up->port.ops = &serial8250_pops;
2075 }
2076
2077 for (i = 0, up = serial8250_ports; i < ARRAY_SIZE(old_serial_port);
2078 i++, up++) {
2079 up->port.iobase = old_serial_port[i].port;
2080 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2081 up->port.uartclk = old_serial_port[i].baud_base * 16;
2082 up->port.flags = old_serial_port[i].flags;
2083 up->port.hub6 = old_serial_port[i].hub6;
2084 up->port.membase = old_serial_port[i].iomem_base;
2085 up->port.iotype = old_serial_port[i].io_type;
2086 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2087 if (share_irqs)
2088 up->port.flags |= UPF_SHARE_IRQ;
2089 }
2090}
2091
2092static void __init
2093serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2094{
2095 int i;
2096
2097 serial8250_isa_init_ports();
2098
2099 for (i = 0; i < UART_NR; i++) {
2100 struct uart_8250_port *up = &serial8250_ports[i];
2101
2102 up->port.dev = dev;
2103 uart_add_one_port(drv, &up->port);
2104 }
2105}
2106
2107#ifdef CONFIG_SERIAL_8250_CONSOLE
2108
2109#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2110
2111/*
2112 * Wait for transmitter & holding register to empty
2113 */
2114static inline void wait_for_xmitr(struct uart_8250_port *up)
2115{
2116 unsigned int status, tmout = 10000;
2117
2118 /* Wait up to 10ms for the character(s) to be sent. */
2119 do {
2120 status = serial_in(up, UART_LSR);
2121
2122 if (status & UART_LSR_BI)
2123 up->lsr_break_flag = UART_LSR_BI;
2124
2125 if (--tmout == 0)
2126 break;
2127 udelay(1);
2128 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2129
2130 /* Wait up to 1s for flow control if necessary */
2131 if (up->port.flags & UPF_CONS_FLOW) {
2132 tmout = 1000000;
2133 while (--tmout &&
2134 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2135 udelay(1);
2136 }
2137}
2138
2139/*
2140 * Print a string to the serial port trying not to disturb
2141 * any possible real use of the port...
2142 *
2143 * The console_lock must be held when we get here.
2144 */
2145static void
2146serial8250_console_write(struct console *co, const char *s, unsigned int count)
2147{
2148 struct uart_8250_port *up = &serial8250_ports[co->index];
2149 unsigned int ier;
2150 int i;
2151
2152 /*
2153 * First save the UER then disable the interrupts
2154 */
2155 ier = serial_in(up, UART_IER);
2156
2157 if (up->capabilities & UART_CAP_UUE)
2158 serial_out(up, UART_IER, UART_IER_UUE);
2159 else
2160 serial_out(up, UART_IER, 0);
2161
2162 /*
2163 * Now, do each character
2164 */
2165 for (i = 0; i < count; i++, s++) {
2166 wait_for_xmitr(up);
2167
2168 /*
2169 * Send the character out.
2170 * If a LF, also do CR...
2171 */
2172 serial_out(up, UART_TX, *s);
2173 if (*s == 10) {
2174 wait_for_xmitr(up);
2175 serial_out(up, UART_TX, 13);
2176 }
2177 }
2178
2179 /*
2180 * Finally, wait for transmitter to become empty
2181 * and restore the IER
2182 */
2183 wait_for_xmitr(up);
2184 serial_out(up, UART_IER, ier);
2185}
2186
2187static int serial8250_console_setup(struct console *co, char *options)
2188{
2189 struct uart_port *port;
2190 int baud = 9600;
2191 int bits = 8;
2192 int parity = 'n';
2193 int flow = 'n';
2194
2195 /*
2196 * Check whether an invalid uart number has been specified, and
2197 * if so, search for the first available port that does have
2198 * console support.
2199 */
2200 if (co->index >= UART_NR)
2201 co->index = 0;
2202 port = &serial8250_ports[co->index].port;
2203 if (!port->iobase && !port->membase)
2204 return -ENODEV;
2205
2206 if (options)
2207 uart_parse_options(options, &baud, &parity, &bits, &flow);
2208
2209 return uart_set_options(port, co, baud, parity, bits, flow);
2210}
2211
2212static struct uart_driver serial8250_reg;
2213static struct console serial8250_console = {
2214 .name = "ttyS",
2215 .write = serial8250_console_write,
2216 .device = uart_console_device,
2217 .setup = serial8250_console_setup,
2218 .flags = CON_PRINTBUFFER,
2219 .index = -1,
2220 .data = &serial8250_reg,
2221};
2222
2223static int __init serial8250_console_init(void)
2224{
2225 serial8250_isa_init_ports();
2226 register_console(&serial8250_console);
2227 return 0;
2228}
2229console_initcall(serial8250_console_init);
2230
2231static int __init find_port(struct uart_port *p)
2232{
2233 int line;
2234 struct uart_port *port;
2235
2236 for (line = 0; line < UART_NR; line++) {
2237 port = &serial8250_ports[line].port;
2238 if (p->iotype == port->iotype &&
2239 p->iobase == port->iobase &&
2240 p->membase == port->membase)
2241 return line;
2242 }
2243 return -ENODEV;
2244}
2245
2246int __init serial8250_start_console(struct uart_port *port, char *options)
2247{
2248 int line;
2249
2250 line = find_port(port);
2251 if (line < 0)
2252 return -ENODEV;
2253
2254 add_preferred_console("ttyS", line, options);
2255 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2256 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2257 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2258 (unsigned long) port->iobase, options);
2259 if (!(serial8250_console.flags & CON_ENABLED)) {
2260 serial8250_console.flags &= ~CON_PRINTBUFFER;
2261 register_console(&serial8250_console);
2262 }
2263 return line;
2264}
2265
2266#define SERIAL8250_CONSOLE &serial8250_console
2267#else
2268#define SERIAL8250_CONSOLE NULL
2269#endif
2270
2271static struct uart_driver serial8250_reg = {
2272 .owner = THIS_MODULE,
2273 .driver_name = "serial",
2274 .devfs_name = "tts/",
2275 .dev_name = "ttyS",
2276 .major = TTY_MAJOR,
2277 .minor = 64,
2278 .nr = UART_NR,
2279 .cons = SERIAL8250_CONSOLE,
2280};
2281
2282int __init early_serial_setup(struct uart_port *port)
2283{
2284 if (port->line >= ARRAY_SIZE(serial8250_ports))
2285 return -ENODEV;
2286
2287 serial8250_isa_init_ports();
2288 serial8250_ports[port->line].port = *port;
2289 serial8250_ports[port->line].port.ops = &serial8250_pops;
2290 return 0;
2291}
2292
2293/**
2294 * serial8250_suspend_port - suspend one serial port
2295 * @line: serial line number
2296 * @level: the level of port suspension, as per uart_suspend_port
2297 *
2298 * Suspend one serial port.
2299 */
2300void serial8250_suspend_port(int line)
2301{
2302 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2303}
2304
2305/**
2306 * serial8250_resume_port - resume one serial port
2307 * @line: serial line number
2308 * @level: the level of port resumption, as per uart_resume_port
2309 *
2310 * Resume one serial port.
2311 */
2312void serial8250_resume_port(int line)
2313{
2314 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2315}
2316
2317/*
2318 * Register a set of serial devices attached to a platform device. The
2319 * list is terminated with a zero flags entry, which means we expect
2320 * all entries to have at least UPF_BOOT_AUTOCONF set.
2321 */
2322static int __devinit serial8250_probe(struct device *dev)
2323{
2324 struct plat_serial8250_port *p = dev->platform_data;
2325 struct uart_port port;
2326
2327 memset(&port, 0, sizeof(struct uart_port));
2328
2329 for (; p && p->flags != 0; p++) {
2330 port.iobase = p->iobase;
2331 port.membase = p->membase;
2332 port.irq = p->irq;
2333 port.uartclk = p->uartclk;
2334 port.regshift = p->regshift;
2335 port.iotype = p->iotype;
2336 port.flags = p->flags;
2337 port.mapbase = p->mapbase;
2338 port.dev = dev;
2339 if (share_irqs)
2340 port.flags |= UPF_SHARE_IRQ;
2341 serial8250_register_port(&port);
2342 }
2343 return 0;
2344}
2345
2346/*
2347 * Remove serial ports registered against a platform device.
2348 */
2349static int __devexit serial8250_remove(struct device *dev)
2350{
2351 int i;
2352
2353 for (i = 0; i < UART_NR; i++) {
2354 struct uart_8250_port *up = &serial8250_ports[i];
2355
2356 if (up->port.dev == dev)
2357 serial8250_unregister_port(i);
2358 }
2359 return 0;
2360}
2361
2362static int serial8250_suspend(struct device *dev, pm_message_t state, u32 level)
2363{
2364 int i;
2365
2366 if (level != SUSPEND_DISABLE)
2367 return 0;
2368
2369 for (i = 0; i < UART_NR; i++) {
2370 struct uart_8250_port *up = &serial8250_ports[i];
2371
2372 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2373 uart_suspend_port(&serial8250_reg, &up->port);
2374 }
2375
2376 return 0;
2377}
2378
2379static int serial8250_resume(struct device *dev, u32 level)
2380{
2381 int i;
2382
2383 if (level != RESUME_ENABLE)
2384 return 0;
2385
2386 for (i = 0; i < UART_NR; i++) {
2387 struct uart_8250_port *up = &serial8250_ports[i];
2388
2389 if (up->port.type != PORT_UNKNOWN && up->port.dev == dev)
2390 uart_resume_port(&serial8250_reg, &up->port);
2391 }
2392
2393 return 0;
2394}
2395
2396static struct device_driver serial8250_isa_driver = {
2397 .name = "serial8250",
2398 .bus = &platform_bus_type,
2399 .probe = serial8250_probe,
2400 .remove = __devexit_p(serial8250_remove),
2401 .suspend = serial8250_suspend,
2402 .resume = serial8250_resume,
2403};
2404
2405/*
2406 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2407 * in the table in include/asm/serial.h
2408 */
2409static struct platform_device *serial8250_isa_devs;
2410
2411/*
2412 * serial8250_register_port and serial8250_unregister_port allows for
2413 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2414 * modems and PCI multiport cards.
2415 */
2416static DECLARE_MUTEX(serial_sem);
2417
2418static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2419{
2420 int i;
2421
2422 /*
2423 * First, find a port entry which matches.
2424 */
2425 for (i = 0; i < UART_NR; i++)
2426 if (uart_match_port(&serial8250_ports[i].port, port))
2427 return &serial8250_ports[i];
2428
2429 /*
2430 * We didn't find a matching entry, so look for the first
2431 * free entry. We look for one which hasn't been previously
2432 * used (indicated by zero iobase).
2433 */
2434 for (i = 0; i < UART_NR; i++)
2435 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2436 serial8250_ports[i].port.iobase == 0)
2437 return &serial8250_ports[i];
2438
2439 /*
2440 * That also failed. Last resort is to find any entry which
2441 * doesn't have a real port associated with it.
2442 */
2443 for (i = 0; i < UART_NR; i++)
2444 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2445 return &serial8250_ports[i];
2446
2447 return NULL;
2448}
2449
2450/**
2451 * serial8250_register_port - register a serial port
2452 * @port: serial port template
2453 *
2454 * Configure the serial port specified by the request. If the
2455 * port exists and is in use, it is hung up and unregistered
2456 * first.
2457 *
2458 * The port is then probed and if necessary the IRQ is autodetected
2459 * If this fails an error is returned.
2460 *
2461 * On success the port is ready to use and the line number is returned.
2462 */
2463int serial8250_register_port(struct uart_port *port)
2464{
2465 struct uart_8250_port *uart;
2466 int ret = -ENOSPC;
2467
2468 if (port->uartclk == 0)
2469 return -EINVAL;
2470
2471 down(&serial_sem);
2472
2473 uart = serial8250_find_match_or_unused(port);
2474 if (uart) {
2475 uart_remove_one_port(&serial8250_reg, &uart->port);
2476
2477 uart->port.iobase = port->iobase;
2478 uart->port.membase = port->membase;
2479 uart->port.irq = port->irq;
2480 uart->port.uartclk = port->uartclk;
2481 uart->port.fifosize = port->fifosize;
2482 uart->port.regshift = port->regshift;
2483 uart->port.iotype = port->iotype;
2484 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2485 uart->port.mapbase = port->mapbase;
2486 if (port->dev)
2487 uart->port.dev = port->dev;
2488
2489 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2490 if (ret == 0)
2491 ret = uart->port.line;
2492 }
2493 up(&serial_sem);
2494
2495 return ret;
2496}
2497EXPORT_SYMBOL(serial8250_register_port);
2498
2499/**
2500 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2501 * @line: serial line number
2502 *
2503 * Remove one serial port. This may not be called from interrupt
2504 * context. We hand the port back to the our control.
2505 */
2506void serial8250_unregister_port(int line)
2507{
2508 struct uart_8250_port *uart = &serial8250_ports[line];
2509
2510 down(&serial_sem);
2511 uart_remove_one_port(&serial8250_reg, &uart->port);
2512 if (serial8250_isa_devs) {
2513 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2514 uart->port.type = PORT_UNKNOWN;
2515 uart->port.dev = &serial8250_isa_devs->dev;
2516 uart_add_one_port(&serial8250_reg, &uart->port);
2517 } else {
2518 uart->port.dev = NULL;
2519 }
2520 up(&serial_sem);
2521}
2522EXPORT_SYMBOL(serial8250_unregister_port);
2523
2524static int __init serial8250_init(void)
2525{
2526 int ret, i;
2527
2528 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2529 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2530 share_irqs ? "en" : "dis");
2531
2532 for (i = 0; i < NR_IRQS; i++)
2533 spin_lock_init(&irq_lists[i].lock);
2534
2535 ret = uart_register_driver(&serial8250_reg);
2536 if (ret)
2537 goto out;
2538
2539 serial8250_isa_devs = platform_device_register_simple("serial8250",
2540 -1, NULL, 0);
2541 if (IS_ERR(serial8250_isa_devs)) {
2542 ret = PTR_ERR(serial8250_isa_devs);
2543 goto unreg;
2544 }
2545
2546 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2547
2548 ret = driver_register(&serial8250_isa_driver);
2549 if (ret == 0)
2550 goto out;
2551
2552 platform_device_unregister(serial8250_isa_devs);
2553 unreg:
2554 uart_unregister_driver(&serial8250_reg);
2555 out:
2556 return ret;
2557}
2558
2559static void __exit serial8250_exit(void)
2560{
2561 struct platform_device *isa_dev = serial8250_isa_devs;
2562
2563 /*
2564 * This tells serial8250_unregister_port() not to re-register
2565 * the ports (thereby making serial8250_isa_driver permanently
2566 * in use.)
2567 */
2568 serial8250_isa_devs = NULL;
2569
2570 driver_unregister(&serial8250_isa_driver);
2571 platform_device_unregister(isa_dev);
2572
2573 uart_unregister_driver(&serial8250_reg);
2574}
2575
2576module_init(serial8250_init);
2577module_exit(serial8250_exit);
2578
2579EXPORT_SYMBOL(serial8250_suspend_port);
2580EXPORT_SYMBOL(serial8250_resume_port);
2581
2582MODULE_LICENSE("GPL");
2583MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2584
2585module_param(share_irqs, uint, 0644);
2586MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2587 " (unsafe)");
2588
2589#ifdef CONFIG_SERIAL_8250_RSA
2590module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2591MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2592#endif
2593MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
2594
2595/**
2596 * register_serial - configure a 16x50 serial port at runtime
2597 * @req: request structure
2598 *
2599 * Configure the serial port specified by the request. If the
2600 * port exists and is in use an error is returned. If the port
2601 * is not currently in the table it is added.
2602 *
2603 * The port is then probed and if necessary the IRQ is autodetected
2604 * If this fails an error is returned.
2605 *
2606 * On success the port is ready to use and the line number is returned.
23907eb8
RK		 2607 *
2608 * Note: this function is deprecated - use serial8250_register_port
2609 * instead.
1da177e4
LT		 2610 */
2611int register_serial(struct serial_struct *req)
2612{
2613 struct uart_port port;
2614
2615 port.iobase = req->port;
2616 port.membase = req->iomem_base;
2617 port.irq = req->irq;
2618 port.uartclk = req->baud_base * 16;
2619 port.fifosize = req->xmit_fifo_size;
2620 port.regshift = req->iomem_reg_shift;
2621 port.iotype = req->io_type;
2622 port.flags = req->flags | UPF_BOOT_AUTOCONF;
2623 port.mapbase = req->iomap_base;
2624 port.dev = NULL;
2625
2626 if (share_irqs)
2627 port.flags |= UPF_SHARE_IRQ;
2628
2629 if (HIGH_BITS_OFFSET)
2630 port.iobase |= (long) req->port_high << HIGH_BITS_OFFSET;
2631
2632 /*
2633 * If a clock rate wasn't specified by the low level driver, then
2634 * default to the standard clock rate. This should be 115200 (*16)
2635 * and should not depend on the architecture's BASE_BAUD definition.
2636 * However, since this API will be deprecated, it's probably a
2637 * better idea to convert the drivers to use the new API
2638 * (serial8250_register_port and serial8250_unregister_port).
2639 */
2640 if (port.uartclk == 0) {
2641 printk(KERN_WARNING
2642 "Serial: registering port at [%08x,%08lx,%p] irq %d with zero baud_base\n",
2643 port.iobase, port.mapbase, port.membase, port.irq);
2644 printk(KERN_WARNING "Serial: see %s:%d for more information\n",
2645 __FILE__, __LINE__);
2646 dump_stack();
2647
2648 /*
2649 * Fix it up for now, but this is only a temporary measure.
2650 */
2651 port.uartclk = BASE_BAUD * 16;
2652 }
2653
2654 return serial8250_register_port(&port);
2655}
2656EXPORT_SYMBOL(register_serial);
2657
2658/**
2659 * unregister_serial - remove a 16x50 serial port at runtime
2660 * @line: serial line number
2661 *
2662 * Remove one serial port. This may not be called from interrupt
2663 * context. We hand the port back to our local PM control.
23907eb8
RK		 2664 *
2665 * Note: this function is deprecated - use serial8250_unregister_port
2666 * instead.
1da177e4
LT		 2667 */
2668void unregister_serial(int line)
2669{
2670 serial8250_unregister_port(line);
2671}
2672EXPORT_SYMBOL(unregister_serial);
Clone of davem's net-next-2.6 tree