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serial: convert early_uart to earlycon for 8250
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
1da177e4
LT		 22
23#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24#define SUPPORT_SYSRQ
25#endif
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/ioport.h>
30#include <linux/init.h>
31#include <linux/console.h>
32#include <linux/sysrq.h>
1da177e4 33#include <linux/delay.h>
d052d1be 34#include <linux/platform_device.h>
1da177e4
LT		 35#include <linux/tty.h>
36#include <linux/tty_flip.h>
37#include <linux/serial_reg.h>
38#include <linux/serial_core.h>
39#include <linux/serial.h>
40#include <linux/serial_8250.h>
78512ece 41#include <linux/nmi.h>
f392ecfa 42#include <linux/mutex.h>
1da177e4
LT		 43
44#include <asm/io.h>
45#include <asm/irq.h>
46
47#include "8250.h"
48
49/*
50 * Configuration:
40663cc7 51 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 52 * is unsafe when used on edge-triggered interrupts.
53 */
408b664a 54static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 55
a61c2d78
DJ		 56static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
57
1da177e4
LT		 58/*
59 * Debugging.
60 */
61#if 0
62#define DEBUG_AUTOCONF(fmt...) printk(fmt)
63#else
64#define DEBUG_AUTOCONF(fmt...) do { } while (0)
65#endif
66
67#if 0
68#define DEBUG_INTR(fmt...) printk(fmt)
69#else
70#define DEBUG_INTR(fmt...) do { } while (0)
71#endif
72
73#define PASS_LIMIT 256
74
75/*
76 * We default to IRQ0 for the "no irq" hack. Some
77 * machine types want others as well - they're free
78 * to redefine this in their header file.
79 */
80#define is_real_interrupt(irq) ((irq) != 0)
81
1da177e4
LT		 82#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
83#define CONFIG_SERIAL_DETECT_IRQ 1
84#endif
1da177e4
LT		 85#ifdef CONFIG_SERIAL_8250_MANY_PORTS
86#define CONFIG_SERIAL_MANY_PORTS 1
87#endif
88
89/*
90 * HUB6 is always on. This will be removed once the header
91 * files have been cleaned.
92 */
93#define CONFIG_HUB6 1
94
95#include <asm/serial.h>
96
97/*
98 * SERIAL_PORT_DFNS tells us about built-in ports that have no
99 * standard enumeration mechanism. Platforms that can find all
100 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 */
102#ifndef SERIAL_PORT_DFNS
103#define SERIAL_PORT_DFNS
104#endif
105
cb3592be 106static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 107 SERIAL_PORT_DFNS /* defined in asm/serial.h */
108};
109
026d02a2 110#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 111
112#ifdef CONFIG_SERIAL_8250_RSA
113
114#define PORT_RSA_MAX 4
115static unsigned long probe_rsa[PORT_RSA_MAX];
116static unsigned int probe_rsa_count;
117#endif /* CONFIG_SERIAL_8250_RSA */
118
119struct uart_8250_port {
120 struct uart_port port;
121 struct timer_list timer; /* "no irq" timer */
122 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 123 unsigned short capabilities; /* port capabilities */
124 unsigned short bugs; /* port bugs */
1da177e4 125 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 126 unsigned char acr;
127 unsigned char ier;
128 unsigned char lcr;
129 unsigned char mcr;
130 unsigned char mcr_mask; /* mask of user bits */
131 unsigned char mcr_force; /* mask of forced bits */
132 unsigned char lsr_break_flag;
133
134 /*
135 * We provide a per-port pm hook.
136 */
137 void (*pm)(struct uart_port *port,
138 unsigned int state, unsigned int old);
139};
140
141struct irq_info {
142 spinlock_t lock;
143 struct list_head *head;
144};
145
146static struct irq_info irq_lists[NR_IRQS];
147
148/*
149 * Here we define the default xmit fifo size used for each type of UART.
150 */
151static const struct serial8250_config uart_config[] = {
152 [PORT_UNKNOWN] = {
153 .name = "unknown",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_8250] = {
158 .name = "8250",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16450] = {
163 .name = "16450",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550] = {
168 .name = "16550",
169 .fifo_size = 1,
170 .tx_loadsz = 1,
171 },
172 [PORT_16550A] = {
173 .name = "16550A",
174 .fifo_size = 16,
175 .tx_loadsz = 16,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
177 .flags = UART_CAP_FIFO,
178 },
179 [PORT_CIRRUS] = {
180 .name = "Cirrus",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 },
184 [PORT_16650] = {
185 .name = "ST16650",
186 .fifo_size = 1,
187 .tx_loadsz = 1,
188 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
189 },
190 [PORT_16650V2] = {
191 .name = "ST16650V2",
192 .fifo_size = 32,
193 .tx_loadsz = 16,
194 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
195 UART_FCR_T_TRIG_00,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
197 },
198 [PORT_16750] = {
199 .name = "TI16750",
200 .fifo_size = 64,
201 .tx_loadsz = 64,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
203 UART_FCR7_64BYTE,
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
205 },
206 [PORT_STARTECH] = {
207 .name = "Startech",
208 .fifo_size = 1,
209 .tx_loadsz = 1,
210 },
211 [PORT_16C950] = {
212 .name = "16C950/954",
213 .fifo_size = 128,
214 .tx_loadsz = 128,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
216 .flags = UART_CAP_FIFO,
217 },
218 [PORT_16654] = {
219 .name = "ST16654",
220 .fifo_size = 64,
221 .tx_loadsz = 32,
222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
223 UART_FCR_T_TRIG_10,
224 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
225 },
226 [PORT_16850] = {
227 .name = "XR16850",
228 .fifo_size = 128,
229 .tx_loadsz = 128,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
231 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
232 },
233 [PORT_RSA] = {
234 .name = "RSA",
235 .fifo_size = 2048,
236 .tx_loadsz = 2048,
237 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
238 .flags = UART_CAP_FIFO,
239 },
240 [PORT_NS16550A] = {
241 .name = "NS16550A",
242 .fifo_size = 16,
243 .tx_loadsz = 16,
244 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_NATSEMI,
246 },
247 [PORT_XSCALE] = {
248 .name = "XScale",
249 .fifo_size = 32,
250 .tx_loadsz = 32,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_UUE,
253 },
bd71c182
TK		 254 [PORT_RM9000] = {
255 .name = "RM9000",
256 .fifo_size = 16,
257 .tx_loadsz = 16,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
259 .flags = UART_CAP_FIFO,
260 },
1da177e4
LT		 261};
262
bd71c182 263#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 264
265/* Au1x00 UART hardware has a weird register layout */
266static const u8 au_io_in_map[] = {
267 [UART_RX] = 0,
268 [UART_IER] = 2,
269 [UART_IIR] = 3,
270 [UART_LCR] = 5,
271 [UART_MCR] = 6,
272 [UART_LSR] = 7,
273 [UART_MSR] = 8,
274};
275
276static const u8 au_io_out_map[] = {
277 [UART_TX] = 1,
278 [UART_IER] = 2,
279 [UART_FCR] = 4,
280 [UART_LCR] = 5,
281 [UART_MCR] = 6,
282};
283
284/* sane hardware needs no mapping */
285static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
286{
287 if (up->port.iotype != UPIO_AU)
288 return offset;
289 return au_io_in_map[offset];
290}
291
292static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
293{
294 if (up->port.iotype != UPIO_AU)
295 return offset;
296 return au_io_out_map[offset];
297}
298
bd71c182
TK		 299#elif defined (CONFIG_SERIAL_8250_RM9K)
300
301static const u8
302 regmap_in[8] = {
303 [UART_RX] = 0x00,
304 [UART_IER] = 0x0c,
305 [UART_IIR] = 0x14,
306 [UART_LCR] = 0x1c,
307 [UART_MCR] = 0x20,
308 [UART_LSR] = 0x24,
309 [UART_MSR] = 0x28,
310 [UART_SCR] = 0x2c
311 },
312 regmap_out[8] = {
313 [UART_TX] = 0x04,
314 [UART_IER] = 0x0c,
315 [UART_FCR] = 0x18,
316 [UART_LCR] = 0x1c,
317 [UART_MCR] = 0x20,
318 [UART_LSR] = 0x24,
319 [UART_MSR] = 0x28,
320 [UART_SCR] = 0x2c
321 };
322
323static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
324{
325 if (up->port.iotype != UPIO_RM9000)
326 return offset;
327 return regmap_in[offset];
328}
329
330static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
331{
332 if (up->port.iotype != UPIO_RM9000)
333 return offset;
334 return regmap_out[offset];
335}
336
21c614a7
PA		 337#else
338
339/* sane hardware needs no mapping */
340#define map_8250_in_reg(up, offset) (offset)
341#define map_8250_out_reg(up, offset) (offset)
342
343#endif
344
ea8874dc 345static unsigned int serial_in(struct uart_8250_port *up, int offset)
1da177e4 346{
3be91ec7 347 unsigned int tmp;
21c614a7 348 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 349
350 switch (up->port.iotype) {
351 case UPIO_HUB6:
352 outb(up->port.hub6 - 1 + offset, up->port.iobase);
353 return inb(up->port.iobase + 1);
354
355 case UPIO_MEM:
beab697a 356 case UPIO_DWAPB:
1da177e4
LT		 357 return readb(up->port.membase + offset);
358
bd71c182 359 case UPIO_RM9000:
1da177e4
LT		 360 case UPIO_MEM32:
361 return readl(up->port.membase + offset);
362
21c614a7
PA		 363#ifdef CONFIG_SERIAL_8250_AU1X00
364 case UPIO_AU:
365 return __raw_readl(up->port.membase + offset);
366#endif
367
3be91ec7
ZR		 368 case UPIO_TSI:
369 if (offset == UART_IIR) {
9e84b60e
AV		 370 tmp = readl(up->port.membase + (UART_IIR & ~3));
371 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
3be91ec7
ZR		 372 } else
373 return readb(up->port.membase + offset);
374
1da177e4
LT		 375 default:
376 return inb(up->port.iobase + offset);
377 }
378}
379
ea8874dc 380static void
1da177e4
LT		 381serial_out(struct uart_8250_port *up, int offset, int value)
382{
beab697a
MSJ		 383 /* Save the offset before it's remapped */
384 int save_offset = offset;
21c614a7 385 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 386
387 switch (up->port.iotype) {
388 case UPIO_HUB6:
389 outb(up->port.hub6 - 1 + offset, up->port.iobase);
390 outb(value, up->port.iobase + 1);
391 break;
392
393 case UPIO_MEM:
394 writeb(value, up->port.membase + offset);
395 break;
396
bd71c182 397 case UPIO_RM9000:
1da177e4
LT		 398 case UPIO_MEM32:
399 writel(value, up->port.membase + offset);
400 break;
401
21c614a7
PA		 402#ifdef CONFIG_SERIAL_8250_AU1X00
403 case UPIO_AU:
404 __raw_writel(value, up->port.membase + offset);
405 break;
406#endif
3be91ec7
ZR		 407 case UPIO_TSI:
408 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
409 writeb(value, up->port.membase + offset);
410 break;
21c614a7 411
beab697a
MSJ		 412 case UPIO_DWAPB:
413 /* Save the LCR value so it can be re-written when a
414 * Busy Detect interrupt occurs. */
415 if (save_offset == UART_LCR)
416 up->lcr = value;
417 writeb(value, up->port.membase + offset);
418 /* Read the IER to ensure any interrupt is cleared before
419 * returning from ISR. */
420 if (save_offset == UART_TX || save_offset == UART_IER)
421 value = serial_in(up, UART_IER);
422 break;
423
1da177e4
LT		 424 default:
425 outb(value, up->port.iobase + offset);
426 }
427}
428
40b36daa
AW		 429static void
430serial_out_sync(struct uart_8250_port *up, int offset, int value)
431{
432 switch (up->port.iotype) {
433 case UPIO_MEM:
434 case UPIO_MEM32:
435#ifdef CONFIG_SERIAL_8250_AU1X00
436 case UPIO_AU:
437#endif
beab697a 438 case UPIO_DWAPB:
40b36daa
AW		 439 serial_out(up, offset, value);
440 serial_in(up, UART_LCR); /* safe, no side-effects */
441 break;
442 default:
443 serial_out(up, offset, value);
444 }
445}
446
1da177e4
LT		 447/*
448 * We used to support using pause I/O for certain machines. We
449 * haven't supported this for a while, but just in case it's badly
450 * needed for certain old 386 machines, I've left these #define's
451 * in....
452 */
453#define serial_inp(up, offset) serial_in(up, offset)
454#define serial_outp(up, offset, value) serial_out(up, offset, value)
455
b32b19b8
JAH		 456/* Uart divisor latch read */
457static inline int _serial_dl_read(struct uart_8250_port *up)
458{
459 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
460}
461
462/* Uart divisor latch write */
463static inline void _serial_dl_write(struct uart_8250_port *up, int value)
464{
465 serial_outp(up, UART_DLL, value & 0xff);
466 serial_outp(up, UART_DLM, value >> 8 & 0xff);
467}
468
bd71c182 469#if defined (CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 470/* Au1x00 haven't got a standard divisor latch */
471static int serial_dl_read(struct uart_8250_port *up)
472{
473 if (up->port.iotype == UPIO_AU)
474 return __raw_readl(up->port.membase + 0x28);
475 else
476 return _serial_dl_read(up);
477}
478
479static void serial_dl_write(struct uart_8250_port *up, int value)
480{
481 if (up->port.iotype == UPIO_AU)
482 __raw_writel(value, up->port.membase + 0x28);
483 else
484 _serial_dl_write(up, value);
485}
bd71c182
TK		 486#elif defined (CONFIG_SERIAL_8250_RM9K)
487static int serial_dl_read(struct uart_8250_port *up)
488{
489 return (up->port.iotype == UPIO_RM9000) ?
490 (((__raw_readl(up->port.membase + 0x10) << 8) |
491 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
492 _serial_dl_read(up);
493}
494
495static void serial_dl_write(struct uart_8250_port *up, int value)
496{
497 if (up->port.iotype == UPIO_RM9000) {
498 __raw_writel(value, up->port.membase + 0x08);
499 __raw_writel(value >> 8, up->port.membase + 0x10);
500 } else {
501 _serial_dl_write(up, value);
502 }
503}
b32b19b8
JAH		 504#else
505#define serial_dl_read(up) _serial_dl_read(up)
506#define serial_dl_write(up, value) _serial_dl_write(up, value)
507#endif
1da177e4
LT		 508
509/*
510 * For the 16C950
511 */
512static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
513{
514 serial_out(up, UART_SCR, offset);
515 serial_out(up, UART_ICR, value);
516}
517
518static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
519{
520 unsigned int value;
521
522 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
523 serial_out(up, UART_SCR, offset);
524 value = serial_in(up, UART_ICR);
525 serial_icr_write(up, UART_ACR, up->acr);
526
527 return value;
528}
529
530/*
531 * FIFO support.
532 */
533static inline void serial8250_clear_fifos(struct uart_8250_port *p)
534{
535 if (p->capabilities & UART_CAP_FIFO) {
536 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
537 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
538 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
539 serial_outp(p, UART_FCR, 0);
540 }
541}
542
543/*
544 * IER sleep support. UARTs which have EFRs need the "extended
545 * capability" bit enabled. Note that on XR16C850s, we need to
546 * reset LCR to write to IER.
547 */
548static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
549{
550 if (p->capabilities & UART_CAP_SLEEP) {
551 if (p->capabilities & UART_CAP_EFR) {
552 serial_outp(p, UART_LCR, 0xBF);
553 serial_outp(p, UART_EFR, UART_EFR_ECB);
554 serial_outp(p, UART_LCR, 0);
555 }
556 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
557 if (p->capabilities & UART_CAP_EFR) {
558 serial_outp(p, UART_LCR, 0xBF);
559 serial_outp(p, UART_EFR, 0);
560 serial_outp(p, UART_LCR, 0);
561 }
562 }
563}
564
565#ifdef CONFIG_SERIAL_8250_RSA
566/*
567 * Attempts to turn on the RSA FIFO. Returns zero on failure.
568 * We set the port uart clock rate if we succeed.
569 */
570static int __enable_rsa(struct uart_8250_port *up)
571{
572 unsigned char mode;
573 int result;
574
575 mode = serial_inp(up, UART_RSA_MSR);
576 result = mode & UART_RSA_MSR_FIFO;
577
578 if (!result) {
579 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
580 mode = serial_inp(up, UART_RSA_MSR);
581 result = mode & UART_RSA_MSR_FIFO;
582 }
583
584 if (result)
585 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
586
587 return result;
588}
589
590static void enable_rsa(struct uart_8250_port *up)
591{
592 if (up->port.type == PORT_RSA) {
593 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
594 spin_lock_irq(&up->port.lock);
595 __enable_rsa(up);
596 spin_unlock_irq(&up->port.lock);
597 }
598 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
599 serial_outp(up, UART_RSA_FRR, 0);
600 }
601}
602
603/*
604 * Attempts to turn off the RSA FIFO. Returns zero on failure.
605 * It is unknown why interrupts were disabled in here. However,
606 * the caller is expected to preserve this behaviour by grabbing
607 * the spinlock before calling this function.
608 */
609static void disable_rsa(struct uart_8250_port *up)
610{
611 unsigned char mode;
612 int result;
613
614 if (up->port.type == PORT_RSA &&
615 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
616 spin_lock_irq(&up->port.lock);
617
618 mode = serial_inp(up, UART_RSA_MSR);
619 result = !(mode & UART_RSA_MSR_FIFO);
620
621 if (!result) {
622 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
623 mode = serial_inp(up, UART_RSA_MSR);
624 result = !(mode & UART_RSA_MSR_FIFO);
625 }
626
627 if (result)
628 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
629 spin_unlock_irq(&up->port.lock);
630 }
631}
632#endif /* CONFIG_SERIAL_8250_RSA */
633
634/*
635 * This is a quickie test to see how big the FIFO is.
636 * It doesn't work at all the time, more's the pity.
637 */
638static int size_fifo(struct uart_8250_port *up)
639{
b32b19b8
JAH		 640 unsigned char old_fcr, old_mcr, old_lcr;
641 unsigned short old_dl;
1da177e4
LT		 642 int count;
643
644 old_lcr = serial_inp(up, UART_LCR);
645 serial_outp(up, UART_LCR, 0);
646 old_fcr = serial_inp(up, UART_FCR);
647 old_mcr = serial_inp(up, UART_MCR);
648 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
649 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
650 serial_outp(up, UART_MCR, UART_MCR_LOOP);
651 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 652 old_dl = serial_dl_read(up);
653 serial_dl_write(up, 0x0001);
1da177e4
LT		 654 serial_outp(up, UART_LCR, 0x03);
655 for (count = 0; count < 256; count++)
656 serial_outp(up, UART_TX, count);
657 mdelay(20);/* FIXME - schedule_timeout */
658 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
659 (count < 256); count++)
660 serial_inp(up, UART_RX);
661 serial_outp(up, UART_FCR, old_fcr);
662 serial_outp(up, UART_MCR, old_mcr);
663 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 664 serial_dl_write(up, old_dl);
1da177e4
LT		 665 serial_outp(up, UART_LCR, old_lcr);
666
667 return count;
668}
669
670/*
671 * Read UART ID using the divisor method - set DLL and DLM to zero
672 * and the revision will be in DLL and device type in DLM. We
673 * preserve the device state across this.
674 */
675static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
676{
677 unsigned char old_dll, old_dlm, old_lcr;
678 unsigned int id;
679
680 old_lcr = serial_inp(p, UART_LCR);
681 serial_outp(p, UART_LCR, UART_LCR_DLAB);
682
683 old_dll = serial_inp(p, UART_DLL);
684 old_dlm = serial_inp(p, UART_DLM);
685
686 serial_outp(p, UART_DLL, 0);
687 serial_outp(p, UART_DLM, 0);
688
689 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
690
691 serial_outp(p, UART_DLL, old_dll);
692 serial_outp(p, UART_DLM, old_dlm);
693 serial_outp(p, UART_LCR, old_lcr);
694
695 return id;
696}
697
698/*
699 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
700 * When this function is called we know it is at least a StarTech
701 * 16650 V2, but it might be one of several StarTech UARTs, or one of
702 * its clones. (We treat the broken original StarTech 16650 V1 as a
703 * 16550, and why not? Startech doesn't seem to even acknowledge its
704 * existence.)
bd71c182 705 *
1da177e4
LT		 706 * What evil have men's minds wrought...
707 */
708static void autoconfig_has_efr(struct uart_8250_port *up)
709{
710 unsigned int id1, id2, id3, rev;
711
712 /*
713 * Everything with an EFR has SLEEP
714 */
715 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
716
717 /*
718 * First we check to see if it's an Oxford Semiconductor UART.
719 *
720 * If we have to do this here because some non-National
721 * Semiconductor clone chips lock up if you try writing to the
722 * LSR register (which serial_icr_read does)
723 */
724
725 /*
726 * Check for Oxford Semiconductor 16C950.
727 *
728 * EFR [4] must be set else this test fails.
729 *
730 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
731 * claims that it's needed for 952 dual UART's (which are not
732 * recommended for new designs).
733 */
734 up->acr = 0;
735 serial_out(up, UART_LCR, 0xBF);
736 serial_out(up, UART_EFR, UART_EFR_ECB);
737 serial_out(up, UART_LCR, 0x00);
738 id1 = serial_icr_read(up, UART_ID1);
739 id2 = serial_icr_read(up, UART_ID2);
740 id3 = serial_icr_read(up, UART_ID3);
741 rev = serial_icr_read(up, UART_REV);
742
743 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
744
745 if (id1 == 0x16 && id2 == 0xC9 &&
746 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
747 up->port.type = PORT_16C950;
4ba5e35d
RK		 748
749 /*
750 * Enable work around for the Oxford Semiconductor 952 rev B
751 * chip which causes it to seriously miscalculate baud rates
752 * when DLL is 0.
753 */
754 if (id3 == 0x52 && rev == 0x01)
755 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 756 return;
757 }
bd71c182 758
1da177e4
LT		 759 /*
760 * We check for a XR16C850 by setting DLL and DLM to 0, and then
761 * reading back DLL and DLM. The chip type depends on the DLM
762 * value read back:
763 * 0x10 - XR16C850 and the DLL contains the chip revision.
764 * 0x12 - XR16C2850.
765 * 0x14 - XR16C854.
766 */
767 id1 = autoconfig_read_divisor_id(up);
768 DEBUG_AUTOCONF("850id=%04x ", id1);
769
770 id2 = id1 >> 8;
771 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 772 up->port.type = PORT_16850;
773 return;
774 }
775
776 /*
777 * It wasn't an XR16C850.
778 *
779 * We distinguish between the '654 and the '650 by counting
780 * how many bytes are in the FIFO. I'm using this for now,
781 * since that's the technique that was sent to me in the
782 * serial driver update, but I'm not convinced this works.
783 * I've had problems doing this in the past. -TYT
784 */
785 if (size_fifo(up) == 64)
786 up->port.type = PORT_16654;
787 else
788 up->port.type = PORT_16650V2;
789}
790
791/*
792 * We detected a chip without a FIFO. Only two fall into
793 * this category - the original 8250 and the 16450. The
794 * 16450 has a scratch register (accessible with LCR=0)
795 */
796static void autoconfig_8250(struct uart_8250_port *up)
797{
798 unsigned char scratch, status1, status2;
799
800 up->port.type = PORT_8250;
801
802 scratch = serial_in(up, UART_SCR);
803 serial_outp(up, UART_SCR, 0xa5);
804 status1 = serial_in(up, UART_SCR);
805 serial_outp(up, UART_SCR, 0x5a);
806 status2 = serial_in(up, UART_SCR);
807 serial_outp(up, UART_SCR, scratch);
808
809 if (status1 == 0xa5 && status2 == 0x5a)
810 up->port.type = PORT_16450;
811}
812
813static int broken_efr(struct uart_8250_port *up)
814{
815 /*
816 * Exar ST16C2550 "A2" devices incorrectly detect as
817 * having an EFR, and report an ID of 0x0201. See
818 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
819 */
820 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
821 return 1;
822
823 return 0;
824}
825
826/*
827 * We know that the chip has FIFOs. Does it have an EFR? The
828 * EFR is located in the same register position as the IIR and
829 * we know the top two bits of the IIR are currently set. The
830 * EFR should contain zero. Try to read the EFR.
831 */
832static void autoconfig_16550a(struct uart_8250_port *up)
833{
834 unsigned char status1, status2;
835 unsigned int iersave;
836
837 up->port.type = PORT_16550A;
838 up->capabilities |= UART_CAP_FIFO;
839
840 /*
841 * Check for presence of the EFR when DLAB is set.
842 * Only ST16C650V1 UARTs pass this test.
843 */
844 serial_outp(up, UART_LCR, UART_LCR_DLAB);
845 if (serial_in(up, UART_EFR) == 0) {
846 serial_outp(up, UART_EFR, 0xA8);
847 if (serial_in(up, UART_EFR) != 0) {
848 DEBUG_AUTOCONF("EFRv1 ");
849 up->port.type = PORT_16650;
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
851 } else {
852 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
853 }
854 serial_outp(up, UART_EFR, 0);
855 return;
856 }
857
858 /*
859 * Maybe it requires 0xbf to be written to the LCR.
860 * (other ST16C650V2 UARTs, TI16C752A, etc)
861 */
862 serial_outp(up, UART_LCR, 0xBF);
863 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
864 DEBUG_AUTOCONF("EFRv2 ");
865 autoconfig_has_efr(up);
866 return;
867 }
868
869 /*
870 * Check for a National Semiconductor SuperIO chip.
871 * Attempt to switch to bank 2, read the value of the LOOP bit
872 * from EXCR1. Switch back to bank 0, change it in MCR. Then
873 * switch back to bank 2, read it from EXCR1 again and check
874 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 875 */
876 serial_outp(up, UART_LCR, 0);
877 status1 = serial_in(up, UART_MCR);
878 serial_outp(up, UART_LCR, 0xE0);
879 status2 = serial_in(up, 0x02); /* EXCR1 */
880
881 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
882 serial_outp(up, UART_LCR, 0);
883 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
884 serial_outp(up, UART_LCR, 0xE0);
885 status2 = serial_in(up, 0x02); /* EXCR1 */
886 serial_outp(up, UART_LCR, 0);
887 serial_outp(up, UART_MCR, status1);
888
889 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 890 unsigned short quot;
891
1da177e4 892 serial_outp(up, UART_LCR, 0xE0);
857dde2e 893
b32b19b8 894 quot = serial_dl_read(up);
857dde2e
DW		 895 quot <<= 3;
896
b5b82df6 897 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 898 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
899 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
900 serial_outp(up, 0x04, status1);
bd71c182 901
b32b19b8 902 serial_dl_write(up, quot);
857dde2e 903
1da177e4 904 serial_outp(up, UART_LCR, 0);
1da177e4 905
857dde2e 906 up->port.uartclk = 921600*16;
1da177e4
LT		 907 up->port.type = PORT_NS16550A;
908 up->capabilities |= UART_NATSEMI;
909 return;
910 }
911 }
912
913 /*
914 * No EFR. Try to detect a TI16750, which only sets bit 5 of
915 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
916 * Try setting it with and without DLAB set. Cheap clones
917 * set bit 5 without DLAB set.
918 */
919 serial_outp(up, UART_LCR, 0);
920 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
921 status1 = serial_in(up, UART_IIR) >> 5;
922 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
923 serial_outp(up, UART_LCR, UART_LCR_DLAB);
924 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
925 status2 = serial_in(up, UART_IIR) >> 5;
926 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
927 serial_outp(up, UART_LCR, 0);
928
929 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
930
931 if (status1 == 6 && status2 == 7) {
932 up->port.type = PORT_16750;
933 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
934 return;
935 }
936
937 /*
938 * Try writing and reading the UART_IER_UUE bit (b6).
939 * If it works, this is probably one of the Xscale platform's
940 * internal UARTs.
941 * We're going to explicitly set the UUE bit to 0 before
942 * trying to write and read a 1 just to make sure it's not
943 * already a 1 and maybe locked there before we even start start.
944 */
945 iersave = serial_in(up, UART_IER);
946 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
947 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
948 /*
949 * OK it's in a known zero state, try writing and reading
950 * without disturbing the current state of the other bits.
951 */
952 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
953 if (serial_in(up, UART_IER) & UART_IER_UUE) {
954 /*
955 * It's an Xscale.
956 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
957 */
958 DEBUG_AUTOCONF("Xscale ");
959 up->port.type = PORT_XSCALE;
960 up->capabilities |= UART_CAP_UUE;
961 return;
962 }
963 } else {
964 /*
965 * If we got here we couldn't force the IER_UUE bit to 0.
966 * Log it and continue.
967 */
968 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
969 }
970 serial_outp(up, UART_IER, iersave);
971}
972
973/*
974 * This routine is called by rs_init() to initialize a specific serial
975 * port. It determines what type of UART chip this serial port is
976 * using: 8250, 16450, 16550, 16550A. The important question is
977 * whether or not this UART is a 16550A or not, since this will
978 * determine whether or not we can use its FIFO features or not.
979 */
980static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
981{
982 unsigned char status1, scratch, scratch2, scratch3;
983 unsigned char save_lcr, save_mcr;
984 unsigned long flags;
985
986 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
987 return;
988
989 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
990 up->port.line, up->port.iobase, up->port.membase);
991
992 /*
993 * We really do need global IRQs disabled here - we're going to
994 * be frobbing the chips IRQ enable register to see if it exists.
995 */
996 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 997
998 up->capabilities = 0;
4ba5e35d 999 up->bugs = 0;
1da177e4
LT		 1000
1001 if (!(up->port.flags & UPF_BUGGY_UART)) {
1002 /*
1003 * Do a simple existence test first; if we fail this,
1004 * there's no point trying anything else.
bd71c182 1005 *
1da177e4
LT		 1006 * 0x80 is used as a nonsense port to prevent against
1007 * false positives due to ISA bus float. The
1008 * assumption is that 0x80 is a non-existent port;
1009 * which should be safe since include/asm/io.h also
1010 * makes this assumption.
1011 *
1012 * Note: this is safe as long as MCR bit 4 is clear
1013 * and the device is in "PC" mode.
1014 */
1015 scratch = serial_inp(up, UART_IER);
1016 serial_outp(up, UART_IER, 0);
1017#ifdef __i386__
1018 outb(0xff, 0x080);
1019#endif
48212008
TH		 1020 /*
1021 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1022 * 16C754B) allow only to modify them if an EFR bit is set.
1023 */
1024 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1025 serial_outp(up, UART_IER, 0x0F);
1026#ifdef __i386__
1027 outb(0, 0x080);
1028#endif
48212008 1029 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1030 serial_outp(up, UART_IER, scratch);
1031 if (scratch2 != 0 || scratch3 != 0x0F) {
1032 /*
1033 * We failed; there's nothing here
1034 */
1035 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1036 scratch2, scratch3);
1037 goto out;
1038 }
1039 }
1040
1041 save_mcr = serial_in(up, UART_MCR);
1042 save_lcr = serial_in(up, UART_LCR);
1043
bd71c182 1044 /*
1da177e4
LT		 1045 * Check to see if a UART is really there. Certain broken
1046 * internal modems based on the Rockwell chipset fail this
1047 * test, because they apparently don't implement the loopback
1048 * test mode. So this test is skipped on the COM 1 through
1049 * COM 4 ports. This *should* be safe, since no board
1050 * manufacturer would be stupid enough to design a board
1051 * that conflicts with COM 1-4 --- we hope!
1052 */
1053 if (!(up->port.flags & UPF_SKIP_TEST)) {
1054 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1055 status1 = serial_inp(up, UART_MSR) & 0xF0;
1056 serial_outp(up, UART_MCR, save_mcr);
1057 if (status1 != 0x90) {
1058 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1059 status1);
1060 goto out;
1061 }
1062 }
1063
1064 /*
1065 * We're pretty sure there's a port here. Lets find out what
1066 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1067 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1068 * determines what we test for next.
1069 *
1070 * We also initialise the EFR (if any) to zero for later. The
1071 * EFR occupies the same register location as the FCR and IIR.
1072 */
1073 serial_outp(up, UART_LCR, 0xBF);
1074 serial_outp(up, UART_EFR, 0);
1075 serial_outp(up, UART_LCR, 0);
1076
1077 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1078 scratch = serial_in(up, UART_IIR) >> 6;
1079
1080 DEBUG_AUTOCONF("iir=%d ", scratch);
1081
1082 switch (scratch) {
1083 case 0:
1084 autoconfig_8250(up);
1085 break;
1086 case 1:
1087 up->port.type = PORT_UNKNOWN;
1088 break;
1089 case 2:
1090 up->port.type = PORT_16550;
1091 break;
1092 case 3:
1093 autoconfig_16550a(up);
1094 break;
1095 }
1096
1097#ifdef CONFIG_SERIAL_8250_RSA
1098 /*
1099 * Only probe for RSA ports if we got the region.
1100 */
1101 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1102 int i;
1103
1104 for (i = 0 ; i < probe_rsa_count; ++i) {
1105 if (probe_rsa[i] == up->port.iobase &&
1106 __enable_rsa(up)) {
1107 up->port.type = PORT_RSA;
1108 break;
1109 }
1110 }
1111 }
1112#endif
21c614a7
PA		 1113
1114#ifdef CONFIG_SERIAL_8250_AU1X00
1115 /* if access method is AU, it is a 16550 with a quirk */
1116 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1117 up->bugs |= UART_BUG_NOMSR;
1118#endif
1119
1da177e4
LT		 1120 serial_outp(up, UART_LCR, save_lcr);
1121
1122 if (up->capabilities != uart_config[up->port.type].flags) {
1123 printk(KERN_WARNING
1124 "ttyS%d: detected caps %08x should be %08x\n",
1125 up->port.line, up->capabilities,
1126 uart_config[up->port.type].flags);
1127 }
1128
1129 up->port.fifosize = uart_config[up->port.type].fifo_size;
1130 up->capabilities = uart_config[up->port.type].flags;
1131 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1132
1133 if (up->port.type == PORT_UNKNOWN)
1134 goto out;
1135
1136 /*
1137 * Reset the UART.
1138 */
1139#ifdef CONFIG_SERIAL_8250_RSA
1140 if (up->port.type == PORT_RSA)
1141 serial_outp(up, UART_RSA_FRR, 0);
1142#endif
1143 serial_outp(up, UART_MCR, save_mcr);
1144 serial8250_clear_fifos(up);
40b36daa 1145 serial_in(up, UART_RX);
5c8c755c
LB		 1146 if (up->capabilities & UART_CAP_UUE)
1147 serial_outp(up, UART_IER, UART_IER_UUE);
1148 else
1149 serial_outp(up, UART_IER, 0);
1da177e4 1150
bd71c182 1151 out:
1da177e4 1152 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1153 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1154}
1155
1156static void autoconfig_irq(struct uart_8250_port *up)
1157{
1158 unsigned char save_mcr, save_ier;
1159 unsigned char save_ICP = 0;
1160 unsigned int ICP = 0;
1161 unsigned long irqs;
1162 int irq;
1163
1164 if (up->port.flags & UPF_FOURPORT) {
1165 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1166 save_ICP = inb_p(ICP);
1167 outb_p(0x80, ICP);
1168 (void) inb_p(ICP);
1169 }
1170
1171 /* forget possible initially masked and pending IRQ */
1172 probe_irq_off(probe_irq_on());
1173 save_mcr = serial_inp(up, UART_MCR);
1174 save_ier = serial_inp(up, UART_IER);
1175 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1176
1da177e4
LT		 1177 irqs = probe_irq_on();
1178 serial_outp(up, UART_MCR, 0);
1179 udelay (10);
1180 if (up->port.flags & UPF_FOURPORT) {
1181 serial_outp(up, UART_MCR,
1182 UART_MCR_DTR | UART_MCR_RTS);
1183 } else {
1184 serial_outp(up, UART_MCR,
1185 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1186 }
1187 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1188 (void)serial_inp(up, UART_LSR);
1189 (void)serial_inp(up, UART_RX);
1190 (void)serial_inp(up, UART_IIR);
1191 (void)serial_inp(up, UART_MSR);
1192 serial_outp(up, UART_TX, 0xFF);
1193 udelay (20);
1194 irq = probe_irq_off(irqs);
1195
1196 serial_outp(up, UART_MCR, save_mcr);
1197 serial_outp(up, UART_IER, save_ier);
1198
1199 if (up->port.flags & UPF_FOURPORT)
1200 outb_p(save_ICP, ICP);
1201
1202 up->port.irq = (irq > 0) ? irq : 0;
1203}
1204
e763b90c
RK		 1205static inline void __stop_tx(struct uart_8250_port *p)
1206{
1207 if (p->ier & UART_IER_THRI) {
1208 p->ier &= ~UART_IER_THRI;
1209 serial_out(p, UART_IER, p->ier);
1210 }
1211}
1212
b129a8cc 1213static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1214{
1215 struct uart_8250_port *up = (struct uart_8250_port *)port;
1216
e763b90c 1217 __stop_tx(up);
1da177e4
LT		 1218
1219 /*
e763b90c 1220 * We really want to stop the transmitter from sending.
1da177e4 1221 */
e763b90c 1222 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1223 up->acr |= UART_ACR_TXDIS;
1224 serial_icr_write(up, UART_ACR, up->acr);
1225 }
1226}
1227
55d3b282
RK		 1228static void transmit_chars(struct uart_8250_port *up);
1229
b129a8cc 1230static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1231{
1232 struct uart_8250_port *up = (struct uart_8250_port *)port;
1233
1234 if (!(up->ier & UART_IER_THRI)) {
1235 up->ier |= UART_IER_THRI;
1236 serial_out(up, UART_IER, up->ier);
55d3b282 1237
67f7654e 1238 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1239 unsigned char lsr, iir;
1240 lsr = serial_in(up, UART_LSR);
bd71c182
TK		 1241 iir = serial_in(up, UART_IIR) & 0x0f;
1242 if ((up->port.type == PORT_RM9000) ?
1243 (lsr & UART_LSR_THRE &&
1244 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1245 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
55d3b282
RK		 1246 transmit_chars(up);
1247 }
1da177e4 1248 }
e763b90c 1249
1da177e4 1250 /*
e763b90c 1251 * Re-enable the transmitter if we disabled it.
1da177e4 1252 */
e763b90c 1253 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1254 up->acr &= ~UART_ACR_TXDIS;
1255 serial_icr_write(up, UART_ACR, up->acr);
1256 }
1257}
1258
1259static void serial8250_stop_rx(struct uart_port *port)
1260{
1261 struct uart_8250_port *up = (struct uart_8250_port *)port;
1262
1263 up->ier &= ~UART_IER_RLSI;
1264 up->port.read_status_mask &= ~UART_LSR_DR;
1265 serial_out(up, UART_IER, up->ier);
1266}
1267
1268static void serial8250_enable_ms(struct uart_port *port)
1269{
1270 struct uart_8250_port *up = (struct uart_8250_port *)port;
1271
21c614a7
PA		 1272 /* no MSR capabilities */
1273 if (up->bugs & UART_BUG_NOMSR)
1274 return;
1275
1da177e4
LT		 1276 up->ier |= UART_IER_MSI;
1277 serial_out(up, UART_IER, up->ier);
1278}
1279
ea8874dc 1280static void
cc79aa9d 1281receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4
LT		 1282{
1283 struct tty_struct *tty = up->port.info->tty;
1284 unsigned char ch, lsr = *status;
1285 int max_count = 256;
1286 char flag;
1287
1288 do {
1da177e4
LT		 1289 ch = serial_inp(up, UART_RX);
1290 flag = TTY_NORMAL;
1291 up->port.icount.rx++;
1292
1293#ifdef CONFIG_SERIAL_8250_CONSOLE
1294 /*
1295 * Recover the break flag from console xmit
1296 */
1297 if (up->port.line == up->port.cons->index) {
1298 lsr |= up->lsr_break_flag;
1299 up->lsr_break_flag = 0;
1300 }
1301#endif
1302
1303 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1304 UART_LSR_FE | UART_LSR_OE))) {
1305 /*
1306 * For statistics only
1307 */
1308 if (lsr & UART_LSR_BI) {
1309 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1310 up->port.icount.brk++;
1311 /*
1312 * We do the SysRQ and SAK checking
1313 * here because otherwise the break
1314 * may get masked by ignore_status_mask
1315 * or read_status_mask.
1316 */
1317 if (uart_handle_break(&up->port))
1318 goto ignore_char;
1319 } else if (lsr & UART_LSR_PE)
1320 up->port.icount.parity++;
1321 else if (lsr & UART_LSR_FE)
1322 up->port.icount.frame++;
1323 if (lsr & UART_LSR_OE)
1324 up->port.icount.overrun++;
1325
1326 /*
23907eb8 1327 * Mask off conditions which should be ignored.
1da177e4
LT		 1328 */
1329 lsr &= up->port.read_status_mask;
1330
1331 if (lsr & UART_LSR_BI) {
1332 DEBUG_INTR("handling break....");
1333 flag = TTY_BREAK;
1334 } else if (lsr & UART_LSR_PE)
1335 flag = TTY_PARITY;
1336 else if (lsr & UART_LSR_FE)
1337 flag = TTY_FRAME;
1338 }
7d12e780 1339 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1340 goto ignore_char;
05ab3014
RK		 1341
1342 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1343
1da177e4
LT		 1344 ignore_char:
1345 lsr = serial_inp(up, UART_LSR);
1346 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1347 spin_unlock(&up->port.lock);
1348 tty_flip_buffer_push(tty);
1349 spin_lock(&up->port.lock);
1350 *status = lsr;
1351}
1352
ea8874dc 1353static void transmit_chars(struct uart_8250_port *up)
1da177e4
LT		 1354{
1355 struct circ_buf *xmit = &up->port.info->xmit;
1356 int count;
1357
1358 if (up->port.x_char) {
1359 serial_outp(up, UART_TX, up->port.x_char);
1360 up->port.icount.tx++;
1361 up->port.x_char = 0;
1362 return;
1363 }
b129a8cc
RK		 1364 if (uart_tx_stopped(&up->port)) {
1365 serial8250_stop_tx(&up->port);
1366 return;
1367 }
1368 if (uart_circ_empty(xmit)) {
e763b90c 1369 __stop_tx(up);
1da177e4
LT		 1370 return;
1371 }
1372
1373 count = up->tx_loadsz;
1374 do {
1375 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1376 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1377 up->port.icount.tx++;
1378 if (uart_circ_empty(xmit))
1379 break;
1380 } while (--count > 0);
1381
1382 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1383 uart_write_wakeup(&up->port);
1384
1385 DEBUG_INTR("THRE...");
1386
1387 if (uart_circ_empty(xmit))
e763b90c 1388 __stop_tx(up);
1da177e4
LT		 1389}
1390
2af7cd68 1391static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1392{
2af7cd68
RK		 1393 unsigned int status = serial_in(up, UART_MSR);
1394
fdc30b3d
TI		 1395 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1396 up->port.info != NULL) {
2af7cd68
RK		 1397 if (status & UART_MSR_TERI)
1398 up->port.icount.rng++;
1399 if (status & UART_MSR_DDSR)
1400 up->port.icount.dsr++;
1401 if (status & UART_MSR_DDCD)
1402 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1403 if (status & UART_MSR_DCTS)
1404 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1405
1406 wake_up_interruptible(&up->port.info->delta_msr_wait);
1407 }
1da177e4 1408
2af7cd68 1409 return status;
1da177e4
LT		 1410}
1411
1412/*
1413 * This handles the interrupt from one port.
1414 */
1415static inline void
7d12e780 1416serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1417{
45e24601 1418 unsigned int status;
4bf3631c 1419 unsigned long flags;
45e24601 1420
4bf3631c 1421 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1422
1423 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1424
1425 DEBUG_INTR("status = %x...", status);
1426
1427 if (status & UART_LSR_DR)
7d12e780 1428 receive_chars(up, &status);
1da177e4
LT		 1429 check_modem_status(up);
1430 if (status & UART_LSR_THRE)
1431 transmit_chars(up);
45e24601 1432
4bf3631c 1433 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1434}
1435
1436/*
1437 * This is the serial driver's interrupt routine.
1438 *
1439 * Arjan thinks the old way was overly complex, so it got simplified.
1440 * Alan disagrees, saying that need the complexity to handle the weird
1441 * nature of ISA shared interrupts. (This is a special exception.)
1442 *
1443 * In order to handle ISA shared interrupts properly, we need to check
1444 * that all ports have been serviced, and therefore the ISA interrupt
1445 * line has been de-asserted.
1446 *
1447 * This means we need to loop through all ports. checking that they
1448 * don't have an interrupt pending.
1449 */
7d12e780 1450static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1451{
1452 struct irq_info *i = dev_id;
1453 struct list_head *l, *end = NULL;
1454 int pass_counter = 0, handled = 0;
1455
1456 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1457
1458 spin_lock(&i->lock);
1459
1460 l = i->head;
1461 do {
1462 struct uart_8250_port *up;
1463 unsigned int iir;
1464
1465 up = list_entry(l, struct uart_8250_port, list);
1466
1467 iir = serial_in(up, UART_IIR);
1468 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1469 serial8250_handle_port(up);
1da177e4
LT		 1470
1471 handled = 1;
1472
beab697a
MSJ		 1473 end = NULL;
1474 } else if (up->port.iotype == UPIO_DWAPB &&
1475 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1476 /* The DesignWare APB UART has an Busy Detect (0x07)
1477 * interrupt meaning an LCR write attempt occured while the
1478 * UART was busy. The interrupt must be cleared by reading
1479 * the UART status register (USR) and the LCR re-written. */
1480 unsigned int status;
1481 status = *(volatile u32 *)up->port.private_data;
1482 serial_out(up, UART_LCR, up->lcr);
1483
1484 handled = 1;
1485
1da177e4
LT		 1486 end = NULL;
1487 } else if (end == NULL)
1488 end = l;
1489
1490 l = l->next;
1491
1492 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1493 /* If we hit this, we're dead. */
1494 printk(KERN_ERR "serial8250: too much work for "
1495 "irq%d\n", irq);
1496 break;
1497 }
1498 } while (l != end);
1499
1500 spin_unlock(&i->lock);
1501
1502 DEBUG_INTR("end.\n");
1503
1504 return IRQ_RETVAL(handled);
1505}
1506
1507/*
1508 * To support ISA shared interrupts, we need to have one interrupt
1509 * handler that ensures that the IRQ line has been deasserted
1510 * before returning. Failing to do this will result in the IRQ
1511 * line being stuck active, and, since ISA irqs are edge triggered,
1512 * no more IRQs will be seen.
1513 */
1514static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1515{
1516 spin_lock_irq(&i->lock);
1517
1518 if (!list_empty(i->head)) {
1519 if (i->head == &up->list)
1520 i->head = i->head->next;
1521 list_del(&up->list);
1522 } else {
1523 BUG_ON(i->head != &up->list);
1524 i->head = NULL;
1525 }
1526
1527 spin_unlock_irq(&i->lock);
1528}
1529
1530static int serial_link_irq_chain(struct uart_8250_port *up)
1531{
1532 struct irq_info *i = irq_lists + up->port.irq;
40663cc7 1533 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4
LT		 1534
1535 spin_lock_irq(&i->lock);
1536
1537 if (i->head) {
1538 list_add(&up->list, i->head);
1539 spin_unlock_irq(&i->lock);
1540
1541 ret = 0;
1542 } else {
1543 INIT_LIST_HEAD(&up->list);
1544 i->head = &up->list;
1545 spin_unlock_irq(&i->lock);
1546
1547 ret = request_irq(up->port.irq, serial8250_interrupt,
1548 irq_flags, "serial", i);
1549 if (ret < 0)
1550 serial_do_unlink(i, up);
1551 }
1552
1553 return ret;
1554}
1555
1556static void serial_unlink_irq_chain(struct uart_8250_port *up)
1557{
1558 struct irq_info *i = irq_lists + up->port.irq;
1559
1560 BUG_ON(i->head == NULL);
1561
1562 if (list_empty(i->head))
1563 free_irq(up->port.irq, i);
1564
1565 serial_do_unlink(i, up);
1566}
1567
40b36daa
AW		 1568/* Base timer interval for polling */
1569static inline int poll_timeout(int timeout)
1570{
1571 return timeout > 6 ? (timeout / 2 - 2) : 1;
1572}
1573
1da177e4
LT		 1574/*
1575 * This function is used to handle ports that do not have an
1576 * interrupt. This doesn't work very well for 16450's, but gives
1577 * barely passable results for a 16550A. (Although at the expense
1578 * of much CPU overhead).
1579 */
1580static void serial8250_timeout(unsigned long data)
1581{
1582 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1583 unsigned int iir;
1584
1585 iir = serial_in(up, UART_IIR);
45e24601 1586 if (!(iir & UART_IIR_NO_INT))
7d12e780 1587 serial8250_handle_port(up);
40b36daa
AW		 1588 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1589}
1590
1591static void serial8250_backup_timeout(unsigned long data)
1592{
1593 struct uart_8250_port *up = (struct uart_8250_port *)data;
1594 unsigned int iir, ier = 0;
1595
1596 /*
1597 * Must disable interrupts or else we risk racing with the interrupt
1598 * based handler.
1599 */
1600 if (is_real_interrupt(up->port.irq)) {
1601 ier = serial_in(up, UART_IER);
1602 serial_out(up, UART_IER, 0);
1603 }
1da177e4 1604
40b36daa
AW		 1605 iir = serial_in(up, UART_IIR);
1606
1607 /*
1608 * This should be a safe test for anyone who doesn't trust the
1609 * IIR bits on their UART, but it's specifically designed for
1610 * the "Diva" UART used on the management processor on many HP
1611 * ia64 and parisc boxes.
1612 */
1613 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1614 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1615 (serial_in(up, UART_LSR) & UART_LSR_THRE)) {
1616 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1617 iir |= UART_IIR_THRI;
1618 }
1619
1620 if (!(iir & UART_IIR_NO_INT))
1621 serial8250_handle_port(up);
1622
1623 if (is_real_interrupt(up->port.irq))
1624 serial_out(up, UART_IER, ier);
1625
1626 /* Standard timer interval plus 0.2s to keep the port running */
1627 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout) + HZ/5);
1da177e4
LT		 1628}
1629
1630static unsigned int serial8250_tx_empty(struct uart_port *port)
1631{
1632 struct uart_8250_port *up = (struct uart_8250_port *)port;
1633 unsigned long flags;
1634 unsigned int ret;
1635
1636 spin_lock_irqsave(&up->port.lock, flags);
1637 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1638 spin_unlock_irqrestore(&up->port.lock, flags);
1639
1640 return ret;
1641}
1642
1643static unsigned int serial8250_get_mctrl(struct uart_port *port)
1644{
1645 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1646 unsigned int status;
1da177e4
LT		 1647 unsigned int ret;
1648
2af7cd68 1649 status = check_modem_status(up);
1da177e4
LT		 1650
1651 ret = 0;
1652 if (status & UART_MSR_DCD)
1653 ret |= TIOCM_CAR;
1654 if (status & UART_MSR_RI)
1655 ret |= TIOCM_RNG;
1656 if (status & UART_MSR_DSR)
1657 ret |= TIOCM_DSR;
1658 if (status & UART_MSR_CTS)
1659 ret |= TIOCM_CTS;
1660 return ret;
1661}
1662
1663static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1664{
1665 struct uart_8250_port *up = (struct uart_8250_port *)port;
1666 unsigned char mcr = 0;
1667
1668 if (mctrl & TIOCM_RTS)
1669 mcr |= UART_MCR_RTS;
1670 if (mctrl & TIOCM_DTR)
1671 mcr |= UART_MCR_DTR;
1672 if (mctrl & TIOCM_OUT1)
1673 mcr |= UART_MCR_OUT1;
1674 if (mctrl & TIOCM_OUT2)
1675 mcr |= UART_MCR_OUT2;
1676 if (mctrl & TIOCM_LOOP)
1677 mcr |= UART_MCR_LOOP;
1678
1679 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1680
1681 serial_out(up, UART_MCR, mcr);
1682}
1683
1684static void serial8250_break_ctl(struct uart_port *port, int break_state)
1685{
1686 struct uart_8250_port *up = (struct uart_8250_port *)port;
1687 unsigned long flags;
1688
1689 spin_lock_irqsave(&up->port.lock, flags);
1690 if (break_state == -1)
1691 up->lcr |= UART_LCR_SBC;
1692 else
1693 up->lcr &= ~UART_LCR_SBC;
1694 serial_out(up, UART_LCR, up->lcr);
1695 spin_unlock_irqrestore(&up->port.lock, flags);
1696}
1697
40b36daa
AW		 1698#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1699
1700/*
1701 * Wait for transmitter & holding register to empty
1702 */
1703static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1704{
1705 unsigned int status, tmout = 10000;
1706
1707 /* Wait up to 10ms for the character(s) to be sent. */
1708 do {
1709 status = serial_in(up, UART_LSR);
1710
1711 if (status & UART_LSR_BI)
1712 up->lsr_break_flag = UART_LSR_BI;
1713
1714 if (--tmout == 0)
1715 break;
1716 udelay(1);
1717 } while ((status & bits) != bits);
1718
1719 /* Wait up to 1s for flow control if necessary */
1720 if (up->port.flags & UPF_CONS_FLOW) {
1721 tmout = 1000000;
1722 while (!(serial_in(up, UART_MSR) & UART_MSR_CTS) && --tmout) {
1723 udelay(1);
1724 touch_nmi_watchdog();
1725 }
1726 }
1727}
1728
1da177e4
LT		 1729static int serial8250_startup(struct uart_port *port)
1730{
1731 struct uart_8250_port *up = (struct uart_8250_port *)port;
1732 unsigned long flags;
55d3b282 1733 unsigned char lsr, iir;
1da177e4
LT		 1734 int retval;
1735
1736 up->capabilities = uart_config[up->port.type].flags;
1737 up->mcr = 0;
1738
1739 if (up->port.type == PORT_16C950) {
1740 /* Wake up and initialize UART */
1741 up->acr = 0;
1742 serial_outp(up, UART_LCR, 0xBF);
1743 serial_outp(up, UART_EFR, UART_EFR_ECB);
1744 serial_outp(up, UART_IER, 0);
1745 serial_outp(up, UART_LCR, 0);
1746 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1747 serial_outp(up, UART_LCR, 0xBF);
1748 serial_outp(up, UART_EFR, UART_EFR_ECB);
1749 serial_outp(up, UART_LCR, 0);
1750 }
1751
1752#ifdef CONFIG_SERIAL_8250_RSA
1753 /*
1754 * If this is an RSA port, see if we can kick it up to the
1755 * higher speed clock.
1756 */
1757 enable_rsa(up);
1758#endif
1759
1760 /*
1761 * Clear the FIFO buffers and disable them.
7f927fcc 1762 * (they will be reenabled in set_termios())
1da177e4
LT		 1763 */
1764 serial8250_clear_fifos(up);
1765
1766 /*
1767 * Clear the interrupt registers.
1768 */
1769 (void) serial_inp(up, UART_LSR);
1770 (void) serial_inp(up, UART_RX);
1771 (void) serial_inp(up, UART_IIR);
1772 (void) serial_inp(up, UART_MSR);
1773
1774 /*
1775 * At this point, there's no way the LSR could still be 0xff;
1776 * if it is, then bail out, because there's likely no UART
1777 * here.
1778 */
1779 if (!(up->port.flags & UPF_BUGGY_UART) &&
1780 (serial_inp(up, UART_LSR) == 0xff)) {
1781 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1782 return -ENODEV;
1783 }
1784
1785 /*
1786 * For a XR16C850, we need to set the trigger levels
1787 */
1788 if (up->port.type == PORT_16850) {
1789 unsigned char fctr;
1790
1791 serial_outp(up, UART_LCR, 0xbf);
1792
1793 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1794 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1795 serial_outp(up, UART_TRG, UART_TRG_96);
1796 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1797 serial_outp(up, UART_TRG, UART_TRG_96);
1798
1799 serial_outp(up, UART_LCR, 0);
1800 }
1801
40b36daa
AW		 1802 if (is_real_interrupt(up->port.irq)) {
1803 /*
1804 * Test for UARTs that do not reassert THRE when the
1805 * transmitter is idle and the interrupt has already
1806 * been cleared. Real 16550s should always reassert
1807 * this interrupt whenever the transmitter is idle and
1808 * the interrupt is enabled. Delays are necessary to
1809 * allow register changes to become visible.
1810 */
1811 spin_lock_irqsave(&up->port.lock, flags);
1812
1813 wait_for_xmitr(up, UART_LSR_THRE);
1814 serial_out_sync(up, UART_IER, UART_IER_THRI);
1815 udelay(1); /* allow THRE to set */
1816 serial_in(up, UART_IIR);
1817 serial_out(up, UART_IER, 0);
1818 serial_out_sync(up, UART_IER, UART_IER_THRI);
1819 udelay(1); /* allow a working UART time to re-assert THRE */
1820 iir = serial_in(up, UART_IIR);
1821 serial_out(up, UART_IER, 0);
1822
1823 spin_unlock_irqrestore(&up->port.lock, flags);
1824
1825 /*
1826 * If the interrupt is not reasserted, setup a timer to
1827 * kick the UART on a regular basis.
1828 */
1829 if (iir & UART_IIR_NO_INT) {
1830 pr_debug("ttyS%d - using backup timer\n", port->line);
1831 up->timer.function = serial8250_backup_timeout;
1832 up->timer.data = (unsigned long)up;
1833 mod_timer(&up->timer, jiffies +
1834 poll_timeout(up->port.timeout) + HZ/5);
1835 }
1836 }
1837
1da177e4
LT		 1838 /*
1839 * If the "interrupt" for this port doesn't correspond with any
1840 * hardware interrupt, we use a timer-based system. The original
1841 * driver used to do this with IRQ0.
1842 */
1843 if (!is_real_interrupt(up->port.irq)) {
1da177e4 1844 up->timer.data = (unsigned long)up;
40b36daa 1845 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 1846 } else {
1847 retval = serial_link_irq_chain(up);
1848 if (retval)
1849 return retval;
1850 }
1851
1852 /*
1853 * Now, initialize the UART
1854 */
1855 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1856
1857 spin_lock_irqsave(&up->port.lock, flags);
1858 if (up->port.flags & UPF_FOURPORT) {
1859 if (!is_real_interrupt(up->port.irq))
1860 up->port.mctrl |= TIOCM_OUT1;
1861 } else
1862 /*
1863 * Most PC uarts need OUT2 raised to enable interrupts.
1864 */
1865 if (is_real_interrupt(up->port.irq))
1866 up->port.mctrl |= TIOCM_OUT2;
1867
1868 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1869
1870 /*
1871 * Do a quick test to see if we receive an
1872 * interrupt when we enable the TX irq.
1873 */
1874 serial_outp(up, UART_IER, UART_IER_THRI);
1875 lsr = serial_in(up, UART_LSR);
1876 iir = serial_in(up, UART_IIR);
1877 serial_outp(up, UART_IER, 0);
1878
1879 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1880 if (!(up->bugs & UART_BUG_TXEN)) {
1881 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1882 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1883 port->line);
1884 }
1885 } else {
67f7654e 1886 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1887 }
1888
1da177e4
LT		 1889 spin_unlock_irqrestore(&up->port.lock, flags);
1890
1891 /*
1892 * Finally, enable interrupts. Note: Modem status interrupts
1893 * are set via set_termios(), which will be occurring imminently
1894 * anyway, so we don't enable them here.
1895 */
1896 up->ier = UART_IER_RLSI | UART_IER_RDI;
1897 serial_outp(up, UART_IER, up->ier);
1898
1899 if (up->port.flags & UPF_FOURPORT) {
1900 unsigned int icp;
1901 /*
1902 * Enable interrupts on the AST Fourport board
1903 */
1904 icp = (up->port.iobase & 0xfe0) | 0x01f;
1905 outb_p(0x80, icp);
1906 (void) inb_p(icp);
1907 }
1908
1909 /*
1910 * And clear the interrupt registers again for luck.
1911 */
1912 (void) serial_inp(up, UART_LSR);
1913 (void) serial_inp(up, UART_RX);
1914 (void) serial_inp(up, UART_IIR);
1915 (void) serial_inp(up, UART_MSR);
1916
1917 return 0;
1918}
1919
1920static void serial8250_shutdown(struct uart_port *port)
1921{
1922 struct uart_8250_port *up = (struct uart_8250_port *)port;
1923 unsigned long flags;
1924
1925 /*
1926 * Disable interrupts from this port
1927 */
1928 up->ier = 0;
1929 serial_outp(up, UART_IER, 0);
1930
1931 spin_lock_irqsave(&up->port.lock, flags);
1932 if (up->port.flags & UPF_FOURPORT) {
1933 /* reset interrupts on the AST Fourport board */
1934 inb((up->port.iobase & 0xfe0) | 0x1f);
1935 up->port.mctrl |= TIOCM_OUT1;
1936 } else
1937 up->port.mctrl &= ~TIOCM_OUT2;
1938
1939 serial8250_set_mctrl(&up->port, up->port.mctrl);
1940 spin_unlock_irqrestore(&up->port.lock, flags);
1941
1942 /*
1943 * Disable break condition and FIFOs
1944 */
1945 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1946 serial8250_clear_fifos(up);
1947
1948#ifdef CONFIG_SERIAL_8250_RSA
1949 /*
1950 * Reset the RSA board back to 115kbps compat mode.
1951 */
1952 disable_rsa(up);
1953#endif
1954
1955 /*
1956 * Read data port to reset things, and then unlink from
1957 * the IRQ chain.
1958 */
1959 (void) serial_in(up, UART_RX);
1960
40b36daa
AW		 1961 del_timer_sync(&up->timer);
1962 up->timer.function = serial8250_timeout;
1963 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 1964 serial_unlink_irq_chain(up);
1965}
1966
1967static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1968{
1969 unsigned int quot;
1970
1971 /*
1972 * Handle magic divisors for baud rates above baud_base on
1973 * SMSC SuperIO chips.
1974 */
1975 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1976 baud == (port->uartclk/4))
1977 quot = 0x8001;
1978 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1979 baud == (port->uartclk/8))
1980 quot = 0x8002;
1981 else
1982 quot = uart_get_divisor(port, baud);
1983
1984 return quot;
1985}
1986
1987static void
606d099c
AC		 1988serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
1989 struct ktermios *old)
1da177e4
LT		 1990{
1991 struct uart_8250_port *up = (struct uart_8250_port *)port;
1992 unsigned char cval, fcr = 0;
1993 unsigned long flags;
1994 unsigned int baud, quot;
1995
1996 switch (termios->c_cflag & CSIZE) {
1997 case CS5:
0a8b80c5 1998 cval = UART_LCR_WLEN5;
1da177e4
LT		 1999 break;
2000 case CS6:
0a8b80c5 2001 cval = UART_LCR_WLEN6;
1da177e4
LT		 2002 break;
2003 case CS7:
0a8b80c5 2004 cval = UART_LCR_WLEN7;
1da177e4
LT		 2005 break;
2006 default:
2007 case CS8:
0a8b80c5 2008 cval = UART_LCR_WLEN8;
1da177e4
LT		 2009 break;
2010 }
2011
2012 if (termios->c_cflag & CSTOPB)
0a8b80c5 2013 cval |= UART_LCR_STOP;
1da177e4
LT		 2014 if (termios->c_cflag & PARENB)
2015 cval |= UART_LCR_PARITY;
2016 if (!(termios->c_cflag & PARODD))
2017 cval |= UART_LCR_EPAR;
2018#ifdef CMSPAR
2019 if (termios->c_cflag & CMSPAR)
2020 cval |= UART_LCR_SPAR;
2021#endif
2022
2023 /*
2024 * Ask the core to calculate the divisor for us.
2025 */
bd71c182 2026 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1da177e4
LT		 2027 quot = serial8250_get_divisor(port, baud);
2028
2029 /*
4ba5e35d 2030 * Oxford Semi 952 rev B workaround
1da177e4 2031 */
4ba5e35d 2032 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 2033 quot ++;
2034
2035 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2036 if (baud < 2400)
2037 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2038 else
2039 fcr = uart_config[up->port.type].fcr;
2040 }
2041
2042 /*
2043 * MCR-based auto flow control. When AFE is enabled, RTS will be
2044 * deasserted when the receive FIFO contains more characters than
2045 * the trigger, or the MCR RTS bit is cleared. In the case where
2046 * the remote UART is not using CTS auto flow control, we must
2047 * have sufficient FIFO entries for the latency of the remote
2048 * UART to respond. IOW, at least 32 bytes of FIFO.
2049 */
2050 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2051 up->mcr &= ~UART_MCR_AFE;
2052 if (termios->c_cflag & CRTSCTS)
2053 up->mcr |= UART_MCR_AFE;
2054 }
2055
2056 /*
2057 * Ok, we're now changing the port state. Do it with
2058 * interrupts disabled.
2059 */
2060 spin_lock_irqsave(&up->port.lock, flags);
2061
2062 /*
2063 * Update the per-port timeout.
2064 */
2065 uart_update_timeout(port, termios->c_cflag, baud);
2066
2067 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2068 if (termios->c_iflag & INPCK)
2069 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2070 if (termios->c_iflag & (BRKINT | PARMRK))
2071 up->port.read_status_mask |= UART_LSR_BI;
2072
2073 /*
2074 * Characteres to ignore
2075 */
2076 up->port.ignore_status_mask = 0;
2077 if (termios->c_iflag & IGNPAR)
2078 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2079 if (termios->c_iflag & IGNBRK) {
2080 up->port.ignore_status_mask |= UART_LSR_BI;
2081 /*
2082 * If we're ignoring parity and break indicators,
2083 * ignore overruns too (for real raw support).
2084 */
2085 if (termios->c_iflag & IGNPAR)
2086 up->port.ignore_status_mask |= UART_LSR_OE;
2087 }
2088
2089 /*
2090 * ignore all characters if CREAD is not set
2091 */
2092 if ((termios->c_cflag & CREAD) == 0)
2093 up->port.ignore_status_mask |= UART_LSR_DR;
2094
2095 /*
2096 * CTS flow control flag and modem status interrupts
2097 */
2098 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2099 if (!(up->bugs & UART_BUG_NOMSR) &&
2100 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2101 up->ier |= UART_IER_MSI;
2102 if (up->capabilities & UART_CAP_UUE)
2103 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2104
2105 serial_out(up, UART_IER, up->ier);
2106
2107 if (up->capabilities & UART_CAP_EFR) {
2108 unsigned char efr = 0;
2109 /*
2110 * TI16C752/Startech hardware flow control. FIXME:
2111 * - TI16C752 requires control thresholds to be set.
2112 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2113 */
2114 if (termios->c_cflag & CRTSCTS)
2115 efr |= UART_EFR_CTS;
2116
2117 serial_outp(up, UART_LCR, 0xBF);
2118 serial_outp(up, UART_EFR, efr);
2119 }
2120
255341c6
JM		 2121#ifdef CONFIG_ARCH_OMAP15XX
2122 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2123 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2124 if (baud == 115200) {
2125 quot = 1;
2126 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2127 } else
2128 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2129 }
2130#endif
2131
1da177e4
LT		 2132 if (up->capabilities & UART_NATSEMI) {
2133 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2134 serial_outp(up, UART_LCR, 0xe0);
2135 } else {
2136 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2137 }
2138
b32b19b8 2139 serial_dl_write(up, quot);
1da177e4
LT		 2140
2141 /*
2142 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2143 * is written without DLAB set, this mode will be disabled.
2144 */
2145 if (up->port.type == PORT_16750)
2146 serial_outp(up, UART_FCR, fcr);
2147
2148 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2149 up->lcr = cval; /* Save LCR */
2150 if (up->port.type != PORT_16750) {
2151 if (fcr & UART_FCR_ENABLE_FIFO) {
2152 /* emulated UARTs (Lucent Venus 167x) need two steps */
2153 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2154 }
2155 serial_outp(up, UART_FCR, fcr); /* set fcr */
2156 }
2157 serial8250_set_mctrl(&up->port, up->port.mctrl);
2158 spin_unlock_irqrestore(&up->port.lock, flags);
2159}
2160
2161static void
2162serial8250_pm(struct uart_port *port, unsigned int state,
2163 unsigned int oldstate)
2164{
2165 struct uart_8250_port *p = (struct uart_8250_port *)port;
2166
2167 serial8250_set_sleep(p, state != 0);
2168
2169 if (p->pm)
2170 p->pm(port, state, oldstate);
2171}
2172
2173/*
2174 * Resource handling.
2175 */
2176static int serial8250_request_std_resource(struct uart_8250_port *up)
2177{
2178 unsigned int size = 8 << up->port.regshift;
2179 int ret = 0;
2180
2181 switch (up->port.iotype) {
85835f44
SS		 2182 case UPIO_AU:
2183 size = 0x100000;
2184 /* fall thru */
0b30d668
SS		 2185 case UPIO_TSI:
2186 case UPIO_MEM32:
1da177e4 2187 case UPIO_MEM:
beab697a 2188 case UPIO_DWAPB:
1da177e4
LT		 2189 if (!up->port.mapbase)
2190 break;
2191
2192 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2193 ret = -EBUSY;
2194 break;
2195 }
2196
2197 if (up->port.flags & UPF_IOREMAP) {
2198 up->port.membase = ioremap(up->port.mapbase, size);
2199 if (!up->port.membase) {
2200 release_mem_region(up->port.mapbase, size);
2201 ret = -ENOMEM;
2202 }
2203 }
2204 break;
2205
2206 case UPIO_HUB6:
2207 case UPIO_PORT:
2208 if (!request_region(up->port.iobase, size, "serial"))
2209 ret = -EBUSY;
2210 break;
2211 }
2212 return ret;
2213}
2214
2215static void serial8250_release_std_resource(struct uart_8250_port *up)
2216{
2217 unsigned int size = 8 << up->port.regshift;
2218
2219 switch (up->port.iotype) {
85835f44
SS		 2220 case UPIO_AU:
2221 size = 0x100000;
2222 /* fall thru */
0b30d668
SS		 2223 case UPIO_TSI:
2224 case UPIO_MEM32:
1da177e4 2225 case UPIO_MEM:
beab697a 2226 case UPIO_DWAPB:
1da177e4
LT		 2227 if (!up->port.mapbase)
2228 break;
2229
2230 if (up->port.flags & UPF_IOREMAP) {
2231 iounmap(up->port.membase);
2232 up->port.membase = NULL;
2233 }
2234
2235 release_mem_region(up->port.mapbase, size);
2236 break;
2237
2238 case UPIO_HUB6:
2239 case UPIO_PORT:
2240 release_region(up->port.iobase, size);
2241 break;
2242 }
2243}
2244
2245static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2246{
2247 unsigned long start = UART_RSA_BASE << up->port.regshift;
2248 unsigned int size = 8 << up->port.regshift;
0b30d668 2249 int ret = -EINVAL;
1da177e4
LT		 2250
2251 switch (up->port.iotype) {
1da177e4
LT		 2252 case UPIO_HUB6:
2253 case UPIO_PORT:
2254 start += up->port.iobase;
0b30d668
SS		 2255 if (request_region(start, size, "serial-rsa"))
2256 ret = 0;
2257 else
1da177e4
LT		 2258 ret = -EBUSY;
2259 break;
2260 }
2261
2262 return ret;
2263}
2264
2265static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2266{
2267 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2268 unsigned int size = 8 << up->port.regshift;
2269
2270 switch (up->port.iotype) {
1da177e4
LT		 2271 case UPIO_HUB6:
2272 case UPIO_PORT:
2273 release_region(up->port.iobase + offset, size);
2274 break;
2275 }
2276}
2277
2278static void serial8250_release_port(struct uart_port *port)
2279{
2280 struct uart_8250_port *up = (struct uart_8250_port *)port;
2281
2282 serial8250_release_std_resource(up);
2283 if (up->port.type == PORT_RSA)
2284 serial8250_release_rsa_resource(up);
2285}
2286
2287static int serial8250_request_port(struct uart_port *port)
2288{
2289 struct uart_8250_port *up = (struct uart_8250_port *)port;
2290 int ret = 0;
2291
2292 ret = serial8250_request_std_resource(up);
2293 if (ret == 0 && up->port.type == PORT_RSA) {
2294 ret = serial8250_request_rsa_resource(up);
2295 if (ret < 0)
2296 serial8250_release_std_resource(up);
2297 }
2298
2299 return ret;
2300}
2301
2302static void serial8250_config_port(struct uart_port *port, int flags)
2303{
2304 struct uart_8250_port *up = (struct uart_8250_port *)port;
2305 int probeflags = PROBE_ANY;
2306 int ret;
2307
1da177e4
LT		 2308 /*
2309 * Find the region that we can probe for. This in turn
2310 * tells us whether we can probe for the type of port.
2311 */
2312 ret = serial8250_request_std_resource(up);
2313 if (ret < 0)
2314 return;
2315
2316 ret = serial8250_request_rsa_resource(up);
2317 if (ret < 0)
2318 probeflags &= ~PROBE_RSA;
2319
2320 if (flags & UART_CONFIG_TYPE)
2321 autoconfig(up, probeflags);
2322 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2323 autoconfig_irq(up);
2324
2325 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2326 serial8250_release_rsa_resource(up);
2327 if (up->port.type == PORT_UNKNOWN)
2328 serial8250_release_std_resource(up);
2329}
2330
2331static int
2332serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2333{
2334 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2335 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2336 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2337 ser->type == PORT_STARTECH)
2338 return -EINVAL;
2339 return 0;
2340}
2341
2342static const char *
2343serial8250_type(struct uart_port *port)
2344{
2345 int type = port->type;
2346
2347 if (type >= ARRAY_SIZE(uart_config))
2348 type = 0;
2349 return uart_config[type].name;
2350}
2351
2352static struct uart_ops serial8250_pops = {
2353 .tx_empty = serial8250_tx_empty,
2354 .set_mctrl = serial8250_set_mctrl,
2355 .get_mctrl = serial8250_get_mctrl,
2356 .stop_tx = serial8250_stop_tx,
2357 .start_tx = serial8250_start_tx,
2358 .stop_rx = serial8250_stop_rx,
2359 .enable_ms = serial8250_enable_ms,
2360 .break_ctl = serial8250_break_ctl,
2361 .startup = serial8250_startup,
2362 .shutdown = serial8250_shutdown,
2363 .set_termios = serial8250_set_termios,
2364 .pm = serial8250_pm,
2365 .type = serial8250_type,
2366 .release_port = serial8250_release_port,
2367 .request_port = serial8250_request_port,
2368 .config_port = serial8250_config_port,
2369 .verify_port = serial8250_verify_port,
2370};
2371
2372static struct uart_8250_port serial8250_ports[UART_NR];
2373
2374static void __init serial8250_isa_init_ports(void)
2375{
2376 struct uart_8250_port *up;
2377 static int first = 1;
2378 int i;
2379
2380 if (!first)
2381 return;
2382 first = 0;
2383
a61c2d78 2384 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2385 struct uart_8250_port *up = &serial8250_ports[i];
2386
2387 up->port.line = i;
2388 spin_lock_init(&up->port.lock);
2389
2390 init_timer(&up->timer);
2391 up->timer.function = serial8250_timeout;
2392
2393 /*
2394 * ALPHA_KLUDGE_MCR needs to be killed.
2395 */
2396 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2397 up->mcr_force = ALPHA_KLUDGE_MCR;
2398
2399 up->port.ops = &serial8250_pops;
2400 }
2401
44454bcd 2402 for (i = 0, up = serial8250_ports;
a61c2d78 2403 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2404 i++, up++) {
2405 up->port.iobase = old_serial_port[i].port;
2406 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2407 up->port.uartclk = old_serial_port[i].baud_base * 16;
2408 up->port.flags = old_serial_port[i].flags;
2409 up->port.hub6 = old_serial_port[i].hub6;
2410 up->port.membase = old_serial_port[i].iomem_base;
2411 up->port.iotype = old_serial_port[i].io_type;
2412 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2413 if (share_irqs)
2414 up->port.flags |= UPF_SHARE_IRQ;
2415 }
2416}
2417
2418static void __init
2419serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2420{
2421 int i;
2422
2423 serial8250_isa_init_ports();
2424
a61c2d78 2425 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2426 struct uart_8250_port *up = &serial8250_ports[i];
2427
2428 up->port.dev = dev;
2429 uart_add_one_port(drv, &up->port);
2430 }
2431}
2432
2433#ifdef CONFIG_SERIAL_8250_CONSOLE
2434
d358788f
RK		 2435static void serial8250_console_putchar(struct uart_port *port, int ch)
2436{
2437 struct uart_8250_port *up = (struct uart_8250_port *)port;
2438
2439 wait_for_xmitr(up, UART_LSR_THRE);
2440 serial_out(up, UART_TX, ch);
2441}
2442
1da177e4
LT		 2443/*
2444 * Print a string to the serial port trying not to disturb
2445 * any possible real use of the port...
2446 *
2447 * The console_lock must be held when we get here.
2448 */
2449static void
2450serial8250_console_write(struct console *co, const char *s, unsigned int count)
2451{
2452 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2453 unsigned long flags;
1da177e4 2454 unsigned int ier;
d8a5a8d7 2455 int locked = 1;
1da177e4 2456
78512ece
AM		 2457 touch_nmi_watchdog();
2458
68aa2c0d
AM		 2459 local_irq_save(flags);
2460 if (up->port.sysrq) {
2461 /* serial8250_handle_port() already took the lock */
2462 locked = 0;
2463 } else if (oops_in_progress) {
2464 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2465 } else
68aa2c0d 2466 spin_lock(&up->port.lock);
d8a5a8d7 2467
1da177e4 2468 /*
dc7bf130 2469 * First save the IER then disable the interrupts
1da177e4
LT		 2470 */
2471 ier = serial_in(up, UART_IER);
2472
2473 if (up->capabilities & UART_CAP_UUE)
2474 serial_out(up, UART_IER, UART_IER_UUE);
2475 else
2476 serial_out(up, UART_IER, 0);
2477
d358788f 2478 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2479
2480 /*
2481 * Finally, wait for transmitter to become empty
2482 * and restore the IER
2483 */
f91a3715 2484 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2485 serial_out(up, UART_IER, ier);
d8a5a8d7
RK		 2486
2487 if (locked)
68aa2c0d
AM		 2488 spin_unlock(&up->port.lock);
2489 local_irq_restore(flags);
1da177e4
LT		 2490}
2491
118c0ace 2492static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2493{
2494 struct uart_port *port;
2495 int baud = 9600;
2496 int bits = 8;
2497 int parity = 'n';
2498 int flow = 'n';
2499
2500 /*
2501 * Check whether an invalid uart number has been specified, and
2502 * if so, search for the first available port that does have
2503 * console support.
2504 */
a61c2d78 2505 if (co->index >= nr_uarts)
1da177e4
LT		 2506 co->index = 0;
2507 port = &serial8250_ports[co->index].port;
2508 if (!port->iobase && !port->membase)
2509 return -ENODEV;
2510
2511 if (options)
2512 uart_parse_options(options, &baud, &parity, &bits, &flow);
2513
2514 return uart_set_options(port, co, baud, parity, bits, flow);
2515}
2516
18a8bd94
YL		 2517static int __init serial8250_console_early_setup(void)
2518{
2519 return serial8250_find_port_for_earlycon();
2520}
2521
1da177e4
LT		 2522static struct uart_driver serial8250_reg;
2523static struct console serial8250_console = {
2524 .name = "ttyS",
2525 .write = serial8250_console_write,
2526 .device = uart_console_device,
2527 .setup = serial8250_console_setup,
18a8bd94 2528 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2529 .flags = CON_PRINTBUFFER,
2530 .index = -1,
2531 .data = &serial8250_reg,
2532};
2533
2534static int __init serial8250_console_init(void)
2535{
2536 serial8250_isa_init_ports();
2537 register_console(&serial8250_console);
2538 return 0;
2539}
2540console_initcall(serial8250_console_init);
2541
18a8bd94 2542int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2543{
2544 int line;
2545 struct uart_port *port;
2546
a61c2d78 2547 for (line = 0; line < nr_uarts; line++) {
1da177e4 2548 port = &serial8250_ports[line].port;
50aec3b5 2549 if (uart_match_port(p, port))
1da177e4
LT		 2550 return line;
2551 }
2552 return -ENODEV;
2553}
2554
1da177e4
LT		 2555#define SERIAL8250_CONSOLE &serial8250_console
2556#else
2557#define SERIAL8250_CONSOLE NULL
2558#endif
2559
2560static struct uart_driver serial8250_reg = {
2561 .owner = THIS_MODULE,
2562 .driver_name = "serial",
1da177e4
LT		 2563 .dev_name = "ttyS",
2564 .major = TTY_MAJOR,
2565 .minor = 64,
2566 .nr = UART_NR,
2567 .cons = SERIAL8250_CONSOLE,
2568};
2569
d856c666
RK		 2570/*
2571 * early_serial_setup - early registration for 8250 ports
2572 *
2573 * Setup an 8250 port structure prior to console initialisation. Use
2574 * after console initialisation will cause undefined behaviour.
2575 */
1da177e4
LT		 2576int __init early_serial_setup(struct uart_port *port)
2577{
2578 if (port->line >= ARRAY_SIZE(serial8250_ports))
2579 return -ENODEV;
2580
2581 serial8250_isa_init_ports();
2582 serial8250_ports[port->line].port = *port;
2583 serial8250_ports[port->line].port.ops = &serial8250_pops;
2584 return 0;
2585}
2586
2587/**
2588 * serial8250_suspend_port - suspend one serial port
2589 * @line: serial line number
1da177e4
LT		 2590 *
2591 * Suspend one serial port.
2592 */
2593void serial8250_suspend_port(int line)
2594{
2595 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2596}
2597
2598/**
2599 * serial8250_resume_port - resume one serial port
2600 * @line: serial line number
1da177e4
LT		 2601 *
2602 * Resume one serial port.
2603 */
2604void serial8250_resume_port(int line)
2605{
b5b82df6
DW		 2606 struct uart_8250_port *up = &serial8250_ports[line];
2607
2608 if (up->capabilities & UART_NATSEMI) {
2609 unsigned char tmp;
2610
2611 /* Ensure it's still in high speed mode */
2612 serial_outp(up, UART_LCR, 0xE0);
2613
2614 tmp = serial_in(up, 0x04); /* EXCR2 */
2615 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2616 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2617 serial_outp(up, 0x04, tmp);
2618
2619 serial_outp(up, UART_LCR, 0);
2620 }
2621 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2622}
2623
2624/*
2625 * Register a set of serial devices attached to a platform device. The
2626 * list is terminated with a zero flags entry, which means we expect
2627 * all entries to have at least UPF_BOOT_AUTOCONF set.
2628 */
3ae5eaec 2629static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2630{
3ae5eaec 2631 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2632 struct uart_port port;
ec9f47cd 2633 int ret, i;
1da177e4
LT		 2634
2635 memset(&port, 0, sizeof(struct uart_port));
2636
ec9f47cd 2637 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2638 port.iobase = p->iobase;
2639 port.membase = p->membase;
2640 port.irq = p->irq;
2641 port.uartclk = p->uartclk;
2642 port.regshift = p->regshift;
2643 port.iotype = p->iotype;
2644 port.flags = p->flags;
2645 port.mapbase = p->mapbase;
ec9f47cd 2646 port.hub6 = p->hub6;
3ae5eaec 2647 port.dev = &dev->dev;
1da177e4
LT		 2648 if (share_irqs)
2649 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2650 ret = serial8250_register_port(&port);
2651 if (ret < 0) {
3ae5eaec 2652 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2653 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2654 p->iobase, p->mapbase, p->irq, ret);
2655 }
1da177e4
LT		 2656 }
2657 return 0;
2658}
2659
2660/*
2661 * Remove serial ports registered against a platform device.
2662 */
3ae5eaec 2663static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2664{
2665 int i;
2666
a61c2d78 2667 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2668 struct uart_8250_port *up = &serial8250_ports[i];
2669
3ae5eaec 2670 if (up->port.dev == &dev->dev)
1da177e4
LT		 2671 serial8250_unregister_port(i);
2672 }
2673 return 0;
2674}
2675
3ae5eaec 2676static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2677{
2678 int i;
2679
1da177e4
LT		 2680 for (i = 0; i < UART_NR; i++) {
2681 struct uart_8250_port *up = &serial8250_ports[i];
2682
3ae5eaec 2683 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2684 uart_suspend_port(&serial8250_reg, &up->port);
2685 }
2686
2687 return 0;
2688}
2689
3ae5eaec 2690static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2691{
2692 int i;
2693
1da177e4
LT		 2694 for (i = 0; i < UART_NR; i++) {
2695 struct uart_8250_port *up = &serial8250_ports[i];
2696
3ae5eaec 2697 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 2698 serial8250_resume_port(i);
1da177e4
LT		 2699 }
2700
2701 return 0;
2702}
2703
3ae5eaec 2704static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2705 .probe = serial8250_probe,
2706 .remove = __devexit_p(serial8250_remove),
2707 .suspend = serial8250_suspend,
2708 .resume = serial8250_resume,
3ae5eaec
RK		 2709 .driver = {
2710 .name = "serial8250",
7493a314 2711 .owner = THIS_MODULE,
3ae5eaec 2712 },
1da177e4
LT		 2713};
2714
2715/*
2716 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2717 * in the table in include/asm/serial.h
2718 */
2719static struct platform_device *serial8250_isa_devs;
2720
2721/*
2722 * serial8250_register_port and serial8250_unregister_port allows for
2723 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2724 * modems and PCI multiport cards.
2725 */
f392ecfa 2726static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 2727
2728static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2729{
2730 int i;
2731
2732 /*
2733 * First, find a port entry which matches.
2734 */
a61c2d78 2735 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2736 if (uart_match_port(&serial8250_ports[i].port, port))
2737 return &serial8250_ports[i];
2738
2739 /*
2740 * We didn't find a matching entry, so look for the first
2741 * free entry. We look for one which hasn't been previously
2742 * used (indicated by zero iobase).
2743 */
a61c2d78 2744 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2745 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2746 serial8250_ports[i].port.iobase == 0)
2747 return &serial8250_ports[i];
2748
2749 /*
2750 * That also failed. Last resort is to find any entry which
2751 * doesn't have a real port associated with it.
2752 */
a61c2d78 2753 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 2754 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2755 return &serial8250_ports[i];
2756
2757 return NULL;
2758}
2759
2760/**
2761 * serial8250_register_port - register a serial port
2762 * @port: serial port template
2763 *
2764 * Configure the serial port specified by the request. If the
2765 * port exists and is in use, it is hung up and unregistered
2766 * first.
2767 *
2768 * The port is then probed and if necessary the IRQ is autodetected
2769 * If this fails an error is returned.
2770 *
2771 * On success the port is ready to use and the line number is returned.
2772 */
2773int serial8250_register_port(struct uart_port *port)
2774{
2775 struct uart_8250_port *uart;
2776 int ret = -ENOSPC;
2777
2778 if (port->uartclk == 0)
2779 return -EINVAL;
2780
f392ecfa 2781 mutex_lock(&serial_mutex);
1da177e4
LT		 2782
2783 uart = serial8250_find_match_or_unused(port);
2784 if (uart) {
2785 uart_remove_one_port(&serial8250_reg, &uart->port);
2786
2787 uart->port.iobase = port->iobase;
2788 uart->port.membase = port->membase;
2789 uart->port.irq = port->irq;
2790 uart->port.uartclk = port->uartclk;
2791 uart->port.fifosize = port->fifosize;
2792 uart->port.regshift = port->regshift;
2793 uart->port.iotype = port->iotype;
2794 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2795 uart->port.mapbase = port->mapbase;
2796 if (port->dev)
2797 uart->port.dev = port->dev;
2798
2799 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2800 if (ret == 0)
2801 ret = uart->port.line;
2802 }
f392ecfa 2803 mutex_unlock(&serial_mutex);
1da177e4
LT		 2804
2805 return ret;
2806}
2807EXPORT_SYMBOL(serial8250_register_port);
2808
2809/**
2810 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2811 * @line: serial line number
2812 *
2813 * Remove one serial port. This may not be called from interrupt
2814 * context. We hand the port back to the our control.
2815 */
2816void serial8250_unregister_port(int line)
2817{
2818 struct uart_8250_port *uart = &serial8250_ports[line];
2819
f392ecfa 2820 mutex_lock(&serial_mutex);
1da177e4
LT		 2821 uart_remove_one_port(&serial8250_reg, &uart->port);
2822 if (serial8250_isa_devs) {
2823 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2824 uart->port.type = PORT_UNKNOWN;
2825 uart->port.dev = &serial8250_isa_devs->dev;
2826 uart_add_one_port(&serial8250_reg, &uart->port);
2827 } else {
2828 uart->port.dev = NULL;
2829 }
f392ecfa 2830 mutex_unlock(&serial_mutex);
1da177e4
LT		 2831}
2832EXPORT_SYMBOL(serial8250_unregister_port);
2833
2834static int __init serial8250_init(void)
2835{
2836 int ret, i;
2837
a61c2d78
DJ		 2838 if (nr_uarts > UART_NR)
2839 nr_uarts = UART_NR;
2840
1da177e4 2841 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
a61c2d78 2842 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 2843 share_irqs ? "en" : "dis");
2844
2845 for (i = 0; i < NR_IRQS; i++)
2846 spin_lock_init(&irq_lists[i].lock);
2847
2848 ret = uart_register_driver(&serial8250_reg);
2849 if (ret)
2850 goto out;
2851
7493a314
DT		 2852 serial8250_isa_devs = platform_device_alloc("serial8250",
2853 PLAT8250_DEV_LEGACY);
2854 if (!serial8250_isa_devs) {
2855 ret = -ENOMEM;
bc965a7f 2856 goto unreg_uart_drv;
1da177e4
LT		 2857 }
2858
7493a314
DT		 2859 ret = platform_device_add(serial8250_isa_devs);
2860 if (ret)
2861 goto put_dev;
2862
1da177e4
LT		 2863 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2864
bc965a7f
RK		 2865 ret = platform_driver_register(&serial8250_isa_driver);
2866 if (ret == 0)
2867 goto out;
1da177e4 2868
bc965a7f 2869 platform_device_del(serial8250_isa_devs);
7493a314
DT		 2870 put_dev:
2871 platform_device_put(serial8250_isa_devs);
7493a314 2872 unreg_uart_drv:
1da177e4
LT		 2873 uart_unregister_driver(&serial8250_reg);
2874 out:
2875 return ret;
2876}
2877
2878static void __exit serial8250_exit(void)
2879{
2880 struct platform_device *isa_dev = serial8250_isa_devs;
2881
2882 /*
2883 * This tells serial8250_unregister_port() not to re-register
2884 * the ports (thereby making serial8250_isa_driver permanently
2885 * in use.)
2886 */
2887 serial8250_isa_devs = NULL;
2888
3ae5eaec 2889 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2890 platform_device_unregister(isa_dev);
2891
2892 uart_unregister_driver(&serial8250_reg);
2893}
2894
2895module_init(serial8250_init);
2896module_exit(serial8250_exit);
2897
2898EXPORT_SYMBOL(serial8250_suspend_port);
2899EXPORT_SYMBOL(serial8250_resume_port);
2900
2901MODULE_LICENSE("GPL");
2902MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2903
2904module_param(share_irqs, uint, 0644);
2905MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2906 " (unsafe)");
2907
a61c2d78
DJ		 2908module_param(nr_uarts, uint, 0644);
2909MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
2910
1da177e4
LT		 2911#ifdef CONFIG_SERIAL_8250_RSA
2912module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2913MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2914#endif
2915MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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