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[SERIAL] Fix matching of MMIO ports
[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
16 *
17 * A note about mapbase / membase
18 *
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
21 */
22#include <linux/config.h>
23
24#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
25#define SUPPORT_SYSRQ
26#endif
27
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/ioport.h>
31#include <linux/init.h>
32#include <linux/console.h>
33#include <linux/sysrq.h>
34#include <linux/mca.h>
35#include <linux/delay.h>
d052d1be 36#include <linux/platform_device.h>
1da177e4
LT		 37#include <linux/tty.h>
38#include <linux/tty_flip.h>
39#include <linux/serial_reg.h>
40#include <linux/serial_core.h>
41#include <linux/serial.h>
42#include <linux/serial_8250.h>
78512ece 43#include <linux/nmi.h>
1da177e4
LT		 44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50/*
51 * Configuration:
52 * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
54 */
408b664a 55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4
LT		 56
57/*
58 * Debugging.
59 */
60#if 0
61#define DEBUG_AUTOCONF(fmt...) printk(fmt)
62#else
63#define DEBUG_AUTOCONF(fmt...) do { } while (0)
64#endif
65
66#if 0
67#define DEBUG_INTR(fmt...) printk(fmt)
68#else
69#define DEBUG_INTR(fmt...) do { } while (0)
70#endif
71
72#define PASS_LIMIT 256
73
74/*
75 * We default to IRQ0 for the "no irq" hack. Some
76 * machine types want others as well - they're free
77 * to redefine this in their header file.
78 */
79#define is_real_interrupt(irq) ((irq) != 0)
80
1da177e4
LT		 81#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
82#define CONFIG_SERIAL_DETECT_IRQ 1
83#endif
1da177e4
LT		 84#ifdef CONFIG_SERIAL_8250_MANY_PORTS
85#define CONFIG_SERIAL_MANY_PORTS 1
86#endif
87
88/*
89 * HUB6 is always on. This will be removed once the header
90 * files have been cleaned.
91 */
92#define CONFIG_HUB6 1
93
94#include <asm/serial.h>
95
96/*
97 * SERIAL_PORT_DFNS tells us about built-in ports that have no
98 * standard enumeration mechanism. Platforms that can find all
99 * serial ports via mechanisms like ACPI or PCI need not supply it.
100 */
101#ifndef SERIAL_PORT_DFNS
102#define SERIAL_PORT_DFNS
103#endif
104
cb3592be 105static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 106 SERIAL_PORT_DFNS /* defined in asm/serial.h */
107};
108
026d02a2 109#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 110
111#ifdef CONFIG_SERIAL_8250_RSA
112
113#define PORT_RSA_MAX 4
114static unsigned long probe_rsa[PORT_RSA_MAX];
115static unsigned int probe_rsa_count;
116#endif /* CONFIG_SERIAL_8250_RSA */
117
118struct uart_8250_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 122 unsigned short capabilities; /* port capabilities */
123 unsigned short bugs; /* port bugs */
1da177e4 124 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 125 unsigned char acr;
126 unsigned char ier;
127 unsigned char lcr;
128 unsigned char mcr;
129 unsigned char mcr_mask; /* mask of user bits */
130 unsigned char mcr_force; /* mask of forced bits */
131 unsigned char lsr_break_flag;
132
133 /*
134 * We provide a per-port pm hook.
135 */
136 void (*pm)(struct uart_port *port,
137 unsigned int state, unsigned int old);
138};
139
140struct irq_info {
141 spinlock_t lock;
142 struct list_head *head;
143};
144
145static struct irq_info irq_lists[NR_IRQS];
146
147/*
148 * Here we define the default xmit fifo size used for each type of UART.
149 */
150static const struct serial8250_config uart_config[] = {
151 [PORT_UNKNOWN] = {
152 .name = "unknown",
153 .fifo_size = 1,
154 .tx_loadsz = 1,
155 },
156 [PORT_8250] = {
157 .name = "8250",
158 .fifo_size = 1,
159 .tx_loadsz = 1,
160 },
161 [PORT_16450] = {
162 .name = "16450",
163 .fifo_size = 1,
164 .tx_loadsz = 1,
165 },
166 [PORT_16550] = {
167 .name = "16550",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16550A] = {
172 .name = "16550A",
173 .fifo_size = 16,
174 .tx_loadsz = 16,
175 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
176 .flags = UART_CAP_FIFO,
177 },
178 [PORT_CIRRUS] = {
179 .name = "Cirrus",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16650] = {
184 .name = "ST16650",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
188 },
189 [PORT_16650V2] = {
190 .name = "ST16650V2",
191 .fifo_size = 32,
192 .tx_loadsz = 16,
193 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
194 UART_FCR_T_TRIG_00,
195 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
196 },
197 [PORT_16750] = {
198 .name = "TI16750",
199 .fifo_size = 64,
200 .tx_loadsz = 64,
201 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
202 UART_FCR7_64BYTE,
203 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
204 },
205 [PORT_STARTECH] = {
206 .name = "Startech",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 },
210 [PORT_16C950] = {
211 .name = "16C950/954",
212 .fifo_size = 128,
213 .tx_loadsz = 128,
214 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
215 .flags = UART_CAP_FIFO,
216 },
217 [PORT_16654] = {
218 .name = "ST16654",
219 .fifo_size = 64,
220 .tx_loadsz = 32,
221 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
222 UART_FCR_T_TRIG_10,
223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
224 },
225 [PORT_16850] = {
226 .name = "XR16850",
227 .fifo_size = 128,
228 .tx_loadsz = 128,
229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
230 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
231 },
232 [PORT_RSA] = {
233 .name = "RSA",
234 .fifo_size = 2048,
235 .tx_loadsz = 2048,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_NS16550A] = {
240 .name = "NS16550A",
241 .fifo_size = 16,
242 .tx_loadsz = 16,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
244 .flags = UART_CAP_FIFO | UART_NATSEMI,
245 },
246 [PORT_XSCALE] = {
247 .name = "XScale",
248 .fifo_size = 32,
249 .tx_loadsz = 32,
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .flags = UART_CAP_FIFO | UART_CAP_UUE,
252 },
253};
254
21c614a7
PA		 255#ifdef CONFIG_SERIAL_8250_AU1X00
256
257/* Au1x00 UART hardware has a weird register layout */
258static const u8 au_io_in_map[] = {
259 [UART_RX] = 0,
260 [UART_IER] = 2,
261 [UART_IIR] = 3,
262 [UART_LCR] = 5,
263 [UART_MCR] = 6,
264 [UART_LSR] = 7,
265 [UART_MSR] = 8,
266};
267
268static const u8 au_io_out_map[] = {
269 [UART_TX] = 1,
270 [UART_IER] = 2,
271 [UART_FCR] = 4,
272 [UART_LCR] = 5,
273 [UART_MCR] = 6,
274};
275
276/* sane hardware needs no mapping */
277static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
278{
279 if (up->port.iotype != UPIO_AU)
280 return offset;
281 return au_io_in_map[offset];
282}
283
284static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
285{
286 if (up->port.iotype != UPIO_AU)
287 return offset;
288 return au_io_out_map[offset];
289}
290
291#else
292
293/* sane hardware needs no mapping */
294#define map_8250_in_reg(up, offset) (offset)
295#define map_8250_out_reg(up, offset) (offset)
296
297#endif
298
1da177e4
LT		 299static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
300{
21c614a7 301 offset = map_8250_in_reg(up, offset) << up->port.regshift;
1da177e4
LT		 302
303 switch (up->port.iotype) {
304 case UPIO_HUB6:
305 outb(up->port.hub6 - 1 + offset, up->port.iobase);
306 return inb(up->port.iobase + 1);
307
308 case UPIO_MEM:
309 return readb(up->port.membase + offset);
310
311 case UPIO_MEM32:
312 return readl(up->port.membase + offset);
313
21c614a7
PA		 314#ifdef CONFIG_SERIAL_8250_AU1X00
315 case UPIO_AU:
316 return __raw_readl(up->port.membase + offset);
317#endif
318
1da177e4
LT		 319 default:
320 return inb(up->port.iobase + offset);
321 }
322}
323
324static _INLINE_ void
325serial_out(struct uart_8250_port *up, int offset, int value)
326{
21c614a7 327 offset = map_8250_out_reg(up, offset) << up->port.regshift;
1da177e4
LT		 328
329 switch (up->port.iotype) {
330 case UPIO_HUB6:
331 outb(up->port.hub6 - 1 + offset, up->port.iobase);
332 outb(value, up->port.iobase + 1);
333 break;
334
335 case UPIO_MEM:
336 writeb(value, up->port.membase + offset);
337 break;
338
339 case UPIO_MEM32:
340 writel(value, up->port.membase + offset);
341 break;
342
21c614a7
PA		 343#ifdef CONFIG_SERIAL_8250_AU1X00
344 case UPIO_AU:
345 __raw_writel(value, up->port.membase + offset);
346 break;
347#endif
348
1da177e4
LT		 349 default:
350 outb(value, up->port.iobase + offset);
351 }
352}
353
354/*
355 * We used to support using pause I/O for certain machines. We
356 * haven't supported this for a while, but just in case it's badly
357 * needed for certain old 386 machines, I've left these #define's
358 * in....
359 */
360#define serial_inp(up, offset) serial_in(up, offset)
361#define serial_outp(up, offset, value) serial_out(up, offset, value)
362
363
364/*
365 * For the 16C950
366 */
367static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
368{
369 serial_out(up, UART_SCR, offset);
370 serial_out(up, UART_ICR, value);
371}
372
373static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
374{
375 unsigned int value;
376
377 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
378 serial_out(up, UART_SCR, offset);
379 value = serial_in(up, UART_ICR);
380 serial_icr_write(up, UART_ACR, up->acr);
381
382 return value;
383}
384
385/*
386 * FIFO support.
387 */
388static inline void serial8250_clear_fifos(struct uart_8250_port *p)
389{
390 if (p->capabilities & UART_CAP_FIFO) {
391 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
392 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
393 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
394 serial_outp(p, UART_FCR, 0);
395 }
396}
397
398/*
399 * IER sleep support. UARTs which have EFRs need the "extended
400 * capability" bit enabled. Note that on XR16C850s, we need to
401 * reset LCR to write to IER.
402 */
403static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
404{
405 if (p->capabilities & UART_CAP_SLEEP) {
406 if (p->capabilities & UART_CAP_EFR) {
407 serial_outp(p, UART_LCR, 0xBF);
408 serial_outp(p, UART_EFR, UART_EFR_ECB);
409 serial_outp(p, UART_LCR, 0);
410 }
411 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
412 if (p->capabilities & UART_CAP_EFR) {
413 serial_outp(p, UART_LCR, 0xBF);
414 serial_outp(p, UART_EFR, 0);
415 serial_outp(p, UART_LCR, 0);
416 }
417 }
418}
419
420#ifdef CONFIG_SERIAL_8250_RSA
421/*
422 * Attempts to turn on the RSA FIFO. Returns zero on failure.
423 * We set the port uart clock rate if we succeed.
424 */
425static int __enable_rsa(struct uart_8250_port *up)
426{
427 unsigned char mode;
428 int result;
429
430 mode = serial_inp(up, UART_RSA_MSR);
431 result = mode & UART_RSA_MSR_FIFO;
432
433 if (!result) {
434 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
435 mode = serial_inp(up, UART_RSA_MSR);
436 result = mode & UART_RSA_MSR_FIFO;
437 }
438
439 if (result)
440 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
441
442 return result;
443}
444
445static void enable_rsa(struct uart_8250_port *up)
446{
447 if (up->port.type == PORT_RSA) {
448 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
449 spin_lock_irq(&up->port.lock);
450 __enable_rsa(up);
451 spin_unlock_irq(&up->port.lock);
452 }
453 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
454 serial_outp(up, UART_RSA_FRR, 0);
455 }
456}
457
458/*
459 * Attempts to turn off the RSA FIFO. Returns zero on failure.
460 * It is unknown why interrupts were disabled in here. However,
461 * the caller is expected to preserve this behaviour by grabbing
462 * the spinlock before calling this function.
463 */
464static void disable_rsa(struct uart_8250_port *up)
465{
466 unsigned char mode;
467 int result;
468
469 if (up->port.type == PORT_RSA &&
470 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
471 spin_lock_irq(&up->port.lock);
472
473 mode = serial_inp(up, UART_RSA_MSR);
474 result = !(mode & UART_RSA_MSR_FIFO);
475
476 if (!result) {
477 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
478 mode = serial_inp(up, UART_RSA_MSR);
479 result = !(mode & UART_RSA_MSR_FIFO);
480 }
481
482 if (result)
483 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
484 spin_unlock_irq(&up->port.lock);
485 }
486}
487#endif /* CONFIG_SERIAL_8250_RSA */
488
489/*
490 * This is a quickie test to see how big the FIFO is.
491 * It doesn't work at all the time, more's the pity.
492 */
493static int size_fifo(struct uart_8250_port *up)
494{
495 unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr;
496 int count;
497
498 old_lcr = serial_inp(up, UART_LCR);
499 serial_outp(up, UART_LCR, 0);
500 old_fcr = serial_inp(up, UART_FCR);
501 old_mcr = serial_inp(up, UART_MCR);
502 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
503 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
504 serial_outp(up, UART_MCR, UART_MCR_LOOP);
505 serial_outp(up, UART_LCR, UART_LCR_DLAB);
506 old_dll = serial_inp(up, UART_DLL);
507 old_dlm = serial_inp(up, UART_DLM);
508 serial_outp(up, UART_DLL, 0x01);
509 serial_outp(up, UART_DLM, 0x00);
510 serial_outp(up, UART_LCR, 0x03);
511 for (count = 0; count < 256; count++)
512 serial_outp(up, UART_TX, count);
513 mdelay(20);/* FIXME - schedule_timeout */
514 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
515 (count < 256); count++)
516 serial_inp(up, UART_RX);
517 serial_outp(up, UART_FCR, old_fcr);
518 serial_outp(up, UART_MCR, old_mcr);
519 serial_outp(up, UART_LCR, UART_LCR_DLAB);
520 serial_outp(up, UART_DLL, old_dll);
521 serial_outp(up, UART_DLM, old_dlm);
522 serial_outp(up, UART_LCR, old_lcr);
523
524 return count;
525}
526
527/*
528 * Read UART ID using the divisor method - set DLL and DLM to zero
529 * and the revision will be in DLL and device type in DLM. We
530 * preserve the device state across this.
531 */
532static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
533{
534 unsigned char old_dll, old_dlm, old_lcr;
535 unsigned int id;
536
537 old_lcr = serial_inp(p, UART_LCR);
538 serial_outp(p, UART_LCR, UART_LCR_DLAB);
539
540 old_dll = serial_inp(p, UART_DLL);
541 old_dlm = serial_inp(p, UART_DLM);
542
543 serial_outp(p, UART_DLL, 0);
544 serial_outp(p, UART_DLM, 0);
545
546 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
547
548 serial_outp(p, UART_DLL, old_dll);
549 serial_outp(p, UART_DLM, old_dlm);
550 serial_outp(p, UART_LCR, old_lcr);
551
552 return id;
553}
554
555/*
556 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
557 * When this function is called we know it is at least a StarTech
558 * 16650 V2, but it might be one of several StarTech UARTs, or one of
559 * its clones. (We treat the broken original StarTech 16650 V1 as a
560 * 16550, and why not? Startech doesn't seem to even acknowledge its
561 * existence.)
562 *
563 * What evil have men's minds wrought...
564 */
565static void autoconfig_has_efr(struct uart_8250_port *up)
566{
567 unsigned int id1, id2, id3, rev;
568
569 /*
570 * Everything with an EFR has SLEEP
571 */
572 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
573
574 /*
575 * First we check to see if it's an Oxford Semiconductor UART.
576 *
577 * If we have to do this here because some non-National
578 * Semiconductor clone chips lock up if you try writing to the
579 * LSR register (which serial_icr_read does)
580 */
581
582 /*
583 * Check for Oxford Semiconductor 16C950.
584 *
585 * EFR [4] must be set else this test fails.
586 *
587 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
588 * claims that it's needed for 952 dual UART's (which are not
589 * recommended for new designs).
590 */
591 up->acr = 0;
592 serial_out(up, UART_LCR, 0xBF);
593 serial_out(up, UART_EFR, UART_EFR_ECB);
594 serial_out(up, UART_LCR, 0x00);
595 id1 = serial_icr_read(up, UART_ID1);
596 id2 = serial_icr_read(up, UART_ID2);
597 id3 = serial_icr_read(up, UART_ID3);
598 rev = serial_icr_read(up, UART_REV);
599
600 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
601
602 if (id1 == 0x16 && id2 == 0xC9 &&
603 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
604 up->port.type = PORT_16C950;
4ba5e35d
RK		 605
606 /*
607 * Enable work around for the Oxford Semiconductor 952 rev B
608 * chip which causes it to seriously miscalculate baud rates
609 * when DLL is 0.
610 */
611 if (id3 == 0x52 && rev == 0x01)
612 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 613 return;
614 }
615
616 /*
617 * We check for a XR16C850 by setting DLL and DLM to 0, and then
618 * reading back DLL and DLM. The chip type depends on the DLM
619 * value read back:
620 * 0x10 - XR16C850 and the DLL contains the chip revision.
621 * 0x12 - XR16C2850.
622 * 0x14 - XR16C854.
623 */
624 id1 = autoconfig_read_divisor_id(up);
625 DEBUG_AUTOCONF("850id=%04x ", id1);
626
627 id2 = id1 >> 8;
628 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 629 up->port.type = PORT_16850;
630 return;
631 }
632
633 /*
634 * It wasn't an XR16C850.
635 *
636 * We distinguish between the '654 and the '650 by counting
637 * how many bytes are in the FIFO. I'm using this for now,
638 * since that's the technique that was sent to me in the
639 * serial driver update, but I'm not convinced this works.
640 * I've had problems doing this in the past. -TYT
641 */
642 if (size_fifo(up) == 64)
643 up->port.type = PORT_16654;
644 else
645 up->port.type = PORT_16650V2;
646}
647
648/*
649 * We detected a chip without a FIFO. Only two fall into
650 * this category - the original 8250 and the 16450. The
651 * 16450 has a scratch register (accessible with LCR=0)
652 */
653static void autoconfig_8250(struct uart_8250_port *up)
654{
655 unsigned char scratch, status1, status2;
656
657 up->port.type = PORT_8250;
658
659 scratch = serial_in(up, UART_SCR);
660 serial_outp(up, UART_SCR, 0xa5);
661 status1 = serial_in(up, UART_SCR);
662 serial_outp(up, UART_SCR, 0x5a);
663 status2 = serial_in(up, UART_SCR);
664 serial_outp(up, UART_SCR, scratch);
665
666 if (status1 == 0xa5 && status2 == 0x5a)
667 up->port.type = PORT_16450;
668}
669
670static int broken_efr(struct uart_8250_port *up)
671{
672 /*
673 * Exar ST16C2550 "A2" devices incorrectly detect as
674 * having an EFR, and report an ID of 0x0201. See
675 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
676 */
677 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
678 return 1;
679
680 return 0;
681}
682
683/*
684 * We know that the chip has FIFOs. Does it have an EFR? The
685 * EFR is located in the same register position as the IIR and
686 * we know the top two bits of the IIR are currently set. The
687 * EFR should contain zero. Try to read the EFR.
688 */
689static void autoconfig_16550a(struct uart_8250_port *up)
690{
691 unsigned char status1, status2;
692 unsigned int iersave;
693
694 up->port.type = PORT_16550A;
695 up->capabilities |= UART_CAP_FIFO;
696
697 /*
698 * Check for presence of the EFR when DLAB is set.
699 * Only ST16C650V1 UARTs pass this test.
700 */
701 serial_outp(up, UART_LCR, UART_LCR_DLAB);
702 if (serial_in(up, UART_EFR) == 0) {
703 serial_outp(up, UART_EFR, 0xA8);
704 if (serial_in(up, UART_EFR) != 0) {
705 DEBUG_AUTOCONF("EFRv1 ");
706 up->port.type = PORT_16650;
707 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
708 } else {
709 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
710 }
711 serial_outp(up, UART_EFR, 0);
712 return;
713 }
714
715 /*
716 * Maybe it requires 0xbf to be written to the LCR.
717 * (other ST16C650V2 UARTs, TI16C752A, etc)
718 */
719 serial_outp(up, UART_LCR, 0xBF);
720 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
721 DEBUG_AUTOCONF("EFRv2 ");
722 autoconfig_has_efr(up);
723 return;
724 }
725
726 /*
727 * Check for a National Semiconductor SuperIO chip.
728 * Attempt to switch to bank 2, read the value of the LOOP bit
729 * from EXCR1. Switch back to bank 0, change it in MCR. Then
730 * switch back to bank 2, read it from EXCR1 again and check
731 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 732 */
733 serial_outp(up, UART_LCR, 0);
734 status1 = serial_in(up, UART_MCR);
735 serial_outp(up, UART_LCR, 0xE0);
736 status2 = serial_in(up, 0x02); /* EXCR1 */
737
738 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
739 serial_outp(up, UART_LCR, 0);
740 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
741 serial_outp(up, UART_LCR, 0xE0);
742 status2 = serial_in(up, 0x02); /* EXCR1 */
743 serial_outp(up, UART_LCR, 0);
744 serial_outp(up, UART_MCR, status1);
745
746 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 747 unsigned short quot;
748
1da177e4 749 serial_outp(up, UART_LCR, 0xE0);
857dde2e
DW		 750
751 quot = serial_inp(up, UART_DLM) << 8;
752 quot += serial_inp(up, UART_DLL);
753 quot <<= 3;
754
1da177e4
LT		 755 status1 = serial_in(up, 0x04); /* EXCR1 */
756 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
757 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
758 serial_outp(up, 0x04, status1);
857dde2e
DW		 759
760 serial_outp(up, UART_DLL, quot & 0xff);
761 serial_outp(up, UART_DLM, quot >> 8);
762
1da177e4 763 serial_outp(up, UART_LCR, 0);
1da177e4 764
857dde2e 765 up->port.uartclk = 921600*16;
1da177e4
LT		 766 up->port.type = PORT_NS16550A;
767 up->capabilities |= UART_NATSEMI;
768 return;
769 }
770 }
771
772 /*
773 * No EFR. Try to detect a TI16750, which only sets bit 5 of
774 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
775 * Try setting it with and without DLAB set. Cheap clones
776 * set bit 5 without DLAB set.
777 */
778 serial_outp(up, UART_LCR, 0);
779 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
780 status1 = serial_in(up, UART_IIR) >> 5;
781 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
782 serial_outp(up, UART_LCR, UART_LCR_DLAB);
783 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
784 status2 = serial_in(up, UART_IIR) >> 5;
785 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
786 serial_outp(up, UART_LCR, 0);
787
788 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
789
790 if (status1 == 6 && status2 == 7) {
791 up->port.type = PORT_16750;
792 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
793 return;
794 }
795
796 /*
797 * Try writing and reading the UART_IER_UUE bit (b6).
798 * If it works, this is probably one of the Xscale platform's
799 * internal UARTs.
800 * We're going to explicitly set the UUE bit to 0 before
801 * trying to write and read a 1 just to make sure it's not
802 * already a 1 and maybe locked there before we even start start.
803 */
804 iersave = serial_in(up, UART_IER);
805 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
806 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
807 /*
808 * OK it's in a known zero state, try writing and reading
809 * without disturbing the current state of the other bits.
810 */
811 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
812 if (serial_in(up, UART_IER) & UART_IER_UUE) {
813 /*
814 * It's an Xscale.
815 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
816 */
817 DEBUG_AUTOCONF("Xscale ");
818 up->port.type = PORT_XSCALE;
819 up->capabilities |= UART_CAP_UUE;
820 return;
821 }
822 } else {
823 /*
824 * If we got here we couldn't force the IER_UUE bit to 0.
825 * Log it and continue.
826 */
827 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
828 }
829 serial_outp(up, UART_IER, iersave);
830}
831
832/*
833 * This routine is called by rs_init() to initialize a specific serial
834 * port. It determines what type of UART chip this serial port is
835 * using: 8250, 16450, 16550, 16550A. The important question is
836 * whether or not this UART is a 16550A or not, since this will
837 * determine whether or not we can use its FIFO features or not.
838 */
839static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
840{
841 unsigned char status1, scratch, scratch2, scratch3;
842 unsigned char save_lcr, save_mcr;
843 unsigned long flags;
844
845 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
846 return;
847
848 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
849 up->port.line, up->port.iobase, up->port.membase);
850
851 /*
852 * We really do need global IRQs disabled here - we're going to
853 * be frobbing the chips IRQ enable register to see if it exists.
854 */
855 spin_lock_irqsave(&up->port.lock, flags);
856// save_flags(flags); cli();
857
858 up->capabilities = 0;
4ba5e35d 859 up->bugs = 0;
1da177e4
LT		 860
861 if (!(up->port.flags & UPF_BUGGY_UART)) {
862 /*
863 * Do a simple existence test first; if we fail this,
864 * there's no point trying anything else.
865 *
866 * 0x80 is used as a nonsense port to prevent against
867 * false positives due to ISA bus float. The
868 * assumption is that 0x80 is a non-existent port;
869 * which should be safe since include/asm/io.h also
870 * makes this assumption.
871 *
872 * Note: this is safe as long as MCR bit 4 is clear
873 * and the device is in "PC" mode.
874 */
875 scratch = serial_inp(up, UART_IER);
876 serial_outp(up, UART_IER, 0);
877#ifdef __i386__
878 outb(0xff, 0x080);
879#endif
880 scratch2 = serial_inp(up, UART_IER);
881 serial_outp(up, UART_IER, 0x0F);
882#ifdef __i386__
883 outb(0, 0x080);
884#endif
885 scratch3 = serial_inp(up, UART_IER);
886 serial_outp(up, UART_IER, scratch);
887 if (scratch2 != 0 || scratch3 != 0x0F) {
888 /*
889 * We failed; there's nothing here
890 */
891 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
892 scratch2, scratch3);
893 goto out;
894 }
895 }
896
897 save_mcr = serial_in(up, UART_MCR);
898 save_lcr = serial_in(up, UART_LCR);
899
900 /*
901 * Check to see if a UART is really there. Certain broken
902 * internal modems based on the Rockwell chipset fail this
903 * test, because they apparently don't implement the loopback
904 * test mode. So this test is skipped on the COM 1 through
905 * COM 4 ports. This *should* be safe, since no board
906 * manufacturer would be stupid enough to design a board
907 * that conflicts with COM 1-4 --- we hope!
908 */
909 if (!(up->port.flags & UPF_SKIP_TEST)) {
910 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
911 status1 = serial_inp(up, UART_MSR) & 0xF0;
912 serial_outp(up, UART_MCR, save_mcr);
913 if (status1 != 0x90) {
914 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
915 status1);
916 goto out;
917 }
918 }
919
920 /*
921 * We're pretty sure there's a port here. Lets find out what
922 * type of port it is. The IIR top two bits allows us to find
6f0d618f 923 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 924 * determines what we test for next.
925 *
926 * We also initialise the EFR (if any) to zero for later. The
927 * EFR occupies the same register location as the FCR and IIR.
928 */
929 serial_outp(up, UART_LCR, 0xBF);
930 serial_outp(up, UART_EFR, 0);
931 serial_outp(up, UART_LCR, 0);
932
933 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
934 scratch = serial_in(up, UART_IIR) >> 6;
935
936 DEBUG_AUTOCONF("iir=%d ", scratch);
937
938 switch (scratch) {
939 case 0:
940 autoconfig_8250(up);
941 break;
942 case 1:
943 up->port.type = PORT_UNKNOWN;
944 break;
945 case 2:
946 up->port.type = PORT_16550;
947 break;
948 case 3:
949 autoconfig_16550a(up);
950 break;
951 }
952
953#ifdef CONFIG_SERIAL_8250_RSA
954 /*
955 * Only probe for RSA ports if we got the region.
956 */
957 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
958 int i;
959
960 for (i = 0 ; i < probe_rsa_count; ++i) {
961 if (probe_rsa[i] == up->port.iobase &&
962 __enable_rsa(up)) {
963 up->port.type = PORT_RSA;
964 break;
965 }
966 }
967 }
968#endif
21c614a7
PA		 969
970#ifdef CONFIG_SERIAL_8250_AU1X00
971 /* if access method is AU, it is a 16550 with a quirk */
972 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
973 up->bugs |= UART_BUG_NOMSR;
974#endif
975
1da177e4
LT		 976 serial_outp(up, UART_LCR, save_lcr);
977
978 if (up->capabilities != uart_config[up->port.type].flags) {
979 printk(KERN_WARNING
980 "ttyS%d: detected caps %08x should be %08x\n",
981 up->port.line, up->capabilities,
982 uart_config[up->port.type].flags);
983 }
984
985 up->port.fifosize = uart_config[up->port.type].fifo_size;
986 up->capabilities = uart_config[up->port.type].flags;
987 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
988
989 if (up->port.type == PORT_UNKNOWN)
990 goto out;
991
992 /*
993 * Reset the UART.
994 */
995#ifdef CONFIG_SERIAL_8250_RSA
996 if (up->port.type == PORT_RSA)
997 serial_outp(up, UART_RSA_FRR, 0);
998#endif
999 serial_outp(up, UART_MCR, save_mcr);
1000 serial8250_clear_fifos(up);
1001 (void)serial_in(up, UART_RX);
5c8c755c
LB		 1002 if (up->capabilities & UART_CAP_UUE)
1003 serial_outp(up, UART_IER, UART_IER_UUE);
1004 else
1005 serial_outp(up, UART_IER, 0);
1da177e4
LT		 1006
1007 out:
1008 spin_unlock_irqrestore(&up->port.lock, flags);
1009// restore_flags(flags);
1010 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1011}
1012
1013static void autoconfig_irq(struct uart_8250_port *up)
1014{
1015 unsigned char save_mcr, save_ier;
1016 unsigned char save_ICP = 0;
1017 unsigned int ICP = 0;
1018 unsigned long irqs;
1019 int irq;
1020
1021 if (up->port.flags & UPF_FOURPORT) {
1022 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1023 save_ICP = inb_p(ICP);
1024 outb_p(0x80, ICP);
1025 (void) inb_p(ICP);
1026 }
1027
1028 /* forget possible initially masked and pending IRQ */
1029 probe_irq_off(probe_irq_on());
1030 save_mcr = serial_inp(up, UART_MCR);
1031 save_ier = serial_inp(up, UART_IER);
1032 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1033
1034 irqs = probe_irq_on();
1035 serial_outp(up, UART_MCR, 0);
1036 udelay (10);
1037 if (up->port.flags & UPF_FOURPORT) {
1038 serial_outp(up, UART_MCR,
1039 UART_MCR_DTR | UART_MCR_RTS);
1040 } else {
1041 serial_outp(up, UART_MCR,
1042 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1043 }
1044 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1045 (void)serial_inp(up, UART_LSR);
1046 (void)serial_inp(up, UART_RX);
1047 (void)serial_inp(up, UART_IIR);
1048 (void)serial_inp(up, UART_MSR);
1049 serial_outp(up, UART_TX, 0xFF);
1050 udelay (20);
1051 irq = probe_irq_off(irqs);
1052
1053 serial_outp(up, UART_MCR, save_mcr);
1054 serial_outp(up, UART_IER, save_ier);
1055
1056 if (up->port.flags & UPF_FOURPORT)
1057 outb_p(save_ICP, ICP);
1058
1059 up->port.irq = (irq > 0) ? irq : 0;
1060}
1061
e763b90c
RK		 1062static inline void __stop_tx(struct uart_8250_port *p)
1063{
1064 if (p->ier & UART_IER_THRI) {
1065 p->ier &= ~UART_IER_THRI;
1066 serial_out(p, UART_IER, p->ier);
1067 }
1068}
1069
b129a8cc 1070static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1071{
1072 struct uart_8250_port *up = (struct uart_8250_port *)port;
1073
e763b90c 1074 __stop_tx(up);
1da177e4
LT		 1075
1076 /*
e763b90c 1077 * We really want to stop the transmitter from sending.
1da177e4 1078 */
e763b90c 1079 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1080 up->acr |= UART_ACR_TXDIS;
1081 serial_icr_write(up, UART_ACR, up->acr);
1082 }
1083}
1084
55d3b282
RK		 1085static void transmit_chars(struct uart_8250_port *up);
1086
b129a8cc 1087static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1088{
1089 struct uart_8250_port *up = (struct uart_8250_port *)port;
1090
1091 if (!(up->ier & UART_IER_THRI)) {
1092 up->ier |= UART_IER_THRI;
1093 serial_out(up, UART_IER, up->ier);
55d3b282 1094
67f7654e 1095 if (up->bugs & UART_BUG_TXEN) {
55d3b282
RK		 1096 unsigned char lsr, iir;
1097 lsr = serial_in(up, UART_LSR);
1098 iir = serial_in(up, UART_IIR);
1099 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT)
1100 transmit_chars(up);
1101 }
1da177e4 1102 }
e763b90c 1103
1da177e4 1104 /*
e763b90c 1105 * Re-enable the transmitter if we disabled it.
1da177e4 1106 */
e763b90c 1107 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1108 up->acr &= ~UART_ACR_TXDIS;
1109 serial_icr_write(up, UART_ACR, up->acr);
1110 }
1111}
1112
1113static void serial8250_stop_rx(struct uart_port *port)
1114{
1115 struct uart_8250_port *up = (struct uart_8250_port *)port;
1116
1117 up->ier &= ~UART_IER_RLSI;
1118 up->port.read_status_mask &= ~UART_LSR_DR;
1119 serial_out(up, UART_IER, up->ier);
1120}
1121
1122static void serial8250_enable_ms(struct uart_port *port)
1123{
1124 struct uart_8250_port *up = (struct uart_8250_port *)port;
1125
21c614a7
PA		 1126 /* no MSR capabilities */
1127 if (up->bugs & UART_BUG_NOMSR)
1128 return;
1129
1da177e4
LT		 1130 up->ier |= UART_IER_MSI;
1131 serial_out(up, UART_IER, up->ier);
1132}
1133
1134static _INLINE_ void
1135receive_chars(struct uart_8250_port *up, int *status, struct pt_regs *regs)
1136{
1137 struct tty_struct *tty = up->port.info->tty;
1138 unsigned char ch, lsr = *status;
1139 int max_count = 256;
1140 char flag;
1141
1142 do {
1143 /* The following is not allowed by the tty layer and
1144 unsafe. It should be fixed ASAP */
1145 if (unlikely(tty->flip.count >= TTY_FLIPBUF_SIZE)) {
1146 if (tty->low_latency) {
1147 spin_unlock(&up->port.lock);
1148 tty_flip_buffer_push(tty);
1149 spin_lock(&up->port.lock);
1150 }
23907eb8
RK		 1151 /*
1152 * If this failed then we will throw away the
1153 * bytes but must do so to clear interrupts
1154 */
1da177e4
LT		 1155 }
1156 ch = serial_inp(up, UART_RX);
1157 flag = TTY_NORMAL;
1158 up->port.icount.rx++;
1159
1160#ifdef CONFIG_SERIAL_8250_CONSOLE
1161 /*
1162 * Recover the break flag from console xmit
1163 */
1164 if (up->port.line == up->port.cons->index) {
1165 lsr |= up->lsr_break_flag;
1166 up->lsr_break_flag = 0;
1167 }
1168#endif
1169
1170 if (unlikely(lsr & (UART_LSR_BI | UART_LSR_PE |
1171 UART_LSR_FE | UART_LSR_OE))) {
1172 /*
1173 * For statistics only
1174 */
1175 if (lsr & UART_LSR_BI) {
1176 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1177 up->port.icount.brk++;
1178 /*
1179 * We do the SysRQ and SAK checking
1180 * here because otherwise the break
1181 * may get masked by ignore_status_mask
1182 * or read_status_mask.
1183 */
1184 if (uart_handle_break(&up->port))
1185 goto ignore_char;
1186 } else if (lsr & UART_LSR_PE)
1187 up->port.icount.parity++;
1188 else if (lsr & UART_LSR_FE)
1189 up->port.icount.frame++;
1190 if (lsr & UART_LSR_OE)
1191 up->port.icount.overrun++;
1192
1193 /*
23907eb8 1194 * Mask off conditions which should be ignored.
1da177e4
LT		 1195 */
1196 lsr &= up->port.read_status_mask;
1197
1198 if (lsr & UART_LSR_BI) {
1199 DEBUG_INTR("handling break....");
1200 flag = TTY_BREAK;
1201 } else if (lsr & UART_LSR_PE)
1202 flag = TTY_PARITY;
1203 else if (lsr & UART_LSR_FE)
1204 flag = TTY_FRAME;
1205 }
1206 if (uart_handle_sysrq_char(&up->port, ch, regs))
1207 goto ignore_char;
05ab3014
RK		 1208
1209 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1210
1da177e4
LT		 1211 ignore_char:
1212 lsr = serial_inp(up, UART_LSR);
1213 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1214 spin_unlock(&up->port.lock);
1215 tty_flip_buffer_push(tty);
1216 spin_lock(&up->port.lock);
1217 *status = lsr;
1218}
1219
1220static _INLINE_ void transmit_chars(struct uart_8250_port *up)
1221{
1222 struct circ_buf *xmit = &up->port.info->xmit;
1223 int count;
1224
1225 if (up->port.x_char) {
1226 serial_outp(up, UART_TX, up->port.x_char);
1227 up->port.icount.tx++;
1228 up->port.x_char = 0;
1229 return;
1230 }
b129a8cc
RK		 1231 if (uart_tx_stopped(&up->port)) {
1232 serial8250_stop_tx(&up->port);
1233 return;
1234 }
1235 if (uart_circ_empty(xmit)) {
e763b90c 1236 __stop_tx(up);
1da177e4
LT		 1237 return;
1238 }
1239
1240 count = up->tx_loadsz;
1241 do {
1242 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1243 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1244 up->port.icount.tx++;
1245 if (uart_circ_empty(xmit))
1246 break;
1247 } while (--count > 0);
1248
1249 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1250 uart_write_wakeup(&up->port);
1251
1252 DEBUG_INTR("THRE...");
1253
1254 if (uart_circ_empty(xmit))
e763b90c 1255 __stop_tx(up);
1da177e4
LT		 1256}
1257
2af7cd68 1258static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1259{
2af7cd68
RK		 1260 unsigned int status = serial_in(up, UART_MSR);
1261
1262 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI) {
1263 if (status & UART_MSR_TERI)
1264 up->port.icount.rng++;
1265 if (status & UART_MSR_DDSR)
1266 up->port.icount.dsr++;
1267 if (status & UART_MSR_DDCD)
1268 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1269 if (status & UART_MSR_DCTS)
1270 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1271
1272 wake_up_interruptible(&up->port.info->delta_msr_wait);
1273 }
1da177e4 1274
2af7cd68 1275 return status;
1da177e4
LT		 1276}
1277
1278/*
1279 * This handles the interrupt from one port.
1280 */
1281static inline void
1282serial8250_handle_port(struct uart_8250_port *up, struct pt_regs *regs)
1283{
1284 unsigned int status = serial_inp(up, UART_LSR);
1285
1286 DEBUG_INTR("status = %x...", status);
1287
1288 if (status & UART_LSR_DR)
1289 receive_chars(up, &status, regs);
1290 check_modem_status(up);
1291 if (status & UART_LSR_THRE)
1292 transmit_chars(up);
1293}
1294
1295/*
1296 * This is the serial driver's interrupt routine.
1297 *
1298 * Arjan thinks the old way was overly complex, so it got simplified.
1299 * Alan disagrees, saying that need the complexity to handle the weird
1300 * nature of ISA shared interrupts. (This is a special exception.)
1301 *
1302 * In order to handle ISA shared interrupts properly, we need to check
1303 * that all ports have been serviced, and therefore the ISA interrupt
1304 * line has been de-asserted.
1305 *
1306 * This means we need to loop through all ports. checking that they
1307 * don't have an interrupt pending.
1308 */
1309static irqreturn_t serial8250_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1310{
1311 struct irq_info *i = dev_id;
1312 struct list_head *l, *end = NULL;
1313 int pass_counter = 0, handled = 0;
1314
1315 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1316
1317 spin_lock(&i->lock);
1318
1319 l = i->head;
1320 do {
1321 struct uart_8250_port *up;
1322 unsigned int iir;
1323
1324 up = list_entry(l, struct uart_8250_port, list);
1325
1326 iir = serial_in(up, UART_IIR);
1327 if (!(iir & UART_IIR_NO_INT)) {
1328 spin_lock(&up->port.lock);
1329 serial8250_handle_port(up, regs);
1330 spin_unlock(&up->port.lock);
1331
1332 handled = 1;
1333
1334 end = NULL;
1335 } else if (end == NULL)
1336 end = l;
1337
1338 l = l->next;
1339
1340 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1341 /* If we hit this, we're dead. */
1342 printk(KERN_ERR "serial8250: too much work for "
1343 "irq%d\n", irq);
1344 break;
1345 }
1346 } while (l != end);
1347
1348 spin_unlock(&i->lock);
1349
1350 DEBUG_INTR("end.\n");
1351
1352 return IRQ_RETVAL(handled);
1353}
1354
1355/*
1356 * To support ISA shared interrupts, we need to have one interrupt
1357 * handler that ensures that the IRQ line has been deasserted
1358 * before returning. Failing to do this will result in the IRQ
1359 * line being stuck active, and, since ISA irqs are edge triggered,
1360 * no more IRQs will be seen.
1361 */
1362static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1363{
1364 spin_lock_irq(&i->lock);
1365
1366 if (!list_empty(i->head)) {
1367 if (i->head == &up->list)
1368 i->head = i->head->next;
1369 list_del(&up->list);
1370 } else {
1371 BUG_ON(i->head != &up->list);
1372 i->head = NULL;
1373 }
1374
1375 spin_unlock_irq(&i->lock);
1376}
1377
1378static int serial_link_irq_chain(struct uart_8250_port *up)
1379{
1380 struct irq_info *i = irq_lists + up->port.irq;
1381 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? SA_SHIRQ : 0;
1382
1383 spin_lock_irq(&i->lock);
1384
1385 if (i->head) {
1386 list_add(&up->list, i->head);
1387 spin_unlock_irq(&i->lock);
1388
1389 ret = 0;
1390 } else {
1391 INIT_LIST_HEAD(&up->list);
1392 i->head = &up->list;
1393 spin_unlock_irq(&i->lock);
1394
1395 ret = request_irq(up->port.irq, serial8250_interrupt,
1396 irq_flags, "serial", i);
1397 if (ret < 0)
1398 serial_do_unlink(i, up);
1399 }
1400
1401 return ret;
1402}
1403
1404static void serial_unlink_irq_chain(struct uart_8250_port *up)
1405{
1406 struct irq_info *i = irq_lists + up->port.irq;
1407
1408 BUG_ON(i->head == NULL);
1409
1410 if (list_empty(i->head))
1411 free_irq(up->port.irq, i);
1412
1413 serial_do_unlink(i, up);
1414}
1415
1416/*
1417 * This function is used to handle ports that do not have an
1418 * interrupt. This doesn't work very well for 16450's, but gives
1419 * barely passable results for a 16550A. (Although at the expense
1420 * of much CPU overhead).
1421 */
1422static void serial8250_timeout(unsigned long data)
1423{
1424 struct uart_8250_port *up = (struct uart_8250_port *)data;
1425 unsigned int timeout;
1426 unsigned int iir;
1427
1428 iir = serial_in(up, UART_IIR);
1429 if (!(iir & UART_IIR_NO_INT)) {
1430 spin_lock(&up->port.lock);
1431 serial8250_handle_port(up, NULL);
1432 spin_unlock(&up->port.lock);
1433 }
1434
1435 timeout = up->port.timeout;
1436 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1437 mod_timer(&up->timer, jiffies + timeout);
1438}
1439
1440static unsigned int serial8250_tx_empty(struct uart_port *port)
1441{
1442 struct uart_8250_port *up = (struct uart_8250_port *)port;
1443 unsigned long flags;
1444 unsigned int ret;
1445
1446 spin_lock_irqsave(&up->port.lock, flags);
1447 ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1448 spin_unlock_irqrestore(&up->port.lock, flags);
1449
1450 return ret;
1451}
1452
1453static unsigned int serial8250_get_mctrl(struct uart_port *port)
1454{
1455 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1456 unsigned int status;
1da177e4
LT		 1457 unsigned int ret;
1458
2af7cd68 1459 status = check_modem_status(up);
1da177e4
LT		 1460
1461 ret = 0;
1462 if (status & UART_MSR_DCD)
1463 ret |= TIOCM_CAR;
1464 if (status & UART_MSR_RI)
1465 ret |= TIOCM_RNG;
1466 if (status & UART_MSR_DSR)
1467 ret |= TIOCM_DSR;
1468 if (status & UART_MSR_CTS)
1469 ret |= TIOCM_CTS;
1470 return ret;
1471}
1472
1473static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1474{
1475 struct uart_8250_port *up = (struct uart_8250_port *)port;
1476 unsigned char mcr = 0;
1477
1478 if (mctrl & TIOCM_RTS)
1479 mcr |= UART_MCR_RTS;
1480 if (mctrl & TIOCM_DTR)
1481 mcr |= UART_MCR_DTR;
1482 if (mctrl & TIOCM_OUT1)
1483 mcr |= UART_MCR_OUT1;
1484 if (mctrl & TIOCM_OUT2)
1485 mcr |= UART_MCR_OUT2;
1486 if (mctrl & TIOCM_LOOP)
1487 mcr |= UART_MCR_LOOP;
1488
1489 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1490
1491 serial_out(up, UART_MCR, mcr);
1492}
1493
1494static void serial8250_break_ctl(struct uart_port *port, int break_state)
1495{
1496 struct uart_8250_port *up = (struct uart_8250_port *)port;
1497 unsigned long flags;
1498
1499 spin_lock_irqsave(&up->port.lock, flags);
1500 if (break_state == -1)
1501 up->lcr |= UART_LCR_SBC;
1502 else
1503 up->lcr &= ~UART_LCR_SBC;
1504 serial_out(up, UART_LCR, up->lcr);
1505 spin_unlock_irqrestore(&up->port.lock, flags);
1506}
1507
1508static int serial8250_startup(struct uart_port *port)
1509{
1510 struct uart_8250_port *up = (struct uart_8250_port *)port;
1511 unsigned long flags;
55d3b282 1512 unsigned char lsr, iir;
1da177e4
LT		 1513 int retval;
1514
1515 up->capabilities = uart_config[up->port.type].flags;
1516 up->mcr = 0;
1517
1518 if (up->port.type == PORT_16C950) {
1519 /* Wake up and initialize UART */
1520 up->acr = 0;
1521 serial_outp(up, UART_LCR, 0xBF);
1522 serial_outp(up, UART_EFR, UART_EFR_ECB);
1523 serial_outp(up, UART_IER, 0);
1524 serial_outp(up, UART_LCR, 0);
1525 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1526 serial_outp(up, UART_LCR, 0xBF);
1527 serial_outp(up, UART_EFR, UART_EFR_ECB);
1528 serial_outp(up, UART_LCR, 0);
1529 }
1530
1531#ifdef CONFIG_SERIAL_8250_RSA
1532 /*
1533 * If this is an RSA port, see if we can kick it up to the
1534 * higher speed clock.
1535 */
1536 enable_rsa(up);
1537#endif
1538
1539 /*
1540 * Clear the FIFO buffers and disable them.
1541 * (they will be reeanbled in set_termios())
1542 */
1543 serial8250_clear_fifos(up);
1544
1545 /*
1546 * Clear the interrupt registers.
1547 */
1548 (void) serial_inp(up, UART_LSR);
1549 (void) serial_inp(up, UART_RX);
1550 (void) serial_inp(up, UART_IIR);
1551 (void) serial_inp(up, UART_MSR);
1552
1553 /*
1554 * At this point, there's no way the LSR could still be 0xff;
1555 * if it is, then bail out, because there's likely no UART
1556 * here.
1557 */
1558 if (!(up->port.flags & UPF_BUGGY_UART) &&
1559 (serial_inp(up, UART_LSR) == 0xff)) {
1560 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1561 return -ENODEV;
1562 }
1563
1564 /*
1565 * For a XR16C850, we need to set the trigger levels
1566 */
1567 if (up->port.type == PORT_16850) {
1568 unsigned char fctr;
1569
1570 serial_outp(up, UART_LCR, 0xbf);
1571
1572 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1573 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1574 serial_outp(up, UART_TRG, UART_TRG_96);
1575 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1576 serial_outp(up, UART_TRG, UART_TRG_96);
1577
1578 serial_outp(up, UART_LCR, 0);
1579 }
1580
1581 /*
1582 * If the "interrupt" for this port doesn't correspond with any
1583 * hardware interrupt, we use a timer-based system. The original
1584 * driver used to do this with IRQ0.
1585 */
1586 if (!is_real_interrupt(up->port.irq)) {
1587 unsigned int timeout = up->port.timeout;
1588
1589 timeout = timeout > 6 ? (timeout / 2 - 2) : 1;
1590
1591 up->timer.data = (unsigned long)up;
1592 mod_timer(&up->timer, jiffies + timeout);
1593 } else {
1594 retval = serial_link_irq_chain(up);
1595 if (retval)
1596 return retval;
1597 }
1598
1599 /*
1600 * Now, initialize the UART
1601 */
1602 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1603
1604 spin_lock_irqsave(&up->port.lock, flags);
1605 if (up->port.flags & UPF_FOURPORT) {
1606 if (!is_real_interrupt(up->port.irq))
1607 up->port.mctrl |= TIOCM_OUT1;
1608 } else
1609 /*
1610 * Most PC uarts need OUT2 raised to enable interrupts.
1611 */
1612 if (is_real_interrupt(up->port.irq))
1613 up->port.mctrl |= TIOCM_OUT2;
1614
1615 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282
RK		 1616
1617 /*
1618 * Do a quick test to see if we receive an
1619 * interrupt when we enable the TX irq.
1620 */
1621 serial_outp(up, UART_IER, UART_IER_THRI);
1622 lsr = serial_in(up, UART_LSR);
1623 iir = serial_in(up, UART_IIR);
1624 serial_outp(up, UART_IER, 0);
1625
1626 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 1627 if (!(up->bugs & UART_BUG_TXEN)) {
1628 up->bugs |= UART_BUG_TXEN;
55d3b282
RK		 1629 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1630 port->line);
1631 }
1632 } else {
67f7654e 1633 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 1634 }
1635
1da177e4
LT		 1636 spin_unlock_irqrestore(&up->port.lock, flags);
1637
1638 /*
1639 * Finally, enable interrupts. Note: Modem status interrupts
1640 * are set via set_termios(), which will be occurring imminently
1641 * anyway, so we don't enable them here.
1642 */
1643 up->ier = UART_IER_RLSI | UART_IER_RDI;
1644 serial_outp(up, UART_IER, up->ier);
1645
1646 if (up->port.flags & UPF_FOURPORT) {
1647 unsigned int icp;
1648 /*
1649 * Enable interrupts on the AST Fourport board
1650 */
1651 icp = (up->port.iobase & 0xfe0) | 0x01f;
1652 outb_p(0x80, icp);
1653 (void) inb_p(icp);
1654 }
1655
1656 /*
1657 * And clear the interrupt registers again for luck.
1658 */
1659 (void) serial_inp(up, UART_LSR);
1660 (void) serial_inp(up, UART_RX);
1661 (void) serial_inp(up, UART_IIR);
1662 (void) serial_inp(up, UART_MSR);
1663
1664 return 0;
1665}
1666
1667static void serial8250_shutdown(struct uart_port *port)
1668{
1669 struct uart_8250_port *up = (struct uart_8250_port *)port;
1670 unsigned long flags;
1671
1672 /*
1673 * Disable interrupts from this port
1674 */
1675 up->ier = 0;
1676 serial_outp(up, UART_IER, 0);
1677
1678 spin_lock_irqsave(&up->port.lock, flags);
1679 if (up->port.flags & UPF_FOURPORT) {
1680 /* reset interrupts on the AST Fourport board */
1681 inb((up->port.iobase & 0xfe0) | 0x1f);
1682 up->port.mctrl |= TIOCM_OUT1;
1683 } else
1684 up->port.mctrl &= ~TIOCM_OUT2;
1685
1686 serial8250_set_mctrl(&up->port, up->port.mctrl);
1687 spin_unlock_irqrestore(&up->port.lock, flags);
1688
1689 /*
1690 * Disable break condition and FIFOs
1691 */
1692 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
1693 serial8250_clear_fifos(up);
1694
1695#ifdef CONFIG_SERIAL_8250_RSA
1696 /*
1697 * Reset the RSA board back to 115kbps compat mode.
1698 */
1699 disable_rsa(up);
1700#endif
1701
1702 /*
1703 * Read data port to reset things, and then unlink from
1704 * the IRQ chain.
1705 */
1706 (void) serial_in(up, UART_RX);
1707
1708 if (!is_real_interrupt(up->port.irq))
1709 del_timer_sync(&up->timer);
1710 else
1711 serial_unlink_irq_chain(up);
1712}
1713
1714static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
1715{
1716 unsigned int quot;
1717
1718 /*
1719 * Handle magic divisors for baud rates above baud_base on
1720 * SMSC SuperIO chips.
1721 */
1722 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1723 baud == (port->uartclk/4))
1724 quot = 0x8001;
1725 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
1726 baud == (port->uartclk/8))
1727 quot = 0x8002;
1728 else
1729 quot = uart_get_divisor(port, baud);
1730
1731 return quot;
1732}
1733
1734static void
1735serial8250_set_termios(struct uart_port *port, struct termios *termios,
1736 struct termios *old)
1737{
1738 struct uart_8250_port *up = (struct uart_8250_port *)port;
1739 unsigned char cval, fcr = 0;
1740 unsigned long flags;
1741 unsigned int baud, quot;
1742
1743 switch (termios->c_cflag & CSIZE) {
1744 case CS5:
0a8b80c5 1745 cval = UART_LCR_WLEN5;
1da177e4
LT		 1746 break;
1747 case CS6:
0a8b80c5 1748 cval = UART_LCR_WLEN6;
1da177e4
LT		 1749 break;
1750 case CS7:
0a8b80c5 1751 cval = UART_LCR_WLEN7;
1da177e4
LT		 1752 break;
1753 default:
1754 case CS8:
0a8b80c5 1755 cval = UART_LCR_WLEN8;
1da177e4
LT		 1756 break;
1757 }
1758
1759 if (termios->c_cflag & CSTOPB)
0a8b80c5 1760 cval |= UART_LCR_STOP;
1da177e4
LT		 1761 if (termios->c_cflag & PARENB)
1762 cval |= UART_LCR_PARITY;
1763 if (!(termios->c_cflag & PARODD))
1764 cval |= UART_LCR_EPAR;
1765#ifdef CMSPAR
1766 if (termios->c_cflag & CMSPAR)
1767 cval |= UART_LCR_SPAR;
1768#endif
1769
1770 /*
1771 * Ask the core to calculate the divisor for us.
1772 */
1773 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
1774 quot = serial8250_get_divisor(port, baud);
1775
1776 /*
4ba5e35d 1777 * Oxford Semi 952 rev B workaround
1da177e4 1778 */
4ba5e35d 1779 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
1da177e4
LT		 1780 quot ++;
1781
1782 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
1783 if (baud < 2400)
1784 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
1785 else
1786 fcr = uart_config[up->port.type].fcr;
1787 }
1788
1789 /*
1790 * MCR-based auto flow control. When AFE is enabled, RTS will be
1791 * deasserted when the receive FIFO contains more characters than
1792 * the trigger, or the MCR RTS bit is cleared. In the case where
1793 * the remote UART is not using CTS auto flow control, we must
1794 * have sufficient FIFO entries for the latency of the remote
1795 * UART to respond. IOW, at least 32 bytes of FIFO.
1796 */
1797 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
1798 up->mcr &= ~UART_MCR_AFE;
1799 if (termios->c_cflag & CRTSCTS)
1800 up->mcr |= UART_MCR_AFE;
1801 }
1802
1803 /*
1804 * Ok, we're now changing the port state. Do it with
1805 * interrupts disabled.
1806 */
1807 spin_lock_irqsave(&up->port.lock, flags);
1808
1809 /*
1810 * Update the per-port timeout.
1811 */
1812 uart_update_timeout(port, termios->c_cflag, baud);
1813
1814 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
1815 if (termios->c_iflag & INPCK)
1816 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
1817 if (termios->c_iflag & (BRKINT | PARMRK))
1818 up->port.read_status_mask |= UART_LSR_BI;
1819
1820 /*
1821 * Characteres to ignore
1822 */
1823 up->port.ignore_status_mask = 0;
1824 if (termios->c_iflag & IGNPAR)
1825 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
1826 if (termios->c_iflag & IGNBRK) {
1827 up->port.ignore_status_mask |= UART_LSR_BI;
1828 /*
1829 * If we're ignoring parity and break indicators,
1830 * ignore overruns too (for real raw support).
1831 */
1832 if (termios->c_iflag & IGNPAR)
1833 up->port.ignore_status_mask |= UART_LSR_OE;
1834 }
1835
1836 /*
1837 * ignore all characters if CREAD is not set
1838 */
1839 if ((termios->c_cflag & CREAD) == 0)
1840 up->port.ignore_status_mask |= UART_LSR_DR;
1841
1842 /*
1843 * CTS flow control flag and modem status interrupts
1844 */
1845 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 1846 if (!(up->bugs & UART_BUG_NOMSR) &&
1847 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 1848 up->ier |= UART_IER_MSI;
1849 if (up->capabilities & UART_CAP_UUE)
1850 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
1851
1852 serial_out(up, UART_IER, up->ier);
1853
1854 if (up->capabilities & UART_CAP_EFR) {
1855 unsigned char efr = 0;
1856 /*
1857 * TI16C752/Startech hardware flow control. FIXME:
1858 * - TI16C752 requires control thresholds to be set.
1859 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
1860 */
1861 if (termios->c_cflag & CRTSCTS)
1862 efr |= UART_EFR_CTS;
1863
1864 serial_outp(up, UART_LCR, 0xBF);
1865 serial_outp(up, UART_EFR, efr);
1866 }
1867
1868 if (up->capabilities & UART_NATSEMI) {
1869 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
1870 serial_outp(up, UART_LCR, 0xe0);
1871 } else {
1872 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
1873 }
1874
1875 serial_outp(up, UART_DLL, quot & 0xff); /* LS of divisor */
1876 serial_outp(up, UART_DLM, quot >> 8); /* MS of divisor */
1877
1878 /*
1879 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
1880 * is written without DLAB set, this mode will be disabled.
1881 */
1882 if (up->port.type == PORT_16750)
1883 serial_outp(up, UART_FCR, fcr);
1884
1885 serial_outp(up, UART_LCR, cval); /* reset DLAB */
1886 up->lcr = cval; /* Save LCR */
1887 if (up->port.type != PORT_16750) {
1888 if (fcr & UART_FCR_ENABLE_FIFO) {
1889 /* emulated UARTs (Lucent Venus 167x) need two steps */
1890 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1891 }
1892 serial_outp(up, UART_FCR, fcr); /* set fcr */
1893 }
1894 serial8250_set_mctrl(&up->port, up->port.mctrl);
1895 spin_unlock_irqrestore(&up->port.lock, flags);
1896}
1897
1898static void
1899serial8250_pm(struct uart_port *port, unsigned int state,
1900 unsigned int oldstate)
1901{
1902 struct uart_8250_port *p = (struct uart_8250_port *)port;
1903
1904 serial8250_set_sleep(p, state != 0);
1905
1906 if (p->pm)
1907 p->pm(port, state, oldstate);
1908}
1909
1910/*
1911 * Resource handling.
1912 */
1913static int serial8250_request_std_resource(struct uart_8250_port *up)
1914{
1915 unsigned int size = 8 << up->port.regshift;
1916 int ret = 0;
1917
1918 switch (up->port.iotype) {
1919 case UPIO_MEM:
1920 if (!up->port.mapbase)
1921 break;
1922
1923 if (!request_mem_region(up->port.mapbase, size, "serial")) {
1924 ret = -EBUSY;
1925 break;
1926 }
1927
1928 if (up->port.flags & UPF_IOREMAP) {
1929 up->port.membase = ioremap(up->port.mapbase, size);
1930 if (!up->port.membase) {
1931 release_mem_region(up->port.mapbase, size);
1932 ret = -ENOMEM;
1933 }
1934 }
1935 break;
1936
1937 case UPIO_HUB6:
1938 case UPIO_PORT:
1939 if (!request_region(up->port.iobase, size, "serial"))
1940 ret = -EBUSY;
1941 break;
1942 }
1943 return ret;
1944}
1945
1946static void serial8250_release_std_resource(struct uart_8250_port *up)
1947{
1948 unsigned int size = 8 << up->port.regshift;
1949
1950 switch (up->port.iotype) {
1951 case UPIO_MEM:
1952 if (!up->port.mapbase)
1953 break;
1954
1955 if (up->port.flags & UPF_IOREMAP) {
1956 iounmap(up->port.membase);
1957 up->port.membase = NULL;
1958 }
1959
1960 release_mem_region(up->port.mapbase, size);
1961 break;
1962
1963 case UPIO_HUB6:
1964 case UPIO_PORT:
1965 release_region(up->port.iobase, size);
1966 break;
1967 }
1968}
1969
1970static int serial8250_request_rsa_resource(struct uart_8250_port *up)
1971{
1972 unsigned long start = UART_RSA_BASE << up->port.regshift;
1973 unsigned int size = 8 << up->port.regshift;
1974 int ret = 0;
1975
1976 switch (up->port.iotype) {
1977 case UPIO_MEM:
1978 ret = -EINVAL;
1979 break;
1980
1981 case UPIO_HUB6:
1982 case UPIO_PORT:
1983 start += up->port.iobase;
1984 if (!request_region(start, size, "serial-rsa"))
1985 ret = -EBUSY;
1986 break;
1987 }
1988
1989 return ret;
1990}
1991
1992static void serial8250_release_rsa_resource(struct uart_8250_port *up)
1993{
1994 unsigned long offset = UART_RSA_BASE << up->port.regshift;
1995 unsigned int size = 8 << up->port.regshift;
1996
1997 switch (up->port.iotype) {
1998 case UPIO_MEM:
1999 break;
2000
2001 case UPIO_HUB6:
2002 case UPIO_PORT:
2003 release_region(up->port.iobase + offset, size);
2004 break;
2005 }
2006}
2007
2008static void serial8250_release_port(struct uart_port *port)
2009{
2010 struct uart_8250_port *up = (struct uart_8250_port *)port;
2011
2012 serial8250_release_std_resource(up);
2013 if (up->port.type == PORT_RSA)
2014 serial8250_release_rsa_resource(up);
2015}
2016
2017static int serial8250_request_port(struct uart_port *port)
2018{
2019 struct uart_8250_port *up = (struct uart_8250_port *)port;
2020 int ret = 0;
2021
2022 ret = serial8250_request_std_resource(up);
2023 if (ret == 0 && up->port.type == PORT_RSA) {
2024 ret = serial8250_request_rsa_resource(up);
2025 if (ret < 0)
2026 serial8250_release_std_resource(up);
2027 }
2028
2029 return ret;
2030}
2031
2032static void serial8250_config_port(struct uart_port *port, int flags)
2033{
2034 struct uart_8250_port *up = (struct uart_8250_port *)port;
2035 int probeflags = PROBE_ANY;
2036 int ret;
2037
2038 /*
2039 * Don't probe for MCA ports on non-MCA machines.
2040 */
2041 if (up->port.flags & UPF_BOOT_ONLYMCA && !MCA_bus)
2042 return;
2043
2044 /*
2045 * Find the region that we can probe for. This in turn
2046 * tells us whether we can probe for the type of port.
2047 */
2048 ret = serial8250_request_std_resource(up);
2049 if (ret < 0)
2050 return;
2051
2052 ret = serial8250_request_rsa_resource(up);
2053 if (ret < 0)
2054 probeflags &= ~PROBE_RSA;
2055
2056 if (flags & UART_CONFIG_TYPE)
2057 autoconfig(up, probeflags);
2058 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2059 autoconfig_irq(up);
2060
2061 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2062 serial8250_release_rsa_resource(up);
2063 if (up->port.type == PORT_UNKNOWN)
2064 serial8250_release_std_resource(up);
2065}
2066
2067static int
2068serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2069{
2070 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2071 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2072 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2073 ser->type == PORT_STARTECH)
2074 return -EINVAL;
2075 return 0;
2076}
2077
2078static const char *
2079serial8250_type(struct uart_port *port)
2080{
2081 int type = port->type;
2082
2083 if (type >= ARRAY_SIZE(uart_config))
2084 type = 0;
2085 return uart_config[type].name;
2086}
2087
2088static struct uart_ops serial8250_pops = {
2089 .tx_empty = serial8250_tx_empty,
2090 .set_mctrl = serial8250_set_mctrl,
2091 .get_mctrl = serial8250_get_mctrl,
2092 .stop_tx = serial8250_stop_tx,
2093 .start_tx = serial8250_start_tx,
2094 .stop_rx = serial8250_stop_rx,
2095 .enable_ms = serial8250_enable_ms,
2096 .break_ctl = serial8250_break_ctl,
2097 .startup = serial8250_startup,
2098 .shutdown = serial8250_shutdown,
2099 .set_termios = serial8250_set_termios,
2100 .pm = serial8250_pm,
2101 .type = serial8250_type,
2102 .release_port = serial8250_release_port,
2103 .request_port = serial8250_request_port,
2104 .config_port = serial8250_config_port,
2105 .verify_port = serial8250_verify_port,
2106};
2107
2108static struct uart_8250_port serial8250_ports[UART_NR];
2109
2110static void __init serial8250_isa_init_ports(void)
2111{
2112 struct uart_8250_port *up;
2113 static int first = 1;
2114 int i;
2115
2116 if (!first)
2117 return;
2118 first = 0;
2119
2120 for (i = 0; i < UART_NR; i++) {
2121 struct uart_8250_port *up = &serial8250_ports[i];
2122
2123 up->port.line = i;
2124 spin_lock_init(&up->port.lock);
2125
2126 init_timer(&up->timer);
2127 up->timer.function = serial8250_timeout;
2128
2129 /*
2130 * ALPHA_KLUDGE_MCR needs to be killed.
2131 */
2132 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2133 up->mcr_force = ALPHA_KLUDGE_MCR;
2134
2135 up->port.ops = &serial8250_pops;
2136 }
2137
44454bcd
RK		 2138 for (i = 0, up = serial8250_ports;
2139 i < ARRAY_SIZE(old_serial_port) && i < UART_NR;
1da177e4
LT		 2140 i++, up++) {
2141 up->port.iobase = old_serial_port[i].port;
2142 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2143 up->port.uartclk = old_serial_port[i].baud_base * 16;
2144 up->port.flags = old_serial_port[i].flags;
2145 up->port.hub6 = old_serial_port[i].hub6;
2146 up->port.membase = old_serial_port[i].iomem_base;
2147 up->port.iotype = old_serial_port[i].io_type;
2148 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2149 if (share_irqs)
2150 up->port.flags |= UPF_SHARE_IRQ;
2151 }
2152}
2153
2154static void __init
2155serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2156{
2157 int i;
2158
2159 serial8250_isa_init_ports();
2160
2161 for (i = 0; i < UART_NR; i++) {
2162 struct uart_8250_port *up = &serial8250_ports[i];
2163
2164 up->port.dev = dev;
2165 uart_add_one_port(drv, &up->port);
2166 }
2167}
2168
2169#ifdef CONFIG_SERIAL_8250_CONSOLE
2170
2171#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
2172
2173/*
2174 * Wait for transmitter & holding register to empty
2175 */
2176static inline void wait_for_xmitr(struct uart_8250_port *up)
2177{
2178 unsigned int status, tmout = 10000;
2179
2180 /* Wait up to 10ms for the character(s) to be sent. */
2181 do {
2182 status = serial_in(up, UART_LSR);
2183
2184 if (status & UART_LSR_BI)
2185 up->lsr_break_flag = UART_LSR_BI;
2186
2187 if (--tmout == 0)
2188 break;
2189 udelay(1);
2190 } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
2191
2192 /* Wait up to 1s for flow control if necessary */
2193 if (up->port.flags & UPF_CONS_FLOW) {
2194 tmout = 1000000;
2195 while (--tmout &&
2196 ((serial_in(up, UART_MSR) & UART_MSR_CTS) == 0))
2197 udelay(1);
2198 }
2199}
2200
2201/*
2202 * Print a string to the serial port trying not to disturb
2203 * any possible real use of the port...
2204 *
2205 * The console_lock must be held when we get here.
2206 */
2207static void
2208serial8250_console_write(struct console *co, const char *s, unsigned int count)
2209{
2210 struct uart_8250_port *up = &serial8250_ports[co->index];
2211 unsigned int ier;
2212 int i;
2213
78512ece
AM		 2214 touch_nmi_watchdog();
2215
1da177e4
LT		 2216 /*
2217 * First save the UER then disable the interrupts
2218 */
2219 ier = serial_in(up, UART_IER);
2220
2221 if (up->capabilities & UART_CAP_UUE)
2222 serial_out(up, UART_IER, UART_IER_UUE);
2223 else
2224 serial_out(up, UART_IER, 0);
2225
2226 /*
2227 * Now, do each character
2228 */
2229 for (i = 0; i < count; i++, s++) {
2230 wait_for_xmitr(up);
2231
2232 /*
2233 * Send the character out.
2234 * If a LF, also do CR...
2235 */
2236 serial_out(up, UART_TX, *s);
2237 if (*s == 10) {
2238 wait_for_xmitr(up);
2239 serial_out(up, UART_TX, 13);
2240 }
2241 }
2242
2243 /*
2244 * Finally, wait for transmitter to become empty
2245 * and restore the IER
2246 */
2247 wait_for_xmitr(up);
2248 serial_out(up, UART_IER, ier);
2249}
2250
2251static int serial8250_console_setup(struct console *co, char *options)
2252{
2253 struct uart_port *port;
2254 int baud = 9600;
2255 int bits = 8;
2256 int parity = 'n';
2257 int flow = 'n';
2258
2259 /*
2260 * Check whether an invalid uart number has been specified, and
2261 * if so, search for the first available port that does have
2262 * console support.
2263 */
2264 if (co->index >= UART_NR)
2265 co->index = 0;
2266 port = &serial8250_ports[co->index].port;
2267 if (!port->iobase && !port->membase)
2268 return -ENODEV;
2269
2270 if (options)
2271 uart_parse_options(options, &baud, &parity, &bits, &flow);
2272
2273 return uart_set_options(port, co, baud, parity, bits, flow);
2274}
2275
2276static struct uart_driver serial8250_reg;
2277static struct console serial8250_console = {
2278 .name = "ttyS",
2279 .write = serial8250_console_write,
2280 .device = uart_console_device,
2281 .setup = serial8250_console_setup,
2282 .flags = CON_PRINTBUFFER,
2283 .index = -1,
2284 .data = &serial8250_reg,
2285};
2286
2287static int __init serial8250_console_init(void)
2288{
2289 serial8250_isa_init_ports();
2290 register_console(&serial8250_console);
2291 return 0;
2292}
2293console_initcall(serial8250_console_init);
2294
2295static int __init find_port(struct uart_port *p)
2296{
2297 int line;
2298 struct uart_port *port;
2299
2300 for (line = 0; line < UART_NR; line++) {
2301 port = &serial8250_ports[line].port;
2302 if (p->iotype == port->iotype &&
2303 p->iobase == port->iobase &&
2304 p->membase == port->membase)
2305 return line;
2306 }
2307 return -ENODEV;
2308}
2309
2310int __init serial8250_start_console(struct uart_port *port, char *options)
2311{
2312 int line;
2313
2314 line = find_port(port);
2315 if (line < 0)
2316 return -ENODEV;
2317
2318 add_preferred_console("ttyS", line, options);
2319 printk("Adding console on ttyS%d at %s 0x%lx (options '%s')\n",
2320 line, port->iotype == UPIO_MEM ? "MMIO" : "I/O port",
2321 port->iotype == UPIO_MEM ? (unsigned long) port->mapbase :
2322 (unsigned long) port->iobase, options);
2323 if (!(serial8250_console.flags & CON_ENABLED)) {
2324 serial8250_console.flags &= ~CON_PRINTBUFFER;
2325 register_console(&serial8250_console);
2326 }
2327 return line;
2328}
2329
2330#define SERIAL8250_CONSOLE &serial8250_console
2331#else
2332#define SERIAL8250_CONSOLE NULL
2333#endif
2334
2335static struct uart_driver serial8250_reg = {
2336 .owner = THIS_MODULE,
2337 .driver_name = "serial",
2338 .devfs_name = "tts/",
2339 .dev_name = "ttyS",
2340 .major = TTY_MAJOR,
2341 .minor = 64,
2342 .nr = UART_NR,
2343 .cons = SERIAL8250_CONSOLE,
2344};
2345
2346int __init early_serial_setup(struct uart_port *port)
2347{
2348 if (port->line >= ARRAY_SIZE(serial8250_ports))
2349 return -ENODEV;
2350
2351 serial8250_isa_init_ports();
2352 serial8250_ports[port->line].port = *port;
2353 serial8250_ports[port->line].port.ops = &serial8250_pops;
2354 return 0;
2355}
2356
2357/**
2358 * serial8250_suspend_port - suspend one serial port
2359 * @line: serial line number
2360 * @level: the level of port suspension, as per uart_suspend_port
2361 *
2362 * Suspend one serial port.
2363 */
2364void serial8250_suspend_port(int line)
2365{
2366 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2367}
2368
2369/**
2370 * serial8250_resume_port - resume one serial port
2371 * @line: serial line number
2372 * @level: the level of port resumption, as per uart_resume_port
2373 *
2374 * Resume one serial port.
2375 */
2376void serial8250_resume_port(int line)
2377{
2378 uart_resume_port(&serial8250_reg, &serial8250_ports[line].port);
2379}
2380
2381/*
2382 * Register a set of serial devices attached to a platform device. The
2383 * list is terminated with a zero flags entry, which means we expect
2384 * all entries to have at least UPF_BOOT_AUTOCONF set.
2385 */
3ae5eaec 2386static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2387{
3ae5eaec 2388 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2389 struct uart_port port;
ec9f47cd 2390 int ret, i;
1da177e4
LT		 2391
2392 memset(&port, 0, sizeof(struct uart_port));
2393
ec9f47cd 2394 for (i = 0; p && p->flags != 0; p++, i++) {
1da177e4
LT		 2395 port.iobase = p->iobase;
2396 port.membase = p->membase;
2397 port.irq = p->irq;
2398 port.uartclk = p->uartclk;
2399 port.regshift = p->regshift;
2400 port.iotype = p->iotype;
2401 port.flags = p->flags;
2402 port.mapbase = p->mapbase;
ec9f47cd 2403 port.hub6 = p->hub6;
3ae5eaec 2404 port.dev = &dev->dev;
1da177e4
LT		 2405 if (share_irqs)
2406 port.flags |= UPF_SHARE_IRQ;
ec9f47cd
RK		 2407 ret = serial8250_register_port(&port);
2408 if (ret < 0) {
3ae5eaec 2409 dev_err(&dev->dev, "unable to register port at index %d "
ec9f47cd
RK		 2410 "(IO%lx MEM%lx IRQ%d): %d\n", i,
2411 p->iobase, p->mapbase, p->irq, ret);
2412 }
1da177e4
LT		 2413 }
2414 return 0;
2415}
2416
2417/*
2418 * Remove serial ports registered against a platform device.
2419 */
3ae5eaec 2420static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2421{
2422 int i;
2423
2424 for (i = 0; i < UART_NR; i++) {
2425 struct uart_8250_port *up = &serial8250_ports[i];
2426
3ae5eaec 2427 if (up->port.dev == &dev->dev)
1da177e4
LT		 2428 serial8250_unregister_port(i);
2429 }
2430 return 0;
2431}
2432
3ae5eaec 2433static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2434{
2435 int i;
2436
1da177e4
LT		 2437 for (i = 0; i < UART_NR; i++) {
2438 struct uart_8250_port *up = &serial8250_ports[i];
2439
3ae5eaec 2440 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2441 uart_suspend_port(&serial8250_reg, &up->port);
2442 }
2443
2444 return 0;
2445}
2446
3ae5eaec 2447static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 2448{
2449 int i;
2450
1da177e4
LT		 2451 for (i = 0; i < UART_NR; i++) {
2452 struct uart_8250_port *up = &serial8250_ports[i];
2453
3ae5eaec 2454 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 2455 uart_resume_port(&serial8250_reg, &up->port);
2456 }
2457
2458 return 0;
2459}
2460
3ae5eaec 2461static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 2462 .probe = serial8250_probe,
2463 .remove = __devexit_p(serial8250_remove),
2464 .suspend = serial8250_suspend,
2465 .resume = serial8250_resume,
3ae5eaec
RK		 2466 .driver = {
2467 .name = "serial8250",
2468 },
1da177e4
LT		 2469};
2470
2471/*
2472 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2473 * in the table in include/asm/serial.h
2474 */
2475static struct platform_device *serial8250_isa_devs;
2476
2477/*
2478 * serial8250_register_port and serial8250_unregister_port allows for
2479 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2480 * modems and PCI multiport cards.
2481 */
2482static DECLARE_MUTEX(serial_sem);
2483
2484static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2485{
2486 int i;
2487
2488 /*
2489 * First, find a port entry which matches.
2490 */
2491 for (i = 0; i < UART_NR; i++)
2492 if (uart_match_port(&serial8250_ports[i].port, port))
2493 return &serial8250_ports[i];
2494
2495 /*
2496 * We didn't find a matching entry, so look for the first
2497 * free entry. We look for one which hasn't been previously
2498 * used (indicated by zero iobase).
2499 */
2500 for (i = 0; i < UART_NR; i++)
2501 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2502 serial8250_ports[i].port.iobase == 0)
2503 return &serial8250_ports[i];
2504
2505 /*
2506 * That also failed. Last resort is to find any entry which
2507 * doesn't have a real port associated with it.
2508 */
2509 for (i = 0; i < UART_NR; i++)
2510 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2511 return &serial8250_ports[i];
2512
2513 return NULL;
2514}
2515
2516/**
2517 * serial8250_register_port - register a serial port
2518 * @port: serial port template
2519 *
2520 * Configure the serial port specified by the request. If the
2521 * port exists and is in use, it is hung up and unregistered
2522 * first.
2523 *
2524 * The port is then probed and if necessary the IRQ is autodetected
2525 * If this fails an error is returned.
2526 *
2527 * On success the port is ready to use and the line number is returned.
2528 */
2529int serial8250_register_port(struct uart_port *port)
2530{
2531 struct uart_8250_port *uart;
2532 int ret = -ENOSPC;
2533
2534 if (port->uartclk == 0)
2535 return -EINVAL;
2536
2537 down(&serial_sem);
2538
2539 uart = serial8250_find_match_or_unused(port);
2540 if (uart) {
2541 uart_remove_one_port(&serial8250_reg, &uart->port);
2542
2543 uart->port.iobase = port->iobase;
2544 uart->port.membase = port->membase;
2545 uart->port.irq = port->irq;
2546 uart->port.uartclk = port->uartclk;
2547 uart->port.fifosize = port->fifosize;
2548 uart->port.regshift = port->regshift;
2549 uart->port.iotype = port->iotype;
2550 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2551 uart->port.mapbase = port->mapbase;
2552 if (port->dev)
2553 uart->port.dev = port->dev;
2554
2555 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2556 if (ret == 0)
2557 ret = uart->port.line;
2558 }
2559 up(&serial_sem);
2560
2561 return ret;
2562}
2563EXPORT_SYMBOL(serial8250_register_port);
2564
2565/**
2566 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2567 * @line: serial line number
2568 *
2569 * Remove one serial port. This may not be called from interrupt
2570 * context. We hand the port back to the our control.
2571 */
2572void serial8250_unregister_port(int line)
2573{
2574 struct uart_8250_port *uart = &serial8250_ports[line];
2575
2576 down(&serial_sem);
2577 uart_remove_one_port(&serial8250_reg, &uart->port);
2578 if (serial8250_isa_devs) {
2579 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2580 uart->port.type = PORT_UNKNOWN;
2581 uart->port.dev = &serial8250_isa_devs->dev;
2582 uart_add_one_port(&serial8250_reg, &uart->port);
2583 } else {
2584 uart->port.dev = NULL;
2585 }
2586 up(&serial_sem);
2587}
2588EXPORT_SYMBOL(serial8250_unregister_port);
2589
2590static int __init serial8250_init(void)
2591{
2592 int ret, i;
2593
2594 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2595 "%d ports, IRQ sharing %sabled\n", (int) UART_NR,
2596 share_irqs ? "en" : "dis");
2597
2598 for (i = 0; i < NR_IRQS; i++)
2599 spin_lock_init(&irq_lists[i].lock);
2600
2601 ret = uart_register_driver(&serial8250_reg);
2602 if (ret)
2603 goto out;
2604
2605 serial8250_isa_devs = platform_device_register_simple("serial8250",
6df29deb 2606 PLAT8250_DEV_LEGACY, NULL, 0);
1da177e4
LT		 2607 if (IS_ERR(serial8250_isa_devs)) {
2608 ret = PTR_ERR(serial8250_isa_devs);
2609 goto unreg;
2610 }
2611
2612 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2613
3ae5eaec 2614 ret = platform_driver_register(&serial8250_isa_driver);
1da177e4
LT		 2615 if (ret == 0)
2616 goto out;
2617
2618 platform_device_unregister(serial8250_isa_devs);
2619 unreg:
2620 uart_unregister_driver(&serial8250_reg);
2621 out:
2622 return ret;
2623}
2624
2625static void __exit serial8250_exit(void)
2626{
2627 struct platform_device *isa_dev = serial8250_isa_devs;
2628
2629 /*
2630 * This tells serial8250_unregister_port() not to re-register
2631 * the ports (thereby making serial8250_isa_driver permanently
2632 * in use.)
2633 */
2634 serial8250_isa_devs = NULL;
2635
3ae5eaec 2636 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 2637 platform_device_unregister(isa_dev);
2638
2639 uart_unregister_driver(&serial8250_reg);
2640}
2641
2642module_init(serial8250_init);
2643module_exit(serial8250_exit);
2644
2645EXPORT_SYMBOL(serial8250_suspend_port);
2646EXPORT_SYMBOL(serial8250_resume_port);
2647
2648MODULE_LICENSE("GPL");
2649MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2650
2651module_param(share_irqs, uint, 0644);
2652MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
2653 " (unsafe)");
2654
2655#ifdef CONFIG_SERIAL_8250_RSA
2656module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
2657MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
2658#endif
2659MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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