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[net-next-2.6.git] / drivers / serial / 8250.c
CommitLineData
1da177e4
LT		 1/*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
1da177e4
LT		 15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
1da177e4
LT		 20
21#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22#define SUPPORT_SYSRQ
23#endif
24
25#include <linux/module.h>
26#include <linux/moduleparam.h>
27#include <linux/ioport.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/sysrq.h>
1da177e4 31#include <linux/delay.h>
d052d1be 32#include <linux/platform_device.h>
1da177e4
LT		 33#include <linux/tty.h>
34#include <linux/tty_flip.h>
35#include <linux/serial_reg.h>
36#include <linux/serial_core.h>
37#include <linux/serial.h>
38#include <linux/serial_8250.h>
78512ece 39#include <linux/nmi.h>
f392ecfa 40#include <linux/mutex.h>
1da177e4
LT		 41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
b70ac771
DM		 47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
1da177e4
LT		 51/*
52 * Configuration:
40663cc7 53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
1da177e4
LT		 54 * is unsafe when used on edge-triggered interrupts.
55 */
408b664a 56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
1da177e4 57
a61c2d78
DJ		 58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
8440838b
DM		 60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
d41a4b51
CE		 67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
1da177e4
LT		 69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 256
85
86/*
87 * We default to IRQ0 for the "no irq" hack. Some
88 * machine types want others as well - they're free
89 * to redefine this in their header file.
90 */
91#define is_real_interrupt(irq) ((irq) != 0)
92
1da177e4
LT		 93#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
94#define CONFIG_SERIAL_DETECT_IRQ 1
95#endif
1da177e4
LT		 96#ifdef CONFIG_SERIAL_8250_MANY_PORTS
97#define CONFIG_SERIAL_MANY_PORTS 1
98#endif
99
100/*
101 * HUB6 is always on. This will be removed once the header
102 * files have been cleaned.
103 */
104#define CONFIG_HUB6 1
105
a4ed1e41 106#include <asm/serial.h>
1da177e4
LT		 107/*
108 * SERIAL_PORT_DFNS tells us about built-in ports that have no
109 * standard enumeration mechanism. Platforms that can find all
110 * serial ports via mechanisms like ACPI or PCI need not supply it.
111 */
112#ifndef SERIAL_PORT_DFNS
113#define SERIAL_PORT_DFNS
114#endif
115
cb3592be 116static const struct old_serial_port old_serial_port[] = {
1da177e4
LT		 117 SERIAL_PORT_DFNS /* defined in asm/serial.h */
118};
119
026d02a2 120#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
1da177e4
LT		 121
122#ifdef CONFIG_SERIAL_8250_RSA
123
124#define PORT_RSA_MAX 4
125static unsigned long probe_rsa[PORT_RSA_MAX];
126static unsigned int probe_rsa_count;
127#endif /* CONFIG_SERIAL_8250_RSA */
128
129struct uart_8250_port {
130 struct uart_port port;
131 struct timer_list timer; /* "no irq" timer */
132 struct list_head list; /* ports on this IRQ */
4ba5e35d
RK		 133 unsigned short capabilities; /* port capabilities */
134 unsigned short bugs; /* port bugs */
1da177e4 135 unsigned int tx_loadsz; /* transmit fifo load size */
1da177e4
LT		 136 unsigned char acr;
137 unsigned char ier;
138 unsigned char lcr;
139 unsigned char mcr;
140 unsigned char mcr_mask; /* mask of user bits */
141 unsigned char mcr_force; /* mask of forced bits */
b8e7e40a 142 unsigned char cur_iotype; /* Running I/O type */
ad4c2aa6
CM		 143
144 /*
145 * Some bits in registers are cleared on a read, so they must
146 * be saved whenever the register is read but the bits will not
147 * be immediately processed.
148 */
149#define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
150 unsigned char lsr_saved_flags;
151#define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
152 unsigned char msr_saved_flags;
1da177e4
LT		 153
154 /*
155 * We provide a per-port pm hook.
156 */
157 void (*pm)(struct uart_port *port,
158 unsigned int state, unsigned int old);
159};
160
161struct irq_info {
25db8ad5
AC		 162 struct hlist_node node;
163 int irq;
164 spinlock_t lock; /* Protects list not the hash */
1da177e4
LT		 165 struct list_head *head;
166};
167
25db8ad5
AC		 168#define NR_IRQ_HASH 32 /* Can be adjusted later */
169static struct hlist_head irq_lists[NR_IRQ_HASH];
170static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
1da177e4
LT		 171
172/*
173 * Here we define the default xmit fifo size used for each type of UART.
174 */
175static const struct serial8250_config uart_config[] = {
176 [PORT_UNKNOWN] = {
177 .name = "unknown",
178 .fifo_size = 1,
179 .tx_loadsz = 1,
180 },
181 [PORT_8250] = {
182 .name = "8250",
183 .fifo_size = 1,
184 .tx_loadsz = 1,
185 },
186 [PORT_16450] = {
187 .name = "16450",
188 .fifo_size = 1,
189 .tx_loadsz = 1,
190 },
191 [PORT_16550] = {
192 .name = "16550",
193 .fifo_size = 1,
194 .tx_loadsz = 1,
195 },
196 [PORT_16550A] = {
197 .name = "16550A",
198 .fifo_size = 16,
199 .tx_loadsz = 16,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 .flags = UART_CAP_FIFO,
202 },
203 [PORT_CIRRUS] = {
204 .name = "Cirrus",
205 .fifo_size = 1,
206 .tx_loadsz = 1,
207 },
208 [PORT_16650] = {
209 .name = "ST16650",
210 .fifo_size = 1,
211 .tx_loadsz = 1,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16650V2] = {
215 .name = "ST16650V2",
216 .fifo_size = 32,
217 .tx_loadsz = 16,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 UART_FCR_T_TRIG_00,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_16750] = {
223 .name = "TI16750",
224 .fifo_size = 64,
225 .tx_loadsz = 64,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
227 UART_FCR7_64BYTE,
228 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
229 },
230 [PORT_STARTECH] = {
231 .name = "Startech",
232 .fifo_size = 1,
233 .tx_loadsz = 1,
234 },
235 [PORT_16C950] = {
236 .name = "16C950/954",
237 .fifo_size = 128,
238 .tx_loadsz = 128,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO,
241 },
242 [PORT_16654] = {
243 .name = "ST16654",
244 .fifo_size = 64,
245 .tx_loadsz = 32,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
247 UART_FCR_T_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
249 },
250 [PORT_16850] = {
251 .name = "XR16850",
252 .fifo_size = 128,
253 .tx_loadsz = 128,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
256 },
257 [PORT_RSA] = {
258 .name = "RSA",
259 .fifo_size = 2048,
260 .tx_loadsz = 2048,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
262 .flags = UART_CAP_FIFO,
263 },
264 [PORT_NS16550A] = {
265 .name = "NS16550A",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
269 .flags = UART_CAP_FIFO | UART_NATSEMI,
270 },
271 [PORT_XSCALE] = {
272 .name = "XScale",
273 .fifo_size = 32,
274 .tx_loadsz = 32,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_UUE,
277 },
bd71c182
TK		 278 [PORT_RM9000] = {
279 .name = "RM9000",
280 .fifo_size = 16,
281 .tx_loadsz = 16,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
6b06f191
DD		 283 .flags = UART_CAP_FIFO,
284 },
285 [PORT_OCTEON] = {
286 .name = "OCTEON",
287 .fifo_size = 64,
288 .tx_loadsz = 64,
289 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
bd71c182
TK		 290 .flags = UART_CAP_FIFO,
291 },
08e0992f
FF		 292 [PORT_AR7] = {
293 .name = "AR7",
294 .fifo_size = 16,
295 .tx_loadsz = 16,
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
297 .flags = UART_CAP_FIFO | UART_CAP_AFE,
298 },
1da177e4
LT		 299};
300
bd71c182 301#if defined (CONFIG_SERIAL_8250_AU1X00)
21c614a7
PA		 302
303/* Au1x00 UART hardware has a weird register layout */
304static const u8 au_io_in_map[] = {
305 [UART_RX] = 0,
306 [UART_IER] = 2,
307 [UART_IIR] = 3,
308 [UART_LCR] = 5,
309 [UART_MCR] = 6,
310 [UART_LSR] = 7,
311 [UART_MSR] = 8,
312};
313
314static const u8 au_io_out_map[] = {
315 [UART_TX] = 1,
316 [UART_IER] = 2,
317 [UART_FCR] = 4,
318 [UART_LCR] = 5,
319 [UART_MCR] = 6,
320};
321
322/* sane hardware needs no mapping */
7d6a07d1 323static inline int map_8250_in_reg(struct uart_port *p, int offset)
21c614a7 324{
7d6a07d1 325 if (p->iotype != UPIO_AU)
21c614a7
PA		 326 return offset;
327 return au_io_in_map[offset];
328}
329
7d6a07d1 330static inline int map_8250_out_reg(struct uart_port *p, int offset)
21c614a7 331{
7d6a07d1 332 if (p->iotype != UPIO_AU)
21c614a7
PA		 333 return offset;
334 return au_io_out_map[offset];
335}
336
6f803cd0 337#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 338
339static const u8
340 regmap_in[8] = {
341 [UART_RX] = 0x00,
342 [UART_IER] = 0x0c,
343 [UART_IIR] = 0x14,
344 [UART_LCR] = 0x1c,
345 [UART_MCR] = 0x20,
346 [UART_LSR] = 0x24,
347 [UART_MSR] = 0x28,
348 [UART_SCR] = 0x2c
349 },
350 regmap_out[8] = {
351 [UART_TX] = 0x04,
352 [UART_IER] = 0x0c,
353 [UART_FCR] = 0x18,
354 [UART_LCR] = 0x1c,
355 [UART_MCR] = 0x20,
356 [UART_LSR] = 0x24,
357 [UART_MSR] = 0x28,
358 [UART_SCR] = 0x2c
359 };
360
7d6a07d1 361static inline int map_8250_in_reg(struct uart_port *p, int offset)
bd71c182 362{
7d6a07d1 363 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 364 return offset;
365 return regmap_in[offset];
366}
367
7d6a07d1 368static inline int map_8250_out_reg(struct uart_port *p, int offset)
bd71c182 369{
7d6a07d1 370 if (p->iotype != UPIO_RM9000)
bd71c182
TK		 371 return offset;
372 return regmap_out[offset];
373}
374
21c614a7
PA		 375#else
376
377/* sane hardware needs no mapping */
378#define map_8250_in_reg(up, offset) (offset)
379#define map_8250_out_reg(up, offset) (offset)
380
381#endif
382
7d6a07d1 383static unsigned int hub6_serial_in(struct uart_port *p, int offset)
1da177e4 384{
7d6a07d1
DD		 385 offset = map_8250_in_reg(p, offset) << p->regshift;
386 outb(p->hub6 - 1 + offset, p->iobase);
387 return inb(p->iobase + 1);
388}
1da177e4 389
7d6a07d1
DD		 390static void hub6_serial_out(struct uart_port *p, int offset, int value)
391{
392 offset = map_8250_out_reg(p, offset) << p->regshift;
393 outb(p->hub6 - 1 + offset, p->iobase);
394 outb(value, p->iobase + 1);
395}
1da177e4 396
7d6a07d1
DD		 397static unsigned int mem_serial_in(struct uart_port *p, int offset)
398{
399 offset = map_8250_in_reg(p, offset) << p->regshift;
400 return readb(p->membase + offset);
401}
1da177e4 402
7d6a07d1
DD		 403static void mem_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 writeb(value, p->membase + offset);
407}
408
409static void mem32_serial_out(struct uart_port *p, int offset, int value)
410{
411 offset = map_8250_out_reg(p, offset) << p->regshift;
412 writel(value, p->membase + offset);
413}
414
415static unsigned int mem32_serial_in(struct uart_port *p, int offset)
416{
417 offset = map_8250_in_reg(p, offset) << p->regshift;
418 return readl(p->membase + offset);
419}
1da177e4 420
21c614a7 421#ifdef CONFIG_SERIAL_8250_AU1X00
7d6a07d1
DD		 422static unsigned int au_serial_in(struct uart_port *p, int offset)
423{
424 offset = map_8250_in_reg(p, offset) << p->regshift;
425 return __raw_readl(p->membase + offset);
426}
427
428static void au_serial_out(struct uart_port *p, int offset, int value)
429{
430 offset = map_8250_out_reg(p, offset) << p->regshift;
431 __raw_writel(value, p->membase + offset);
432}
21c614a7
PA		 433#endif
434
7d6a07d1
DD		 435static unsigned int tsi_serial_in(struct uart_port *p, int offset)
436{
437 unsigned int tmp;
438 offset = map_8250_in_reg(p, offset) << p->regshift;
439 if (offset == UART_IIR) {
440 tmp = readl(p->membase + (UART_IIR & ~3));
441 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
442 } else
443 return readb(p->membase + offset);
444}
3be91ec7 445
7d6a07d1
DD		 446static void tsi_serial_out(struct uart_port *p, int offset, int value)
447{
448 offset = map_8250_out_reg(p, offset) << p->regshift;
449 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
450 writeb(value, p->membase + offset);
1da177e4
LT		 451}
452
7d6a07d1 453static void dwapb_serial_out(struct uart_port *p, int offset, int value)
1da177e4 454{
beab697a 455 int save_offset = offset;
7d6a07d1
DD		 456 offset = map_8250_out_reg(p, offset) << p->regshift;
457 /* Save the LCR value so it can be re-written when a
458 * Busy Detect interrupt occurs. */
459 if (save_offset == UART_LCR) {
460 struct uart_8250_port *up = (struct uart_8250_port *)p;
461 up->lcr = value;
462 }
463 writeb(value, p->membase + offset);
464 /* Read the IER to ensure any interrupt is cleared before
465 * returning from ISR. */
466 if (save_offset == UART_TX || save_offset == UART_IER)
467 value = p->serial_in(p, UART_IER);
468}
1da177e4 469
7d6a07d1
DD		 470static unsigned int io_serial_in(struct uart_port *p, int offset)
471{
472 offset = map_8250_in_reg(p, offset) << p->regshift;
473 return inb(p->iobase + offset);
474}
475
476static void io_serial_out(struct uart_port *p, int offset, int value)
477{
478 offset = map_8250_out_reg(p, offset) << p->regshift;
479 outb(value, p->iobase + offset);
480}
481
482static void set_io_from_upio(struct uart_port *p)
483{
b8e7e40a 484 struct uart_8250_port *up = (struct uart_8250_port *)p;
7d6a07d1 485 switch (p->iotype) {
1da177e4 486 case UPIO_HUB6:
7d6a07d1
DD		 487 p->serial_in = hub6_serial_in;
488 p->serial_out = hub6_serial_out;
1da177e4
LT		 489 break;
490
491 case UPIO_MEM:
7d6a07d1
DD		 492 p->serial_in = mem_serial_in;
493 p->serial_out = mem_serial_out;
1da177e4
LT		 494 break;
495
bd71c182 496 case UPIO_RM9000:
1da177e4 497 case UPIO_MEM32:
7d6a07d1
DD		 498 p->serial_in = mem32_serial_in;
499 p->serial_out = mem32_serial_out;
1da177e4
LT		 500 break;
501
21c614a7
PA		 502#ifdef CONFIG_SERIAL_8250_AU1X00
503 case UPIO_AU:
7d6a07d1
DD		 504 p->serial_in = au_serial_in;
505 p->serial_out = au_serial_out;
21c614a7
PA		 506 break;
507#endif
3be91ec7 508 case UPIO_TSI:
7d6a07d1
DD		 509 p->serial_in = tsi_serial_in;
510 p->serial_out = tsi_serial_out;
3be91ec7 511 break;
21c614a7 512
beab697a 513 case UPIO_DWAPB:
7d6a07d1
DD		 514 p->serial_in = mem_serial_in;
515 p->serial_out = dwapb_serial_out;
beab697a
MSJ		 516 break;
517
1da177e4 518 default:
7d6a07d1
DD		 519 p->serial_in = io_serial_in;
520 p->serial_out = io_serial_out;
521 break;
1da177e4 522 }
b8e7e40a
AC		 523 /* Remember loaded iotype */
524 up->cur_iotype = p->iotype;
1da177e4
LT		 525}
526
40b36daa
AW		 527static void
528serial_out_sync(struct uart_8250_port *up, int offset, int value)
529{
7d6a07d1
DD		 530 struct uart_port *p = &up->port;
531 switch (p->iotype) {
40b36daa
AW		 532 case UPIO_MEM:
533 case UPIO_MEM32:
534#ifdef CONFIG_SERIAL_8250_AU1X00
535 case UPIO_AU:
536#endif
beab697a 537 case UPIO_DWAPB:
7d6a07d1
DD		 538 p->serial_out(p, offset, value);
539 p->serial_in(p, UART_LCR); /* safe, no side-effects */
40b36daa
AW		 540 break;
541 default:
7d6a07d1 542 p->serial_out(p, offset, value);
40b36daa
AW		 543 }
544}
545
7d6a07d1
DD		 546#define serial_in(up, offset) \
547 (up->port.serial_in(&(up)->port, (offset)))
548#define serial_out(up, offset, value) \
549 (up->port.serial_out(&(up)->port, (offset), (value)))
1da177e4
LT		 550/*
551 * We used to support using pause I/O for certain machines. We
552 * haven't supported this for a while, but just in case it's badly
553 * needed for certain old 386 machines, I've left these #define's
554 * in....
555 */
556#define serial_inp(up, offset) serial_in(up, offset)
557#define serial_outp(up, offset, value) serial_out(up, offset, value)
558
b32b19b8
JAH		 559/* Uart divisor latch read */
560static inline int _serial_dl_read(struct uart_8250_port *up)
561{
562 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
563}
564
565/* Uart divisor latch write */
566static inline void _serial_dl_write(struct uart_8250_port *up, int value)
567{
568 serial_outp(up, UART_DLL, value & 0xff);
569 serial_outp(up, UART_DLM, value >> 8 & 0xff);
570}
571
6f803cd0 572#if defined(CONFIG_SERIAL_8250_AU1X00)
b32b19b8
JAH		 573/* Au1x00 haven't got a standard divisor latch */
574static int serial_dl_read(struct uart_8250_port *up)
575{
576 if (up->port.iotype == UPIO_AU)
577 return __raw_readl(up->port.membase + 0x28);
578 else
579 return _serial_dl_read(up);
580}
581
582static void serial_dl_write(struct uart_8250_port *up, int value)
583{
584 if (up->port.iotype == UPIO_AU)
585 __raw_writel(value, up->port.membase + 0x28);
586 else
587 _serial_dl_write(up, value);
588}
6f803cd0 589#elif defined(CONFIG_SERIAL_8250_RM9K)
bd71c182
TK		 590static int serial_dl_read(struct uart_8250_port *up)
591{
592 return (up->port.iotype == UPIO_RM9000) ?
593 (((__raw_readl(up->port.membase + 0x10) << 8) |
594 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
595 _serial_dl_read(up);
596}
597
598static void serial_dl_write(struct uart_8250_port *up, int value)
599{
600 if (up->port.iotype == UPIO_RM9000) {
601 __raw_writel(value, up->port.membase + 0x08);
602 __raw_writel(value >> 8, up->port.membase + 0x10);
603 } else {
604 _serial_dl_write(up, value);
605 }
606}
b32b19b8
JAH		 607#else
608#define serial_dl_read(up) _serial_dl_read(up)
609#define serial_dl_write(up, value) _serial_dl_write(up, value)
610#endif
1da177e4
LT		 611
612/*
613 * For the 16C950
614 */
615static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
616{
617 serial_out(up, UART_SCR, offset);
618 serial_out(up, UART_ICR, value);
619}
620
621static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
622{
623 unsigned int value;
624
625 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
626 serial_out(up, UART_SCR, offset);
627 value = serial_in(up, UART_ICR);
628 serial_icr_write(up, UART_ACR, up->acr);
629
630 return value;
631}
632
633/*
634 * FIFO support.
635 */
b5d674ab 636static void serial8250_clear_fifos(struct uart_8250_port *p)
1da177e4
LT		 637{
638 if (p->capabilities & UART_CAP_FIFO) {
639 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
640 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
641 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
642 serial_outp(p, UART_FCR, 0);
643 }
644}
645
646/*
647 * IER sleep support. UARTs which have EFRs need the "extended
648 * capability" bit enabled. Note that on XR16C850s, we need to
649 * reset LCR to write to IER.
650 */
b5d674ab 651static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
1da177e4
LT		 652{
653 if (p->capabilities & UART_CAP_SLEEP) {
654 if (p->capabilities & UART_CAP_EFR) {
655 serial_outp(p, UART_LCR, 0xBF);
656 serial_outp(p, UART_EFR, UART_EFR_ECB);
657 serial_outp(p, UART_LCR, 0);
658 }
659 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
660 if (p->capabilities & UART_CAP_EFR) {
661 serial_outp(p, UART_LCR, 0xBF);
662 serial_outp(p, UART_EFR, 0);
663 serial_outp(p, UART_LCR, 0);
664 }
665 }
666}
667
668#ifdef CONFIG_SERIAL_8250_RSA
669/*
670 * Attempts to turn on the RSA FIFO. Returns zero on failure.
671 * We set the port uart clock rate if we succeed.
672 */
673static int __enable_rsa(struct uart_8250_port *up)
674{
675 unsigned char mode;
676 int result;
677
678 mode = serial_inp(up, UART_RSA_MSR);
679 result = mode & UART_RSA_MSR_FIFO;
680
681 if (!result) {
682 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
683 mode = serial_inp(up, UART_RSA_MSR);
684 result = mode & UART_RSA_MSR_FIFO;
685 }
686
687 if (result)
688 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
689
690 return result;
691}
692
693static void enable_rsa(struct uart_8250_port *up)
694{
695 if (up->port.type == PORT_RSA) {
696 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
697 spin_lock_irq(&up->port.lock);
698 __enable_rsa(up);
699 spin_unlock_irq(&up->port.lock);
700 }
701 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
702 serial_outp(up, UART_RSA_FRR, 0);
703 }
704}
705
706/*
707 * Attempts to turn off the RSA FIFO. Returns zero on failure.
708 * It is unknown why interrupts were disabled in here. However,
709 * the caller is expected to preserve this behaviour by grabbing
710 * the spinlock before calling this function.
711 */
712static void disable_rsa(struct uart_8250_port *up)
713{
714 unsigned char mode;
715 int result;
716
717 if (up->port.type == PORT_RSA &&
718 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
719 spin_lock_irq(&up->port.lock);
720
721 mode = serial_inp(up, UART_RSA_MSR);
722 result = !(mode & UART_RSA_MSR_FIFO);
723
724 if (!result) {
725 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
726 mode = serial_inp(up, UART_RSA_MSR);
727 result = !(mode & UART_RSA_MSR_FIFO);
728 }
729
730 if (result)
731 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
732 spin_unlock_irq(&up->port.lock);
733 }
734}
735#endif /* CONFIG_SERIAL_8250_RSA */
736
737/*
738 * This is a quickie test to see how big the FIFO is.
739 * It doesn't work at all the time, more's the pity.
740 */
741static int size_fifo(struct uart_8250_port *up)
742{
b32b19b8
JAH		 743 unsigned char old_fcr, old_mcr, old_lcr;
744 unsigned short old_dl;
1da177e4
LT		 745 int count;
746
747 old_lcr = serial_inp(up, UART_LCR);
748 serial_outp(up, UART_LCR, 0);
749 old_fcr = serial_inp(up, UART_FCR);
750 old_mcr = serial_inp(up, UART_MCR);
751 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
752 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
753 serial_outp(up, UART_MCR, UART_MCR_LOOP);
754 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8
JAH		 755 old_dl = serial_dl_read(up);
756 serial_dl_write(up, 0x0001);
1da177e4
LT		 757 serial_outp(up, UART_LCR, 0x03);
758 for (count = 0; count < 256; count++)
759 serial_outp(up, UART_TX, count);
760 mdelay(20);/* FIXME - schedule_timeout */
761 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
762 (count < 256); count++)
763 serial_inp(up, UART_RX);
764 serial_outp(up, UART_FCR, old_fcr);
765 serial_outp(up, UART_MCR, old_mcr);
766 serial_outp(up, UART_LCR, UART_LCR_DLAB);
b32b19b8 767 serial_dl_write(up, old_dl);
1da177e4
LT		 768 serial_outp(up, UART_LCR, old_lcr);
769
770 return count;
771}
772
773/*
774 * Read UART ID using the divisor method - set DLL and DLM to zero
775 * and the revision will be in DLL and device type in DLM. We
776 * preserve the device state across this.
777 */
778static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
779{
780 unsigned char old_dll, old_dlm, old_lcr;
781 unsigned int id;
782
783 old_lcr = serial_inp(p, UART_LCR);
784 serial_outp(p, UART_LCR, UART_LCR_DLAB);
785
786 old_dll = serial_inp(p, UART_DLL);
787 old_dlm = serial_inp(p, UART_DLM);
788
789 serial_outp(p, UART_DLL, 0);
790 serial_outp(p, UART_DLM, 0);
791
792 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
793
794 serial_outp(p, UART_DLL, old_dll);
795 serial_outp(p, UART_DLM, old_dlm);
796 serial_outp(p, UART_LCR, old_lcr);
797
798 return id;
799}
800
801/*
802 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
803 * When this function is called we know it is at least a StarTech
804 * 16650 V2, but it might be one of several StarTech UARTs, or one of
805 * its clones. (We treat the broken original StarTech 16650 V1 as a
806 * 16550, and why not? Startech doesn't seem to even acknowledge its
807 * existence.)
bd71c182 808 *
1da177e4
LT		 809 * What evil have men's minds wrought...
810 */
811static void autoconfig_has_efr(struct uart_8250_port *up)
812{
813 unsigned int id1, id2, id3, rev;
814
815 /*
816 * Everything with an EFR has SLEEP
817 */
818 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
819
820 /*
821 * First we check to see if it's an Oxford Semiconductor UART.
822 *
823 * If we have to do this here because some non-National
824 * Semiconductor clone chips lock up if you try writing to the
825 * LSR register (which serial_icr_read does)
826 */
827
828 /*
829 * Check for Oxford Semiconductor 16C950.
830 *
831 * EFR [4] must be set else this test fails.
832 *
833 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
834 * claims that it's needed for 952 dual UART's (which are not
835 * recommended for new designs).
836 */
837 up->acr = 0;
838 serial_out(up, UART_LCR, 0xBF);
839 serial_out(up, UART_EFR, UART_EFR_ECB);
840 serial_out(up, UART_LCR, 0x00);
841 id1 = serial_icr_read(up, UART_ID1);
842 id2 = serial_icr_read(up, UART_ID2);
843 id3 = serial_icr_read(up, UART_ID3);
844 rev = serial_icr_read(up, UART_REV);
845
846 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
847
848 if (id1 == 0x16 && id2 == 0xC9 &&
849 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
850 up->port.type = PORT_16C950;
4ba5e35d
RK		 851
852 /*
853 * Enable work around for the Oxford Semiconductor 952 rev B
854 * chip which causes it to seriously miscalculate baud rates
855 * when DLL is 0.
856 */
857 if (id3 == 0x52 && rev == 0x01)
858 up->bugs |= UART_BUG_QUOT;
1da177e4
LT		 859 return;
860 }
bd71c182 861
1da177e4
LT		 862 /*
863 * We check for a XR16C850 by setting DLL and DLM to 0, and then
864 * reading back DLL and DLM. The chip type depends on the DLM
865 * value read back:
866 * 0x10 - XR16C850 and the DLL contains the chip revision.
867 * 0x12 - XR16C2850.
868 * 0x14 - XR16C854.
869 */
870 id1 = autoconfig_read_divisor_id(up);
871 DEBUG_AUTOCONF("850id=%04x ", id1);
872
873 id2 = id1 >> 8;
874 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
1da177e4
LT		 875 up->port.type = PORT_16850;
876 return;
877 }
878
879 /*
880 * It wasn't an XR16C850.
881 *
882 * We distinguish between the '654 and the '650 by counting
883 * how many bytes are in the FIFO. I'm using this for now,
884 * since that's the technique that was sent to me in the
885 * serial driver update, but I'm not convinced this works.
886 * I've had problems doing this in the past. -TYT
887 */
888 if (size_fifo(up) == 64)
889 up->port.type = PORT_16654;
890 else
891 up->port.type = PORT_16650V2;
892}
893
894/*
895 * We detected a chip without a FIFO. Only two fall into
896 * this category - the original 8250 and the 16450. The
897 * 16450 has a scratch register (accessible with LCR=0)
898 */
899static void autoconfig_8250(struct uart_8250_port *up)
900{
901 unsigned char scratch, status1, status2;
902
903 up->port.type = PORT_8250;
904
905 scratch = serial_in(up, UART_SCR);
906 serial_outp(up, UART_SCR, 0xa5);
907 status1 = serial_in(up, UART_SCR);
908 serial_outp(up, UART_SCR, 0x5a);
909 status2 = serial_in(up, UART_SCR);
910 serial_outp(up, UART_SCR, scratch);
911
912 if (status1 == 0xa5 && status2 == 0x5a)
913 up->port.type = PORT_16450;
914}
915
916static int broken_efr(struct uart_8250_port *up)
917{
918 /*
919 * Exar ST16C2550 "A2" devices incorrectly detect as
920 * having an EFR, and report an ID of 0x0201. See
921 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
922 */
923 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
924 return 1;
925
926 return 0;
927}
928
929/*
930 * We know that the chip has FIFOs. Does it have an EFR? The
931 * EFR is located in the same register position as the IIR and
932 * we know the top two bits of the IIR are currently set. The
933 * EFR should contain zero. Try to read the EFR.
934 */
935static void autoconfig_16550a(struct uart_8250_port *up)
936{
937 unsigned char status1, status2;
938 unsigned int iersave;
939
940 up->port.type = PORT_16550A;
941 up->capabilities |= UART_CAP_FIFO;
942
943 /*
944 * Check for presence of the EFR when DLAB is set.
945 * Only ST16C650V1 UARTs pass this test.
946 */
947 serial_outp(up, UART_LCR, UART_LCR_DLAB);
948 if (serial_in(up, UART_EFR) == 0) {
949 serial_outp(up, UART_EFR, 0xA8);
950 if (serial_in(up, UART_EFR) != 0) {
951 DEBUG_AUTOCONF("EFRv1 ");
952 up->port.type = PORT_16650;
953 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
954 } else {
955 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
956 }
957 serial_outp(up, UART_EFR, 0);
958 return;
959 }
960
961 /*
962 * Maybe it requires 0xbf to be written to the LCR.
963 * (other ST16C650V2 UARTs, TI16C752A, etc)
964 */
965 serial_outp(up, UART_LCR, 0xBF);
966 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
967 DEBUG_AUTOCONF("EFRv2 ");
968 autoconfig_has_efr(up);
969 return;
970 }
971
972 /*
973 * Check for a National Semiconductor SuperIO chip.
974 * Attempt to switch to bank 2, read the value of the LOOP bit
975 * from EXCR1. Switch back to bank 0, change it in MCR. Then
976 * switch back to bank 2, read it from EXCR1 again and check
977 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1da177e4
LT		 978 */
979 serial_outp(up, UART_LCR, 0);
980 status1 = serial_in(up, UART_MCR);
981 serial_outp(up, UART_LCR, 0xE0);
982 status2 = serial_in(up, 0x02); /* EXCR1 */
983
984 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
985 serial_outp(up, UART_LCR, 0);
986 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
987 serial_outp(up, UART_LCR, 0xE0);
988 status2 = serial_in(up, 0x02); /* EXCR1 */
989 serial_outp(up, UART_LCR, 0);
990 serial_outp(up, UART_MCR, status1);
991
992 if ((status2 ^ status1) & UART_MCR_LOOP) {
857dde2e
DW		 993 unsigned short quot;
994
1da177e4 995 serial_outp(up, UART_LCR, 0xE0);
857dde2e 996
b32b19b8 997 quot = serial_dl_read(up);
857dde2e
DW		 998 quot <<= 3;
999
b5b82df6 1000 status1 = serial_in(up, 0x04); /* EXCR2 */
1da177e4
LT		 1001 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
1002 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
1003 serial_outp(up, 0x04, status1);
bd71c182 1004
b32b19b8 1005 serial_dl_write(up, quot);
857dde2e 1006
1da177e4 1007 serial_outp(up, UART_LCR, 0);
1da177e4 1008
857dde2e 1009 up->port.uartclk = 921600*16;
1da177e4
LT		 1010 up->port.type = PORT_NS16550A;
1011 up->capabilities |= UART_NATSEMI;
1012 return;
1013 }
1014 }
1015
1016 /*
1017 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1018 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1019 * Try setting it with and without DLAB set. Cheap clones
1020 * set bit 5 without DLAB set.
1021 */
1022 serial_outp(up, UART_LCR, 0);
1023 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1024 status1 = serial_in(up, UART_IIR) >> 5;
1025 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1026 serial_outp(up, UART_LCR, UART_LCR_DLAB);
1027 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1028 status2 = serial_in(up, UART_IIR) >> 5;
1029 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1030 serial_outp(up, UART_LCR, 0);
1031
1032 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1033
1034 if (status1 == 6 && status2 == 7) {
1035 up->port.type = PORT_16750;
1036 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1037 return;
1038 }
1039
1040 /*
1041 * Try writing and reading the UART_IER_UUE bit (b6).
1042 * If it works, this is probably one of the Xscale platform's
1043 * internal UARTs.
1044 * We're going to explicitly set the UUE bit to 0 before
1045 * trying to write and read a 1 just to make sure it's not
1046 * already a 1 and maybe locked there before we even start start.
1047 */
1048 iersave = serial_in(up, UART_IER);
1049 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1050 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1051 /*
1052 * OK it's in a known zero state, try writing and reading
1053 * without disturbing the current state of the other bits.
1054 */
1055 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1056 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1057 /*
1058 * It's an Xscale.
1059 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1060 */
1061 DEBUG_AUTOCONF("Xscale ");
1062 up->port.type = PORT_XSCALE;
1063 up->capabilities |= UART_CAP_UUE;
1064 return;
1065 }
1066 } else {
1067 /*
1068 * If we got here we couldn't force the IER_UUE bit to 0.
1069 * Log it and continue.
1070 */
1071 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1072 }
1073 serial_outp(up, UART_IER, iersave);
1074}
1075
1076/*
1077 * This routine is called by rs_init() to initialize a specific serial
1078 * port. It determines what type of UART chip this serial port is
1079 * using: 8250, 16450, 16550, 16550A. The important question is
1080 * whether or not this UART is a 16550A or not, since this will
1081 * determine whether or not we can use its FIFO features or not.
1082 */
1083static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1084{
1085 unsigned char status1, scratch, scratch2, scratch3;
1086 unsigned char save_lcr, save_mcr;
1087 unsigned long flags;
1088
1089 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1090 return;
1091
80647b95 1092 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
8440838b 1093 serial_index(&up->port), up->port.iobase, up->port.membase);
1da177e4
LT		 1094
1095 /*
1096 * We really do need global IRQs disabled here - we're going to
1097 * be frobbing the chips IRQ enable register to see if it exists.
1098 */
1099 spin_lock_irqsave(&up->port.lock, flags);
1da177e4
LT		 1100
1101 up->capabilities = 0;
4ba5e35d 1102 up->bugs = 0;
1da177e4
LT		 1103
1104 if (!(up->port.flags & UPF_BUGGY_UART)) {
1105 /*
1106 * Do a simple existence test first; if we fail this,
1107 * there's no point trying anything else.
bd71c182 1108 *
1da177e4
LT		 1109 * 0x80 is used as a nonsense port to prevent against
1110 * false positives due to ISA bus float. The
1111 * assumption is that 0x80 is a non-existent port;
1112 * which should be safe since include/asm/io.h also
1113 * makes this assumption.
1114 *
1115 * Note: this is safe as long as MCR bit 4 is clear
1116 * and the device is in "PC" mode.
1117 */
1118 scratch = serial_inp(up, UART_IER);
1119 serial_outp(up, UART_IER, 0);
1120#ifdef __i386__
1121 outb(0xff, 0x080);
1122#endif
48212008
TH		 1123 /*
1124 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1125 * 16C754B) allow only to modify them if an EFR bit is set.
1126 */
1127 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1128 serial_outp(up, UART_IER, 0x0F);
1129#ifdef __i386__
1130 outb(0, 0x080);
1131#endif
48212008 1132 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1da177e4
LT		 1133 serial_outp(up, UART_IER, scratch);
1134 if (scratch2 != 0 || scratch3 != 0x0F) {
1135 /*
1136 * We failed; there's nothing here
1137 */
1138 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1139 scratch2, scratch3);
1140 goto out;
1141 }
1142 }
1143
1144 save_mcr = serial_in(up, UART_MCR);
1145 save_lcr = serial_in(up, UART_LCR);
1146
bd71c182 1147 /*
1da177e4
LT		 1148 * Check to see if a UART is really there. Certain broken
1149 * internal modems based on the Rockwell chipset fail this
1150 * test, because they apparently don't implement the loopback
1151 * test mode. So this test is skipped on the COM 1 through
1152 * COM 4 ports. This *should* be safe, since no board
1153 * manufacturer would be stupid enough to design a board
1154 * that conflicts with COM 1-4 --- we hope!
1155 */
1156 if (!(up->port.flags & UPF_SKIP_TEST)) {
1157 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1158 status1 = serial_inp(up, UART_MSR) & 0xF0;
1159 serial_outp(up, UART_MCR, save_mcr);
1160 if (status1 != 0x90) {
1161 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1162 status1);
1163 goto out;
1164 }
1165 }
1166
1167 /*
1168 * We're pretty sure there's a port here. Lets find out what
1169 * type of port it is. The IIR top two bits allows us to find
6f0d618f 1170 * out if it's 8250 or 16450, 16550, 16550A or later. This
1da177e4
LT		 1171 * determines what we test for next.
1172 *
1173 * We also initialise the EFR (if any) to zero for later. The
1174 * EFR occupies the same register location as the FCR and IIR.
1175 */
1176 serial_outp(up, UART_LCR, 0xBF);
1177 serial_outp(up, UART_EFR, 0);
1178 serial_outp(up, UART_LCR, 0);
1179
1180 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1181 scratch = serial_in(up, UART_IIR) >> 6;
1182
1183 DEBUG_AUTOCONF("iir=%d ", scratch);
1184
1185 switch (scratch) {
1186 case 0:
1187 autoconfig_8250(up);
1188 break;
1189 case 1:
1190 up->port.type = PORT_UNKNOWN;
1191 break;
1192 case 2:
1193 up->port.type = PORT_16550;
1194 break;
1195 case 3:
1196 autoconfig_16550a(up);
1197 break;
1198 }
1199
1200#ifdef CONFIG_SERIAL_8250_RSA
1201 /*
1202 * Only probe for RSA ports if we got the region.
1203 */
1204 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1205 int i;
1206
1207 for (i = 0 ; i < probe_rsa_count; ++i) {
1208 if (probe_rsa[i] == up->port.iobase &&
1209 __enable_rsa(up)) {
1210 up->port.type = PORT_RSA;
1211 break;
1212 }
1213 }
1214 }
1215#endif
21c614a7
PA		 1216
1217#ifdef CONFIG_SERIAL_8250_AU1X00
1218 /* if access method is AU, it is a 16550 with a quirk */
1219 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1220 up->bugs |= UART_BUG_NOMSR;
1221#endif
1222
1da177e4
LT		 1223 serial_outp(up, UART_LCR, save_lcr);
1224
1225 if (up->capabilities != uart_config[up->port.type].flags) {
1226 printk(KERN_WARNING
1227 "ttyS%d: detected caps %08x should be %08x\n",
8440838b
DM		 1228 serial_index(&up->port), up->capabilities,
1229 uart_config[up->port.type].flags);
1da177e4
LT		 1230 }
1231
1232 up->port.fifosize = uart_config[up->port.type].fifo_size;
1233 up->capabilities = uart_config[up->port.type].flags;
1234 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1235
1236 if (up->port.type == PORT_UNKNOWN)
1237 goto out;
1238
1239 /*
1240 * Reset the UART.
1241 */
1242#ifdef CONFIG_SERIAL_8250_RSA
1243 if (up->port.type == PORT_RSA)
1244 serial_outp(up, UART_RSA_FRR, 0);
1245#endif
1246 serial_outp(up, UART_MCR, save_mcr);
1247 serial8250_clear_fifos(up);
40b36daa 1248 serial_in(up, UART_RX);
5c8c755c
LB		 1249 if (up->capabilities & UART_CAP_UUE)
1250 serial_outp(up, UART_IER, UART_IER_UUE);
1251 else
1252 serial_outp(up, UART_IER, 0);
1da177e4 1253
bd71c182 1254 out:
1da177e4 1255 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1256 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1257}
1258
1259static void autoconfig_irq(struct uart_8250_port *up)
1260{
1261 unsigned char save_mcr, save_ier;
1262 unsigned char save_ICP = 0;
1263 unsigned int ICP = 0;
1264 unsigned long irqs;
1265 int irq;
1266
1267 if (up->port.flags & UPF_FOURPORT) {
1268 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1269 save_ICP = inb_p(ICP);
1270 outb_p(0x80, ICP);
1271 (void) inb_p(ICP);
1272 }
1273
1274 /* forget possible initially masked and pending IRQ */
1275 probe_irq_off(probe_irq_on());
1276 save_mcr = serial_inp(up, UART_MCR);
1277 save_ier = serial_inp(up, UART_IER);
1278 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
bd71c182 1279
1da177e4
LT		 1280 irqs = probe_irq_on();
1281 serial_outp(up, UART_MCR, 0);
6f803cd0
AC		 1282 udelay(10);
1283 if (up->port.flags & UPF_FOURPORT) {
1da177e4
LT		 1284 serial_outp(up, UART_MCR,
1285 UART_MCR_DTR | UART_MCR_RTS);
1286 } else {
1287 serial_outp(up, UART_MCR,
1288 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1289 }
1290 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1291 (void)serial_inp(up, UART_LSR);
1292 (void)serial_inp(up, UART_RX);
1293 (void)serial_inp(up, UART_IIR);
1294 (void)serial_inp(up, UART_MSR);
1295 serial_outp(up, UART_TX, 0xFF);
6f803cd0 1296 udelay(20);
1da177e4
LT		 1297 irq = probe_irq_off(irqs);
1298
1299 serial_outp(up, UART_MCR, save_mcr);
1300 serial_outp(up, UART_IER, save_ier);
1301
1302 if (up->port.flags & UPF_FOURPORT)
1303 outb_p(save_ICP, ICP);
1304
1305 up->port.irq = (irq > 0) ? irq : 0;
1306}
1307
e763b90c
RK		 1308static inline void __stop_tx(struct uart_8250_port *p)
1309{
1310 if (p->ier & UART_IER_THRI) {
1311 p->ier &= ~UART_IER_THRI;
1312 serial_out(p, UART_IER, p->ier);
1313 }
1314}
1315
b129a8cc 1316static void serial8250_stop_tx(struct uart_port *port)
1da177e4
LT		 1317{
1318 struct uart_8250_port *up = (struct uart_8250_port *)port;
1319
e763b90c 1320 __stop_tx(up);
1da177e4
LT		 1321
1322 /*
e763b90c 1323 * We really want to stop the transmitter from sending.
1da177e4 1324 */
e763b90c 1325 if (up->port.type == PORT_16C950) {
1da177e4
LT		 1326 up->acr |= UART_ACR_TXDIS;
1327 serial_icr_write(up, UART_ACR, up->acr);
1328 }
1329}
1330
55d3b282
RK		 1331static void transmit_chars(struct uart_8250_port *up);
1332
b129a8cc 1333static void serial8250_start_tx(struct uart_port *port)
1da177e4
LT		 1334{
1335 struct uart_8250_port *up = (struct uart_8250_port *)port;
1336
1337 if (!(up->ier & UART_IER_THRI)) {
1338 up->ier |= UART_IER_THRI;
1339 serial_out(up, UART_IER, up->ier);
55d3b282 1340
67f7654e 1341 if (up->bugs & UART_BUG_TXEN) {
68cb4f8e 1342 unsigned char lsr;
55d3b282 1343 lsr = serial_in(up, UART_LSR);
ad4c2aa6 1344 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
bd71c182 1345 if ((up->port.type == PORT_RM9000) ?
68cb4f8e
IJ		 1346 (lsr & UART_LSR_THRE) :
1347 (lsr & UART_LSR_TEMT))
55d3b282
RK		 1348 transmit_chars(up);
1349 }
1da177e4 1350 }
e763b90c 1351
1da177e4 1352 /*
e763b90c 1353 * Re-enable the transmitter if we disabled it.
1da177e4 1354 */
e763b90c 1355 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1da177e4
LT		 1356 up->acr &= ~UART_ACR_TXDIS;
1357 serial_icr_write(up, UART_ACR, up->acr);
1358 }
1359}
1360
1361static void serial8250_stop_rx(struct uart_port *port)
1362{
1363 struct uart_8250_port *up = (struct uart_8250_port *)port;
1364
1365 up->ier &= ~UART_IER_RLSI;
1366 up->port.read_status_mask &= ~UART_LSR_DR;
1367 serial_out(up, UART_IER, up->ier);
1368}
1369
1370static void serial8250_enable_ms(struct uart_port *port)
1371{
1372 struct uart_8250_port *up = (struct uart_8250_port *)port;
1373
21c614a7
PA		 1374 /* no MSR capabilities */
1375 if (up->bugs & UART_BUG_NOMSR)
1376 return;
1377
1da177e4
LT		 1378 up->ier |= UART_IER_MSI;
1379 serial_out(up, UART_IER, up->ier);
1380}
1381
ea8874dc 1382static void
cc79aa9d 1383receive_chars(struct uart_8250_port *up, unsigned int *status)
1da177e4 1384{
ebd2c8f6 1385 struct tty_struct *tty = up->port.state->port.tty;
1da177e4
LT		 1386 unsigned char ch, lsr = *status;
1387 int max_count = 256;
1388 char flag;
1389
1390 do {
7500b1f6
AR		 1391 if (likely(lsr & UART_LSR_DR))
1392 ch = serial_inp(up, UART_RX);
1393 else
1394 /*
1395 * Intel 82571 has a Serial Over Lan device that will
1396 * set UART_LSR_BI without setting UART_LSR_DR when
1397 * it receives a break. To avoid reading from the
1398 * receive buffer without UART_LSR_DR bit set, we
1399 * just force the read character to be 0
1400 */
1401 ch = 0;
1402
1da177e4
LT		 1403 flag = TTY_NORMAL;
1404 up->port.icount.rx++;
1405
ad4c2aa6
CM		 1406 lsr |= up->lsr_saved_flags;
1407 up->lsr_saved_flags = 0;
1da177e4 1408
ad4c2aa6 1409 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1da177e4
LT		 1410 /*
1411 * For statistics only
1412 */
1413 if (lsr & UART_LSR_BI) {
1414 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1415 up->port.icount.brk++;
1416 /*
1417 * We do the SysRQ and SAK checking
1418 * here because otherwise the break
1419 * may get masked by ignore_status_mask
1420 * or read_status_mask.
1421 */
1422 if (uart_handle_break(&up->port))
1423 goto ignore_char;
1424 } else if (lsr & UART_LSR_PE)
1425 up->port.icount.parity++;
1426 else if (lsr & UART_LSR_FE)
1427 up->port.icount.frame++;
1428 if (lsr & UART_LSR_OE)
1429 up->port.icount.overrun++;
1430
1431 /*
23907eb8 1432 * Mask off conditions which should be ignored.
1da177e4
LT		 1433 */
1434 lsr &= up->port.read_status_mask;
1435
1436 if (lsr & UART_LSR_BI) {
1437 DEBUG_INTR("handling break....");
1438 flag = TTY_BREAK;
1439 } else if (lsr & UART_LSR_PE)
1440 flag = TTY_PARITY;
1441 else if (lsr & UART_LSR_FE)
1442 flag = TTY_FRAME;
1443 }
7d12e780 1444 if (uart_handle_sysrq_char(&up->port, ch))
1da177e4 1445 goto ignore_char;
05ab3014
RK		 1446
1447 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1448
6f803cd0 1449ignore_char:
1da177e4 1450 lsr = serial_inp(up, UART_LSR);
7500b1f6 1451 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1da177e4
LT		 1452 spin_unlock(&up->port.lock);
1453 tty_flip_buffer_push(tty);
1454 spin_lock(&up->port.lock);
1455 *status = lsr;
1456}
1457
ea8874dc 1458static void transmit_chars(struct uart_8250_port *up)
1da177e4 1459{
ebd2c8f6 1460 struct circ_buf *xmit = &up->port.state->xmit;
1da177e4
LT		 1461 int count;
1462
1463 if (up->port.x_char) {
1464 serial_outp(up, UART_TX, up->port.x_char);
1465 up->port.icount.tx++;
1466 up->port.x_char = 0;
1467 return;
1468 }
b129a8cc
RK		 1469 if (uart_tx_stopped(&up->port)) {
1470 serial8250_stop_tx(&up->port);
1471 return;
1472 }
1473 if (uart_circ_empty(xmit)) {
e763b90c 1474 __stop_tx(up);
1da177e4
LT		 1475 return;
1476 }
1477
1478 count = up->tx_loadsz;
1479 do {
1480 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1481 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1482 up->port.icount.tx++;
1483 if (uart_circ_empty(xmit))
1484 break;
1485 } while (--count > 0);
1486
1487 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1488 uart_write_wakeup(&up->port);
1489
1490 DEBUG_INTR("THRE...");
1491
1492 if (uart_circ_empty(xmit))
e763b90c 1493 __stop_tx(up);
1da177e4
LT		 1494}
1495
2af7cd68 1496static unsigned int check_modem_status(struct uart_8250_port *up)
1da177e4 1497{
2af7cd68
RK		 1498 unsigned int status = serial_in(up, UART_MSR);
1499
ad4c2aa6
CM		 1500 status |= up->msr_saved_flags;
1501 up->msr_saved_flags = 0;
fdc30b3d 1502 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
ebd2c8f6 1503 up->port.state != NULL) {
2af7cd68
RK		 1504 if (status & UART_MSR_TERI)
1505 up->port.icount.rng++;
1506 if (status & UART_MSR_DDSR)
1507 up->port.icount.dsr++;
1508 if (status & UART_MSR_DDCD)
1509 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1510 if (status & UART_MSR_DCTS)
1511 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1512
bdc04e31 1513 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
2af7cd68 1514 }
1da177e4 1515
2af7cd68 1516 return status;
1da177e4
LT		 1517}
1518
1519/*
1520 * This handles the interrupt from one port.
1521 */
b5d674ab 1522static void serial8250_handle_port(struct uart_8250_port *up)
1da177e4 1523{
45e24601 1524 unsigned int status;
4bf3631c 1525 unsigned long flags;
45e24601 1526
4bf3631c 1527 spin_lock_irqsave(&up->port.lock, flags);
45e24601
RK		 1528
1529 status = serial_inp(up, UART_LSR);
1da177e4
LT		 1530
1531 DEBUG_INTR("status = %x...", status);
1532
7500b1f6 1533 if (status & (UART_LSR_DR | UART_LSR_BI))
7d12e780 1534 receive_chars(up, &status);
1da177e4
LT		 1535 check_modem_status(up);
1536 if (status & UART_LSR_THRE)
1537 transmit_chars(up);
45e24601 1538
4bf3631c 1539 spin_unlock_irqrestore(&up->port.lock, flags);
1da177e4
LT		 1540}
1541
1542/*
1543 * This is the serial driver's interrupt routine.
1544 *
1545 * Arjan thinks the old way was overly complex, so it got simplified.
1546 * Alan disagrees, saying that need the complexity to handle the weird
1547 * nature of ISA shared interrupts. (This is a special exception.)
1548 *
1549 * In order to handle ISA shared interrupts properly, we need to check
1550 * that all ports have been serviced, and therefore the ISA interrupt
1551 * line has been de-asserted.
1552 *
1553 * This means we need to loop through all ports. checking that they
1554 * don't have an interrupt pending.
1555 */
7d12e780 1556static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1da177e4
LT		 1557{
1558 struct irq_info *i = dev_id;
1559 struct list_head *l, *end = NULL;
1560 int pass_counter = 0, handled = 0;
1561
1562 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1563
1564 spin_lock(&i->lock);
1565
1566 l = i->head;
1567 do {
1568 struct uart_8250_port *up;
1569 unsigned int iir;
1570
1571 up = list_entry(l, struct uart_8250_port, list);
1572
1573 iir = serial_in(up, UART_IIR);
1574 if (!(iir & UART_IIR_NO_INT)) {
7d12e780 1575 serial8250_handle_port(up);
1da177e4
LT		 1576
1577 handled = 1;
1578
beab697a
MSJ		 1579 end = NULL;
1580 } else if (up->port.iotype == UPIO_DWAPB &&
1581 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1582 /* The DesignWare APB UART has an Busy Detect (0x07)
1583 * interrupt meaning an LCR write attempt occured while the
1584 * UART was busy. The interrupt must be cleared by reading
1585 * the UART status register (USR) and the LCR re-written. */
1586 unsigned int status;
1587 status = *(volatile u32 *)up->port.private_data;
1588 serial_out(up, UART_LCR, up->lcr);
1589
1590 handled = 1;
1591
1da177e4
LT		 1592 end = NULL;
1593 } else if (end == NULL)
1594 end = l;
1595
1596 l = l->next;
1597
1598 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1599 /* If we hit this, we're dead. */
1600 printk(KERN_ERR "serial8250: too much work for "
1601 "irq%d\n", irq);
1602 break;
1603 }
1604 } while (l != end);
1605
1606 spin_unlock(&i->lock);
1607
1608 DEBUG_INTR("end.\n");
1609
1610 return IRQ_RETVAL(handled);
1611}
1612
1613/*
1614 * To support ISA shared interrupts, we need to have one interrupt
1615 * handler that ensures that the IRQ line has been deasserted
1616 * before returning. Failing to do this will result in the IRQ
1617 * line being stuck active, and, since ISA irqs are edge triggered,
1618 * no more IRQs will be seen.
1619 */
1620static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1621{
1622 spin_lock_irq(&i->lock);
1623
1624 if (!list_empty(i->head)) {
1625 if (i->head == &up->list)
1626 i->head = i->head->next;
1627 list_del(&up->list);
1628 } else {
1629 BUG_ON(i->head != &up->list);
1630 i->head = NULL;
1631 }
1da177e4 1632 spin_unlock_irq(&i->lock);
25db8ad5
AC		 1633 /* List empty so throw away the hash node */
1634 if (i->head == NULL) {
1635 hlist_del(&i->node);
1636 kfree(i);
1637 }
1da177e4
LT		 1638}
1639
1640static int serial_link_irq_chain(struct uart_8250_port *up)
1641{
25db8ad5
AC		 1642 struct hlist_head *h;
1643 struct hlist_node *n;
1644 struct irq_info *i;
40663cc7 1645 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1da177e4 1646
25db8ad5
AC		 1647 mutex_lock(&hash_mutex);
1648
1649 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1650
1651 hlist_for_each(n, h) {
1652 i = hlist_entry(n, struct irq_info, node);
1653 if (i->irq == up->port.irq)
1654 break;
1655 }
1656
1657 if (n == NULL) {
1658 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1659 if (i == NULL) {
1660 mutex_unlock(&hash_mutex);
1661 return -ENOMEM;
1662 }
1663 spin_lock_init(&i->lock);
1664 i->irq = up->port.irq;
1665 hlist_add_head(&i->node, h);
1666 }
1667 mutex_unlock(&hash_mutex);
1668
1da177e4
LT		 1669 spin_lock_irq(&i->lock);
1670
1671 if (i->head) {
1672 list_add(&up->list, i->head);
1673 spin_unlock_irq(&i->lock);
1674
1675 ret = 0;
1676 } else {
1677 INIT_LIST_HEAD(&up->list);
1678 i->head = &up->list;
1679 spin_unlock_irq(&i->lock);
1c2f0493 1680 irq_flags |= up->port.irqflags;
1da177e4
LT		 1681 ret = request_irq(up->port.irq, serial8250_interrupt,
1682 irq_flags, "serial", i);
1683 if (ret < 0)
1684 serial_do_unlink(i, up);
1685 }
1686
1687 return ret;
1688}
1689
1690static void serial_unlink_irq_chain(struct uart_8250_port *up)
1691{
25db8ad5
AC		 1692 struct irq_info *i;
1693 struct hlist_node *n;
1694 struct hlist_head *h;
1da177e4 1695
25db8ad5
AC		 1696 mutex_lock(&hash_mutex);
1697
1698 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1699
1700 hlist_for_each(n, h) {
1701 i = hlist_entry(n, struct irq_info, node);
1702 if (i->irq == up->port.irq)
1703 break;
1704 }
1705
1706 BUG_ON(n == NULL);
1da177e4
LT		 1707 BUG_ON(i->head == NULL);
1708
1709 if (list_empty(i->head))
1710 free_irq(up->port.irq, i);
1711
1712 serial_do_unlink(i, up);
25db8ad5 1713 mutex_unlock(&hash_mutex);
1da177e4
LT		 1714}
1715
40b36daa
AW		 1716/* Base timer interval for polling */
1717static inline int poll_timeout(int timeout)
1718{
1719 return timeout > 6 ? (timeout / 2 - 2) : 1;
1720}
1721
1da177e4
LT		 1722/*
1723 * This function is used to handle ports that do not have an
1724 * interrupt. This doesn't work very well for 16450's, but gives
1725 * barely passable results for a 16550A. (Although at the expense
1726 * of much CPU overhead).
1727 */
1728static void serial8250_timeout(unsigned long data)
1729{
1730 struct uart_8250_port *up = (struct uart_8250_port *)data;
1da177e4
LT		 1731 unsigned int iir;
1732
1733 iir = serial_in(up, UART_IIR);
45e24601 1734 if (!(iir & UART_IIR_NO_INT))
7d12e780 1735 serial8250_handle_port(up);
40b36daa
AW		 1736 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1737}
1738
1739static void serial8250_backup_timeout(unsigned long data)
1740{
1741 struct uart_8250_port *up = (struct uart_8250_port *)data;
ad4c2aa6
CM		 1742 unsigned int iir, ier = 0, lsr;
1743 unsigned long flags;
40b36daa
AW		 1744
1745 /*
1746 * Must disable interrupts or else we risk racing with the interrupt
1747 * based handler.
1748 */
1749 if (is_real_interrupt(up->port.irq)) {
1750 ier = serial_in(up, UART_IER);
1751 serial_out(up, UART_IER, 0);
1752 }
1da177e4 1753
40b36daa
AW		 1754 iir = serial_in(up, UART_IIR);
1755
1756 /*
1757 * This should be a safe test for anyone who doesn't trust the
1758 * IIR bits on their UART, but it's specifically designed for
1759 * the "Diva" UART used on the management processor on many HP
1760 * ia64 and parisc boxes.
1761 */
ad4c2aa6
CM		 1762 spin_lock_irqsave(&up->port.lock, flags);
1763 lsr = serial_in(up, UART_LSR);
1764 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1765 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa 1766 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
ebd2c8f6 1767 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
ad4c2aa6 1768 (lsr & UART_LSR_THRE)) {
40b36daa
AW		 1769 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1770 iir |= UART_IIR_THRI;
1771 }
1772
1773 if (!(iir & UART_IIR_NO_INT))
1774 serial8250_handle_port(up);
1775
1776 if (is_real_interrupt(up->port.irq))
1777 serial_out(up, UART_IER, ier);
1778
1779 /* Standard timer interval plus 0.2s to keep the port running */
6f803cd0
AC		 1780 mod_timer(&up->timer,
1781 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1da177e4
LT		 1782}
1783
1784static unsigned int serial8250_tx_empty(struct uart_port *port)
1785{
1786 struct uart_8250_port *up = (struct uart_8250_port *)port;
1787 unsigned long flags;
ad4c2aa6 1788 unsigned int lsr;
1da177e4
LT		 1789
1790 spin_lock_irqsave(&up->port.lock, flags);
ad4c2aa6
CM		 1791 lsr = serial_in(up, UART_LSR);
1792 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1da177e4
LT		 1793 spin_unlock_irqrestore(&up->port.lock, flags);
1794
ad4c2aa6 1795 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1da177e4
LT		 1796}
1797
1798static unsigned int serial8250_get_mctrl(struct uart_port *port)
1799{
1800 struct uart_8250_port *up = (struct uart_8250_port *)port;
2af7cd68 1801 unsigned int status;
1da177e4
LT		 1802 unsigned int ret;
1803
2af7cd68 1804 status = check_modem_status(up);
1da177e4
LT		 1805
1806 ret = 0;
1807 if (status & UART_MSR_DCD)
1808 ret |= TIOCM_CAR;
1809 if (status & UART_MSR_RI)
1810 ret |= TIOCM_RNG;
1811 if (status & UART_MSR_DSR)
1812 ret |= TIOCM_DSR;
1813 if (status & UART_MSR_CTS)
1814 ret |= TIOCM_CTS;
1815 return ret;
1816}
1817
1818static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1819{
1820 struct uart_8250_port *up = (struct uart_8250_port *)port;
1821 unsigned char mcr = 0;
1822
1823 if (mctrl & TIOCM_RTS)
1824 mcr |= UART_MCR_RTS;
1825 if (mctrl & TIOCM_DTR)
1826 mcr |= UART_MCR_DTR;
1827 if (mctrl & TIOCM_OUT1)
1828 mcr |= UART_MCR_OUT1;
1829 if (mctrl & TIOCM_OUT2)
1830 mcr |= UART_MCR_OUT2;
1831 if (mctrl & TIOCM_LOOP)
1832 mcr |= UART_MCR_LOOP;
1833
1834 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1835
1836 serial_out(up, UART_MCR, mcr);
1837}
1838
1839static void serial8250_break_ctl(struct uart_port *port, int break_state)
1840{
1841 struct uart_8250_port *up = (struct uart_8250_port *)port;
1842 unsigned long flags;
1843
1844 spin_lock_irqsave(&up->port.lock, flags);
1845 if (break_state == -1)
1846 up->lcr |= UART_LCR_SBC;
1847 else
1848 up->lcr &= ~UART_LCR_SBC;
1849 serial_out(up, UART_LCR, up->lcr);
1850 spin_unlock_irqrestore(&up->port.lock, flags);
1851}
1852
40b36daa
AW		 1853#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1854
1855/*
1856 * Wait for transmitter & holding register to empty
1857 */
b5d674ab 1858static void wait_for_xmitr(struct uart_8250_port *up, int bits)
40b36daa
AW		 1859{
1860 unsigned int status, tmout = 10000;
1861
1862 /* Wait up to 10ms for the character(s) to be sent. */
1863 do {
1864 status = serial_in(up, UART_LSR);
1865
ad4c2aa6 1866 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
40b36daa
AW		 1867
1868 if (--tmout == 0)
1869 break;
1870 udelay(1);
1871 } while ((status & bits) != bits);
1872
1873 /* Wait up to 1s for flow control if necessary */
1874 if (up->port.flags & UPF_CONS_FLOW) {
ad4c2aa6
CM		 1875 unsigned int tmout;
1876 for (tmout = 1000000; tmout; tmout--) {
1877 unsigned int msr = serial_in(up, UART_MSR);
1878 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1879 if (msr & UART_MSR_CTS)
1880 break;
40b36daa
AW		 1881 udelay(1);
1882 touch_nmi_watchdog();
1883 }
1884 }
1885}
1886
f2d937f3
JW		 1887#ifdef CONFIG_CONSOLE_POLL
1888/*
1889 * Console polling routines for writing and reading from the uart while
1890 * in an interrupt or debug context.
1891 */
1892
1893static int serial8250_get_poll_char(struct uart_port *port)
1894{
1895 struct uart_8250_port *up = (struct uart_8250_port *)port;
1896 unsigned char lsr = serial_inp(up, UART_LSR);
1897
1898 while (!(lsr & UART_LSR_DR))
1899 lsr = serial_inp(up, UART_LSR);
1900
1901 return serial_inp(up, UART_RX);
1902}
1903
1904
1905static void serial8250_put_poll_char(struct uart_port *port,
1906 unsigned char c)
1907{
1908 unsigned int ier;
1909 struct uart_8250_port *up = (struct uart_8250_port *)port;
1910
1911 /*
1912 * First save the IER then disable the interrupts
1913 */
1914 ier = serial_in(up, UART_IER);
1915 if (up->capabilities & UART_CAP_UUE)
1916 serial_out(up, UART_IER, UART_IER_UUE);
1917 else
1918 serial_out(up, UART_IER, 0);
1919
1920 wait_for_xmitr(up, BOTH_EMPTY);
1921 /*
1922 * Send the character out.
1923 * If a LF, also do CR...
1924 */
1925 serial_out(up, UART_TX, c);
1926 if (c == 10) {
1927 wait_for_xmitr(up, BOTH_EMPTY);
1928 serial_out(up, UART_TX, 13);
1929 }
1930
1931 /*
1932 * Finally, wait for transmitter to become empty
1933 * and restore the IER
1934 */
1935 wait_for_xmitr(up, BOTH_EMPTY);
1936 serial_out(up, UART_IER, ier);
1937}
1938
1939#endif /* CONFIG_CONSOLE_POLL */
1940
1da177e4
LT		 1941static int serial8250_startup(struct uart_port *port)
1942{
1943 struct uart_8250_port *up = (struct uart_8250_port *)port;
1944 unsigned long flags;
55d3b282 1945 unsigned char lsr, iir;
1da177e4
LT		 1946 int retval;
1947
1948 up->capabilities = uart_config[up->port.type].flags;
1949 up->mcr = 0;
1950
b8e7e40a
AC		 1951 if (up->port.iotype != up->cur_iotype)
1952 set_io_from_upio(port);
1953
1da177e4
LT		 1954 if (up->port.type == PORT_16C950) {
1955 /* Wake up and initialize UART */
1956 up->acr = 0;
1957 serial_outp(up, UART_LCR, 0xBF);
1958 serial_outp(up, UART_EFR, UART_EFR_ECB);
1959 serial_outp(up, UART_IER, 0);
1960 serial_outp(up, UART_LCR, 0);
1961 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1962 serial_outp(up, UART_LCR, 0xBF);
1963 serial_outp(up, UART_EFR, UART_EFR_ECB);
1964 serial_outp(up, UART_LCR, 0);
1965 }
1966
1967#ifdef CONFIG_SERIAL_8250_RSA
1968 /*
1969 * If this is an RSA port, see if we can kick it up to the
1970 * higher speed clock.
1971 */
1972 enable_rsa(up);
1973#endif
1974
1975 /*
1976 * Clear the FIFO buffers and disable them.
7f927fcc 1977 * (they will be reenabled in set_termios())
1da177e4
LT		 1978 */
1979 serial8250_clear_fifos(up);
1980
1981 /*
1982 * Clear the interrupt registers.
1983 */
1984 (void) serial_inp(up, UART_LSR);
1985 (void) serial_inp(up, UART_RX);
1986 (void) serial_inp(up, UART_IIR);
1987 (void) serial_inp(up, UART_MSR);
1988
1989 /*
1990 * At this point, there's no way the LSR could still be 0xff;
1991 * if it is, then bail out, because there's likely no UART
1992 * here.
1993 */
1994 if (!(up->port.flags & UPF_BUGGY_UART) &&
1995 (serial_inp(up, UART_LSR) == 0xff)) {
8440838b
DM		 1996 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1997 serial_index(&up->port));
1da177e4
LT		 1998 return -ENODEV;
1999 }
2000
2001 /*
2002 * For a XR16C850, we need to set the trigger levels
2003 */
2004 if (up->port.type == PORT_16850) {
2005 unsigned char fctr;
2006
2007 serial_outp(up, UART_LCR, 0xbf);
2008
2009 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2010 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2011 serial_outp(up, UART_TRG, UART_TRG_96);
2012 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2013 serial_outp(up, UART_TRG, UART_TRG_96);
2014
2015 serial_outp(up, UART_LCR, 0);
2016 }
2017
40b36daa 2018 if (is_real_interrupt(up->port.irq)) {
01c194d9 2019 unsigned char iir1;
40b36daa
AW		 2020 /*
2021 * Test for UARTs that do not reassert THRE when the
2022 * transmitter is idle and the interrupt has already
2023 * been cleared. Real 16550s should always reassert
2024 * this interrupt whenever the transmitter is idle and
2025 * the interrupt is enabled. Delays are necessary to
2026 * allow register changes to become visible.
2027 */
c389d27b 2028 spin_lock_irqsave(&up->port.lock, flags);
1c2f0493 2029 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2030 disable_irq_nosync(up->port.irq);
40b36daa
AW		 2031
2032 wait_for_xmitr(up, UART_LSR_THRE);
2033 serial_out_sync(up, UART_IER, UART_IER_THRI);
2034 udelay(1); /* allow THRE to set */
01c194d9 2035 iir1 = serial_in(up, UART_IIR);
40b36daa
AW		 2036 serial_out(up, UART_IER, 0);
2037 serial_out_sync(up, UART_IER, UART_IER_THRI);
2038 udelay(1); /* allow a working UART time to re-assert THRE */
2039 iir = serial_in(up, UART_IIR);
2040 serial_out(up, UART_IER, 0);
2041
1c2f0493 2042 if (up->port.irqflags & IRQF_SHARED)
768aec0b 2043 enable_irq(up->port.irq);
c389d27b 2044 spin_unlock_irqrestore(&up->port.lock, flags);
40b36daa
AW		 2045
2046 /*
2047 * If the interrupt is not reasserted, setup a timer to
2048 * kick the UART on a regular basis.
2049 */
01c194d9 2050 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
363f66fe 2051 up->bugs |= UART_BUG_THRE;
8440838b
DM		 2052 pr_debug("ttyS%d - using backup timer\n",
2053 serial_index(port));
40b36daa
AW		 2054 }
2055 }
2056
363f66fe
WN		 2057 /*
2058 * The above check will only give an accurate result the first time
2059 * the port is opened so this value needs to be preserved.
2060 */
2061 if (up->bugs & UART_BUG_THRE) {
2062 up->timer.function = serial8250_backup_timeout;
2063 up->timer.data = (unsigned long)up;
2064 mod_timer(&up->timer, jiffies +
2065 poll_timeout(up->port.timeout) + HZ / 5);
2066 }
2067
1da177e4
LT		 2068 /*
2069 * If the "interrupt" for this port doesn't correspond with any
2070 * hardware interrupt, we use a timer-based system. The original
2071 * driver used to do this with IRQ0.
2072 */
2073 if (!is_real_interrupt(up->port.irq)) {
1da177e4 2074 up->timer.data = (unsigned long)up;
40b36daa 2075 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1da177e4
LT		 2076 } else {
2077 retval = serial_link_irq_chain(up);
2078 if (retval)
2079 return retval;
2080 }
2081
2082 /*
2083 * Now, initialize the UART
2084 */
2085 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2086
2087 spin_lock_irqsave(&up->port.lock, flags);
2088 if (up->port.flags & UPF_FOURPORT) {
2089 if (!is_real_interrupt(up->port.irq))
2090 up->port.mctrl |= TIOCM_OUT1;
2091 } else
2092 /*
2093 * Most PC uarts need OUT2 raised to enable interrupts.
2094 */
2095 if (is_real_interrupt(up->port.irq))
2096 up->port.mctrl |= TIOCM_OUT2;
2097
2098 serial8250_set_mctrl(&up->port, up->port.mctrl);
55d3b282 2099
b6adea33
MCC		 2100 /* Serial over Lan (SoL) hack:
2101 Intel 8257x Gigabit ethernet chips have a
2102 16550 emulation, to be used for Serial Over Lan.
2103 Those chips take a longer time than a normal
2104 serial device to signalize that a transmission
2105 data was queued. Due to that, the above test generally
2106 fails. One solution would be to delay the reading of
2107 iir. However, this is not reliable, since the timeout
2108 is variable. So, let's just don't test if we receive
2109 TX irq. This way, we'll never enable UART_BUG_TXEN.
2110 */
d41a4b51 2111 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
b6adea33
MCC		 2112 goto dont_test_tx_en;
2113
55d3b282
RK		 2114 /*
2115 * Do a quick test to see if we receive an
2116 * interrupt when we enable the TX irq.
2117 */
2118 serial_outp(up, UART_IER, UART_IER_THRI);
2119 lsr = serial_in(up, UART_LSR);
2120 iir = serial_in(up, UART_IIR);
2121 serial_outp(up, UART_IER, 0);
2122
2123 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
67f7654e
RK		 2124 if (!(up->bugs & UART_BUG_TXEN)) {
2125 up->bugs |= UART_BUG_TXEN;
55d3b282 2126 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
8440838b 2127 serial_index(port));
55d3b282
RK		 2128 }
2129 } else {
67f7654e 2130 up->bugs &= ~UART_BUG_TXEN;
55d3b282
RK		 2131 }
2132
b6adea33 2133dont_test_tx_en:
1da177e4
LT		 2134 spin_unlock_irqrestore(&up->port.lock, flags);
2135
ad4c2aa6
CM		 2136 /*
2137 * Clear the interrupt registers again for luck, and clear the
2138 * saved flags to avoid getting false values from polling
2139 * routines or the previous session.
2140 */
2141 serial_inp(up, UART_LSR);
2142 serial_inp(up, UART_RX);
2143 serial_inp(up, UART_IIR);
2144 serial_inp(up, UART_MSR);
2145 up->lsr_saved_flags = 0;
2146 up->msr_saved_flags = 0;
2147
1da177e4
LT		 2148 /*
2149 * Finally, enable interrupts. Note: Modem status interrupts
2150 * are set via set_termios(), which will be occurring imminently
2151 * anyway, so we don't enable them here.
2152 */
2153 up->ier = UART_IER_RLSI | UART_IER_RDI;
2154 serial_outp(up, UART_IER, up->ier);
2155
2156 if (up->port.flags & UPF_FOURPORT) {
2157 unsigned int icp;
2158 /*
2159 * Enable interrupts on the AST Fourport board
2160 */
2161 icp = (up->port.iobase & 0xfe0) | 0x01f;
2162 outb_p(0x80, icp);
2163 (void) inb_p(icp);
2164 }
2165
1da177e4
LT		 2166 return 0;
2167}
2168
2169static void serial8250_shutdown(struct uart_port *port)
2170{
2171 struct uart_8250_port *up = (struct uart_8250_port *)port;
2172 unsigned long flags;
2173
2174 /*
2175 * Disable interrupts from this port
2176 */
2177 up->ier = 0;
2178 serial_outp(up, UART_IER, 0);
2179
2180 spin_lock_irqsave(&up->port.lock, flags);
2181 if (up->port.flags & UPF_FOURPORT) {
2182 /* reset interrupts on the AST Fourport board */
2183 inb((up->port.iobase & 0xfe0) | 0x1f);
2184 up->port.mctrl |= TIOCM_OUT1;
2185 } else
2186 up->port.mctrl &= ~TIOCM_OUT2;
2187
2188 serial8250_set_mctrl(&up->port, up->port.mctrl);
2189 spin_unlock_irqrestore(&up->port.lock, flags);
2190
2191 /*
2192 * Disable break condition and FIFOs
2193 */
2194 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2195 serial8250_clear_fifos(up);
2196
2197#ifdef CONFIG_SERIAL_8250_RSA
2198 /*
2199 * Reset the RSA board back to 115kbps compat mode.
2200 */
2201 disable_rsa(up);
2202#endif
2203
2204 /*
2205 * Read data port to reset things, and then unlink from
2206 * the IRQ chain.
2207 */
2208 (void) serial_in(up, UART_RX);
2209
40b36daa
AW		 2210 del_timer_sync(&up->timer);
2211 up->timer.function = serial8250_timeout;
2212 if (is_real_interrupt(up->port.irq))
1da177e4
LT		 2213 serial_unlink_irq_chain(up);
2214}
2215
2216static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2217{
2218 unsigned int quot;
2219
2220 /*
2221 * Handle magic divisors for baud rates above baud_base on
2222 * SMSC SuperIO chips.
2223 */
2224 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2225 baud == (port->uartclk/4))
2226 quot = 0x8001;
2227 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2228 baud == (port->uartclk/8))
2229 quot = 0x8002;
2230 else
2231 quot = uart_get_divisor(port, baud);
2232
2233 return quot;
2234}
2235
2236static void
606d099c
AC		 2237serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2238 struct ktermios *old)
1da177e4
LT		 2239{
2240 struct uart_8250_port *up = (struct uart_8250_port *)port;
2241 unsigned char cval, fcr = 0;
2242 unsigned long flags;
2243 unsigned int baud, quot;
2244
2245 switch (termios->c_cflag & CSIZE) {
2246 case CS5:
0a8b80c5 2247 cval = UART_LCR_WLEN5;
1da177e4
LT		 2248 break;
2249 case CS6:
0a8b80c5 2250 cval = UART_LCR_WLEN6;
1da177e4
LT		 2251 break;
2252 case CS7:
0a8b80c5 2253 cval = UART_LCR_WLEN7;
1da177e4
LT		 2254 break;
2255 default:
2256 case CS8:
0a8b80c5 2257 cval = UART_LCR_WLEN8;
1da177e4
LT		 2258 break;
2259 }
2260
2261 if (termios->c_cflag & CSTOPB)
0a8b80c5 2262 cval |= UART_LCR_STOP;
1da177e4
LT		 2263 if (termios->c_cflag & PARENB)
2264 cval |= UART_LCR_PARITY;
2265 if (!(termios->c_cflag & PARODD))
2266 cval |= UART_LCR_EPAR;
2267#ifdef CMSPAR
2268 if (termios->c_cflag & CMSPAR)
2269 cval |= UART_LCR_SPAR;
2270#endif
2271
2272 /*
2273 * Ask the core to calculate the divisor for us.
2274 */
24d481ec
AV		 2275 baud = uart_get_baud_rate(port, termios, old,
2276 port->uartclk / 16 / 0xffff,
2277 port->uartclk / 16);
1da177e4
LT		 2278 quot = serial8250_get_divisor(port, baud);
2279
2280 /*
4ba5e35d 2281 * Oxford Semi 952 rev B workaround
1da177e4 2282 */
4ba5e35d 2283 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
3e8d4e20 2284 quot++;
1da177e4
LT		 2285
2286 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2287 if (baud < 2400)
2288 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2289 else
2290 fcr = uart_config[up->port.type].fcr;
2291 }
2292
2293 /*
2294 * MCR-based auto flow control. When AFE is enabled, RTS will be
2295 * deasserted when the receive FIFO contains more characters than
2296 * the trigger, or the MCR RTS bit is cleared. In the case where
2297 * the remote UART is not using CTS auto flow control, we must
2298 * have sufficient FIFO entries for the latency of the remote
2299 * UART to respond. IOW, at least 32 bytes of FIFO.
2300 */
2301 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2302 up->mcr &= ~UART_MCR_AFE;
2303 if (termios->c_cflag & CRTSCTS)
2304 up->mcr |= UART_MCR_AFE;
2305 }
2306
2307 /*
2308 * Ok, we're now changing the port state. Do it with
2309 * interrupts disabled.
2310 */
2311 spin_lock_irqsave(&up->port.lock, flags);
2312
2313 /*
2314 * Update the per-port timeout.
2315 */
2316 uart_update_timeout(port, termios->c_cflag, baud);
2317
2318 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2319 if (termios->c_iflag & INPCK)
2320 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2321 if (termios->c_iflag & (BRKINT | PARMRK))
2322 up->port.read_status_mask |= UART_LSR_BI;
2323
2324 /*
2325 * Characteres to ignore
2326 */
2327 up->port.ignore_status_mask = 0;
2328 if (termios->c_iflag & IGNPAR)
2329 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2330 if (termios->c_iflag & IGNBRK) {
2331 up->port.ignore_status_mask |= UART_LSR_BI;
2332 /*
2333 * If we're ignoring parity and break indicators,
2334 * ignore overruns too (for real raw support).
2335 */
2336 if (termios->c_iflag & IGNPAR)
2337 up->port.ignore_status_mask |= UART_LSR_OE;
2338 }
2339
2340 /*
2341 * ignore all characters if CREAD is not set
2342 */
2343 if ((termios->c_cflag & CREAD) == 0)
2344 up->port.ignore_status_mask |= UART_LSR_DR;
2345
2346 /*
2347 * CTS flow control flag and modem status interrupts
2348 */
2349 up->ier &= ~UART_IER_MSI;
21c614a7
PA		 2350 if (!(up->bugs & UART_BUG_NOMSR) &&
2351 UART_ENABLE_MS(&up->port, termios->c_cflag))
1da177e4
LT		 2352 up->ier |= UART_IER_MSI;
2353 if (up->capabilities & UART_CAP_UUE)
2354 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2355
2356 serial_out(up, UART_IER, up->ier);
2357
2358 if (up->capabilities & UART_CAP_EFR) {
2359 unsigned char efr = 0;
2360 /*
2361 * TI16C752/Startech hardware flow control. FIXME:
2362 * - TI16C752 requires control thresholds to be set.
2363 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2364 */
2365 if (termios->c_cflag & CRTSCTS)
2366 efr |= UART_EFR_CTS;
2367
2368 serial_outp(up, UART_LCR, 0xBF);
2369 serial_outp(up, UART_EFR, efr);
2370 }
2371
f2eda27d 2372#ifdef CONFIG_ARCH_OMAP
255341c6 2373 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
5668545a 2374 if (cpu_is_omap1510() && is_omap_port(up)) {
255341c6
JM		 2375 if (baud == 115200) {
2376 quot = 1;
2377 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2378 } else
2379 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2380 }
2381#endif
2382
1da177e4
LT		 2383 if (up->capabilities & UART_NATSEMI) {
2384 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2385 serial_outp(up, UART_LCR, 0xe0);
2386 } else {
2387 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2388 }
2389
b32b19b8 2390 serial_dl_write(up, quot);
1da177e4
LT		 2391
2392 /*
2393 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2394 * is written without DLAB set, this mode will be disabled.
2395 */
2396 if (up->port.type == PORT_16750)
2397 serial_outp(up, UART_FCR, fcr);
2398
2399 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2400 up->lcr = cval; /* Save LCR */
2401 if (up->port.type != PORT_16750) {
2402 if (fcr & UART_FCR_ENABLE_FIFO) {
2403 /* emulated UARTs (Lucent Venus 167x) need two steps */
2404 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2405 }
2406 serial_outp(up, UART_FCR, fcr); /* set fcr */
2407 }
2408 serial8250_set_mctrl(&up->port, up->port.mctrl);
2409 spin_unlock_irqrestore(&up->port.lock, flags);
e991a2bd
AC		 2410 /* Don't rewrite B0 */
2411 if (tty_termios_baud_rate(termios))
2412 tty_termios_encode_baud_rate(termios, baud, baud);
1da177e4
LT		 2413}
2414
2415static void
2416serial8250_pm(struct uart_port *port, unsigned int state,
2417 unsigned int oldstate)
2418{
2419 struct uart_8250_port *p = (struct uart_8250_port *)port;
2420
2421 serial8250_set_sleep(p, state != 0);
2422
2423 if (p->pm)
2424 p->pm(port, state, oldstate);
2425}
2426
f2eda27d
RK		 2427static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2428{
2429 if (pt->port.iotype == UPIO_AU)
2430 return 0x100000;
2431#ifdef CONFIG_ARCH_OMAP
2432 if (is_omap_port(pt))
2433 return 0x16 << pt->port.regshift;
2434#endif
2435 return 8 << pt->port.regshift;
2436}
2437
1da177e4
LT		 2438/*
2439 * Resource handling.
2440 */
2441static int serial8250_request_std_resource(struct uart_8250_port *up)
2442{
f2eda27d 2443 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2444 int ret = 0;
2445
2446 switch (up->port.iotype) {
85835f44 2447 case UPIO_AU:
0b30d668
SS		 2448 case UPIO_TSI:
2449 case UPIO_MEM32:
1da177e4 2450 case UPIO_MEM:
beab697a 2451 case UPIO_DWAPB:
1da177e4
LT		 2452 if (!up->port.mapbase)
2453 break;
2454
2455 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2456 ret = -EBUSY;
2457 break;
2458 }
2459
2460 if (up->port.flags & UPF_IOREMAP) {
6f441fe9
AC		 2461 up->port.membase = ioremap_nocache(up->port.mapbase,
2462 size);
1da177e4
LT		 2463 if (!up->port.membase) {
2464 release_mem_region(up->port.mapbase, size);
2465 ret = -ENOMEM;
2466 }
2467 }
2468 break;
2469
2470 case UPIO_HUB6:
2471 case UPIO_PORT:
2472 if (!request_region(up->port.iobase, size, "serial"))
2473 ret = -EBUSY;
2474 break;
2475 }
2476 return ret;
2477}
2478
2479static void serial8250_release_std_resource(struct uart_8250_port *up)
2480{
f2eda27d 2481 unsigned int size = serial8250_port_size(up);
1da177e4
LT		 2482
2483 switch (up->port.iotype) {
85835f44 2484 case UPIO_AU:
0b30d668
SS		 2485 case UPIO_TSI:
2486 case UPIO_MEM32:
1da177e4 2487 case UPIO_MEM:
beab697a 2488 case UPIO_DWAPB:
1da177e4
LT		 2489 if (!up->port.mapbase)
2490 break;
2491
2492 if (up->port.flags & UPF_IOREMAP) {
2493 iounmap(up->port.membase);
2494 up->port.membase = NULL;
2495 }
2496
2497 release_mem_region(up->port.mapbase, size);
2498 break;
2499
2500 case UPIO_HUB6:
2501 case UPIO_PORT:
2502 release_region(up->port.iobase, size);
2503 break;
2504 }
2505}
2506
2507static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2508{
2509 unsigned long start = UART_RSA_BASE << up->port.regshift;
2510 unsigned int size = 8 << up->port.regshift;
0b30d668 2511 int ret = -EINVAL;
1da177e4
LT		 2512
2513 switch (up->port.iotype) {
1da177e4
LT		 2514 case UPIO_HUB6:
2515 case UPIO_PORT:
2516 start += up->port.iobase;
0b30d668
SS		 2517 if (request_region(start, size, "serial-rsa"))
2518 ret = 0;
2519 else
1da177e4
LT		 2520 ret = -EBUSY;
2521 break;
2522 }
2523
2524 return ret;
2525}
2526
2527static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2528{
2529 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2530 unsigned int size = 8 << up->port.regshift;
2531
2532 switch (up->port.iotype) {
1da177e4
LT		 2533 case UPIO_HUB6:
2534 case UPIO_PORT:
2535 release_region(up->port.iobase + offset, size);
2536 break;
2537 }
2538}
2539
2540static void serial8250_release_port(struct uart_port *port)
2541{
2542 struct uart_8250_port *up = (struct uart_8250_port *)port;
2543
2544 serial8250_release_std_resource(up);
2545 if (up->port.type == PORT_RSA)
2546 serial8250_release_rsa_resource(up);
2547}
2548
2549static int serial8250_request_port(struct uart_port *port)
2550{
2551 struct uart_8250_port *up = (struct uart_8250_port *)port;
2552 int ret = 0;
2553
2554 ret = serial8250_request_std_resource(up);
2555 if (ret == 0 && up->port.type == PORT_RSA) {
2556 ret = serial8250_request_rsa_resource(up);
2557 if (ret < 0)
2558 serial8250_release_std_resource(up);
2559 }
2560
2561 return ret;
2562}
2563
2564static void serial8250_config_port(struct uart_port *port, int flags)
2565{
2566 struct uart_8250_port *up = (struct uart_8250_port *)port;
2567 int probeflags = PROBE_ANY;
2568 int ret;
2569
1da177e4
LT		 2570 /*
2571 * Find the region that we can probe for. This in turn
2572 * tells us whether we can probe for the type of port.
2573 */
2574 ret = serial8250_request_std_resource(up);
2575 if (ret < 0)
2576 return;
2577
2578 ret = serial8250_request_rsa_resource(up);
2579 if (ret < 0)
2580 probeflags &= ~PROBE_RSA;
2581
b8e7e40a
AC		 2582 if (up->port.iotype != up->cur_iotype)
2583 set_io_from_upio(port);
2584
1da177e4
LT		 2585 if (flags & UART_CONFIG_TYPE)
2586 autoconfig(up, probeflags);
2587 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2588 autoconfig_irq(up);
2589
2590 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2591 serial8250_release_rsa_resource(up);
2592 if (up->port.type == PORT_UNKNOWN)
2593 serial8250_release_std_resource(up);
2594}
2595
2596static int
2597serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2598{
a62c4133 2599 if (ser->irq >= nr_irqs || ser->irq < 0 ||
1da177e4
LT		 2600 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2601 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2602 ser->type == PORT_STARTECH)
2603 return -EINVAL;
2604 return 0;
2605}
2606
2607static const char *
2608serial8250_type(struct uart_port *port)
2609{
2610 int type = port->type;
2611
2612 if (type >= ARRAY_SIZE(uart_config))
2613 type = 0;
2614 return uart_config[type].name;
2615}
2616
2617static struct uart_ops serial8250_pops = {
2618 .tx_empty = serial8250_tx_empty,
2619 .set_mctrl = serial8250_set_mctrl,
2620 .get_mctrl = serial8250_get_mctrl,
2621 .stop_tx = serial8250_stop_tx,
2622 .start_tx = serial8250_start_tx,
2623 .stop_rx = serial8250_stop_rx,
2624 .enable_ms = serial8250_enable_ms,
2625 .break_ctl = serial8250_break_ctl,
2626 .startup = serial8250_startup,
2627 .shutdown = serial8250_shutdown,
2628 .set_termios = serial8250_set_termios,
2629 .pm = serial8250_pm,
2630 .type = serial8250_type,
2631 .release_port = serial8250_release_port,
2632 .request_port = serial8250_request_port,
2633 .config_port = serial8250_config_port,
2634 .verify_port = serial8250_verify_port,
f2d937f3
JW		 2635#ifdef CONFIG_CONSOLE_POLL
2636 .poll_get_char = serial8250_get_poll_char,
2637 .poll_put_char = serial8250_put_poll_char,
2638#endif
1da177e4
LT		 2639};
2640
2641static struct uart_8250_port serial8250_ports[UART_NR];
2642
2643static void __init serial8250_isa_init_ports(void)
2644{
2645 struct uart_8250_port *up;
2646 static int first = 1;
4c0ebb80 2647 int i, irqflag = 0;
1da177e4
LT		 2648
2649 if (!first)
2650 return;
2651 first = 0;
2652
a61c2d78 2653 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2654 struct uart_8250_port *up = &serial8250_ports[i];
2655
2656 up->port.line = i;
2657 spin_lock_init(&up->port.lock);
2658
2659 init_timer(&up->timer);
2660 up->timer.function = serial8250_timeout;
2661
2662 /*
2663 * ALPHA_KLUDGE_MCR needs to be killed.
2664 */
2665 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2666 up->mcr_force = ALPHA_KLUDGE_MCR;
2667
2668 up->port.ops = &serial8250_pops;
2669 }
2670
4c0ebb80
AGR		 2671 if (share_irqs)
2672 irqflag = IRQF_SHARED;
2673
44454bcd 2674 for (i = 0, up = serial8250_ports;
a61c2d78 2675 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
1da177e4
LT		 2676 i++, up++) {
2677 up->port.iobase = old_serial_port[i].port;
2678 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
1c2f0493 2679 up->port.irqflags = old_serial_port[i].irqflags;
1da177e4
LT		 2680 up->port.uartclk = old_serial_port[i].baud_base * 16;
2681 up->port.flags = old_serial_port[i].flags;
2682 up->port.hub6 = old_serial_port[i].hub6;
2683 up->port.membase = old_serial_port[i].iomem_base;
2684 up->port.iotype = old_serial_port[i].io_type;
2685 up->port.regshift = old_serial_port[i].iomem_reg_shift;
7d6a07d1 2686 set_io_from_upio(&up->port);
4c0ebb80 2687 up->port.irqflags |= irqflag;
1da177e4
LT		 2688 }
2689}
2690
2691static void __init
2692serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2693{
2694 int i;
2695
b8e7e40a
AC		 2696 for (i = 0; i < nr_uarts; i++) {
2697 struct uart_8250_port *up = &serial8250_ports[i];
2698 up->cur_iotype = 0xFF;
2699 }
2700
1da177e4
LT		 2701 serial8250_isa_init_ports();
2702
a61c2d78 2703 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2704 struct uart_8250_port *up = &serial8250_ports[i];
2705
2706 up->port.dev = dev;
2707 uart_add_one_port(drv, &up->port);
2708 }
2709}
2710
2711#ifdef CONFIG_SERIAL_8250_CONSOLE
2712
d358788f
RK		 2713static void serial8250_console_putchar(struct uart_port *port, int ch)
2714{
2715 struct uart_8250_port *up = (struct uart_8250_port *)port;
2716
2717 wait_for_xmitr(up, UART_LSR_THRE);
2718 serial_out(up, UART_TX, ch);
2719}
2720
1da177e4
LT		 2721/*
2722 * Print a string to the serial port trying not to disturb
2723 * any possible real use of the port...
2724 *
2725 * The console_lock must be held when we get here.
2726 */
2727static void
2728serial8250_console_write(struct console *co, const char *s, unsigned int count)
2729{
2730 struct uart_8250_port *up = &serial8250_ports[co->index];
d8a5a8d7 2731 unsigned long flags;
1da177e4 2732 unsigned int ier;
d8a5a8d7 2733 int locked = 1;
1da177e4 2734
78512ece
AM		 2735 touch_nmi_watchdog();
2736
68aa2c0d
AM		 2737 local_irq_save(flags);
2738 if (up->port.sysrq) {
2739 /* serial8250_handle_port() already took the lock */
2740 locked = 0;
2741 } else if (oops_in_progress) {
2742 locked = spin_trylock(&up->port.lock);
d8a5a8d7 2743 } else
68aa2c0d 2744 spin_lock(&up->port.lock);
d8a5a8d7 2745
1da177e4 2746 /*
dc7bf130 2747 * First save the IER then disable the interrupts
1da177e4
LT		 2748 */
2749 ier = serial_in(up, UART_IER);
2750
2751 if (up->capabilities & UART_CAP_UUE)
2752 serial_out(up, UART_IER, UART_IER_UUE);
2753 else
2754 serial_out(up, UART_IER, 0);
2755
d358788f 2756 uart_console_write(&up->port, s, count, serial8250_console_putchar);
1da177e4
LT		 2757
2758 /*
2759 * Finally, wait for transmitter to become empty
2760 * and restore the IER
2761 */
f91a3715 2762 wait_for_xmitr(up, BOTH_EMPTY);
a88d75b2 2763 serial_out(up, UART_IER, ier);
d8a5a8d7 2764
ad4c2aa6
CM		 2765 /*
2766 * The receive handling will happen properly because the
2767 * receive ready bit will still be set; it is not cleared
2768 * on read. However, modem control will not, we must
2769 * call it if we have saved something in the saved flags
2770 * while processing with interrupts off.
2771 */
2772 if (up->msr_saved_flags)
2773 check_modem_status(up);
2774
d8a5a8d7 2775 if (locked)
68aa2c0d
AM		 2776 spin_unlock(&up->port.lock);
2777 local_irq_restore(flags);
1da177e4
LT		 2778}
2779
118c0ace 2780static int __init serial8250_console_setup(struct console *co, char *options)
1da177e4
LT		 2781{
2782 struct uart_port *port;
2783 int baud = 9600;
2784 int bits = 8;
2785 int parity = 'n';
2786 int flow = 'n';
2787
2788 /*
2789 * Check whether an invalid uart number has been specified, and
2790 * if so, search for the first available port that does have
2791 * console support.
2792 */
a61c2d78 2793 if (co->index >= nr_uarts)
1da177e4
LT		 2794 co->index = 0;
2795 port = &serial8250_ports[co->index].port;
2796 if (!port->iobase && !port->membase)
2797 return -ENODEV;
2798
2799 if (options)
2800 uart_parse_options(options, &baud, &parity, &bits, &flow);
2801
2802 return uart_set_options(port, co, baud, parity, bits, flow);
2803}
2804
b6b1d877 2805static int serial8250_console_early_setup(void)
18a8bd94
YL		 2806{
2807 return serial8250_find_port_for_earlycon();
2808}
2809
1da177e4
LT		 2810static struct console serial8250_console = {
2811 .name = "ttyS",
2812 .write = serial8250_console_write,
2813 .device = uart_console_device,
2814 .setup = serial8250_console_setup,
18a8bd94 2815 .early_setup = serial8250_console_early_setup,
1da177e4
LT		 2816 .flags = CON_PRINTBUFFER,
2817 .index = -1,
2818 .data = &serial8250_reg,
2819};
2820
2821static int __init serial8250_console_init(void)
2822{
05d81d22
EB		 2823 if (nr_uarts > UART_NR)
2824 nr_uarts = UART_NR;
2825
1da177e4
LT		 2826 serial8250_isa_init_ports();
2827 register_console(&serial8250_console);
2828 return 0;
2829}
2830console_initcall(serial8250_console_init);
2831
18a8bd94 2832int serial8250_find_port(struct uart_port *p)
1da177e4
LT		 2833{
2834 int line;
2835 struct uart_port *port;
2836
a61c2d78 2837 for (line = 0; line < nr_uarts; line++) {
1da177e4 2838 port = &serial8250_ports[line].port;
50aec3b5 2839 if (uart_match_port(p, port))
1da177e4
LT		 2840 return line;
2841 }
2842 return -ENODEV;
2843}
2844
1da177e4
LT		 2845#define SERIAL8250_CONSOLE &serial8250_console
2846#else
2847#define SERIAL8250_CONSOLE NULL
2848#endif
2849
2850static struct uart_driver serial8250_reg = {
2851 .owner = THIS_MODULE,
2852 .driver_name = "serial",
1da177e4
LT		 2853 .dev_name = "ttyS",
2854 .major = TTY_MAJOR,
2855 .minor = 64,
1da177e4
LT		 2856 .cons = SERIAL8250_CONSOLE,
2857};
2858
d856c666
RK		 2859/*
2860 * early_serial_setup - early registration for 8250 ports
2861 *
2862 * Setup an 8250 port structure prior to console initialisation. Use
2863 * after console initialisation will cause undefined behaviour.
2864 */
1da177e4
LT		 2865int __init early_serial_setup(struct uart_port *port)
2866{
b430428a
DD		 2867 struct uart_port *p;
2868
1da177e4
LT		 2869 if (port->line >= ARRAY_SIZE(serial8250_ports))
2870 return -ENODEV;
2871
2872 serial8250_isa_init_ports();
b430428a
DD		 2873 p = &serial8250_ports[port->line].port;
2874 p->iobase = port->iobase;
2875 p->membase = port->membase;
2876 p->irq = port->irq;
1c2f0493 2877 p->irqflags = port->irqflags;
b430428a
DD		 2878 p->uartclk = port->uartclk;
2879 p->fifosize = port->fifosize;
2880 p->regshift = port->regshift;
2881 p->iotype = port->iotype;
2882 p->flags = port->flags;
2883 p->mapbase = port->mapbase;
2884 p->private_data = port->private_data;
125c97d8
HD		 2885 p->type = port->type;
2886 p->line = port->line;
7d6a07d1
DD		 2887
2888 set_io_from_upio(p);
2889 if (port->serial_in)
2890 p->serial_in = port->serial_in;
2891 if (port->serial_out)
2892 p->serial_out = port->serial_out;
2893
1da177e4
LT		 2894 return 0;
2895}
2896
2897/**
2898 * serial8250_suspend_port - suspend one serial port
2899 * @line: serial line number
1da177e4
LT		 2900 *
2901 * Suspend one serial port.
2902 */
2903void serial8250_suspend_port(int line)
2904{
2905 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2906}
2907
2908/**
2909 * serial8250_resume_port - resume one serial port
2910 * @line: serial line number
1da177e4
LT		 2911 *
2912 * Resume one serial port.
2913 */
2914void serial8250_resume_port(int line)
2915{
b5b82df6
DW		 2916 struct uart_8250_port *up = &serial8250_ports[line];
2917
2918 if (up->capabilities & UART_NATSEMI) {
2919 unsigned char tmp;
2920
2921 /* Ensure it's still in high speed mode */
2922 serial_outp(up, UART_LCR, 0xE0);
2923
2924 tmp = serial_in(up, 0x04); /* EXCR2 */
2925 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2926 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2927 serial_outp(up, 0x04, tmp);
2928
2929 serial_outp(up, UART_LCR, 0);
2930 }
2931 uart_resume_port(&serial8250_reg, &up->port);
1da177e4
LT		 2932}
2933
2934/*
2935 * Register a set of serial devices attached to a platform device. The
2936 * list is terminated with a zero flags entry, which means we expect
2937 * all entries to have at least UPF_BOOT_AUTOCONF set.
2938 */
3ae5eaec 2939static int __devinit serial8250_probe(struct platform_device *dev)
1da177e4 2940{
3ae5eaec 2941 struct plat_serial8250_port *p = dev->dev.platform_data;
1da177e4 2942 struct uart_port port;
4c0ebb80 2943 int ret, i, irqflag = 0;
1da177e4
LT		 2944
2945 memset(&port, 0, sizeof(struct uart_port));
2946
4c0ebb80
AGR		 2947 if (share_irqs)
2948 irqflag = IRQF_SHARED;
2949
ec9f47cd 2950 for (i = 0; p && p->flags != 0; p++, i++) {
74a19741
WN		 2951 port.iobase = p->iobase;
2952 port.membase = p->membase;
2953 port.irq = p->irq;
1c2f0493 2954 port.irqflags = p->irqflags;
74a19741
WN		 2955 port.uartclk = p->uartclk;
2956 port.regshift = p->regshift;
2957 port.iotype = p->iotype;
2958 port.flags = p->flags;
2959 port.mapbase = p->mapbase;
2960 port.hub6 = p->hub6;
2961 port.private_data = p->private_data;
8e23fcc8 2962 port.type = p->type;
7d6a07d1
DD		 2963 port.serial_in = p->serial_in;
2964 port.serial_out = p->serial_out;
74a19741 2965 port.dev = &dev->dev;
4c0ebb80 2966 port.irqflags |= irqflag;
ec9f47cd
RK		 2967 ret = serial8250_register_port(&port);
2968 if (ret < 0) {
3ae5eaec 2969 dev_err(&dev->dev, "unable to register port at index %d "
4f640efb
JB		 2970 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2971 p->iobase, (unsigned long long)p->mapbase,
2972 p->irq, ret);
ec9f47cd 2973 }
1da177e4
LT		 2974 }
2975 return 0;
2976}
2977
2978/*
2979 * Remove serial ports registered against a platform device.
2980 */
3ae5eaec 2981static int __devexit serial8250_remove(struct platform_device *dev)
1da177e4
LT		 2982{
2983 int i;
2984
a61c2d78 2985 for (i = 0; i < nr_uarts; i++) {
1da177e4
LT		 2986 struct uart_8250_port *up = &serial8250_ports[i];
2987
3ae5eaec 2988 if (up->port.dev == &dev->dev)
1da177e4
LT		 2989 serial8250_unregister_port(i);
2990 }
2991 return 0;
2992}
2993
3ae5eaec 2994static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
1da177e4
LT		 2995{
2996 int i;
2997
1da177e4
LT		 2998 for (i = 0; i < UART_NR; i++) {
2999 struct uart_8250_port *up = &serial8250_ports[i];
3000
3ae5eaec 3001 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
1da177e4
LT		 3002 uart_suspend_port(&serial8250_reg, &up->port);
3003 }
3004
3005 return 0;
3006}
3007
3ae5eaec 3008static int serial8250_resume(struct platform_device *dev)
1da177e4
LT		 3009{
3010 int i;
3011
1da177e4
LT		 3012 for (i = 0; i < UART_NR; i++) {
3013 struct uart_8250_port *up = &serial8250_ports[i];
3014
3ae5eaec 3015 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
b5b82df6 3016 serial8250_resume_port(i);
1da177e4
LT		 3017 }
3018
3019 return 0;
3020}
3021
3ae5eaec 3022static struct platform_driver serial8250_isa_driver = {
1da177e4
LT		 3023 .probe = serial8250_probe,
3024 .remove = __devexit_p(serial8250_remove),
3025 .suspend = serial8250_suspend,
3026 .resume = serial8250_resume,
3ae5eaec
RK		 3027 .driver = {
3028 .name = "serial8250",
7493a314 3029 .owner = THIS_MODULE,
3ae5eaec 3030 },
1da177e4
LT		 3031};
3032
3033/*
3034 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3035 * in the table in include/asm/serial.h
3036 */
3037static struct platform_device *serial8250_isa_devs;
3038
3039/*
3040 * serial8250_register_port and serial8250_unregister_port allows for
3041 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3042 * modems and PCI multiport cards.
3043 */
f392ecfa 3044static DEFINE_MUTEX(serial_mutex);
1da177e4
LT		 3045
3046static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3047{
3048 int i;
3049
3050 /*
3051 * First, find a port entry which matches.
3052 */
a61c2d78 3053 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3054 if (uart_match_port(&serial8250_ports[i].port, port))
3055 return &serial8250_ports[i];
3056
3057 /*
3058 * We didn't find a matching entry, so look for the first
3059 * free entry. We look for one which hasn't been previously
3060 * used (indicated by zero iobase).
3061 */
a61c2d78 3062 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3063 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3064 serial8250_ports[i].port.iobase == 0)
3065 return &serial8250_ports[i];
3066
3067 /*
3068 * That also failed. Last resort is to find any entry which
3069 * doesn't have a real port associated with it.
3070 */
a61c2d78 3071 for (i = 0; i < nr_uarts; i++)
1da177e4
LT		 3072 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3073 return &serial8250_ports[i];
3074
3075 return NULL;
3076}
3077
3078/**
3079 * serial8250_register_port - register a serial port
3080 * @port: serial port template
3081 *
3082 * Configure the serial port specified by the request. If the
3083 * port exists and is in use, it is hung up and unregistered
3084 * first.
3085 *
3086 * The port is then probed and if necessary the IRQ is autodetected
3087 * If this fails an error is returned.
3088 *
3089 * On success the port is ready to use and the line number is returned.
3090 */
3091int serial8250_register_port(struct uart_port *port)
3092{
3093 struct uart_8250_port *uart;
3094 int ret = -ENOSPC;
3095
3096 if (port->uartclk == 0)
3097 return -EINVAL;
3098
f392ecfa 3099 mutex_lock(&serial_mutex);
1da177e4
LT		 3100
3101 uart = serial8250_find_match_or_unused(port);
3102 if (uart) {
3103 uart_remove_one_port(&serial8250_reg, &uart->port);
3104
74a19741
WN		 3105 uart->port.iobase = port->iobase;
3106 uart->port.membase = port->membase;
3107 uart->port.irq = port->irq;
1c2f0493 3108 uart->port.irqflags = port->irqflags;
74a19741
WN		 3109 uart->port.uartclk = port->uartclk;
3110 uart->port.fifosize = port->fifosize;
3111 uart->port.regshift = port->regshift;
3112 uart->port.iotype = port->iotype;
3113 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3114 uart->port.mapbase = port->mapbase;
3115 uart->port.private_data = port->private_data;
1da177e4
LT		 3116 if (port->dev)
3117 uart->port.dev = port->dev;
8e23fcc8
DD		 3118
3119 if (port->flags & UPF_FIXED_TYPE) {
3120 uart->port.type = port->type;
3121 uart->port.fifosize = uart_config[port->type].fifo_size;
3122 uart->capabilities = uart_config[port->type].flags;
3123 uart->tx_loadsz = uart_config[port->type].tx_loadsz;
3124 }
3125
7d6a07d1
DD		 3126 set_io_from_upio(&uart->port);
3127 /* Possibly override default I/O functions. */
3128 if (port->serial_in)
3129 uart->port.serial_in = port->serial_in;
3130 if (port->serial_out)
3131 uart->port.serial_out = port->serial_out;
1da177e4
LT		 3132
3133 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3134 if (ret == 0)
3135 ret = uart->port.line;
3136 }
f392ecfa 3137 mutex_unlock(&serial_mutex);
1da177e4
LT		 3138
3139 return ret;
3140}
3141EXPORT_SYMBOL(serial8250_register_port);
3142
3143/**
3144 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3145 * @line: serial line number
3146 *
3147 * Remove one serial port. This may not be called from interrupt
3148 * context. We hand the port back to the our control.
3149 */
3150void serial8250_unregister_port(int line)
3151{
3152 struct uart_8250_port *uart = &serial8250_ports[line];
3153
f392ecfa 3154 mutex_lock(&serial_mutex);
1da177e4
LT		 3155 uart_remove_one_port(&serial8250_reg, &uart->port);
3156 if (serial8250_isa_devs) {
3157 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3158 uart->port.type = PORT_UNKNOWN;
3159 uart->port.dev = &serial8250_isa_devs->dev;
3160 uart_add_one_port(&serial8250_reg, &uart->port);
3161 } else {
3162 uart->port.dev = NULL;
3163 }
f392ecfa 3164 mutex_unlock(&serial_mutex);
1da177e4
LT		 3165}
3166EXPORT_SYMBOL(serial8250_unregister_port);
3167
3168static int __init serial8250_init(void)
3169{
25db8ad5 3170 int ret;
1da177e4 3171
a61c2d78
DJ		 3172 if (nr_uarts > UART_NR)
3173 nr_uarts = UART_NR;
3174
f1fb9bb8 3175 printk(KERN_INFO "Serial: 8250/16550 driver, "
a61c2d78 3176 "%d ports, IRQ sharing %sabled\n", nr_uarts,
1da177e4
LT		 3177 share_irqs ? "en" : "dis");
3178
b70ac771
DM		 3179#ifdef CONFIG_SPARC
3180 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3181#else
3182 serial8250_reg.nr = UART_NR;
1da177e4 3183 ret = uart_register_driver(&serial8250_reg);
b70ac771 3184#endif
1da177e4
LT		 3185 if (ret)
3186 goto out;
3187
7493a314
DT		 3188 serial8250_isa_devs = platform_device_alloc("serial8250",
3189 PLAT8250_DEV_LEGACY);
3190 if (!serial8250_isa_devs) {
3191 ret = -ENOMEM;
bc965a7f 3192 goto unreg_uart_drv;
1da177e4
LT		 3193 }
3194
7493a314
DT		 3195 ret = platform_device_add(serial8250_isa_devs);
3196 if (ret)
3197 goto put_dev;
3198
1da177e4
LT		 3199 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3200
bc965a7f
RK		 3201 ret = platform_driver_register(&serial8250_isa_driver);
3202 if (ret == 0)
3203 goto out;
1da177e4 3204
bc965a7f 3205 platform_device_del(serial8250_isa_devs);
25db8ad5 3206put_dev:
7493a314 3207 platform_device_put(serial8250_isa_devs);
25db8ad5 3208unreg_uart_drv:
b70ac771
DM		 3209#ifdef CONFIG_SPARC
3210 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3211#else
1da177e4 3212 uart_unregister_driver(&serial8250_reg);
b70ac771 3213#endif
25db8ad5 3214out:
1da177e4
LT		 3215 return ret;
3216}
3217
3218static void __exit serial8250_exit(void)
3219{
3220 struct platform_device *isa_dev = serial8250_isa_devs;
3221
3222 /*
3223 * This tells serial8250_unregister_port() not to re-register
3224 * the ports (thereby making serial8250_isa_driver permanently
3225 * in use.)
3226 */
3227 serial8250_isa_devs = NULL;
3228
3ae5eaec 3229 platform_driver_unregister(&serial8250_isa_driver);
1da177e4
LT		 3230 platform_device_unregister(isa_dev);
3231
b70ac771
DM		 3232#ifdef CONFIG_SPARC
3233 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3234#else
1da177e4 3235 uart_unregister_driver(&serial8250_reg);
b70ac771 3236#endif
1da177e4
LT		 3237}
3238
3239module_init(serial8250_init);
3240module_exit(serial8250_exit);
3241
3242EXPORT_SYMBOL(serial8250_suspend_port);
3243EXPORT_SYMBOL(serial8250_resume_port);
3244
3245MODULE_LICENSE("GPL");
d87a6d95 3246MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
1da177e4
LT		 3247
3248module_param(share_irqs, uint, 0644);
3249MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3250 " (unsafe)");
3251
a61c2d78
DJ		 3252module_param(nr_uarts, uint, 0644);
3253MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3254
d41a4b51
CE		 3255module_param(skip_txen_test, uint, 0644);
3256MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3257
1da177e4
LT		 3258#ifdef CONFIG_SERIAL_8250_RSA
3259module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3260MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3261#endif
3262MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
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