[net-next-2.6.git] / drivers / scsi / sun_esp.c

/* sun_esp.c: ESP front-end for Sparc SBUS systems.
 *
 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
 */

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/mm.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/gfp.h>

#include <asm/irq.h>
#include <asm/io.h>
#include <asm/dma.h>

#include <scsi/scsi_host.h>

#include "esp_scsi.h"

#define DRV_MODULE_NAME		"sun_esp"
#define PFX DRV_MODULE_NAME	": "
#define DRV_VERSION		"1.100"
#define DRV_MODULE_RELDATE	"August 27, 2008"

#define dma_read32(REG) \
	sbus_readl(esp->dma_regs + (REG))
#define dma_write32(VAL, REG) \
	sbus_writel((VAL), esp->dma_regs + (REG))

/* DVMA chip revisions */
enum dvma_rev {
	dvmarev0,
	dvmaesc1,
	dvmarev1,
	dvmarev2,
	dvmarev3,
	dvmarevplus,
	dvmahme
};

static int __devinit esp_sbus_setup_dma(struct esp *esp,
					struct of_device *dma_of)
{
	esp->dma = dma_of;

	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
				   resource_size(&dma_of->resource[0]),
				   "espdma");
	if (!esp->dma_regs)
		return -ENOMEM;

	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	case DMA_VERS0:
		esp->dmarev = dvmarev0;
		break;
	case DMA_ESCV1:
		esp->dmarev = dvmaesc1;
		break;
	case DMA_VERS1:
		esp->dmarev = dvmarev1;
		break;
	case DMA_VERS2:
		esp->dmarev = dvmarev2;
		break;
	case DMA_VERHME:
		esp->dmarev = dvmahme;
		break;
	case DMA_VERSPLUS:
		esp->dmarev = dvmarevplus;
		break;
	}

	return 0;

}

static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
{
	struct of_device *op = esp->dev;
	struct resource *res;

	/* On HME, two reg sets exist, first is DVMA,
	 * second is ESP registers.
	 */
	if (hme)
		res = &op->resource[1];
	else
		res = &op->resource[0];

	esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
	if (!esp->regs)
		return -ENOMEM;

	return 0;
}

static int __devinit esp_sbus_map_command_block(struct esp *esp)
{
	struct of_device *op = esp->dev;

	esp->command_block = dma_alloc_coherent(&op->dev, 16,
						&esp->command_block_dma,
						GFP_ATOMIC);
	if (!esp->command_block)
		return -ENOMEM;
	return 0;
}

static int __devinit esp_sbus_register_irq(struct esp *esp)
{
	struct Scsi_Host *host = esp->host;
	struct of_device *op = esp->dev;

	host->irq = op->irqs[0];
	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
}

static void __devinit esp_get_scsi_id(struct esp *esp, struct of_device *espdma)
{
	struct of_device *op = esp->dev;
	struct device_node *dp;

	dp = op->node;
	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	if (esp->scsi_id != 0xff)
		goto done;

	esp->scsi_id = of_getintprop_default(espdma->node,
					     "scsi-initiator-id", 7);

done:
	esp->host->this_id = esp->scsi_id;
	esp->scsi_id_mask = (1 << esp->scsi_id);
}

static void __devinit esp_get_differential(struct esp *esp)
{
	struct of_device *op = esp->dev;
	struct device_node *dp;

	dp = op->node;
	if (of_find_property(dp, "differential", NULL))
		esp->flags |= ESP_FLAG_DIFFERENTIAL;
	else
		esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
}

static void __devinit esp_get_clock_params(struct esp *esp)
{
	struct of_device *op = esp->dev;
	struct device_node *bus_dp, *dp;
	int fmhz;

	dp = op->node;
	bus_dp = dp->parent;

	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	if (fmhz == 0)
		fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);

	esp->cfreq = fmhz;
}

static void __devinit esp_get_bursts(struct esp *esp, struct of_device *dma_of)
{
	struct device_node *dma_dp = dma_of->node;
	struct of_device *op = esp->dev;
	struct device_node *dp;
	u8 bursts, val;

	dp = op->node;
	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
	if (val != 0xff)
		bursts &= val;

	if (bursts == 0xff ||
	    (bursts & DMA_BURST16) == 0 ||
	    (bursts & DMA_BURST32) == 0)
		bursts = (DMA_BURST32 - 1);

	esp->bursts = bursts;
}

static void __devinit esp_sbus_get_props(struct esp *esp, struct of_device *espdma)
{
	esp_get_scsi_id(esp, espdma);
	esp_get_differential(esp);
	esp_get_clock_params(esp);
	esp_get_bursts(esp, espdma);
}

static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
{
	sbus_writeb(val, esp->regs + (reg * 4UL));
}

static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
{
	return sbus_readb(esp->regs + (reg * 4UL));
}

static dma_addr_t sbus_esp_map_single(struct esp *esp, void *buf,
				      size_t sz, int dir)
{
	struct of_device *op = esp->dev;

	return dma_map_single(&op->dev, buf, sz, dir);
}

static int sbus_esp_map_sg(struct esp *esp, struct scatterlist *sg,
				  int num_sg, int dir)
{
	struct of_device *op = esp->dev;

	return dma_map_sg(&op->dev, sg, num_sg, dir);
}

static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
				  size_t sz, int dir)
{
	struct of_device *op = esp->dev;

	dma_unmap_single(&op->dev, addr, sz, dir);
}

static void sbus_esp_unmap_sg(struct esp *esp, struct scatterlist *sg,
			      int num_sg, int dir)
{
	struct of_device *op = esp->dev;

	dma_unmap_sg(&op->dev, sg, num_sg, dir);
}

static int sbus_esp_irq_pending(struct esp *esp)
{
	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR | DMA_HNDL_ERROR))
		return 1;
	return 0;
}

static void sbus_esp_reset_dma(struct esp *esp)
{
	int can_do_burst16, can_do_burst32, can_do_burst64;
	int can_do_sbus64, lim;
	struct of_device *op;
	u32 val;

	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	can_do_burst64 = 0;
	can_do_sbus64 = 0;
	op = esp->dev;
	if (sbus_can_dma_64bit())
		can_do_sbus64 = 1;
	if (sbus_can_burst64())
		can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;

	/* Put the DVMA into a known state. */
	if (esp->dmarev != dvmahme) {
		val = dma_read32(DMA_CSR);
		dma_write32(val | DMA_RST_SCSI, DMA_CSR);
		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}
	switch (esp->dmarev) {
	case dvmahme:
		dma_write32(DMA_RESET_FAS366, DMA_CSR);
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = (DMA_PARITY_OFF | DMA_2CLKS |
					DMA_SCSI_DISAB | DMA_INT_ENAB);

		esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
					  DMA_BRST_SZ);

		if (can_do_burst64)
			esp->prev_hme_dmacsr |= DMA_BRST64;
		else if (can_do_burst32)
			esp->prev_hme_dmacsr |= DMA_BRST32;

		if (can_do_sbus64) {
			esp->prev_hme_dmacsr |= DMA_SCSI_SBUS64;
			sbus_set_sbus64(&op->dev, esp->bursts);
		}

		lim = 1000;
		while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
				       "will not clear!\n",
				       esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		dma_write32(0, DMA_ADDR);
		break;

	case dvmarev2:
		if (esp->rev != ESP100) {
			val = dma_read32(DMA_CSR);
			dma_write32(val | DMA_3CLKS, DMA_CSR);
		}
		break;

	case dvmarev3:
		val = dma_read32(DMA_CSR);
		val &= ~DMA_3CLKS;
		val |= DMA_2CLKS;
		if (can_do_burst32) {
			val &= ~DMA_BRST_SZ;
			val |= DMA_BRST32;
		}
		dma_write32(val, DMA_CSR);
		break;

	case dvmaesc1:
		val = dma_read32(DMA_CSR);
		val |= DMA_ADD_ENABLE;
		val &= ~DMA_BCNT_ENAB;
		if (!can_do_burst32 && can_do_burst16) {
			val |= DMA_ESC_BURST;
		} else {
			val &= ~(DMA_ESC_BURST);
		}
		dma_write32(val, DMA_CSR);
		break;

	default:
		break;
	}

	/* Enable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val | DMA_INT_ENAB, DMA_CSR);
}

static void sbus_esp_dma_drain(struct esp *esp)
{
	u32 csr;
	int lim;

	if (esp->dmarev == dvmahme)
		return;

	csr = dma_read32(DMA_CSR);
	if (!(csr & DMA_FIFO_ISDRAIN))
		return;

	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
		dma_write32(csr | DMA_FIFO_STDRAIN, DMA_CSR);

	lim = 1000;
	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
		if (--lim == 0) {
			printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
			       esp->host->unique_id);
			break;
		}
		udelay(1);
	}
}

static void sbus_esp_dma_invalidate(struct esp *esp)
{
	if (esp->dmarev == dvmahme) {
		dma_write32(DMA_RST_SCSI, DMA_CSR);

		esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr |
					 (DMA_PARITY_OFF | DMA_2CLKS |
					  DMA_SCSI_DISAB | DMA_INT_ENAB)) &
					~(DMA_ST_WRITE | DMA_ENABLE));

		dma_write32(0, DMA_CSR);
		dma_write32(esp->prev_hme_dmacsr, DMA_CSR);

		/* This is necessary to avoid having the SCSI channel
		 * engine lock up on us.
		 */
		dma_write32(0, DMA_ADDR);
	} else {
		u32 val;
		int lim;

		lim = 1000;
		while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
			if (--lim == 0) {
				printk(KERN_ALERT PFX "esp%d: DMA will not "
				       "invalidate!\n", esp->host->unique_id);
				break;
			}
			udelay(1);
		}

		val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
		val |= DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
		val &= ~DMA_FIFO_INV;
		dma_write32(val, DMA_CSR);
	}
}

static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
				  u32 dma_count, int write, u8 cmd)
{
	u32 csr;

	BUG_ON(!(cmd & ESP_CMD_DMA));

	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	if (esp->rev == FASHME) {
		sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
		sbus_esp_write8(esp, 0, FAS_RHI);

		scsi_esp_cmd(esp, cmd);

		csr = esp->prev_hme_dmacsr;
		csr |= DMA_SCSI_DISAB | DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		esp->prev_hme_dmacsr = csr;

		dma_write32(dma_count, DMA_COUNT);
		dma_write32(addr, DMA_ADDR);
		dma_write32(csr, DMA_CSR);
	} else {
		csr = dma_read32(DMA_CSR);
		csr |= DMA_ENABLE;
		if (write)
			csr |= DMA_ST_WRITE;
		else
			csr &= ~DMA_ST_WRITE;
		dma_write32(csr, DMA_CSR);
		if (esp->dmarev == dvmaesc1) {
			u32 end = PAGE_ALIGN(addr + dma_count + 16U);
			dma_write32(end - addr, DMA_COUNT);
		}
		dma_write32(addr, DMA_ADDR);

		scsi_esp_cmd(esp, cmd);
	}

}

static int sbus_esp_dma_error(struct esp *esp)
{
	u32 csr = dma_read32(DMA_CSR);

	if (csr & DMA_HNDL_ERROR)
		return 1;

	return 0;
}

static const struct esp_driver_ops sbus_esp_ops = {
	.esp_write8	=	sbus_esp_write8,
	.esp_read8	=	sbus_esp_read8,
	.map_single	=	sbus_esp_map_single,
	.map_sg		=	sbus_esp_map_sg,
	.unmap_single	=	sbus_esp_unmap_single,
	.unmap_sg	=	sbus_esp_unmap_sg,
	.irq_pending	=	sbus_esp_irq_pending,
	.reset_dma	=	sbus_esp_reset_dma,
	.dma_drain	=	sbus_esp_dma_drain,
	.dma_invalidate	=	sbus_esp_dma_invalidate,
	.send_dma_cmd	=	sbus_esp_send_dma_cmd,
	.dma_error	=	sbus_esp_dma_error,
};

static int __devinit esp_sbus_probe_one(struct of_device *op,
					struct of_device *espdma,
					int hme)
{
	struct scsi_host_template *tpnt = &scsi_esp_template;
	struct Scsi_Host *host;
	struct esp *esp;
	int err;

	host = scsi_host_alloc(tpnt, sizeof(struct esp));

	err = -ENOMEM;
	if (!host)
		goto fail;

	host->max_id = (hme ? 16 : 8);
	esp = shost_priv(host);

	esp->host = host;
	esp->dev = op;
	esp->ops = &sbus_esp_ops;

	if (hme)
		esp->flags |= ESP_FLAG_WIDE_CAPABLE;

	err = esp_sbus_setup_dma(esp, espdma);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_regs(esp, hme);
	if (err < 0)
		goto fail_unlink;

	err = esp_sbus_map_command_block(esp);
	if (err < 0)
		goto fail_unmap_regs;

	err = esp_sbus_register_irq(esp);
	if (err < 0)
		goto fail_unmap_command_block;

	esp_sbus_get_props(esp, espdma);

	/* Before we try to touch the ESP chip, ESC1 dma can
	 * come up with the reset bit set, so make sure that
	 * is clear first.
	 */
	if (esp->dmarev == dvmaesc1) {
		u32 val = dma_read32(DMA_CSR);

		dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	}

	dev_set_drvdata(&op->dev, esp);

	err = scsi_esp_register(esp, &op->dev);
	if (err)
		goto fail_free_irq;

	return 0;

fail_free_irq:
	free_irq(host->irq, esp);
fail_unmap_command_block:
	dma_free_coherent(&op->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
fail_unmap_regs:
	of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
fail_unlink:
	scsi_host_put(host);
fail:
	return err;
}

static int __devinit esp_sbus_probe(struct of_device *op, const struct of_device_id *match)
{
	struct device_node *dma_node = NULL;
	struct device_node *dp = op->node;
	struct of_device *dma_of = NULL;
	int hme = 0;

	if (dp->parent &&
	    (!strcmp(dp->parent->name, "espdma") ||
	     !strcmp(dp->parent->name, "dma")))
		dma_node = dp->parent;
	else if (!strcmp(dp->name, "SUNW,fas")) {
		dma_node = op->node;
		hme = 1;
	}
	if (dma_node)
		dma_of = of_find_device_by_node(dma_node);
	if (!dma_of)
		return -ENODEV;

	return esp_sbus_probe_one(op, dma_of, hme);
}

static int __devexit esp_sbus_remove(struct of_device *op)
{
	struct esp *esp = dev_get_drvdata(&op->dev);
	struct of_device *dma_of = esp->dma;
	unsigned int irq = esp->host->irq;
	bool is_hme;
	u32 val;

	scsi_esp_unregister(esp);

	/* Disable interrupts.  */
	val = dma_read32(DMA_CSR);
	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);

	free_irq(irq, esp);

	is_hme = (esp->dmarev == dvmahme);

	dma_free_coherent(&op->dev, 16,
			  esp->command_block,
			  esp->command_block_dma);
	of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
		   SBUS_ESP_REG_SIZE);
	of_iounmap(&dma_of->resource[0], esp->dma_regs,
		   resource_size(&dma_of->resource[0]));

	scsi_host_put(esp->host);

	dev_set_drvdata(&op->dev, NULL);

	return 0;
}

static const struct of_device_id esp_match[] = {
	{
		.name = "SUNW,esp",
	},
	{
		.name = "SUNW,fas",
	},
	{
		.name = "esp",
	},
	{},
};
MODULE_DEVICE_TABLE(of, esp_match);

static struct of_platform_driver esp_sbus_driver = {
	.name		= "esp",
	.match_table	= esp_match,
	.probe		= esp_sbus_probe,
	.remove		= __devexit_p(esp_sbus_remove),
};

static int __init sunesp_init(void)
{
	return of_register_driver(&esp_sbus_driver, &of_bus_type);
}

static void __exit sunesp_exit(void)
{
	of_unregister_driver(&esp_sbus_driver);
}

MODULE_DESCRIPTION("Sun ESP SCSI driver");
MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

module_init(sunesp_init);
module_exit(sunesp_exit);
Commit	Line	Data
cd9ad58d DM	1	/* sun_esp.c: ESP front-end for Sparc SBUS systems.
cd9ad58d DM	2	*
334ae614	3	* Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net)
cd9ad58d DM	4	*/
	5
	6	#include <linux/kernel.h>
	7	#include <linux/types.h>
6025dfe5	8	#include <linux/delay.h>
cd9ad58d	9	#include <linux/module.h>
27ac792c	10	#include <linux/mm.h>
cd9ad58d	11	#include <linux/init.h>
738f2b7b	12	#include <linux/dma-mapping.h>
05bb5e93 DM	13	#include <linux/of.h>
05bb5e93 DM	14	#include <linux/of_device.h>
5a0e3ad6	15	#include <linux/gfp.h>
cd9ad58d DM	16
	17	#include <asm/irq.h>
	18	#include <asm/io.h>
	19	#include <asm/dma.h>
	20
cd9ad58d DM	21	#include <scsi/scsi_host.h>
	22
	23	#include "esp_scsi.h"
	24
	25	#define DRV_MODULE_NAME "sun_esp"
	26	#define PFX DRV_MODULE_NAME ": "
05bb5e93 DM	27	#define DRV_VERSION "1.100"
05bb5e93 DM	28	#define DRV_MODULE_RELDATE "August 27, 2008"
cd9ad58d DM	29
	30	#define dma_read32(REG) \
	31	sbus_readl(esp->dma_regs + (REG))
	32	#define dma_write32(VAL, REG) \
	33	sbus_writel((VAL), esp->dma_regs + (REG))
	34
334ae614 DM	35	/* DVMA chip revisions */
	36	enum dvma_rev {
	37	dvmarev0,
	38	dvmaesc1,
	39	dvmarev1,
	40	dvmarev2,
	41	dvmarev3,
	42	dvmarevplus,
	43	dvmahme
	44	};
cd9ad58d	45
334ae614 DM	46	static int __devinit esp_sbus_setup_dma(struct esp *esp,
	47	struct of_device *dma_of)
	48	{
	49	esp->dma = dma_of;
cd9ad58d	50
334ae614 DM	51	esp->dma_regs = of_ioremap(&dma_of->resource[0], 0,
	52	resource_size(&dma_of->resource[0]),
	53	"espdma");
	54	if (!esp->dma_regs)
	55	return -ENOMEM;
cd9ad58d	56
334ae614 DM	57	switch (dma_read32(DMA_CSR) & DMA_DEVICE_ID) {
	58	case DMA_VERS0:
	59	esp->dmarev = dvmarev0;
	60	break;
	61	case DMA_ESCV1:
	62	esp->dmarev = dvmaesc1;
	63	break;
	64	case DMA_VERS1:
	65	esp->dmarev = dvmarev1;
	66	break;
	67	case DMA_VERS2:
	68	esp->dmarev = dvmarev2;
	69	break;
	70	case DMA_VERHME:
	71	esp->dmarev = dvmahme;
	72	break;
	73	case DMA_VERSPLUS:
	74	esp->dmarev = dvmarevplus;
	75	break;
cd9ad58d	76	}
cd9ad58d DM	77
	78	return 0;
	79
	80	}
	81
	82	static int __devinit esp_sbus_map_regs(struct esp *esp, int hme)
	83	{
05bb5e93	84	struct of_device *op = esp->dev;
cd9ad58d DM	85	struct resource *res;
	86
	87	/* On HME, two reg sets exist, first is DVMA,
	88	* second is ESP registers.
	89	*/
	90	if (hme)
05bb5e93	91	res = &op->resource[1];
cd9ad58d	92	else
05bb5e93	93	res = &op->resource[0];
cd9ad58d	94
05bb5e93	95	esp->regs = of_ioremap(res, 0, SBUS_ESP_REG_SIZE, "ESP");
cd9ad58d DM	96	if (!esp->regs)
	97	return -ENOMEM;
	98
	99	return 0;
	100	}
	101
	102	static int __devinit esp_sbus_map_command_block(struct esp *esp)
	103	{
05bb5e93	104	struct of_device *op = esp->dev;
cd9ad58d	105
05bb5e93	106	esp->command_block = dma_alloc_coherent(&op->dev, 16,
738f2b7b DM	107	&esp->command_block_dma,
738f2b7b DM	108	GFP_ATOMIC);
cd9ad58d DM	109	if (!esp->command_block)
	110	return -ENOMEM;
	111	return 0;
	112	}
	113
	114	static int __devinit esp_sbus_register_irq(struct esp *esp)
	115	{
	116	struct Scsi_Host *host = esp->host;
05bb5e93	117	struct of_device *op = esp->dev;
cd9ad58d	118
05bb5e93	119	host->irq = op->irqs[0];
cd9ad58d DM	120	return request_irq(host->irq, scsi_esp_intr, IRQF_SHARED, "ESP", esp);
	121	}
	122
05bb5e93	123	static void __devinit esp_get_scsi_id(struct esp esp, struct of_device espdma)
cd9ad58d	124	{
05bb5e93 DM	125	struct of_device *op = esp->dev;
05bb5e93 DM	126	struct device_node *dp;
cd9ad58d	127
05bb5e93	128	dp = op->node;
cd9ad58d DM	129	esp->scsi_id = of_getintprop_default(dp, "initiator-id", 0xff);
	130	if (esp->scsi_id != 0xff)
	131	goto done;
	132
	133	esp->scsi_id = of_getintprop_default(dp, "scsi-initiator-id", 0xff);
	134	if (esp->scsi_id != 0xff)
	135	goto done;
	136
05bb5e93	137	esp->scsi_id = of_getintprop_default(espdma->node,
cd9ad58d DM	138	"scsi-initiator-id", 7);
	139
	140	done:
	141	esp->host->this_id = esp->scsi_id;
	142	esp->scsi_id_mask = (1 << esp->scsi_id);
	143	}
	144
	145	static void __devinit esp_get_differential(struct esp *esp)
	146	{
05bb5e93 DM	147	struct of_device *op = esp->dev;
05bb5e93 DM	148	struct device_node *dp;
cd9ad58d	149
05bb5e93	150	dp = op->node;
cd9ad58d DM	151	if (of_find_property(dp, "differential", NULL))
	152	esp->flags \|= ESP_FLAG_DIFFERENTIAL;
	153	else
	154	esp->flags &= ~ESP_FLAG_DIFFERENTIAL;
	155	}
	156
	157	static void __devinit esp_get_clock_params(struct esp *esp)
	158	{
05bb5e93 DM	159	struct of_device *op = esp->dev;
05bb5e93 DM	160	struct device_node bus_dp, dp;
cd9ad58d DM	161	int fmhz;
cd9ad58d DM	162
05bb5e93 DM	163	dp = op->node;
05bb5e93 DM	164	bus_dp = dp->parent;
cd9ad58d DM	165
	166	fmhz = of_getintprop_default(dp, "clock-frequency", 0);
	167	if (fmhz == 0)
05bb5e93	168	fmhz = of_getintprop_default(bus_dp, "clock-frequency", 0);
cd9ad58d DM	169
	170	esp->cfreq = fmhz;
	171	}
	172
334ae614	173	static void __devinit esp_get_bursts(struct esp esp, struct of_device dma_of)
cd9ad58d	174	{
334ae614	175	struct device_node *dma_dp = dma_of->node;
05bb5e93	176	struct of_device *op = esp->dev;
334ae614 DM	177	struct device_node *dp;
334ae614 DM	178	u8 bursts, val;
cd9ad58d	179
05bb5e93	180	dp = op->node;
cd9ad58d	181	bursts = of_getintprop_default(dp, "burst-sizes", 0xff);
334ae614 DM	182	val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
	183	if (val != 0xff)
	184	bursts &= val;
cd9ad58d	185
05bb5e93 DM	186	val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
	187	if (val != 0xff)
	188	bursts &= val;
cd9ad58d DM	189
	190	if (bursts == 0xff \|\|
	191	(bursts & DMA_BURST16) == 0 \|\|
	192	(bursts & DMA_BURST32) == 0)
	193	bursts = (DMA_BURST32 - 1);
	194
	195	esp->bursts = bursts;
	196	}
	197
334ae614	198	static void __devinit esp_sbus_get_props(struct esp esp, struct of_device espdma)
cd9ad58d	199	{
05bb5e93	200	esp_get_scsi_id(esp, espdma);
cd9ad58d DM	201	esp_get_differential(esp);
	202	esp_get_clock_params(esp);
	203	esp_get_bursts(esp, espdma);
	204	}
	205
	206	static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
	207	{
	208	sbus_writeb(val, esp->regs + (reg * 4UL));
	209	}
	210
	211	static u8 sbus_esp_read8(struct esp *esp, unsigned long reg)
	212	{
	213	return sbus_readb(esp->regs + (reg * 4UL));
	214	}
	215
	216	static dma_addr_t sbus_esp_map_single(struct esp esp, void buf,
	217	size_t sz, int dir)
	218	{
05bb5e93	219	struct of_device *op = esp->dev;
7a715f46	220
05bb5e93	221	return dma_map_single(&op->dev, buf, sz, dir);
cd9ad58d DM	222	}
	223
	224	static int sbus_esp_map_sg(struct esp esp, struct scatterlist sg,
	225	int num_sg, int dir)
	226	{
05bb5e93	227	struct of_device *op = esp->dev;
7a715f46	228
05bb5e93	229	return dma_map_sg(&op->dev, sg, num_sg, dir);
cd9ad58d DM	230	}
	231
	232	static void sbus_esp_unmap_single(struct esp *esp, dma_addr_t addr,
	233	size_t sz, int dir)
	234	{
05bb5e93	235	struct of_device *op = esp->dev;
7a715f46	236
05bb5e93	237	dma_unmap_single(&op->dev, addr, sz, dir);
cd9ad58d DM	238	}
	239
	240	static void sbus_esp_unmap_sg(struct esp esp, struct scatterlist sg,
	241	int num_sg, int dir)
	242	{
05bb5e93	243	struct of_device *op = esp->dev;
7a715f46	244
05bb5e93	245	dma_unmap_sg(&op->dev, sg, num_sg, dir);
cd9ad58d DM	246	}
	247
	248	static int sbus_esp_irq_pending(struct esp *esp)
	249	{
	250	if (dma_read32(DMA_CSR) & (DMA_HNDL_INTR \| DMA_HNDL_ERROR))
	251	return 1;
	252	return 0;
	253	}
	254
	255	static void sbus_esp_reset_dma(struct esp *esp)
	256	{
	257	int can_do_burst16, can_do_burst32, can_do_burst64;
	258	int can_do_sbus64, lim;
05bb5e93	259	struct of_device *op;
cd9ad58d DM	260	u32 val;
	261
	262	can_do_burst16 = (esp->bursts & DMA_BURST16) != 0;
	263	can_do_burst32 = (esp->bursts & DMA_BURST32) != 0;
	264	can_do_burst64 = 0;
	265	can_do_sbus64 = 0;
05bb5e93	266	op = esp->dev;
63237eeb	267	if (sbus_can_dma_64bit())
cd9ad58d	268	can_do_sbus64 = 1;
63237eeb	269	if (sbus_can_burst64())
cd9ad58d DM	270	can_do_burst64 = (esp->bursts & DMA_BURST64) != 0;
	271
	272	/* Put the DVMA into a known state. */
334ae614	273	if (esp->dmarev != dvmahme) {
cd9ad58d DM	274	val = dma_read32(DMA_CSR);
	275	dma_write32(val \| DMA_RST_SCSI, DMA_CSR);
	276	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	277	}
334ae614	278	switch (esp->dmarev) {
cd9ad58d DM	279	case dvmahme:
	280	dma_write32(DMA_RESET_FAS366, DMA_CSR);
	281	dma_write32(DMA_RST_SCSI, DMA_CSR);
	282
	283	esp->prev_hme_dmacsr = (DMA_PARITY_OFF \| DMA_2CLKS \|
	284	DMA_SCSI_DISAB \| DMA_INT_ENAB);
	285
	286	esp->prev_hme_dmacsr &= ~(DMA_ENABLE \| DMA_ST_WRITE \|
	287	DMA_BRST_SZ);
	288
	289	if (can_do_burst64)
	290	esp->prev_hme_dmacsr \|= DMA_BRST64;
	291	else if (can_do_burst32)
	292	esp->prev_hme_dmacsr \|= DMA_BRST32;
	293
	294	if (can_do_sbus64) {
	295	esp->prev_hme_dmacsr \|= DMA_SCSI_SBUS64;
05bb5e93	296	sbus_set_sbus64(&op->dev, esp->bursts);
cd9ad58d DM	297	}
	298
	299	lim = 1000;
	300	while (dma_read32(DMA_CSR) & DMA_PEND_READ) {
	301	if (--lim == 0) {
	302	printk(KERN_ALERT PFX "esp%d: DMA_PEND_READ "
	303	"will not clear!\n",
	304	esp->host->unique_id);
	305	break;
	306	}
	307	udelay(1);
	308	}
	309
	310	dma_write32(0, DMA_CSR);
	311	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	312
	313	dma_write32(0, DMA_ADDR);
	314	break;
	315
	316	case dvmarev2:
	317	if (esp->rev != ESP100) {
	318	val = dma_read32(DMA_CSR);
	319	dma_write32(val \| DMA_3CLKS, DMA_CSR);
	320	}
	321	break;
	322
	323	case dvmarev3:
	324	val = dma_read32(DMA_CSR);
	325	val &= ~DMA_3CLKS;
	326	val \|= DMA_2CLKS;
	327	if (can_do_burst32) {
	328	val &= ~DMA_BRST_SZ;
	329	val \|= DMA_BRST32;
	330	}
	331	dma_write32(val, DMA_CSR);
	332	break;
	333
	334	case dvmaesc1:
	335	val = dma_read32(DMA_CSR);
	336	val \|= DMA_ADD_ENABLE;
	337	val &= ~DMA_BCNT_ENAB;
	338	if (!can_do_burst32 && can_do_burst16) {
	339	val \|= DMA_ESC_BURST;
	340	} else {
	341	val &= ~(DMA_ESC_BURST);
	342	}
	343	dma_write32(val, DMA_CSR);
	344	break;
	345
	346	default:
	347	break;
	348	}
	349
	350	/* Enable interrupts. */
	351	val = dma_read32(DMA_CSR);
	352	dma_write32(val \| DMA_INT_ENAB, DMA_CSR);
	353	}
	354
	355	static void sbus_esp_dma_drain(struct esp *esp)
	356	{
	357	u32 csr;
	358	int lim;
	359
334ae614	360	if (esp->dmarev == dvmahme)
cd9ad58d DM	361	return;
	362
	363	csr = dma_read32(DMA_CSR);
	364	if (!(csr & DMA_FIFO_ISDRAIN))
	365	return;
	366
334ae614	367	if (esp->dmarev != dvmarev3 && esp->dmarev != dvmaesc1)
cd9ad58d DM	368	dma_write32(csr \| DMA_FIFO_STDRAIN, DMA_CSR);
	369
	370	lim = 1000;
	371	while (dma_read32(DMA_CSR) & DMA_FIFO_ISDRAIN) {
	372	if (--lim == 0) {
	373	printk(KERN_ALERT PFX "esp%d: DMA will not drain!\n",
	374	esp->host->unique_id);
	375	break;
	376	}
	377	udelay(1);
	378	}
	379	}
	380
	381	static void sbus_esp_dma_invalidate(struct esp *esp)
	382	{
334ae614	383	if (esp->dmarev == dvmahme) {
cd9ad58d DM	384	dma_write32(DMA_RST_SCSI, DMA_CSR);
	385
	386	esp->prev_hme_dmacsr = ((esp->prev_hme_dmacsr \|
	387	(DMA_PARITY_OFF \| DMA_2CLKS \|
	388	DMA_SCSI_DISAB \| DMA_INT_ENAB)) &
	389	~(DMA_ST_WRITE \| DMA_ENABLE));
	390
	391	dma_write32(0, DMA_CSR);
	392	dma_write32(esp->prev_hme_dmacsr, DMA_CSR);
	393
	394	/* This is necessary to avoid having the SCSI channel
	395	* engine lock up on us.
	396	*/
	397	dma_write32(0, DMA_ADDR);
	398	} else {
	399	u32 val;
	400	int lim;
	401
	402	lim = 1000;
	403	while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
	404	if (--lim == 0) {
	405	printk(KERN_ALERT PFX "esp%d: DMA will not "
	406	"invalidate!\n", esp->host->unique_id);
	407	break;
	408	}
	409	udelay(1);
	410	}
	411
	412	val &= ~(DMA_ENABLE \| DMA_ST_WRITE \| DMA_BCNT_ENAB);
	413	val \|= DMA_FIFO_INV;
	414	dma_write32(val, DMA_CSR);
	415	val &= ~DMA_FIFO_INV;
	416	dma_write32(val, DMA_CSR);
	417	}
	418	}
	419
	420	static void sbus_esp_send_dma_cmd(struct esp *esp, u32 addr, u32 esp_count,
	421	u32 dma_count, int write, u8 cmd)
	422	{
	423	u32 csr;
	424
	425	BUG_ON(!(cmd & ESP_CMD_DMA));
	426
	427	sbus_esp_write8(esp, (esp_count >> 0) & 0xff, ESP_TCLOW);
	428	sbus_esp_write8(esp, (esp_count >> 8) & 0xff, ESP_TCMED);
	429	if (esp->rev == FASHME) {
	430	sbus_esp_write8(esp, (esp_count >> 16) & 0xff, FAS_RLO);
	431	sbus_esp_write8(esp, 0, FAS_RHI);
	432
	433	scsi_esp_cmd(esp, cmd);
	434
	435	csr = esp->prev_hme_dmacsr;
	436	csr \|= DMA_SCSI_DISAB \| DMA_ENABLE;
	437	if (write)
	438	csr \|= DMA_ST_WRITE;
	439	else
	440	csr &= ~DMA_ST_WRITE;
	441	esp->prev_hme_dmacsr = csr;
	442
	443	dma_write32(dma_count, DMA_COUNT);
	444	dma_write32(addr, DMA_ADDR);
	445	dma_write32(csr, DMA_CSR);
	446	} else {
	447	csr = dma_read32(DMA_CSR);
448	csr \|= DMA_ENABLE;
449	if (write)
450	csr \|= DMA_ST_WRITE;
451	else
452	csr &= ~DMA_ST_WRITE;
453	dma_write32(csr, DMA_CSR);
334ae614	454	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	455	u32 end = PAGE_ALIGN(addr + dma_count + 16U);
	456	dma_write32(end - addr, DMA_COUNT);
	457	}
	458	dma_write32(addr, DMA_ADDR);
	459
	460	scsi_esp_cmd(esp, cmd);
	461	}
	462
	463	}
	464
	465	static int sbus_esp_dma_error(struct esp *esp)
	466	{
	467	u32 csr = dma_read32(DMA_CSR);
	468
	469	if (csr & DMA_HNDL_ERROR)
	470	return 1;
	471
	472	return 0;
	473	}
	474
	475	static const struct esp_driver_ops sbus_esp_ops = {
	476	.esp_write8 = sbus_esp_write8,
	477	.esp_read8 = sbus_esp_read8,
	478	.map_single = sbus_esp_map_single,
	479	.map_sg = sbus_esp_map_sg,
	480	.unmap_single = sbus_esp_unmap_single,
	481	.unmap_sg = sbus_esp_unmap_sg,
	482	.irq_pending = sbus_esp_irq_pending,
	483	.reset_dma = sbus_esp_reset_dma,
	484	.dma_drain = sbus_esp_dma_drain,
	485	.dma_invalidate = sbus_esp_dma_invalidate,
	486	.send_dma_cmd = sbus_esp_send_dma_cmd,
	487	.dma_error = sbus_esp_dma_error,
	488	};
	489
05bb5e93	490	static int __devinit esp_sbus_probe_one(struct of_device *op,
334ae614	491	struct of_device *espdma,
cd9ad58d DM	492	int hme)
	493	{
	494	struct scsi_host_template *tpnt = &scsi_esp_template;
	495	struct Scsi_Host *host;
	496	struct esp *esp;
	497	int err;
	498
	499	host = scsi_host_alloc(tpnt, sizeof(struct esp));
	500
	501	err = -ENOMEM;
	502	if (!host)
	503	goto fail;
	504
	505	host->max_id = (hme ? 16 : 8);
2b14ec78	506	esp = shost_priv(host);
cd9ad58d DM	507
cd9ad58d DM	508	esp->host = host;
05bb5e93	509	esp->dev = op;
cd9ad58d DM	510	esp->ops = &sbus_esp_ops;
	511
	512	if (hme)
	513	esp->flags \|= ESP_FLAG_WIDE_CAPABLE;
	514
334ae614	515	err = esp_sbus_setup_dma(esp, espdma);
cd9ad58d DM	516	if (err < 0)
	517	goto fail_unlink;
	518
	519	err = esp_sbus_map_regs(esp, hme);
	520	if (err < 0)
	521	goto fail_unlink;
	522
	523	err = esp_sbus_map_command_block(esp);
	524	if (err < 0)
	525	goto fail_unmap_regs;
	526
	527	err = esp_sbus_register_irq(esp);
	528	if (err < 0)
	529	goto fail_unmap_command_block;
	530
	531	esp_sbus_get_props(esp, espdma);
	532
	533	/* Before we try to touch the ESP chip, ESC1 dma can
	534	* come up with the reset bit set, so make sure that
	535	* is clear first.
	536	*/
334ae614	537	if (esp->dmarev == dvmaesc1) {
cd9ad58d DM	538	u32 val = dma_read32(DMA_CSR);
	539
	540	dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
	541	}
	542
05bb5e93	543	dev_set_drvdata(&op->dev, esp);
cd9ad58d	544
05bb5e93	545	err = scsi_esp_register(esp, &op->dev);
cd9ad58d DM	546	if (err)
	547	goto fail_free_irq;
	548
	549	return 0;
	550
	551	fail_free_irq:
	552	free_irq(host->irq, esp);
	553	fail_unmap_command_block:
05bb5e93	554	dma_free_coherent(&op->dev, 16,
738f2b7b DM	555	esp->command_block,
738f2b7b DM	556	esp->command_block_dma);
cd9ad58d	557	fail_unmap_regs:
05bb5e93	558	of_iounmap(&op->resource[(hme ? 1 : 0)], esp->regs, SBUS_ESP_REG_SIZE);
cd9ad58d DM	559	fail_unlink:
	560	scsi_host_put(host);
	561	fail:
	562	return err;
	563	}
	564
05bb5e93	565	static int __devinit esp_sbus_probe(struct of_device op, const struct of_device_id match)
cd9ad58d	566	{
334ae614	567	struct device_node *dma_node = NULL;
05bb5e93	568	struct device_node *dp = op->node;
334ae614	569	struct of_device *dma_of = NULL;
cd9ad58d DM	570	int hme = 0;
	571
	572	if (dp->parent &&
	573	(!strcmp(dp->parent->name, "espdma") \|\|
	574	!strcmp(dp->parent->name, "dma")))
334ae614	575	dma_node = dp->parent;
cd9ad58d	576	else if (!strcmp(dp->name, "SUNW,fas")) {
05bb5e93	577	dma_node = op->node;
cd9ad58d DM	578	hme = 1;
cd9ad58d DM	579	}
334ae614 DM	580	if (dma_node)
	581	dma_of = of_find_device_by_node(dma_node);
	582	if (!dma_of)
	583	return -ENODEV;
cd9ad58d	584
05bb5e93	585	return esp_sbus_probe_one(op, dma_of, hme);
cd9ad58d DM	586	}
cd9ad58d DM	587
05bb5e93	588	static int __devexit esp_sbus_remove(struct of_device *op)
cd9ad58d	589	{
05bb5e93	590	struct esp *esp = dev_get_drvdata(&op->dev);
334ae614	591	struct of_device *dma_of = esp->dma;
cd9ad58d	592	unsigned int irq = esp->host->irq;
05bb5e93	593	bool is_hme;
cd9ad58d DM	594	u32 val;
	595
	596	scsi_esp_unregister(esp);
	597
	598	/* Disable interrupts. */
	599	val = dma_read32(DMA_CSR);
	600	dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);
	601
	602	free_irq(irq, esp);
05bb5e93 DM	603
	604	is_hme = (esp->dmarev == dvmahme);
	605
	606	dma_free_coherent(&op->dev, 16,
738f2b7b DM	607	esp->command_block,
738f2b7b DM	608	esp->command_block_dma);
05bb5e93 DM	609	of_iounmap(&op->resource[(is_hme ? 1 : 0)], esp->regs,
05bb5e93 DM	610	SBUS_ESP_REG_SIZE);
334ae614 DM	611	of_iounmap(&dma_of->resource[0], esp->dma_regs,
334ae614 DM	612	resource_size(&dma_of->resource[0]));
cd9ad58d DM	613
	614	scsi_host_put(esp->host);
	615
05bb5e93 DM	616	dev_set_drvdata(&op->dev, NULL);
05bb5e93 DM	617
cd9ad58d DM	618	return 0;
	619	}
	620
fd098316	621	static const struct of_device_id esp_match[] = {
cd9ad58d DM	622	{
	623	.name = "SUNW,esp",
	624	},
	625	{
	626	.name = "SUNW,fas",
	627	},
	628	{
	629	.name = "esp",
	630	},
	631	{},
	632	};
	633	MODULE_DEVICE_TABLE(of, esp_match);
	634
	635	static struct of_platform_driver esp_sbus_driver = {
	636	.name = "esp",
	637	.match_table = esp_match,
	638	.probe = esp_sbus_probe,
	639	.remove = __devexit_p(esp_sbus_remove),
	640	};
	641
	642	static int __init sunesp_init(void)
	643	{
05bb5e93	644	return of_register_driver(&esp_sbus_driver, &of_bus_type);
cd9ad58d DM	645	}
	646
	647	static void __exit sunesp_exit(void)
	648	{
	649	of_unregister_driver(&esp_sbus_driver);
	650	}
	651
	652	MODULE_DESCRIPTION("Sun ESP SCSI driver");
	653	MODULE_AUTHOR("David S. Miller (davem@davemloft.net)");
	654	MODULE_LICENSE("GPL");
	655	MODULE_VERSION(DRV_VERSION);
	656
	657	module_init(sunesp_init);
	658	module_exit(sunesp_exit);