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[SCSI] stex: add value check in hard reset routine
[net-next-2.6.git] / drivers / scsi / stex.c
CommitLineData
5a25ba16
JG		 1/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
4 * Copyright (C) 2005, 2006 Promise Technology Inc.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
fb4f66be 14 * Version: 3.0.0.1
5a25ba16
JG		 15 *
16 */
17
18#include <linux/init.h>
19#include <linux/errno.h>
20#include <linux/kernel.h>
21#include <linux/delay.h>
22#include <linux/sched.h>
23#include <linux/time.h>
24#include <linux/pci.h>
25#include <linux/blkdev.h>
26#include <linux/interrupt.h>
27#include <linux/types.h>
28#include <linux/module.h>
29#include <linux/spinlock.h>
30#include <asm/io.h>
31#include <asm/irq.h>
32#include <asm/byteorder.h>
33#include <scsi/scsi.h>
34#include <scsi/scsi_device.h>
35#include <scsi/scsi_cmnd.h>
36#include <scsi/scsi_host.h>
cf355883 37#include <scsi/scsi_tcq.h>
5a25ba16
JG		 38
39#define DRV_NAME "stex"
fb4f66be
EL		 40#define ST_DRIVER_VERSION "3.0.0.1"
41#define ST_VER_MAJOR 3
42#define ST_VER_MINOR 0
5a25ba16 43#define ST_OEM 0
fb4f66be 44#define ST_BUILD_VER 1
5a25ba16
JG		 45
46enum {
47 /* MU register offset */
48 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
49 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
50 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
51 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
52 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
53 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
54 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
55 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
56 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
57 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
58
59 /* MU register value */
60 MU_INBOUND_DOORBELL_HANDSHAKE = 1,
61 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
62 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
63 MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
64 MU_INBOUND_DOORBELL_RESET = 16,
65
66 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
67 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
68 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
69 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
70 MU_OUTBOUND_DOORBELL_HASEVENT = 16,
71
72 /* MU status code */
73 MU_STATE_STARTING = 1,
74 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
75 MU_STATE_SEND_HANDSHAKE_FRAME = 3,
76 MU_STATE_STARTED = 4,
77 MU_STATE_RESETTING = 5,
78
79 MU_MAX_DELAY_TIME = 240000,
80 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
81 HMU_PARTNER_TYPE = 2,
82
83 /* firmware returned values */
84 SRB_STATUS_SUCCESS = 0x01,
85 SRB_STATUS_ERROR = 0x04,
86 SRB_STATUS_BUSY = 0x05,
87 SRB_STATUS_INVALID_REQUEST = 0x06,
88 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
89 SRB_SEE_SENSE = 0x80,
90
91 /* task attribute */
92 TASK_ATTRIBUTE_SIMPLE = 0x0,
93 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
94 TASK_ATTRIBUTE_ORDERED = 0x2,
95 TASK_ATTRIBUTE_ACA = 0x4,
96
97 /* request count, etc. */
98 MU_MAX_REQUEST = 32,
5a25ba16
JG		 99
100 /* one message wasted, use MU_MAX_REQUEST+1
101 to handle MU_MAX_REQUEST messages */
102 MU_REQ_COUNT = (MU_MAX_REQUEST + 1),
103 MU_STATUS_COUNT = (MU_MAX_REQUEST + 1),
104
105 STEX_CDB_LENGTH = MAX_COMMAND_SIZE,
106 REQ_VARIABLE_LEN = 1024,
107 STATUS_VAR_LEN = 128,
108 ST_CAN_QUEUE = MU_MAX_REQUEST,
109 ST_CMD_PER_LUN = MU_MAX_REQUEST,
110 ST_MAX_SG = 32,
111
112 /* sg flags */
113 SG_CF_EOT = 0x80, /* end of table */
114 SG_CF_64B = 0x40, /* 64 bit item */
115 SG_CF_HOST = 0x20, /* sg in host memory */
116
117 ST_MAX_ARRAY_SUPPORTED = 16,
118 ST_MAX_TARGET_NUM = (ST_MAX_ARRAY_SUPPORTED+1),
119 ST_MAX_LUN_PER_TARGET = 16,
120
121 st_shasta = 0,
122 st_vsc = 1,
fb4f66be 123 st_yosemite = 2,
5a25ba16
JG		 124
125 PASSTHRU_REQ_TYPE = 0x00000001,
126 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
127 ST_INTERNAL_TIMEOUT = 30,
128
fb4f66be
EL		 129 ST_TO_CMD = 0,
130 ST_FROM_CMD = 1,
131
5a25ba16 132 /* vendor specific commands of Promise */
fb4f66be
EL		 133 MGT_CMD = 0xd8,
134 SINBAND_MGT_CMD = 0xd9,
5a25ba16
JG		 135 ARRAY_CMD = 0xe0,
136 CONTROLLER_CMD = 0xe1,
137 DEBUGGING_CMD = 0xe2,
138 PASSTHRU_CMD = 0xe3,
139
140 PASSTHRU_GET_ADAPTER = 0x05,
141 PASSTHRU_GET_DRVVER = 0x10,
fb4f66be
EL		 142
143 CTLR_CONFIG_CMD = 0x03,
144 CTLR_SHUTDOWN = 0x0d,
145
5a25ba16
JG		 146 CTLR_POWER_STATE_CHANGE = 0x0e,
147 CTLR_POWER_SAVING = 0x01,
148
149 PASSTHRU_SIGNATURE = 0x4e415041,
fb4f66be 150 MGT_CMD_SIGNATURE = 0xba,
5a25ba16
JG		 151
152 INQUIRY_EVPD = 0x01,
153};
154
fb4f66be
EL		 155/* SCSI inquiry data */
156typedef struct st_inq {
157 u8 DeviceType :5;
158 u8 DeviceTypeQualifier :3;
159 u8 DeviceTypeModifier :7;
160 u8 RemovableMedia :1;
161 u8 Versions;
162 u8 ResponseDataFormat :4;
163 u8 HiSupport :1;
164 u8 NormACA :1;
165 u8 ReservedBit :1;
166 u8 AERC :1;
167 u8 AdditionalLength;
168 u8 Reserved[2];
169 u8 SoftReset :1;
170 u8 CommandQueue :1;
171 u8 Reserved2 :1;
172 u8 LinkedCommands :1;
173 u8 Synchronous :1;
174 u8 Wide16Bit :1;
175 u8 Wide32Bit :1;
176 u8 RelativeAddressing :1;
177 u8 VendorId[8];
178 u8 ProductId[16];
179 u8 ProductRevisionLevel[4];
180 u8 VendorSpecific[20];
181 u8 Reserved3[40];
182} ST_INQ;
183
5a25ba16
JG		 184struct st_sgitem {
185 u8 ctrl; /* SG_CF_xxx */
186 u8 reserved[3];
187 __le32 count;
188 __le32 addr;
189 __le32 addr_hi;
190};
191
192struct st_sgtable {
193 __le16 sg_count;
194 __le16 max_sg_count;
195 __le32 sz_in_byte;
196 struct st_sgitem table[ST_MAX_SG];
197};
198
199struct handshake_frame {
200 __le32 rb_phy; /* request payload queue physical address */
201 __le32 rb_phy_hi;
202 __le16 req_sz; /* size of each request payload */
203 __le16 req_cnt; /* count of reqs the buffer can hold */
204 __le16 status_sz; /* size of each status payload */
205 __le16 status_cnt; /* count of status the buffer can hold */
206 __le32 hosttime; /* seconds from Jan 1, 1970 (GMT) */
207 __le32 hosttime_hi;
208 u8 partner_type; /* who sends this frame */
209 u8 reserved0[7];
210 __le32 partner_ver_major;
211 __le32 partner_ver_minor;
212 __le32 partner_ver_oem;
213 __le32 partner_ver_build;
214 u32 reserved1[4];
215};
216
217struct req_msg {
218 __le16 tag;
219 u8 lun;
220 u8 target;
221 u8 task_attr;
222 u8 task_manage;
223 u8 prd_entry;
f903d7b7 224 u8 payload_sz; /* payload size in 4-byte, not used */
5a25ba16
JG		 225 u8 cdb[STEX_CDB_LENGTH];
226 u8 variable[REQ_VARIABLE_LEN];
227};
228
229struct status_msg {
230 __le16 tag;
231 u8 lun;
232 u8 target;
233 u8 srb_status;
234 u8 scsi_status;
235 u8 reserved;
236 u8 payload_sz; /* payload size in 4-byte */
237 u8 variable[STATUS_VAR_LEN];
238};
239
240struct ver_info {
241 u32 major;
242 u32 minor;
243 u32 oem;
244 u32 build;
245 u32 reserved[2];
246};
247
248struct st_frame {
249 u32 base[6];
250 u32 rom_addr;
251
252 struct ver_info drv_ver;
253 struct ver_info bios_ver;
254
255 u32 bus;
256 u32 slot;
257 u32 irq_level;
258 u32 irq_vec;
259 u32 id;
260 u32 subid;
261
262 u32 dimm_size;
263 u8 dimm_type;
264 u8 reserved[3];
265
266 u32 channel;
267 u32 reserved1;
268};
269
270struct st_drvver {
271 u32 major;
272 u32 minor;
273 u32 oem;
274 u32 build;
275 u32 signature[2];
276 u8 console_id;
277 u8 host_no;
278 u8 reserved0[2];
279 u32 reserved[3];
280};
281
282#define MU_REQ_BUFFER_SIZE (MU_REQ_COUNT * sizeof(struct req_msg))
283#define MU_STATUS_BUFFER_SIZE (MU_STATUS_COUNT * sizeof(struct status_msg))
284#define MU_BUFFER_SIZE (MU_REQ_BUFFER_SIZE + MU_STATUS_BUFFER_SIZE)
fb4f66be
EL		 285#define STEX_EXTRA_SIZE max(sizeof(struct st_frame), sizeof(ST_INQ))
286#define STEX_BUFFER_SIZE (MU_BUFFER_SIZE + STEX_EXTRA_SIZE)
5a25ba16
JG		 287
288struct st_ccb {
289 struct req_msg *req;
290 struct scsi_cmnd *cmd;
291
292 void *sense_buffer;
293 unsigned int sense_bufflen;
294 int sg_count;
295
296 u32 req_type;
297 u8 srb_status;
298 u8 scsi_status;
299};
300
301struct st_hba {
302 void __iomem *mmio_base; /* iomapped PCI memory space */
303 void *dma_mem;
304 dma_addr_t dma_handle;
305
306 struct Scsi_Host *host;
307 struct pci_dev *pdev;
308
5a25ba16
JG		 309 u32 req_head;
310 u32 req_tail;
311 u32 status_head;
312 u32 status_tail;
313
314 struct status_msg *status_buffer;
315 void *copy_buffer; /* temp buffer for driver-handled commands */
316 struct st_ccb ccb[MU_MAX_REQUEST];
317 struct st_ccb *wait_ccb;
318 wait_queue_head_t waitq;
319
320 unsigned int mu_status;
321 int out_req_cnt;
322
323 unsigned int cardtype;
324};
325
326static const char console_inq_page[] =
327{
328 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
329 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
330 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
331 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
332 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
333 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
334 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
335 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
336};
337
338MODULE_AUTHOR("Ed Lin");
339MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
340MODULE_LICENSE("GPL");
341MODULE_VERSION(ST_DRIVER_VERSION);
342
343static void stex_gettime(__le32 *time)
344{
345 struct timeval tv;
346 do_gettimeofday(&tv);
347
348 *time = cpu_to_le32(tv.tv_sec & 0xffffffff);
349 *(time + 1) = cpu_to_le32((tv.tv_sec >> 16) >> 16);
350}
351
5a25ba16
JG		 352static struct status_msg *stex_get_status(struct st_hba *hba)
353{
354 struct status_msg *status =
355 hba->status_buffer + hba->status_tail;
356
357 ++hba->status_tail;
358 hba->status_tail %= MU_STATUS_COUNT;
359
360 return status;
361}
362
363static void stex_set_sense(struct scsi_cmnd *cmd, u8 sk, u8 asc, u8 ascq)
364{
365 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
366
367 cmd->sense_buffer[0] = 0x70; /* fixed format, current */
368 cmd->sense_buffer[2] = sk;
369 cmd->sense_buffer[7] = 18 - 8; /* additional sense length */
370 cmd->sense_buffer[12] = asc;
371 cmd->sense_buffer[13] = ascq;
372}
373
374static void stex_invalid_field(struct scsi_cmnd *cmd,
375 void (*done)(struct scsi_cmnd *))
376{
377 /* "Invalid field in cbd" */
378 stex_set_sense(cmd, ILLEGAL_REQUEST, 0x24, 0x0);
379 done(cmd);
380}
381
382static struct req_msg *stex_alloc_req(struct st_hba *hba)
383{
384 struct req_msg *req = ((struct req_msg *)hba->dma_mem) +
385 hba->req_head;
386
387 ++hba->req_head;
388 hba->req_head %= MU_REQ_COUNT;
389
390 return req;
391}
392
393static int stex_map_sg(struct st_hba *hba,
394 struct req_msg *req, struct st_ccb *ccb)
395{
396 struct pci_dev *pdev = hba->pdev;
397 struct scsi_cmnd *cmd;
398 dma_addr_t dma_handle;
399 struct scatterlist *src;
400 struct st_sgtable *dst;
401 int i;
402
403 cmd = ccb->cmd;
404 dst = (struct st_sgtable *)req->variable;
405 dst->max_sg_count = cpu_to_le16(ST_MAX_SG);
406 dst->sz_in_byte = cpu_to_le32(cmd->request_bufflen);
407
408 if (cmd->use_sg) {
409 int n_elem;
410
411 src = (struct scatterlist *) cmd->request_buffer;
412 n_elem = pci_map_sg(pdev, src,
413 cmd->use_sg, cmd->sc_data_direction);
414 if (n_elem <= 0)
415 return -EIO;
416
417 ccb->sg_count = n_elem;
418 dst->sg_count = cpu_to_le16((u16)n_elem);
419
420 for (i = 0; i < n_elem; i++, src++) {
421 dst->table[i].count = cpu_to_le32((u32)sg_dma_len(src));
422 dst->table[i].addr =
423 cpu_to_le32(sg_dma_address(src) & 0xffffffff);
424 dst->table[i].addr_hi =
425 cpu_to_le32((sg_dma_address(src) >> 16) >> 16);
426 dst->table[i].ctrl = SG_CF_64B | SG_CF_HOST;
427 }
428 dst->table[--i].ctrl |= SG_CF_EOT;
429 return 0;
430 }
431
432 dma_handle = pci_map_single(pdev, cmd->request_buffer,
433 cmd->request_bufflen, cmd->sc_data_direction);
434 cmd->SCp.dma_handle = dma_handle;
435
436 ccb->sg_count = 1;
437 dst->sg_count = cpu_to_le16(1);
438 dst->table[0].addr = cpu_to_le32(dma_handle & 0xffffffff);
439 dst->table[0].addr_hi = cpu_to_le32((dma_handle >> 16) >> 16);
440 dst->table[0].count = cpu_to_le32((u32)cmd->request_bufflen);
441 dst->table[0].ctrl = SG_CF_EOT | SG_CF_64B | SG_CF_HOST;
442
443 return 0;
444}
445
446static void stex_internal_copy(struct scsi_cmnd *cmd,
fb4f66be 447 const void *src, size_t *count, int sg_count, int direction)
5a25ba16
JG		 448{
449 size_t lcount;
450 size_t len;
451 void *s, *d, *base = NULL;
452 if (*count > cmd->request_bufflen)
453 *count = cmd->request_bufflen;
454 lcount = *count;
455 while (lcount) {
456 len = lcount;
457 s = (void *)src;
458 if (cmd->use_sg) {
459 size_t offset = *count - lcount;
460 s += offset;
461 base = scsi_kmap_atomic_sg(cmd->request_buffer,
462 sg_count, &offset, &len);
463 if (base == NULL) {
464 *count -= lcount;
465 return;
466 }
467 d = base + offset;
468 } else
469 d = cmd->request_buffer;
470
fb4f66be
EL		 471 if (direction == ST_TO_CMD)
472 memcpy(d, s, len);
473 else
474 memcpy(s, d, len);
5a25ba16
JG		 475
476 lcount -= len;
477 if (cmd->use_sg)
478 scsi_kunmap_atomic_sg(base);
479 }
480}
481
482static int stex_direct_copy(struct scsi_cmnd *cmd,
483 const void *src, size_t count)
484{
485 struct st_hba *hba = (struct st_hba *) &cmd->device->host->hostdata[0];
486 size_t cp_len = count;
487 int n_elem = 0;
488
489 if (cmd->use_sg) {
490 n_elem = pci_map_sg(hba->pdev, cmd->request_buffer,
491 cmd->use_sg, cmd->sc_data_direction);
492 if (n_elem <= 0)
493 return 0;
494 }
495
fb4f66be 496 stex_internal_copy(cmd, src, &cp_len, n_elem, ST_TO_CMD);
5a25ba16
JG		 497
498 if (cmd->use_sg)
499 pci_unmap_sg(hba->pdev, cmd->request_buffer,
500 cmd->use_sg, cmd->sc_data_direction);
501 return cp_len == count;
502}
503
504static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
505{
506 struct st_frame *p;
507 size_t count = sizeof(struct st_frame);
508
509 p = hba->copy_buffer;
4eea9dc4 510 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_FROM_CMD);
5a25ba16
JG		 511 memset(p->base, 0, sizeof(u32)*6);
512 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
513 p->rom_addr = 0;
514
515 p->drv_ver.major = ST_VER_MAJOR;
516 p->drv_ver.minor = ST_VER_MINOR;
517 p->drv_ver.oem = ST_OEM;
518 p->drv_ver.build = ST_BUILD_VER;
519
520 p->bus = hba->pdev->bus->number;
521 p->slot = hba->pdev->devfn;
522 p->irq_level = 0;
523 p->irq_vec = hba->pdev->irq;
524 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
525 p->subid =
526 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
527
fb4f66be 528 stex_internal_copy(ccb->cmd, p, &count, ccb->sg_count, ST_TO_CMD);
5a25ba16
JG		 529}
530
531static void
532stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
533{
534 req->tag = cpu_to_le16(tag);
535 req->task_attr = TASK_ATTRIBUTE_SIMPLE;
536 req->task_manage = 0; /* not supported yet */
5a25ba16
JG		 537
538 hba->ccb[tag].req = req;
539 hba->out_req_cnt++;
540
541 writel(hba->req_head, hba->mmio_base + IMR0);
542 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
543 readl(hba->mmio_base + IDBL); /* flush */
544}
545
cf355883
EL		 546static int
547stex_slave_alloc(struct scsi_device *sdev)
548{
549 /* Cheat: usually extracted from Inquiry data */
550 sdev->tagged_supported = 1;
551
552 scsi_activate_tcq(sdev, sdev->host->can_queue);
553
554 return 0;
555}
556
5a25ba16
JG		 557static int
558stex_slave_config(struct scsi_device *sdev)
559{
560 sdev->use_10_for_rw = 1;
561 sdev->use_10_for_ms = 1;
562 sdev->timeout = 60 * HZ;
cf355883
EL		 563 sdev->tagged_supported = 1;
564
5a25ba16
JG		 565 return 0;
566}
567
568static void
569stex_slave_destroy(struct scsi_device *sdev)
570{
cf355883 571 scsi_deactivate_tcq(sdev, 1);
5a25ba16
JG		 572}
573
574static int
575stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
576{
577 struct st_hba *hba;
578 struct Scsi_Host *host;
579 unsigned int id,lun;
580 struct req_msg *req;
581 u16 tag;
582 host = cmd->device->host;
583 id = cmd->device->id;
584 lun = cmd->device->channel; /* firmware lun issue work around */
585 hba = (struct st_hba *) &host->hostdata[0];
586
587 switch (cmd->cmnd[0]) {
588 case MODE_SENSE_10:
589 {
590 static char ms10_caching_page[12] =
591 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
592 unsigned char page;
593 page = cmd->cmnd[2] & 0x3f;
594 if (page == 0x8 || page == 0x3f) {
595 stex_direct_copy(cmd, ms10_caching_page,
596 sizeof(ms10_caching_page));
597 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
598 done(cmd);
599 } else
600 stex_invalid_field(cmd, done);
601 return 0;
602 }
603 case INQUIRY:
604 if (id != ST_MAX_ARRAY_SUPPORTED)
605 break;
606 if (lun == 0 && (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
607 stex_direct_copy(cmd, console_inq_page,
608 sizeof(console_inq_page));
609 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
610 done(cmd);
611 } else
612 stex_invalid_field(cmd, done);
613 return 0;
614 case PASSTHRU_CMD:
615 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
616 struct st_drvver ver;
617 ver.major = ST_VER_MAJOR;
618 ver.minor = ST_VER_MINOR;
619 ver.oem = ST_OEM;
620 ver.build = ST_BUILD_VER;
621 ver.signature[0] = PASSTHRU_SIGNATURE;
622 ver.console_id = ST_MAX_ARRAY_SUPPORTED;
623 ver.host_no = hba->host->host_no;
624 cmd->result = stex_direct_copy(cmd, &ver, sizeof(ver)) ?
625 DID_OK << 16 | COMMAND_COMPLETE << 8 :
626 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
627 done(cmd);
628 return 0;
629 }
630 default:
631 break;
632 }
633
634 cmd->scsi_done = done;
635
cf355883
EL		 636 tag = cmd->request->tag;
637
638 if (unlikely(tag >= host->can_queue))
5a25ba16
JG		 639 return SCSI_MLQUEUE_HOST_BUSY;
640
641 req = stex_alloc_req(hba);
fb4f66be
EL		 642
643 if (hba->cardtype == st_yosemite) {
644 req->lun = lun * (ST_MAX_TARGET_NUM - 1) + id;
645 req->target = 0;
646 } else {
647 req->lun = lun;
648 req->target = id;
649 }
5a25ba16
JG		 650
651 /* cdb */
652 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
653
654 hba->ccb[tag].cmd = cmd;
655 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
656 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
657 hba->ccb[tag].req_type = 0;
658
659 if (cmd->sc_data_direction != DMA_NONE)
660 stex_map_sg(hba, req, &hba->ccb[tag]);
661
662 stex_send_cmd(hba, req, tag);
663 return 0;
664}
665
666static void stex_unmap_sg(struct st_hba *hba, struct scsi_cmnd *cmd)
667{
668 if (cmd->sc_data_direction != DMA_NONE) {
669 if (cmd->use_sg)
670 pci_unmap_sg(hba->pdev, cmd->request_buffer,
671 cmd->use_sg, cmd->sc_data_direction);
672 else
673 pci_unmap_single(hba->pdev, cmd->SCp.dma_handle,
674 cmd->request_bufflen, cmd->sc_data_direction);
675 }
676}
677
678static void stex_scsi_done(struct st_ccb *ccb)
679{
680 struct scsi_cmnd *cmd = ccb->cmd;
681 int result;
682
683 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
684 result = ccb->scsi_status;
685 switch (ccb->scsi_status) {
686 case SAM_STAT_GOOD:
687 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
688 break;
689 case SAM_STAT_CHECK_CONDITION:
690 result |= DRIVER_SENSE << 24;
691 break;
692 case SAM_STAT_BUSY:
693 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
694 break;
695 default:
696 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
697 break;
698 }
699 }
700 else if (ccb->srb_status & SRB_SEE_SENSE)
701 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
702 else switch (ccb->srb_status) {
703 case SRB_STATUS_SELECTION_TIMEOUT:
704 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
705 break;
706 case SRB_STATUS_BUSY:
707 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
708 break;
709 case SRB_STATUS_INVALID_REQUEST:
710 case SRB_STATUS_ERROR:
711 default:
712 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
713 break;
714 }
715
716 cmd->result = result;
717 cmd->scsi_done(cmd);
718}
719
720static void stex_copy_data(struct st_ccb *ccb,
721 struct status_msg *resp, unsigned int variable)
722{
723 size_t count = variable;
724 if (resp->scsi_status != SAM_STAT_GOOD) {
725 if (ccb->sense_buffer != NULL)
726 memcpy(ccb->sense_buffer, resp->variable,
727 min(variable, ccb->sense_bufflen));
728 return;
729 }
730
731 if (ccb->cmd == NULL)
732 return;
fb4f66be
EL		 733 stex_internal_copy(ccb->cmd,
734 resp->variable, &count, ccb->sg_count, ST_TO_CMD);
735}
736
737static void stex_ys_commands(struct st_hba *hba,
738 struct st_ccb *ccb, struct status_msg *resp)
739{
740 size_t count;
741
742 if (ccb->cmd->cmnd[0] == MGT_CMD &&
743 resp->scsi_status != SAM_STAT_CHECK_CONDITION) {
744 ccb->cmd->request_bufflen =
745 le32_to_cpu(*(__le32 *)&resp->variable[0]);
746 return;
747 }
748
749 if (resp->srb_status != 0)
750 return;
751
752 /* determine inquiry command status by DeviceTypeQualifier */
753 if (ccb->cmd->cmnd[0] == INQUIRY &&
754 resp->scsi_status == SAM_STAT_GOOD) {
755 ST_INQ *inq_data;
756
757 count = STEX_EXTRA_SIZE;
758 stex_internal_copy(ccb->cmd, hba->copy_buffer,
759 &count, ccb->sg_count, ST_FROM_CMD);
760 inq_data = (ST_INQ *)hba->copy_buffer;
761 if (inq_data->DeviceTypeQualifier != 0)
762 ccb->srb_status = SRB_STATUS_SELECTION_TIMEOUT;
763 else
764 ccb->srb_status = SRB_STATUS_SUCCESS;
765 } else if (ccb->cmd->cmnd[0] == REPORT_LUNS) {
766 u8 *report_lun_data = (u8 *)hba->copy_buffer;
767
768 count = STEX_EXTRA_SIZE;
769 stex_internal_copy(ccb->cmd, report_lun_data,
770 &count, ccb->sg_count, ST_FROM_CMD);
771 if (report_lun_data[2] || report_lun_data[3]) {
772 report_lun_data[2] = 0x00;
773 report_lun_data[3] = 0x08;
774 stex_internal_copy(ccb->cmd, report_lun_data,
775 &count, ccb->sg_count, ST_TO_CMD);
776 }
777 }
5a25ba16
JG		 778}
779
780static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
781{
782 void __iomem *base = hba->mmio_base;
783 struct status_msg *resp;
784 struct st_ccb *ccb;
785 unsigned int size;
786 u16 tag;
787
788 if (!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED))
789 return;
790
791 /* status payloads */
792 hba->status_head = readl(base + OMR1);
793 if (unlikely(hba->status_head >= MU_STATUS_COUNT)) {
794 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
795 pci_name(hba->pdev));
796 return;
797 }
798
fb4f66be
EL		 799 /*
800 * it's not a valid status payload if:
801 * 1. there are no pending requests(e.g. during init stage)
802 * 2. there are some pending requests, but the controller is in
803 * reset status, and its type is not st_yosemite
804 * firmware of st_yosemite in reset status will return pending requests
805 * to driver, so we allow it to pass
806 */
807 if (unlikely(hba->out_req_cnt <= 0 ||
808 (hba->mu_status == MU_STATE_RESETTING &&
809 hba->cardtype != st_yosemite))) {
5a25ba16
JG		 810 hba->status_tail = hba->status_head;
811 goto update_status;
812 }
813
814 while (hba->status_tail != hba->status_head) {
815 resp = stex_get_status(hba);
816 tag = le16_to_cpu(resp->tag);
cf355883 817 if (unlikely(tag >= hba->host->can_queue)) {
5a25ba16
JG		 818 printk(KERN_WARNING DRV_NAME
819 "(%s): invalid tag\n", pci_name(hba->pdev));
820 continue;
821 }
5a25ba16 822
5a25ba16
JG		 823 ccb = &hba->ccb[tag];
824 if (hba->wait_ccb == ccb)
825 hba->wait_ccb = NULL;
826 if (unlikely(ccb->req == NULL)) {
827 printk(KERN_WARNING DRV_NAME
828 "(%s): lagging req\n", pci_name(hba->pdev));
fb4f66be 829 hba->out_req_cnt--;
5a25ba16
JG		 830 continue;
831 }
832
833 size = resp->payload_sz * sizeof(u32); /* payload size */
834 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
835 size > sizeof(*resp))) {
836 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
837 pci_name(hba->pdev));
838 } else {
839 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
840 if (size)
841 stex_copy_data(ccb, resp, size);
842 }
843
844 ccb->srb_status = resp->srb_status;
845 ccb->scsi_status = resp->scsi_status;
846
cf355883 847 if (likely(ccb->cmd != NULL)) {
fb4f66be
EL		 848 if (hba->cardtype == st_yosemite)
849 stex_ys_commands(hba, ccb, resp);
850
cf355883
EL		 851 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
852 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
853 stex_controller_info(hba, ccb);
fb4f66be 854
cf355883
EL		 855 stex_unmap_sg(hba, ccb->cmd);
856 stex_scsi_done(ccb);
857 hba->out_req_cnt--;
858 } else if (ccb->req_type & PASSTHRU_REQ_TYPE) {
859 hba->out_req_cnt--;
5a25ba16
JG		 860 if (ccb->req_type & PASSTHRU_REQ_NO_WAKEUP) {
861 ccb->req_type = 0;
862 continue;
863 }
864 ccb->req_type = 0;
865 if (waitqueue_active(&hba->waitq))
866 wake_up(&hba->waitq);
5a25ba16 867 }
5a25ba16
JG		 868 }
869
870update_status:
871 writel(hba->status_head, base + IMR1);
872 readl(base + IMR1); /* flush */
873}
874
7d12e780 875static irqreturn_t stex_intr(int irq, void *__hba)
5a25ba16
JG		 876{
877 struct st_hba *hba = __hba;
878 void __iomem *base = hba->mmio_base;
879 u32 data;
880 unsigned long flags;
881 int handled = 0;
882
883 spin_lock_irqsave(hba->host->host_lock, flags);
884
885 data = readl(base + ODBL);
886
887 if (data && data != 0xffffffff) {
888 /* clear the interrupt */
889 writel(data, base + ODBL);
890 readl(base + ODBL); /* flush */
891 stex_mu_intr(hba, data);
892 handled = 1;
893 }
894
895 spin_unlock_irqrestore(hba->host->host_lock, flags);
896
897 return IRQ_RETVAL(handled);
898}
899
900static int stex_handshake(struct st_hba *hba)
901{
902 void __iomem *base = hba->mmio_base;
903 struct handshake_frame *h;
904 dma_addr_t status_phys;
905 int i;
906
907 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
908 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
909 readl(base + IDBL);
910 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
911 && i < MU_MAX_DELAY_TIME; i++) {
912 rmb();
913 msleep(1);
914 }
915
916 if (i == MU_MAX_DELAY_TIME) {
917 printk(KERN_ERR DRV_NAME
918 "(%s): no handshake signature\n",
919 pci_name(hba->pdev));
920 return -1;
921 }
922 }
923
924 udelay(10);
925
926 h = (struct handshake_frame *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
927 h->rb_phy = cpu_to_le32(hba->dma_handle);
928 h->rb_phy_hi = cpu_to_le32((hba->dma_handle >> 16) >> 16);
929 h->req_sz = cpu_to_le16(sizeof(struct req_msg));
930 h->req_cnt = cpu_to_le16(MU_REQ_COUNT);
931 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
932 h->status_cnt = cpu_to_le16(MU_STATUS_COUNT);
933 stex_gettime(&h->hosttime);
934 h->partner_type = HMU_PARTNER_TYPE;
935
936 status_phys = hba->dma_handle + MU_REQ_BUFFER_SIZE;
937 writel(status_phys, base + IMR0);
938 readl(base + IMR0);
939 writel((status_phys >> 16) >> 16, base + IMR1);
940 readl(base + IMR1);
941
942 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
943 readl(base + OMR0);
944 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
945 readl(base + IDBL); /* flush */
946
947 udelay(10);
948 for (i = 0; readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE
949 && i < MU_MAX_DELAY_TIME; i++) {
950 rmb();
951 msleep(1);
952 }
953
954 if (i == MU_MAX_DELAY_TIME) {
955 printk(KERN_ERR DRV_NAME
956 "(%s): no signature after handshake frame\n",
957 pci_name(hba->pdev));
958 return -1;
959 }
960
961 writel(0, base + IMR0);
962 readl(base + IMR0);
963 writel(0, base + OMR0);
964 readl(base + OMR0);
965 writel(0, base + IMR1);
966 readl(base + IMR1);
967 writel(0, base + OMR1);
968 readl(base + OMR1); /* flush */
969 hba->mu_status = MU_STATE_STARTED;
970 return 0;
971}
972
973static int stex_abort(struct scsi_cmnd *cmd)
974{
975 struct Scsi_Host *host = cmd->device->host;
976 struct st_hba *hba = (struct st_hba *)host->hostdata;
cf355883 977 u16 tag = cmd->request->tag;
5a25ba16
JG		 978 void __iomem *base;
979 u32 data;
980 int result = SUCCESS;
981 unsigned long flags;
982 base = hba->mmio_base;
983 spin_lock_irqsave(host->host_lock, flags);
cf355883
EL		 984 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
985 hba->wait_ccb = &hba->ccb[tag];
986 else {
987 for (tag = 0; tag < host->can_queue; tag++)
988 if (hba->ccb[tag].cmd == cmd) {
989 hba->wait_ccb = &hba->ccb[tag];
990 break;
991 }
992 if (tag >= host->can_queue)
993 goto out;
994 }
5a25ba16
JG		 995
996 data = readl(base + ODBL);
997 if (data == 0 || data == 0xffffffff)
998 goto fail_out;
999
1000 writel(data, base + ODBL);
1001 readl(base + ODBL); /* flush */
1002
1003 stex_mu_intr(hba, data);
1004
1005 if (hba->wait_ccb == NULL) {
1006 printk(KERN_WARNING DRV_NAME
1007 "(%s): lost interrupt\n", pci_name(hba->pdev));
1008 goto out;
1009 }
1010
1011fail_out:
cf355883 1012 stex_unmap_sg(hba, cmd);
5a25ba16
JG		 1013 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1014 hba->wait_ccb = NULL;
1015 result = FAILED;
1016out:
1017 spin_unlock_irqrestore(host->host_lock, flags);
1018 return result;
1019}
1020
1021static void stex_hard_reset(struct st_hba *hba)
1022{
1023 struct pci_bus *bus;
1024 int i;
1025 u16 pci_cmd;
1026 u8 pci_bctl;
1027
1028 for (i = 0; i < 16; i++)
1029 pci_read_config_dword(hba->pdev, i * 4,
1030 &hba->pdev->saved_config_space[i]);
1031
1032 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1033 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1034 bus = hba->pdev->bus;
1035 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1036 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1037 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1038 msleep(1);
1039 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1040 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1041
1042 for (i = 0; i < MU_MAX_DELAY_TIME; i++) {
1043 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
47c4f997 1044 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
5a25ba16
JG		 1045 break;
1046 msleep(1);
1047 }
1048
1049 ssleep(5);
1050 for (i = 0; i < 16; i++)
1051 pci_write_config_dword(hba->pdev, i * 4,
1052 hba->pdev->saved_config_space[i]);
1053}
1054
1055static int stex_reset(struct scsi_cmnd *cmd)
1056{
1057 struct st_hba *hba;
1058 unsigned long flags;
fb4f66be 1059 unsigned long before;
5a25ba16
JG		 1060 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1061
1062 hba->mu_status = MU_STATE_RESETTING;
1063
1064 if (hba->cardtype == st_shasta)
1065 stex_hard_reset(hba);
1066
fb4f66be
EL		 1067 if (hba->cardtype != st_yosemite) {
1068 if (stex_handshake(hba)) {
1069 printk(KERN_WARNING DRV_NAME
1070 "(%s): resetting: handshake failed\n",
1071 pci_name(hba->pdev));
1072 return FAILED;
1073 }
1074 spin_lock_irqsave(hba->host->host_lock, flags);
1075 hba->req_head = 0;
1076 hba->req_tail = 0;
1077 hba->status_head = 0;
1078 hba->status_tail = 0;
1079 hba->out_req_cnt = 0;
1080 spin_unlock_irqrestore(hba->host->host_lock, flags);
1081 return SUCCESS;
5a25ba16 1082 }
5a25ba16 1083
fb4f66be
EL		 1084 /* st_yosemite */
1085 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1086 readl(hba->mmio_base + IDBL); /* flush */
1087 before = jiffies;
1088 while (hba->out_req_cnt > 0) {
1089 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1090 printk(KERN_WARNING DRV_NAME
1091 "(%s): reset timeout\n", pci_name(hba->pdev));
1092 return FAILED;
1093 }
1094 msleep(1);
1095 }
1096
1097 hba->mu_status = MU_STATE_STARTED;
5a25ba16
JG		 1098 return SUCCESS;
1099}
1100
1101static int stex_biosparam(struct scsi_device *sdev,
1102 struct block_device *bdev, sector_t capacity, int geom[])
1103{
b4b8bed1 1104 int heads = 255, sectors = 63;
5a25ba16
JG		 1105
1106 if (capacity < 0x200000) {
1107 heads = 64;
1108 sectors = 32;
1109 }
1110
b4b8bed1 1111 sector_div(capacity, heads * sectors);
5a25ba16
JG		 1112
1113 geom[0] = heads;
1114 geom[1] = sectors;
b4b8bed1 1115 geom[2] = capacity;
5a25ba16
JG		 1116
1117 return 0;
1118}
1119
1120static struct scsi_host_template driver_template = {
1121 .module = THIS_MODULE,
1122 .name = DRV_NAME,
1123 .proc_name = DRV_NAME,
1124 .bios_param = stex_biosparam,
1125 .queuecommand = stex_queuecommand,
cf355883 1126 .slave_alloc = stex_slave_alloc,
5a25ba16
JG		 1127 .slave_configure = stex_slave_config,
1128 .slave_destroy = stex_slave_destroy,
1129 .eh_abort_handler = stex_abort,
1130 .eh_host_reset_handler = stex_reset,
1131 .can_queue = ST_CAN_QUEUE,
1132 .this_id = -1,
1133 .sg_tablesize = ST_MAX_SG,
1134 .cmd_per_lun = ST_CMD_PER_LUN,
1135};
1136
1137static int stex_set_dma_mask(struct pci_dev * pdev)
1138{
1139 int ret;
1140 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)
1141 && !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1142 return 0;
1143 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1144 if (!ret)
1145 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1146 return ret;
1147}
1148
1149static int __devinit
1150stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1151{
1152 struct st_hba *hba;
1153 struct Scsi_Host *host;
1154 int err;
1155
1156 err = pci_enable_device(pdev);
1157 if (err)
1158 return err;
1159
1160 pci_set_master(pdev);
1161
1162 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1163
1164 if (!host) {
1165 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1166 pci_name(pdev));
1167 err = -ENOMEM;
1168 goto out_disable;
1169 }
1170
1171 hba = (struct st_hba *)host->hostdata;
1172 memset(hba, 0, sizeof(struct st_hba));
1173
1174 err = pci_request_regions(pdev, DRV_NAME);
1175 if (err < 0) {
1176 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1177 pci_name(pdev));
1178 goto out_scsi_host_put;
1179 }
1180
1181 hba->mmio_base = ioremap(pci_resource_start(pdev, 0),
1182 pci_resource_len(pdev, 0));
1183 if ( !hba->mmio_base) {
1184 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1185 pci_name(pdev));
1186 err = -ENOMEM;
1187 goto out_release_regions;
1188 }
1189
1190 err = stex_set_dma_mask(pdev);
1191 if (err) {
1192 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1193 pci_name(pdev));
1194 goto out_iounmap;
1195 }
1196
1197 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
1198 STEX_BUFFER_SIZE, &hba->dma_handle, GFP_KERNEL);
1199 if (!hba->dma_mem) {
1200 err = -ENOMEM;
1201 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1202 pci_name(pdev));
1203 goto out_iounmap;
1204 }
1205
1206 hba->status_buffer =
1207 (struct status_msg *)(hba->dma_mem + MU_REQ_BUFFER_SIZE);
1208 hba->copy_buffer = hba->dma_mem + MU_BUFFER_SIZE;
1209 hba->mu_status = MU_STATE_STARTING;
1210
1211 hba->cardtype = (unsigned int) id->driver_data;
1212
1213 /* firmware uses id/lun pair for a logical drive, but lun would be
1214 always 0 if CONFIG_SCSI_MULTI_LUN not configured, so we use
1215 channel to map lun here */
1216 host->max_channel = ST_MAX_LUN_PER_TARGET - 1;
1217 host->max_id = ST_MAX_TARGET_NUM;
1218 host->max_lun = 1;
1219 host->unique_id = host->host_no;
1220 host->max_cmd_len = STEX_CDB_LENGTH;
1221
1222 hba->host = host;
1223 hba->pdev = pdev;
1224 init_waitqueue_head(&hba->waitq);
1225
1226 err = request_irq(pdev->irq, stex_intr, IRQF_SHARED, DRV_NAME, hba);
1227 if (err) {
1228 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1229 pci_name(pdev));
1230 goto out_pci_free;
1231 }
1232
1233 err = stex_handshake(hba);
1234 if (err)
1235 goto out_free_irq;
1236
deb81d80
JB		 1237 err = scsi_init_shared_tag_map(host, ST_CAN_QUEUE);
1238 if (err) {
cf355883
EL		 1239 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1240 pci_name(pdev));
1241 goto out_free_irq;
1242 }
1243
5a25ba16
JG		 1244 pci_set_drvdata(pdev, hba);
1245
1246 err = scsi_add_host(host, &pdev->dev);
1247 if (err) {
1248 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1249 pci_name(pdev));
1250 goto out_free_irq;
1251 }
1252
1253 scsi_scan_host(host);
1254
1255 return 0;
1256
1257out_free_irq:
1258 free_irq(pdev->irq, hba);
1259out_pci_free:
1260 dma_free_coherent(&pdev->dev, STEX_BUFFER_SIZE,
1261 hba->dma_mem, hba->dma_handle);
1262out_iounmap:
1263 iounmap(hba->mmio_base);
1264out_release_regions:
1265 pci_release_regions(pdev);
1266out_scsi_host_put:
1267 scsi_host_put(host);
1268out_disable:
1269 pci_disable_device(pdev);
1270
1271 return err;
1272}
1273
1274static void stex_hba_stop(struct st_hba *hba)
1275{
1276 struct req_msg *req;
1277 unsigned long flags;
1278 unsigned long before;
cf355883 1279 u16 tag = 0;
5a25ba16
JG		 1280
1281 spin_lock_irqsave(hba->host->host_lock, flags);
1282 req = stex_alloc_req(hba);
1283 memset(req->cdb, 0, STEX_CDB_LENGTH);
1284
fb4f66be
EL		 1285 if (hba->cardtype == st_yosemite) {
1286 req->cdb[0] = MGT_CMD;
1287 req->cdb[1] = MGT_CMD_SIGNATURE;
1288 req->cdb[2] = CTLR_CONFIG_CMD;
1289 req->cdb[3] = CTLR_SHUTDOWN;
1290 } else {
1291 req->cdb[0] = CONTROLLER_CMD;
1292 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1293 req->cdb[2] = CTLR_POWER_SAVING;
1294 }
5a25ba16
JG		 1295
1296 hba->ccb[tag].cmd = NULL;
1297 hba->ccb[tag].sg_count = 0;
1298 hba->ccb[tag].sense_bufflen = 0;
1299 hba->ccb[tag].sense_buffer = NULL;
1300 hba->ccb[tag].req_type |= PASSTHRU_REQ_TYPE;
1301
1302 stex_send_cmd(hba, req, tag);
1303 spin_unlock_irqrestore(hba->host->host_lock, flags);
1304
cf355883
EL		 1305 before = jiffies;
1306 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
1307 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ))
1308 return;
1309 msleep(10);
1310 }
5a25ba16
JG		 1311}
1312
1313static void stex_hba_free(struct st_hba *hba)
1314{
1315 free_irq(hba->pdev->irq, hba);
1316
1317 iounmap(hba->mmio_base);
1318
1319 pci_release_regions(hba->pdev);
1320
1321 dma_free_coherent(&hba->pdev->dev, STEX_BUFFER_SIZE,
1322 hba->dma_mem, hba->dma_handle);
1323}
1324
1325static void stex_remove(struct pci_dev *pdev)
1326{
1327 struct st_hba *hba = pci_get_drvdata(pdev);
1328
1329 scsi_remove_host(hba->host);
1330
1331 pci_set_drvdata(pdev, NULL);
1332
1333 stex_hba_stop(hba);
1334
1335 stex_hba_free(hba);
1336
1337 scsi_host_put(hba->host);
1338
1339 pci_disable_device(pdev);
1340}
1341
1342static void stex_shutdown(struct pci_dev *pdev)
1343{
1344 struct st_hba *hba = pci_get_drvdata(pdev);
1345
1346 stex_hba_stop(hba);
1347}
1348
1349static struct pci_device_id stex_pci_tbl[] = {
1350 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1351 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1352 { 0x105a, 0xf350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1353 { 0x105a, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1354 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1355 { 0x105a, 0x8301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1356 { 0x105a, 0x8302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_shasta },
1357 { 0x1725, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
fb4f66be 1358 { 0x105a, 0x8650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yosemite },
5a25ba16
JG		 1359 { } /* terminate list */
1360};
1361MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1362
1363static struct pci_driver stex_pci_driver = {
1364 .name = DRV_NAME,
1365 .id_table = stex_pci_tbl,
1366 .probe = stex_probe,
1367 .remove = __devexit_p(stex_remove),
1368 .shutdown = stex_shutdown,
1369};
1370
1371static int __init stex_init(void)
1372{
1373 printk(KERN_INFO DRV_NAME
1374 ": Promise SuperTrak EX Driver version: %s\n",
1375 ST_DRIVER_VERSION);
1376
1377 return pci_register_driver(&stex_pci_driver);
1378}
1379
1380static void __exit stex_exit(void)
1381{
1382 pci_unregister_driver(&stex_pci_driver);
1383}
1384
1385module_init(stex_init);
1386module_exit(stex_exit);
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