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[SCSI] mptfusion: Bump version to 3.04.13
[net-next-2.6.git] / drivers / scsi / stex.c
CommitLineData
5a25ba16
JG		 1/*
2 * SuperTrak EX Series Storage Controller driver for Linux
3 *
bd5cd9cd 4 * Copyright (C) 2005-2009 Promise Technology Inc.
5a25ba16
JG		 5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 * Written By:
12 * Ed Lin <promise_linux@promise.com>
13 *
5a25ba16
JG		 14 */
15
16#include <linux/init.h>
17#include <linux/errno.h>
18#include <linux/kernel.h>
19#include <linux/delay.h>
5a25ba16
JG		 20#include <linux/time.h>
21#include <linux/pci.h>
22#include <linux/blkdev.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/module.h>
26#include <linux/spinlock.h>
27#include <asm/io.h>
28#include <asm/irq.h>
29#include <asm/byteorder.h>
30#include <scsi/scsi.h>
31#include <scsi/scsi_device.h>
32#include <scsi/scsi_cmnd.h>
33#include <scsi/scsi_host.h>
cf355883 34#include <scsi/scsi_tcq.h>
c25da0af 35#include <scsi/scsi_dbg.h>
11002fbc 36#include <scsi/scsi_eh.h>
5a25ba16
JG		 37
38#define DRV_NAME "stex"
05b4460b
EL		 39#define ST_DRIVER_VERSION "4.6.0000.3"
40#define ST_VER_MAJOR 4
41#define ST_VER_MINOR 6
42#define ST_OEM 0
43#define ST_BUILD_VER 3
5a25ba16
JG		 44
45enum {
46 /* MU register offset */
47 IMR0 = 0x10, /* MU_INBOUND_MESSAGE_REG0 */
48 IMR1 = 0x14, /* MU_INBOUND_MESSAGE_REG1 */
49 OMR0 = 0x18, /* MU_OUTBOUND_MESSAGE_REG0 */
50 OMR1 = 0x1c, /* MU_OUTBOUND_MESSAGE_REG1 */
51 IDBL = 0x20, /* MU_INBOUND_DOORBELL */
52 IIS = 0x24, /* MU_INBOUND_INTERRUPT_STATUS */
53 IIM = 0x28, /* MU_INBOUND_INTERRUPT_MASK */
54 ODBL = 0x2c, /* MU_OUTBOUND_DOORBELL */
55 OIS = 0x30, /* MU_OUTBOUND_INTERRUPT_STATUS */
56 OIM = 0x3c, /* MU_OUTBOUND_INTERRUPT_MASK */
57
69cb4875 58 YIOA_STATUS = 0x00,
0f3f6ee6
EL		 59 YH2I_INT = 0x20,
60 YINT_EN = 0x34,
61 YI2H_INT = 0x9c,
62 YI2H_INT_C = 0xa0,
63 YH2I_REQ = 0xc0,
64 YH2I_REQ_HI = 0xc4,
65
5a25ba16
JG		 66 /* MU register value */
67 MU_INBOUND_DOORBELL_HANDSHAKE = 1,
68 MU_INBOUND_DOORBELL_REQHEADCHANGED = 2,
69 MU_INBOUND_DOORBELL_STATUSTAILCHANGED = 4,
70 MU_INBOUND_DOORBELL_HMUSTOPPED = 8,
71 MU_INBOUND_DOORBELL_RESET = 16,
72
73 MU_OUTBOUND_DOORBELL_HANDSHAKE = 1,
74 MU_OUTBOUND_DOORBELL_REQUESTTAILCHANGED = 2,
75 MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED = 4,
76 MU_OUTBOUND_DOORBELL_BUSCHANGE = 8,
77 MU_OUTBOUND_DOORBELL_HASEVENT = 16,
78
79 /* MU status code */
80 MU_STATE_STARTING = 1,
81 MU_STATE_FMU_READY_FOR_HANDSHAKE = 2,
82 MU_STATE_SEND_HANDSHAKE_FRAME = 3,
83 MU_STATE_STARTED = 4,
84 MU_STATE_RESETTING = 5,
85
76fbf96f 86 MU_MAX_DELAY = 120,
5a25ba16 87 MU_HANDSHAKE_SIGNATURE = 0x55aaaa55,
529e7a62 88 MU_HANDSHAKE_SIGNATURE_HALF = 0x5a5a0000,
76fbf96f 89 MU_HARD_RESET_WAIT = 30000,
5a25ba16
JG		 90 HMU_PARTNER_TYPE = 2,
91
92 /* firmware returned values */
93 SRB_STATUS_SUCCESS = 0x01,
94 SRB_STATUS_ERROR = 0x04,
95 SRB_STATUS_BUSY = 0x05,
96 SRB_STATUS_INVALID_REQUEST = 0x06,
97 SRB_STATUS_SELECTION_TIMEOUT = 0x0A,
98 SRB_SEE_SENSE = 0x80,
99
100 /* task attribute */
101 TASK_ATTRIBUTE_SIMPLE = 0x0,
102 TASK_ATTRIBUTE_HEADOFQUEUE = 0x1,
103 TASK_ATTRIBUTE_ORDERED = 0x2,
104 TASK_ATTRIBUTE_ACA = 0x4,
105
0f3f6ee6
EL		 106 SS_STS_NORMAL = 0x80000000,
107 SS_STS_DONE = 0x40000000,
108 SS_STS_HANDSHAKE = 0x20000000,
109
110 SS_HEAD_HANDSHAKE = 0x80,
111
69cb4875
EL		 112 SS_H2I_INT_RESET = 0x100,
113
114 SS_MU_OPERATIONAL = 0x80000000,
115
7cfe99a5 116 STEX_CDB_LENGTH = 16,
5a25ba16 117 STATUS_VAR_LEN = 128,
5a25ba16
JG		 118
119 /* sg flags */
120 SG_CF_EOT = 0x80, /* end of table */
121 SG_CF_64B = 0x40, /* 64 bit item */
122 SG_CF_HOST = 0x20, /* sg in host memory */
7cfe99a5
ELP		 123 MSG_DATA_DIR_ND = 0,
124 MSG_DATA_DIR_IN = 1,
125 MSG_DATA_DIR_OUT = 2,
5a25ba16 126
5a25ba16
JG		 127 st_shasta = 0,
128 st_vsc = 1,
591a3a5f
EL		 129 st_yosemite = 2,
130 st_seq = 3,
0f3f6ee6 131 st_yel = 4,
5a25ba16
JG		 132
133 PASSTHRU_REQ_TYPE = 0x00000001,
134 PASSTHRU_REQ_NO_WAKEUP = 0x00000100,
7cfe99a5 135 ST_INTERNAL_TIMEOUT = 180,
5a25ba16 136
fb4f66be
EL		 137 ST_TO_CMD = 0,
138 ST_FROM_CMD = 1,
139
5a25ba16 140 /* vendor specific commands of Promise */
fb4f66be
EL		 141 MGT_CMD = 0xd8,
142 SINBAND_MGT_CMD = 0xd9,
5a25ba16
JG		 143 ARRAY_CMD = 0xe0,
144 CONTROLLER_CMD = 0xe1,
145 DEBUGGING_CMD = 0xe2,
146 PASSTHRU_CMD = 0xe3,
147
148 PASSTHRU_GET_ADAPTER = 0x05,
149 PASSTHRU_GET_DRVVER = 0x10,
fb4f66be
EL		 150
151 CTLR_CONFIG_CMD = 0x03,
152 CTLR_SHUTDOWN = 0x0d,
153
5a25ba16
JG		 154 CTLR_POWER_STATE_CHANGE = 0x0e,
155 CTLR_POWER_SAVING = 0x01,
156
157 PASSTHRU_SIGNATURE = 0x4e415041,
fb4f66be 158 MGT_CMD_SIGNATURE = 0xba,
5a25ba16
JG		 159
160 INQUIRY_EVPD = 0x01,
94e9108b
EL		 161
162 ST_ADDITIONAL_MEM = 0x200000,
5a25ba16
JG		 163};
164
165struct st_sgitem {
166 u8 ctrl; /* SG_CF_xxx */
167 u8 reserved[3];
168 __le32 count;
f1498161 169 __le64 addr;
5a25ba16
JG		 170};
171
0f3f6ee6
EL		 172struct st_ss_sgitem {
173 __le32 addr;
174 __le32 addr_hi;
175 __le32 count;
176};
177
5a25ba16
JG		 178struct st_sgtable {
179 __le16 sg_count;
180 __le16 max_sg_count;
181 __le32 sz_in_byte;
5a25ba16
JG		 182};
183
0f3f6ee6
EL		 184struct st_msg_header {
185 __le64 handle;
186 u8 flag;
187 u8 channel;
188 __le16 timeout;
189 u32 reserved;
190};
191
5a25ba16 192struct handshake_frame {
f1498161 193 __le64 rb_phy; /* request payload queue physical address */
5a25ba16
JG		 194 __le16 req_sz; /* size of each request payload */
195 __le16 req_cnt; /* count of reqs the buffer can hold */
196 __le16 status_sz; /* size of each status payload */
197 __le16 status_cnt; /* count of status the buffer can hold */
f1498161 198 __le64 hosttime; /* seconds from Jan 1, 1970 (GMT) */
5a25ba16
JG		 199 u8 partner_type; /* who sends this frame */
200 u8 reserved0[7];
201 __le32 partner_ver_major;
202 __le32 partner_ver_minor;
203 __le32 partner_ver_oem;
204 __le32 partner_ver_build;
94e9108b
EL		 205 __le32 extra_offset; /* NEW */
206 __le32 extra_size; /* NEW */
0f3f6ee6
EL		 207 __le32 scratch_size;
208 u32 reserved1;
5a25ba16
JG		 209};
210
211struct req_msg {
212 __le16 tag;
213 u8 lun;
214 u8 target;
215 u8 task_attr;
216 u8 task_manage;
7cfe99a5 217 u8 data_dir;
f903d7b7 218 u8 payload_sz; /* payload size in 4-byte, not used */
5a25ba16 219 u8 cdb[STEX_CDB_LENGTH];
591a3a5f 220 u32 variable[0];
5a25ba16
JG		 221};
222
223struct status_msg {
224 __le16 tag;
225 u8 lun;
226 u8 target;
227 u8 srb_status;
228 u8 scsi_status;
229 u8 reserved;
230 u8 payload_sz; /* payload size in 4-byte */
231 u8 variable[STATUS_VAR_LEN];
232};
233
234struct ver_info {
235 u32 major;
236 u32 minor;
237 u32 oem;
238 u32 build;
239 u32 reserved[2];
240};
241
242struct st_frame {
243 u32 base[6];
244 u32 rom_addr;
245
246 struct ver_info drv_ver;
247 struct ver_info bios_ver;
248
249 u32 bus;
250 u32 slot;
251 u32 irq_level;
252 u32 irq_vec;
253 u32 id;
254 u32 subid;
255
256 u32 dimm_size;
257 u8 dimm_type;
258 u8 reserved[3];
259
260 u32 channel;
261 u32 reserved1;
262};
263
264struct st_drvver {
265 u32 major;
266 u32 minor;
267 u32 oem;
268 u32 build;
269 u32 signature[2];
270 u8 console_id;
271 u8 host_no;
272 u8 reserved0[2];
273 u32 reserved[3];
274};
275
5a25ba16
JG		 276struct st_ccb {
277 struct req_msg *req;
278 struct scsi_cmnd *cmd;
279
280 void *sense_buffer;
281 unsigned int sense_bufflen;
282 int sg_count;
283
284 u32 req_type;
285 u8 srb_status;
286 u8 scsi_status;
f1498161 287 u8 reserved[2];
5a25ba16
JG		 288};
289
290struct st_hba {
291 void __iomem *mmio_base; /* iomapped PCI memory space */
292 void *dma_mem;
293 dma_addr_t dma_handle;
94e9108b 294 size_t dma_size;
5a25ba16
JG		 295
296 struct Scsi_Host *host;
297 struct pci_dev *pdev;
298
0f3f6ee6
EL		 299 struct req_msg * (*alloc_rq) (struct st_hba *);
300 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
301 void (*send) (struct st_hba *, struct req_msg *, u16);
302
5a25ba16
JG		 303 u32 req_head;
304 u32 req_tail;
305 u32 status_head;
306 u32 status_tail;
307
308 struct status_msg *status_buffer;
309 void *copy_buffer; /* temp buffer for driver-handled commands */
591a3a5f 310 struct st_ccb *ccb;
5a25ba16 311 struct st_ccb *wait_ccb;
0f3f6ee6 312 __le32 *scratch;
5a25ba16
JG		 313
314 unsigned int mu_status;
5a25ba16 315 unsigned int cardtype;
99946f81
EL		 316 int msi_enabled;
317 int out_req_cnt;
591a3a5f
EL		 318 u32 extra_offset;
319 u16 rq_count;
320 u16 rq_size;
321 u16 sts_count;
322};
323
324struct st_card_info {
0f3f6ee6
EL		 325 struct req_msg * (*alloc_rq) (struct st_hba *);
326 int (*map_sg)(struct st_hba *, struct req_msg *, struct st_ccb *);
327 void (*send) (struct st_hba *, struct req_msg *, u16);
591a3a5f
EL		 328 unsigned int max_id;
329 unsigned int max_lun;
330 unsigned int max_channel;
331 u16 rq_count;
332 u16 rq_size;
333 u16 sts_count;
5a25ba16
JG		 334};
335
99946f81
EL		 336static int msi;
337module_param(msi, int, 0);
338MODULE_PARM_DESC(msi, "Enable Message Signaled Interrupts(0=off, 1=on)");
339
5a25ba16
JG		 340static const char console_inq_page[] =
341{
342 0x03,0x00,0x03,0x03,0xFA,0x00,0x00,0x30,
343 0x50,0x72,0x6F,0x6D,0x69,0x73,0x65,0x20, /* "Promise " */
344 0x52,0x41,0x49,0x44,0x20,0x43,0x6F,0x6E, /* "RAID Con" */
345 0x73,0x6F,0x6C,0x65,0x20,0x20,0x20,0x20, /* "sole " */
346 0x31,0x2E,0x30,0x30,0x20,0x20,0x20,0x20, /* "1.00 " */
347 0x53,0x58,0x2F,0x52,0x53,0x41,0x46,0x2D, /* "SX/RSAF-" */
348 0x54,0x45,0x31,0x2E,0x30,0x30,0x20,0x20, /* "TE1.00 " */
349 0x0C,0x20,0x20,0x20,0x20,0x20,0x20,0x20
350};
351
352MODULE_AUTHOR("Ed Lin");
353MODULE_DESCRIPTION("Promise Technology SuperTrak EX Controllers");
354MODULE_LICENSE("GPL");
355MODULE_VERSION(ST_DRIVER_VERSION);
356
f1498161 357static void stex_gettime(__le64 *time)
5a25ba16
JG		 358{
359 struct timeval tv;
5a25ba16 360
7cfe99a5 361 do_gettimeofday(&tv);
f1498161 362 *time = cpu_to_le64(tv.tv_sec);
5a25ba16
JG		 363}
364
5a25ba16
JG		 365static struct status_msg *stex_get_status(struct st_hba *hba)
366{
f1498161 367 struct status_msg *status = hba->status_buffer + hba->status_tail;
5a25ba16
JG		 368
369 ++hba->status_tail;
591a3a5f 370 hba->status_tail %= hba->sts_count+1;
5a25ba16
JG		 371
372 return status;
373}
374
5a25ba16
JG		 375static void stex_invalid_field(struct scsi_cmnd *cmd,
376 void (*done)(struct scsi_cmnd *))
377{
11002fbc
FT		 378 cmd->result = (DRIVER_SENSE << 24) | SAM_STAT_CHECK_CONDITION;
379
7cfe99a5 380 /* "Invalid field in cdb" */
11002fbc
FT		 381 scsi_build_sense_buffer(0, cmd->sense_buffer, ILLEGAL_REQUEST, 0x24,
382 0x0);
5a25ba16
JG		 383 done(cmd);
384}
385
386static struct req_msg *stex_alloc_req(struct st_hba *hba)
387{
591a3a5f 388 struct req_msg *req = hba->dma_mem + hba->req_head * hba->rq_size;
5a25ba16
JG		 389
390 ++hba->req_head;
591a3a5f 391 hba->req_head %= hba->rq_count+1;
5a25ba16
JG		 392
393 return req;
394}
395
0f3f6ee6
EL		 396static struct req_msg *stex_ss_alloc_req(struct st_hba *hba)
397{
398 return (struct req_msg *)(hba->dma_mem +
399 hba->req_head * hba->rq_size + sizeof(struct st_msg_header));
400}
401
5a25ba16
JG		 402static int stex_map_sg(struct st_hba *hba,
403 struct req_msg *req, struct st_ccb *ccb)
404{
5a25ba16 405 struct scsi_cmnd *cmd;
d5587d5d 406 struct scatterlist *sg;
5a25ba16 407 struct st_sgtable *dst;
f1498161 408 struct st_sgitem *table;
d5587d5d 409 int i, nseg;
5a25ba16
JG		 410
411 cmd = ccb->cmd;
d5587d5d 412 nseg = scsi_dma_map(cmd);
f1498161 413 BUG_ON(nseg < 0);
d5587d5d 414 if (nseg) {
f1498161
EL		 415 dst = (struct st_sgtable *)req->variable;
416
d5587d5d
FT		 417 ccb->sg_count = nseg;
418 dst->sg_count = cpu_to_le16((u16)nseg);
f1498161
EL		 419 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
420 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
5a25ba16 421
f1498161 422 table = (struct st_sgitem *)(dst + 1);
d5587d5d 423 scsi_for_each_sg(cmd, sg, nseg, i) {
f1498161
EL		 424 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
425 table[i].addr = cpu_to_le64(sg_dma_address(sg));
426 table[i].ctrl = SG_CF_64B | SG_CF_HOST;
5a25ba16 427 }
f1498161 428 table[--i].ctrl |= SG_CF_EOT;
5a25ba16
JG		 429 }
430
f1498161 431 return nseg;
5a25ba16
JG		 432}
433
0f3f6ee6
EL		 434static int stex_ss_map_sg(struct st_hba *hba,
435 struct req_msg *req, struct st_ccb *ccb)
436{
437 struct scsi_cmnd *cmd;
438 struct scatterlist *sg;
439 struct st_sgtable *dst;
440 struct st_ss_sgitem *table;
441 int i, nseg;
442
443 cmd = ccb->cmd;
444 nseg = scsi_dma_map(cmd);
445 BUG_ON(nseg < 0);
446 if (nseg) {
447 dst = (struct st_sgtable *)req->variable;
448
449 ccb->sg_count = nseg;
450 dst->sg_count = cpu_to_le16((u16)nseg);
451 dst->max_sg_count = cpu_to_le16(hba->host->sg_tablesize);
452 dst->sz_in_byte = cpu_to_le32(scsi_bufflen(cmd));
453
454 table = (struct st_ss_sgitem *)(dst + 1);
455 scsi_for_each_sg(cmd, sg, nseg, i) {
456 table[i].count = cpu_to_le32((u32)sg_dma_len(sg));
457 table[i].addr =
458 cpu_to_le32(sg_dma_address(sg) & 0xffffffff);
459 table[i].addr_hi =
460 cpu_to_le32((sg_dma_address(sg) >> 16) >> 16);
461 }
462 }
463
464 return nseg;
465}
466
5a25ba16
JG		 467static void stex_controller_info(struct st_hba *hba, struct st_ccb *ccb)
468{
469 struct st_frame *p;
470 size_t count = sizeof(struct st_frame);
471
472 p = hba->copy_buffer;
f1498161 473 scsi_sg_copy_to_buffer(ccb->cmd, p, count);
5a25ba16
JG		 474 memset(p->base, 0, sizeof(u32)*6);
475 *(unsigned long *)(p->base) = pci_resource_start(hba->pdev, 0);
476 p->rom_addr = 0;
477
478 p->drv_ver.major = ST_VER_MAJOR;
479 p->drv_ver.minor = ST_VER_MINOR;
480 p->drv_ver.oem = ST_OEM;
481 p->drv_ver.build = ST_BUILD_VER;
482
483 p->bus = hba->pdev->bus->number;
484 p->slot = hba->pdev->devfn;
485 p->irq_level = 0;
486 p->irq_vec = hba->pdev->irq;
487 p->id = hba->pdev->vendor << 16 | hba->pdev->device;
488 p->subid =
489 hba->pdev->subsystem_vendor << 16 | hba->pdev->subsystem_device;
490
f1498161 491 scsi_sg_copy_from_buffer(ccb->cmd, p, count);
5a25ba16
JG		 492}
493
494static void
495stex_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
496{
497 req->tag = cpu_to_le16(tag);
5a25ba16
JG		 498
499 hba->ccb[tag].req = req;
500 hba->out_req_cnt++;
501
502 writel(hba->req_head, hba->mmio_base + IMR0);
503 writel(MU_INBOUND_DOORBELL_REQHEADCHANGED, hba->mmio_base + IDBL);
504 readl(hba->mmio_base + IDBL); /* flush */
505}
506
0f3f6ee6
EL		 507static void
508stex_ss_send_cmd(struct st_hba *hba, struct req_msg *req, u16 tag)
509{
510 struct scsi_cmnd *cmd;
511 struct st_msg_header *msg_h;
512 dma_addr_t addr;
513
514 req->tag = cpu_to_le16(tag);
515
516 hba->ccb[tag].req = req;
517 hba->out_req_cnt++;
518
519 cmd = hba->ccb[tag].cmd;
520 msg_h = (struct st_msg_header *)req - 1;
521 if (likely(cmd)) {
522 msg_h->channel = (u8)cmd->device->channel;
523 msg_h->timeout = cpu_to_le16(cmd->request->timeout/HZ);
524 }
525 addr = hba->dma_handle + hba->req_head * hba->rq_size;
526 addr += (hba->ccb[tag].sg_count+4)/11;
527 msg_h->handle = cpu_to_le64(addr);
528
529 ++hba->req_head;
530 hba->req_head %= hba->rq_count+1;
531
532 writel((addr >> 16) >> 16, hba->mmio_base + YH2I_REQ_HI);
533 readl(hba->mmio_base + YH2I_REQ_HI); /* flush */
534 writel(addr, hba->mmio_base + YH2I_REQ);
535 readl(hba->mmio_base + YH2I_REQ); /* flush */
536}
537
cf355883
EL		 538static int
539stex_slave_alloc(struct scsi_device *sdev)
540{
541 /* Cheat: usually extracted from Inquiry data */
542 sdev->tagged_supported = 1;
543
f1498161 544 scsi_activate_tcq(sdev, sdev->host->can_queue);
cf355883
EL		 545
546 return 0;
547}
548
5a25ba16
JG		 549static int
550stex_slave_config(struct scsi_device *sdev)
551{
552 sdev->use_10_for_rw = 1;
553 sdev->use_10_for_ms = 1;
dc5c49bf 554 blk_queue_rq_timeout(sdev->request_queue, 60 * HZ);
cf355883
EL		 555 sdev->tagged_supported = 1;
556
5a25ba16
JG		 557 return 0;
558}
559
560static void
561stex_slave_destroy(struct scsi_device *sdev)
562{
cf355883 563 scsi_deactivate_tcq(sdev, 1);
5a25ba16
JG		 564}
565
566static int
567stex_queuecommand(struct scsi_cmnd *cmd, void (* done)(struct scsi_cmnd *))
568{
569 struct st_hba *hba;
570 struct Scsi_Host *host;
f1498161 571 unsigned int id, lun;
5a25ba16
JG		 572 struct req_msg *req;
573 u16 tag;
7cfe99a5 574
5a25ba16
JG		 575 host = cmd->device->host;
576 id = cmd->device->id;
e0b2e597 577 lun = cmd->device->lun;
5a25ba16
JG		 578 hba = (struct st_hba *) &host->hostdata[0];
579
580 switch (cmd->cmnd[0]) {
581 case MODE_SENSE_10:
582 {
583 static char ms10_caching_page[12] =
584 { 0, 0x12, 0, 0, 0, 0, 0, 0, 0x8, 0xa, 0x4, 0 };
585 unsigned char page;
7cfe99a5 586
5a25ba16
JG		 587 page = cmd->cmnd[2] & 0x3f;
588 if (page == 0x8 || page == 0x3f) {
31fe47d4
FT		 589 scsi_sg_copy_from_buffer(cmd, ms10_caching_page,
590 sizeof(ms10_caching_page));
5a25ba16
JG		 591 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
592 done(cmd);
593 } else
594 stex_invalid_field(cmd, done);
595 return 0;
596 }
e0b2e597
EL		 597 case REPORT_LUNS:
598 /*
599 * The shasta firmware does not report actual luns in the
600 * target, so fail the command to force sequential lun scan.
601 * Also, the console device does not support this command.
602 */
603 if (hba->cardtype == st_shasta || id == host->max_id - 1) {
604 stex_invalid_field(cmd, done);
605 return 0;
606 }
607 break;
d116a7bc
EL		 608 case TEST_UNIT_READY:
609 if (id == host->max_id - 1) {
610 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
611 done(cmd);
612 return 0;
613 }
614 break;
5a25ba16 615 case INQUIRY:
e0b2e597 616 if (id != host->max_id - 1)
5a25ba16 617 break;
0f3f6ee6
EL		 618 if (!lun && !cmd->device->channel &&
619 (cmd->cmnd[1] & INQUIRY_EVPD) == 0) {
31fe47d4
FT		 620 scsi_sg_copy_from_buffer(cmd, (void *)console_inq_page,
621 sizeof(console_inq_page));
5a25ba16
JG		 622 cmd->result = DID_OK << 16 | COMMAND_COMPLETE << 8;
623 done(cmd);
624 } else
625 stex_invalid_field(cmd, done);
626 return 0;
627 case PASSTHRU_CMD:
628 if (cmd->cmnd[1] == PASSTHRU_GET_DRVVER) {
629 struct st_drvver ver;
26106e3c 630 size_t cp_len = sizeof(ver);
7cfe99a5 631
5a25ba16
JG		 632 ver.major = ST_VER_MAJOR;
633 ver.minor = ST_VER_MINOR;
634 ver.oem = ST_OEM;
635 ver.build = ST_BUILD_VER;
636 ver.signature[0] = PASSTHRU_SIGNATURE;
e0b2e597 637 ver.console_id = host->max_id - 1;
5a25ba16 638 ver.host_no = hba->host->host_no;
31fe47d4 639 cp_len = scsi_sg_copy_from_buffer(cmd, &ver, cp_len);
26106e3c 640 cmd->result = sizeof(ver) == cp_len ?
5a25ba16
JG		 641 DID_OK << 16 | COMMAND_COMPLETE << 8 :
642 DID_ERROR << 16 | COMMAND_COMPLETE << 8;
643 done(cmd);
644 return 0;
645 }
646 default:
647 break;
648 }
649
650 cmd->scsi_done = done;
651
cf355883
EL		 652 tag = cmd->request->tag;
653
654 if (unlikely(tag >= host->can_queue))
5a25ba16
JG		 655 return SCSI_MLQUEUE_HOST_BUSY;
656
0f3f6ee6 657 req = hba->alloc_rq(hba);
fb4f66be 658
e0b2e597
EL		 659 req->lun = lun;
660 req->target = id;
5a25ba16
JG		 661
662 /* cdb */
663 memcpy(req->cdb, cmd->cmnd, STEX_CDB_LENGTH);
664
7cfe99a5
ELP		 665 if (cmd->sc_data_direction == DMA_FROM_DEVICE)
666 req->data_dir = MSG_DATA_DIR_IN;
667 else if (cmd->sc_data_direction == DMA_TO_DEVICE)
668 req->data_dir = MSG_DATA_DIR_OUT;
669 else
670 req->data_dir = MSG_DATA_DIR_ND;
671
5a25ba16
JG		 672 hba->ccb[tag].cmd = cmd;
673 hba->ccb[tag].sense_bufflen = SCSI_SENSE_BUFFERSIZE;
674 hba->ccb[tag].sense_buffer = cmd->sense_buffer;
5a25ba16 675
0f3f6ee6
EL		 676 if (!hba->map_sg(hba, req, &hba->ccb[tag])) {
677 hba->ccb[tag].sg_count = 0;
678 memset(&req->variable[0], 0, 8);
679 }
5a25ba16 680
0f3f6ee6 681 hba->send(hba, req, tag);
5a25ba16
JG		 682 return 0;
683}
684
5a25ba16
JG		 685static void stex_scsi_done(struct st_ccb *ccb)
686{
687 struct scsi_cmnd *cmd = ccb->cmd;
688 int result;
689
f1498161 690 if (ccb->srb_status == SRB_STATUS_SUCCESS || ccb->srb_status == 0) {
5a25ba16
JG		 691 result = ccb->scsi_status;
692 switch (ccb->scsi_status) {
693 case SAM_STAT_GOOD:
694 result |= DID_OK << 16 | COMMAND_COMPLETE << 8;
695 break;
696 case SAM_STAT_CHECK_CONDITION:
697 result |= DRIVER_SENSE << 24;
698 break;
699 case SAM_STAT_BUSY:
700 result |= DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
701 break;
702 default:
703 result |= DID_ERROR << 16 | COMMAND_COMPLETE << 8;
704 break;
705 }
706 }
707 else if (ccb->srb_status & SRB_SEE_SENSE)
708 result = DRIVER_SENSE << 24 | SAM_STAT_CHECK_CONDITION;
709 else switch (ccb->srb_status) {
710 case SRB_STATUS_SELECTION_TIMEOUT:
711 result = DID_NO_CONNECT << 16 | COMMAND_COMPLETE << 8;
712 break;
713 case SRB_STATUS_BUSY:
714 result = DID_BUS_BUSY << 16 | COMMAND_COMPLETE << 8;
715 break;
716 case SRB_STATUS_INVALID_REQUEST:
717 case SRB_STATUS_ERROR:
718 default:
719 result = DID_ERROR << 16 | COMMAND_COMPLETE << 8;
720 break;
721 }
722
723 cmd->result = result;
724 cmd->scsi_done(cmd);
725}
726
727static void stex_copy_data(struct st_ccb *ccb,
728 struct status_msg *resp, unsigned int variable)
729{
5a25ba16
JG		 730 if (resp->scsi_status != SAM_STAT_GOOD) {
731 if (ccb->sense_buffer != NULL)
732 memcpy(ccb->sense_buffer, resp->variable,
733 min(variable, ccb->sense_bufflen));
734 return;
735 }
736
737 if (ccb->cmd == NULL)
738 return;
f1498161 739 scsi_sg_copy_from_buffer(ccb->cmd, resp->variable, variable);
fb4f66be
EL		 740}
741
f1498161 742static void stex_check_cmd(struct st_hba *hba,
fb4f66be
EL		 743 struct st_ccb *ccb, struct status_msg *resp)
744{
fb4f66be 745 if (ccb->cmd->cmnd[0] == MGT_CMD &&
f1498161 746 resp->scsi_status != SAM_STAT_CHECK_CONDITION)
968a5763
EL		 747 scsi_set_resid(ccb->cmd, scsi_bufflen(ccb->cmd) -
748 le32_to_cpu(*(__le32 *)&resp->variable[0]));
5a25ba16
JG		 749}
750
751static void stex_mu_intr(struct st_hba *hba, u32 doorbell)
752{
753 void __iomem *base = hba->mmio_base;
754 struct status_msg *resp;
755 struct st_ccb *ccb;
756 unsigned int size;
757 u16 tag;
758
f1498161 759 if (unlikely(!(doorbell & MU_OUTBOUND_DOORBELL_STATUSHEADCHANGED)))
5a25ba16
JG		 760 return;
761
762 /* status payloads */
763 hba->status_head = readl(base + OMR1);
591a3a5f 764 if (unlikely(hba->status_head > hba->sts_count)) {
5a25ba16
JG		 765 printk(KERN_WARNING DRV_NAME "(%s): invalid status head\n",
766 pci_name(hba->pdev));
767 return;
768 }
769
fb4f66be
EL		 770 /*
771 * it's not a valid status payload if:
772 * 1. there are no pending requests(e.g. during init stage)
773 * 2. there are some pending requests, but the controller is in
774 * reset status, and its type is not st_yosemite
775 * firmware of st_yosemite in reset status will return pending requests
776 * to driver, so we allow it to pass
777 */
778 if (unlikely(hba->out_req_cnt <= 0 ||
779 (hba->mu_status == MU_STATE_RESETTING &&
780 hba->cardtype != st_yosemite))) {
5a25ba16
JG		 781 hba->status_tail = hba->status_head;
782 goto update_status;
783 }
784
785 while (hba->status_tail != hba->status_head) {
786 resp = stex_get_status(hba);
787 tag = le16_to_cpu(resp->tag);
cf355883 788 if (unlikely(tag >= hba->host->can_queue)) {
5a25ba16
JG		 789 printk(KERN_WARNING DRV_NAME
790 "(%s): invalid tag\n", pci_name(hba->pdev));
791 continue;
792 }
5a25ba16 793
f1498161 794 hba->out_req_cnt--;
5a25ba16 795 ccb = &hba->ccb[tag];
f1498161 796 if (unlikely(hba->wait_ccb == ccb))
5a25ba16
JG		 797 hba->wait_ccb = NULL;
798 if (unlikely(ccb->req == NULL)) {
799 printk(KERN_WARNING DRV_NAME
800 "(%s): lagging req\n", pci_name(hba->pdev));
5a25ba16
JG		 801 continue;
802 }
803
804 size = resp->payload_sz * sizeof(u32); /* payload size */
805 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
806 size > sizeof(*resp))) {
807 printk(KERN_WARNING DRV_NAME "(%s): bad status size\n",
808 pci_name(hba->pdev));
809 } else {
810 size -= sizeof(*resp) - STATUS_VAR_LEN; /* copy size */
811 if (size)
812 stex_copy_data(ccb, resp, size);
813 }
814
dd48ebf7 815 ccb->req = NULL;
5a25ba16
JG		 816 ccb->srb_status = resp->srb_status;
817 ccb->scsi_status = resp->scsi_status;
818
cf355883 819 if (likely(ccb->cmd != NULL)) {
fb4f66be 820 if (hba->cardtype == st_yosemite)
f1498161 821 stex_check_cmd(hba, ccb, resp);
fb4f66be 822
cf355883
EL		 823 if (unlikely(ccb->cmd->cmnd[0] == PASSTHRU_CMD &&
824 ccb->cmd->cmnd[1] == PASSTHRU_GET_ADAPTER))
825 stex_controller_info(hba, ccb);
fb4f66be 826
d5587d5d 827 scsi_dma_unmap(ccb->cmd);
cf355883 828 stex_scsi_done(ccb);
f1498161 829 } else
5a25ba16 830 ccb->req_type = 0;
5a25ba16
JG		 831 }
832
833update_status:
834 writel(hba->status_head, base + IMR1);
835 readl(base + IMR1); /* flush */
836}
837
7d12e780 838static irqreturn_t stex_intr(int irq, void *__hba)
5a25ba16
JG		 839{
840 struct st_hba *hba = __hba;
841 void __iomem *base = hba->mmio_base;
842 u32 data;
843 unsigned long flags;
844 int handled = 0;
845
846 spin_lock_irqsave(hba->host->host_lock, flags);
847
848 data = readl(base + ODBL);
849
850 if (data && data != 0xffffffff) {
851 /* clear the interrupt */
852 writel(data, base + ODBL);
853 readl(base + ODBL); /* flush */
854 stex_mu_intr(hba, data);
855 handled = 1;
856 }
857
858 spin_unlock_irqrestore(hba->host->host_lock, flags);
859
860 return IRQ_RETVAL(handled);
861}
862
0f3f6ee6
EL		 863static void stex_ss_mu_intr(struct st_hba *hba)
864{
865 struct status_msg *resp;
866 struct st_ccb *ccb;
867 __le32 *scratch;
868 unsigned int size;
869 int count = 0;
870 u32 value;
871 u16 tag;
872
873 if (unlikely(hba->out_req_cnt <= 0 ||
874 hba->mu_status == MU_STATE_RESETTING))
875 return;
876
877 while (count < hba->sts_count) {
878 scratch = hba->scratch + hba->status_tail;
879 value = le32_to_cpu(*scratch);
880 if (unlikely(!(value & SS_STS_NORMAL)))
881 return;
882
883 resp = hba->status_buffer + hba->status_tail;
884 *scratch = 0;
885 ++count;
886 ++hba->status_tail;
887 hba->status_tail %= hba->sts_count+1;
888
889 tag = (u16)value;
890 if (unlikely(tag >= hba->host->can_queue)) {
891 printk(KERN_WARNING DRV_NAME
69cb4875 892 "(%s): invalid tag\n", pci_name(hba->pdev));
0f3f6ee6
EL		 893 continue;
894 }
895
896 hba->out_req_cnt--;
897 ccb = &hba->ccb[tag];
898 if (unlikely(hba->wait_ccb == ccb))
899 hba->wait_ccb = NULL;
900 if (unlikely(ccb->req == NULL)) {
901 printk(KERN_WARNING DRV_NAME
902 "(%s): lagging req\n", pci_name(hba->pdev));
903 continue;
904 }
905
906 ccb->req = NULL;
907 if (likely(value & SS_STS_DONE)) { /* normal case */
908 ccb->srb_status = SRB_STATUS_SUCCESS;
909 ccb->scsi_status = SAM_STAT_GOOD;
910 } else {
911 ccb->srb_status = resp->srb_status;
912 ccb->scsi_status = resp->scsi_status;
913 size = resp->payload_sz * sizeof(u32);
914 if (unlikely(size < sizeof(*resp) - STATUS_VAR_LEN ||
915 size > sizeof(*resp))) {
916 printk(KERN_WARNING DRV_NAME
917 "(%s): bad status size\n",
918 pci_name(hba->pdev));
919 } else {
920 size -= sizeof(*resp) - STATUS_VAR_LEN;
921 if (size)
922 stex_copy_data(ccb, resp, size);
923 }
924 if (likely(ccb->cmd != NULL))
925 stex_check_cmd(hba, ccb, resp);
926 }
927
928 if (likely(ccb->cmd != NULL)) {
929 scsi_dma_unmap(ccb->cmd);
930 stex_scsi_done(ccb);
931 } else
932 ccb->req_type = 0;
933 }
934}
935
936static irqreturn_t stex_ss_intr(int irq, void *__hba)
937{
938 struct st_hba *hba = __hba;
939 void __iomem *base = hba->mmio_base;
940 u32 data;
941 unsigned long flags;
942 int handled = 0;
943
944 spin_lock_irqsave(hba->host->host_lock, flags);
945
946 data = readl(base + YI2H_INT);
947 if (data && data != 0xffffffff) {
948 /* clear the interrupt */
949 writel(data, base + YI2H_INT_C);
950 stex_ss_mu_intr(hba);
951 handled = 1;
952 }
953
954 spin_unlock_irqrestore(hba->host->host_lock, flags);
955
956 return IRQ_RETVAL(handled);
957}
958
959static int stex_common_handshake(struct st_hba *hba)
5a25ba16
JG		 960{
961 void __iomem *base = hba->mmio_base;
962 struct handshake_frame *h;
963 dma_addr_t status_phys;
529e7a62 964 u32 data;
76fbf96f 965 unsigned long before;
5a25ba16
JG		 966
967 if (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
968 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
969 readl(base + IDBL);
76fbf96f
EL		 970 before = jiffies;
971 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
972 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
973 printk(KERN_ERR DRV_NAME
974 "(%s): no handshake signature\n",
975 pci_name(hba->pdev));
976 return -1;
977 }
5a25ba16
JG		 978 rmb();
979 msleep(1);
980 }
5a25ba16
JG		 981 }
982
983 udelay(10);
984
529e7a62
EL		 985 data = readl(base + OMR1);
986 if ((data & 0xffff0000) == MU_HANDSHAKE_SIGNATURE_HALF) {
987 data &= 0x0000ffff;
f1498161 988 if (hba->host->can_queue > data) {
529e7a62 989 hba->host->can_queue = data;
f1498161
EL		 990 hba->host->cmd_per_lun = data;
991 }
529e7a62
EL		 992 }
993
f1498161
EL		 994 h = (struct handshake_frame *)hba->status_buffer;
995 h->rb_phy = cpu_to_le64(hba->dma_handle);
591a3a5f
EL		 996 h->req_sz = cpu_to_le16(hba->rq_size);
997 h->req_cnt = cpu_to_le16(hba->rq_count+1);
5a25ba16 998 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
591a3a5f 999 h->status_cnt = cpu_to_le16(hba->sts_count+1);
5a25ba16
JG		 1000 stex_gettime(&h->hosttime);
1001 h->partner_type = HMU_PARTNER_TYPE;
591a3a5f
EL		 1002 if (hba->extra_offset) {
1003 h->extra_offset = cpu_to_le32(hba->extra_offset);
94e9108b
EL		 1004 h->extra_size = cpu_to_le32(ST_ADDITIONAL_MEM);
1005 } else
1006 h->extra_offset = h->extra_size = 0;
5a25ba16 1007
591a3a5f 1008 status_phys = hba->dma_handle + (hba->rq_count+1) * hba->rq_size;
5a25ba16
JG		 1009 writel(status_phys, base + IMR0);
1010 readl(base + IMR0);
1011 writel((status_phys >> 16) >> 16, base + IMR1);
1012 readl(base + IMR1);
1013
1014 writel((status_phys >> 16) >> 16, base + OMR0); /* old fw compatible */
1015 readl(base + OMR0);
1016 writel(MU_INBOUND_DOORBELL_HANDSHAKE, base + IDBL);
1017 readl(base + IDBL); /* flush */
1018
1019 udelay(10);
76fbf96f
EL		 1020 before = jiffies;
1021 while (readl(base + OMR0) != MU_HANDSHAKE_SIGNATURE) {
1022 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1023 printk(KERN_ERR DRV_NAME
1024 "(%s): no signature after handshake frame\n",
1025 pci_name(hba->pdev));
1026 return -1;
1027 }
5a25ba16
JG		 1028 rmb();
1029 msleep(1);
1030 }
1031
5a25ba16
JG		 1032 writel(0, base + IMR0);
1033 readl(base + IMR0);
1034 writel(0, base + OMR0);
1035 readl(base + OMR0);
1036 writel(0, base + IMR1);
1037 readl(base + IMR1);
1038 writel(0, base + OMR1);
1039 readl(base + OMR1); /* flush */
5a25ba16
JG		 1040 return 0;
1041}
1042
0f3f6ee6
EL		 1043static int stex_ss_handshake(struct st_hba *hba)
1044{
1045 void __iomem *base = hba->mmio_base;
1046 struct st_msg_header *msg_h;
1047 struct handshake_frame *h;
69cb4875 1048 __le32 *scratch;
0f3f6ee6
EL		 1049 u32 data;
1050 unsigned long before;
1051 int ret = 0;
1052
69cb4875
EL		 1053 before = jiffies;
1054 while ((readl(base + YIOA_STATUS) & SS_MU_OPERATIONAL) == 0) {
1055 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1056 printk(KERN_ERR DRV_NAME
1057 "(%s): firmware not operational\n",
1058 pci_name(hba->pdev));
1059 return -1;
1060 }
1061 msleep(1);
1062 }
1063
1064 msg_h = (struct st_msg_header *)hba->dma_mem;
0f3f6ee6
EL		 1065 msg_h->handle = cpu_to_le64(hba->dma_handle);
1066 msg_h->flag = SS_HEAD_HANDSHAKE;
1067
69cb4875 1068 h = (struct handshake_frame *)(msg_h + 1);
0f3f6ee6
EL		 1069 h->rb_phy = cpu_to_le64(hba->dma_handle);
1070 h->req_sz = cpu_to_le16(hba->rq_size);
1071 h->req_cnt = cpu_to_le16(hba->rq_count+1);
1072 h->status_sz = cpu_to_le16(sizeof(struct status_msg));
1073 h->status_cnt = cpu_to_le16(hba->sts_count+1);
1074 stex_gettime(&h->hosttime);
1075 h->partner_type = HMU_PARTNER_TYPE;
1076 h->extra_offset = h->extra_size = 0;
1077 h->scratch_size = cpu_to_le32((hba->sts_count+1)*sizeof(u32));
1078
1079 data = readl(base + YINT_EN);
1080 data &= ~4;
1081 writel(data, base + YINT_EN);
1082 writel((hba->dma_handle >> 16) >> 16, base + YH2I_REQ_HI);
1083 writel(hba->dma_handle, base + YH2I_REQ);
1084
1085 scratch = hba->scratch;
1086 before = jiffies;
1087 while (!(le32_to_cpu(*scratch) & SS_STS_HANDSHAKE)) {
1088 if (time_after(jiffies, before + MU_MAX_DELAY * HZ)) {
1089 printk(KERN_ERR DRV_NAME
1090 "(%s): no signature after handshake frame\n",
1091 pci_name(hba->pdev));
1092 ret = -1;
1093 break;
1094 }
1095 rmb();
1096 msleep(1);
1097 }
1098
1099 *scratch = 0;
1100 msg_h->flag = 0;
1101 return ret;
1102}
1103
1104static int stex_handshake(struct st_hba *hba)
1105{
1106 int err;
1107 unsigned long flags;
1108
1109 err = (hba->cardtype == st_yel) ?
1110 stex_ss_handshake(hba) : stex_common_handshake(hba);
1111 if (err == 0) {
1112 spin_lock_irqsave(hba->host->host_lock, flags);
1113 hba->req_head = 0;
1114 hba->req_tail = 0;
1115 hba->status_head = 0;
1116 hba->status_tail = 0;
1117 hba->out_req_cnt = 0;
1118 hba->mu_status = MU_STATE_STARTED;
1119 spin_unlock_irqrestore(hba->host->host_lock, flags);
1120 }
1121 return err;
1122}
1123
5a25ba16
JG		 1124static int stex_abort(struct scsi_cmnd *cmd)
1125{
1126 struct Scsi_Host *host = cmd->device->host;
1127 struct st_hba *hba = (struct st_hba *)host->hostdata;
cf355883 1128 u16 tag = cmd->request->tag;
5a25ba16
JG		 1129 void __iomem *base;
1130 u32 data;
1131 int result = SUCCESS;
1132 unsigned long flags;
c25da0af
EL		 1133
1134 printk(KERN_INFO DRV_NAME
1135 "(%s): aborting command\n", pci_name(hba->pdev));
1136 scsi_print_command(cmd);
1137
5a25ba16
JG		 1138 base = hba->mmio_base;
1139 spin_lock_irqsave(host->host_lock, flags);
cf355883
EL		 1140 if (tag < host->can_queue && hba->ccb[tag].cmd == cmd)
1141 hba->wait_ccb = &hba->ccb[tag];
1142 else {
1143 for (tag = 0; tag < host->can_queue; tag++)
1144 if (hba->ccb[tag].cmd == cmd) {
1145 hba->wait_ccb = &hba->ccb[tag];
1146 break;
1147 }
1148 if (tag >= host->can_queue)
1149 goto out;
1150 }
5a25ba16 1151
0f3f6ee6
EL		 1152 if (hba->cardtype == st_yel) {
1153 data = readl(base + YI2H_INT);
1154 if (data == 0 || data == 0xffffffff)
1155 goto fail_out;
5a25ba16 1156
0f3f6ee6
EL		 1157 writel(data, base + YI2H_INT_C);
1158 stex_ss_mu_intr(hba);
1159 } else {
1160 data = readl(base + ODBL);
1161 if (data == 0 || data == 0xffffffff)
1162 goto fail_out;
5a25ba16 1163
0f3f6ee6
EL		 1164 writel(data, base + ODBL);
1165 readl(base + ODBL); /* flush */
5a25ba16 1166
0f3f6ee6
EL		 1167 stex_mu_intr(hba, data);
1168 }
5a25ba16
JG		 1169 if (hba->wait_ccb == NULL) {
1170 printk(KERN_WARNING DRV_NAME
1171 "(%s): lost interrupt\n", pci_name(hba->pdev));
1172 goto out;
1173 }
1174
1175fail_out:
d5587d5d 1176 scsi_dma_unmap(cmd);
5a25ba16
JG		 1177 hba->wait_ccb->req = NULL; /* nullify the req's future return */
1178 hba->wait_ccb = NULL;
1179 result = FAILED;
1180out:
1181 spin_unlock_irqrestore(host->host_lock, flags);
1182 return result;
1183}
1184
1185static void stex_hard_reset(struct st_hba *hba)
1186{
1187 struct pci_bus *bus;
1188 int i;
1189 u16 pci_cmd;
1190 u8 pci_bctl;
1191
1192 for (i = 0; i < 16; i++)
1193 pci_read_config_dword(hba->pdev, i * 4,
1194 &hba->pdev->saved_config_space[i]);
1195
1196 /* Reset secondary bus. Our controller(MU/ATU) is the only device on
1197 secondary bus. Consult Intel 80331/3 developer's manual for detail */
1198 bus = hba->pdev->bus;
1199 pci_read_config_byte(bus->self, PCI_BRIDGE_CONTROL, &pci_bctl);
1200 pci_bctl |= PCI_BRIDGE_CTL_BUS_RESET;
1201 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
69f4a513
EL		 1202
1203 /*
1204 * 1 ms may be enough for 8-port controllers. But 16-port controllers
1205 * require more time to finish bus reset. Use 100 ms here for safety
1206 */
1207 msleep(100);
5a25ba16
JG		 1208 pci_bctl &= ~PCI_BRIDGE_CTL_BUS_RESET;
1209 pci_write_config_byte(bus->self, PCI_BRIDGE_CONTROL, pci_bctl);
1210
76fbf96f 1211 for (i = 0; i < MU_HARD_RESET_WAIT; i++) {
5a25ba16 1212 pci_read_config_word(hba->pdev, PCI_COMMAND, &pci_cmd);
47c4f997 1213 if (pci_cmd != 0xffff && (pci_cmd & PCI_COMMAND_MASTER))
5a25ba16
JG		 1214 break;
1215 msleep(1);
1216 }
1217
1218 ssleep(5);
1219 for (i = 0; i < 16; i++)
1220 pci_write_config_dword(hba->pdev, i * 4,
1221 hba->pdev->saved_config_space[i]);
1222}
1223
69cb4875
EL		 1224static void stex_ss_reset(struct st_hba *hba)
1225{
1226 writel(SS_H2I_INT_RESET, hba->mmio_base + YH2I_INT);
1227 readl(hba->mmio_base + YH2I_INT);
1228 ssleep(5);
1229}
1230
5a25ba16
JG		 1231static int stex_reset(struct scsi_cmnd *cmd)
1232{
1233 struct st_hba *hba;
f1498161
EL		 1234 void __iomem *base;
1235 unsigned long flags, before;
7cfe99a5 1236
5a25ba16
JG		 1237 hba = (struct st_hba *) &cmd->device->host->hostdata[0];
1238
c25da0af
EL		 1239 printk(KERN_INFO DRV_NAME
1240 "(%s): resetting host\n", pci_name(hba->pdev));
1241 scsi_print_command(cmd);
1242
5a25ba16
JG		 1243 hba->mu_status = MU_STATE_RESETTING;
1244
1245 if (hba->cardtype == st_shasta)
1246 stex_hard_reset(hba);
69cb4875
EL		 1247 else if (hba->cardtype == st_yel)
1248 stex_ss_reset(hba);
5a25ba16 1249
fb4f66be
EL		 1250 if (hba->cardtype != st_yosemite) {
1251 if (stex_handshake(hba)) {
1252 printk(KERN_WARNING DRV_NAME
1253 "(%s): resetting: handshake failed\n",
1254 pci_name(hba->pdev));
1255 return FAILED;
1256 }
fb4f66be 1257 return SUCCESS;
5a25ba16 1258 }
5a25ba16 1259
fb4f66be
EL		 1260 /* st_yosemite */
1261 writel(MU_INBOUND_DOORBELL_RESET, hba->mmio_base + IDBL);
1262 readl(hba->mmio_base + IDBL); /* flush */
1263 before = jiffies;
1264 while (hba->out_req_cnt > 0) {
1265 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1266 printk(KERN_WARNING DRV_NAME
1267 "(%s): reset timeout\n", pci_name(hba->pdev));
1268 return FAILED;
1269 }
1270 msleep(1);
1271 }
1272
f1498161
EL		 1273 base = hba->mmio_base;
1274 writel(0, base + IMR0);
1275 readl(base + IMR0);
1276 writel(0, base + OMR0);
1277 readl(base + OMR0);
1278 writel(0, base + IMR1);
1279 readl(base + IMR1);
1280 writel(0, base + OMR1);
1281 readl(base + OMR1); /* flush */
1282 spin_lock_irqsave(hba->host->host_lock, flags);
1283 hba->req_head = 0;
1284 hba->req_tail = 0;
1285 hba->status_head = 0;
1286 hba->status_tail = 0;
1287 hba->out_req_cnt = 0;
fb4f66be 1288 hba->mu_status = MU_STATE_STARTED;
f1498161 1289 spin_unlock_irqrestore(hba->host->host_lock, flags);
5a25ba16
JG		 1290 return SUCCESS;
1291}
1292
1293static int stex_biosparam(struct scsi_device *sdev,
1294 struct block_device *bdev, sector_t capacity, int geom[])
1295{
b4b8bed1 1296 int heads = 255, sectors = 63;
5a25ba16
JG		 1297
1298 if (capacity < 0x200000) {
1299 heads = 64;
1300 sectors = 32;
1301 }
1302
b4b8bed1 1303 sector_div(capacity, heads * sectors);
5a25ba16
JG		 1304
1305 geom[0] = heads;
1306 geom[1] = sectors;
b4b8bed1 1307 geom[2] = capacity;
5a25ba16
JG		 1308
1309 return 0;
1310}
1311
1312static struct scsi_host_template driver_template = {
1313 .module = THIS_MODULE,
1314 .name = DRV_NAME,
1315 .proc_name = DRV_NAME,
1316 .bios_param = stex_biosparam,
1317 .queuecommand = stex_queuecommand,
cf355883 1318 .slave_alloc = stex_slave_alloc,
5a25ba16
JG		 1319 .slave_configure = stex_slave_config,
1320 .slave_destroy = stex_slave_destroy,
1321 .eh_abort_handler = stex_abort,
1322 .eh_host_reset_handler = stex_reset,
5a25ba16 1323 .this_id = -1,
591a3a5f
EL		 1324};
1325
1326static struct pci_device_id stex_pci_tbl[] = {
1327 /* st_shasta */
1328 { 0x105a, 0x8350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1329 st_shasta }, /* SuperTrak EX8350/8300/16350/16300 */
1330 { 0x105a, 0xc350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1331 st_shasta }, /* SuperTrak EX12350 */
1332 { 0x105a, 0x4302, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1333 st_shasta }, /* SuperTrak EX4350 */
1334 { 0x105a, 0xe350, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1335 st_shasta }, /* SuperTrak EX24350 */
1336
1337 /* st_vsc */
1338 { 0x105a, 0x7250, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_vsc },
1339
1340 /* st_yosemite */
0f3f6ee6 1341 { 0x105a, 0x8650, 0x105a, PCI_ANY_ID, 0, 0, st_yosemite },
591a3a5f
EL		 1342
1343 /* st_seq */
1344 { 0x105a, 0x3360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_seq },
0f3f6ee6
EL		 1345
1346 /* st_yel */
1347 { 0x105a, 0x8650, 0x1033, PCI_ANY_ID, 0, 0, st_yel },
1348 { 0x105a, 0x8760, PCI_ANY_ID, PCI_ANY_ID, 0, 0, st_yel },
591a3a5f
EL		 1349 { } /* terminate list */
1350};
1351
1352static struct st_card_info stex_card_info[] = {
1353 /* st_shasta */
1354 {
1355 .max_id = 17,
1356 .max_lun = 8,
1357 .max_channel = 0,
1358 .rq_count = 32,
1359 .rq_size = 1048,
1360 .sts_count = 32,
0f3f6ee6
EL		 1361 .alloc_rq = stex_alloc_req,
1362 .map_sg = stex_map_sg,
1363 .send = stex_send_cmd,
591a3a5f
EL		 1364 },
1365
1366 /* st_vsc */
1367 {
1368 .max_id = 129,
1369 .max_lun = 1,
1370 .max_channel = 0,
1371 .rq_count = 32,
1372 .rq_size = 1048,
1373 .sts_count = 32,
0f3f6ee6
EL		 1374 .alloc_rq = stex_alloc_req,
1375 .map_sg = stex_map_sg,
1376 .send = stex_send_cmd,
591a3a5f
EL		 1377 },
1378
1379 /* st_yosemite */
1380 {
1381 .max_id = 2,
1382 .max_lun = 256,
1383 .max_channel = 0,
1384 .rq_count = 256,
1385 .rq_size = 1048,
1386 .sts_count = 256,
0f3f6ee6
EL		 1387 .alloc_rq = stex_alloc_req,
1388 .map_sg = stex_map_sg,
1389 .send = stex_send_cmd,
591a3a5f
EL		 1390 },
1391
1392 /* st_seq */
1393 {
1394 .max_id = 129,
1395 .max_lun = 1,
1396 .max_channel = 0,
1397 .rq_count = 32,
1398 .rq_size = 1048,
1399 .sts_count = 32,
0f3f6ee6
EL		 1400 .alloc_rq = stex_alloc_req,
1401 .map_sg = stex_map_sg,
1402 .send = stex_send_cmd,
1403 },
1404
1405 /* st_yel */
1406 {
1407 .max_id = 129,
1408 .max_lun = 256,
1409 .max_channel = 3,
1410 .rq_count = 801,
1411 .rq_size = 512,
1412 .sts_count = 801,
1413 .alloc_rq = stex_ss_alloc_req,
1414 .map_sg = stex_ss_map_sg,
1415 .send = stex_ss_send_cmd,
591a3a5f 1416 },
5a25ba16
JG		 1417};
1418
1419static int stex_set_dma_mask(struct pci_dev * pdev)
1420{
1421 int ret;
7cfe99a5 1422
6a35528a
YH		 1423 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))
1424 && !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)))
5a25ba16 1425 return 0;
284901a9 1426 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5a25ba16 1427 if (!ret)
284901a9 1428 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5a25ba16
JG		 1429 return ret;
1430}
1431
99946f81
EL		 1432static int stex_request_irq(struct st_hba *hba)
1433{
1434 struct pci_dev *pdev = hba->pdev;
1435 int status;
1436
1437 if (msi) {
1438 status = pci_enable_msi(pdev);
1439 if (status != 0)
1440 printk(KERN_ERR DRV_NAME
1441 "(%s): error %d setting up MSI\n",
1442 pci_name(pdev), status);
1443 else
1444 hba->msi_enabled = 1;
1445 } else
1446 hba->msi_enabled = 0;
1447
0f3f6ee6
EL		 1448 status = request_irq(pdev->irq, hba->cardtype == st_yel ?
1449 stex_ss_intr : stex_intr, IRQF_SHARED, DRV_NAME, hba);
99946f81
EL		 1450
1451 if (status != 0) {
1452 if (hba->msi_enabled)
1453 pci_disable_msi(pdev);
1454 }
1455 return status;
1456}
1457
1458static void stex_free_irq(struct st_hba *hba)
1459{
1460 struct pci_dev *pdev = hba->pdev;
1461
1462 free_irq(pdev->irq, hba);
1463 if (hba->msi_enabled)
1464 pci_disable_msi(pdev);
1465}
1466
5a25ba16
JG		 1467static int __devinit
1468stex_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1469{
1470 struct st_hba *hba;
1471 struct Scsi_Host *host;
591a3a5f 1472 const struct st_card_info *ci = NULL;
0f3f6ee6 1473 u32 sts_offset, cp_offset, scratch_offset;
5a25ba16
JG		 1474 int err;
1475
1476 err = pci_enable_device(pdev);
1477 if (err)
1478 return err;
1479
1480 pci_set_master(pdev);
1481
1482 host = scsi_host_alloc(&driver_template, sizeof(struct st_hba));
1483
1484 if (!host) {
1485 printk(KERN_ERR DRV_NAME "(%s): scsi_host_alloc failed\n",
1486 pci_name(pdev));
1487 err = -ENOMEM;
1488 goto out_disable;
1489 }
1490
1491 hba = (struct st_hba *)host->hostdata;
1492 memset(hba, 0, sizeof(struct st_hba));
1493
1494 err = pci_request_regions(pdev, DRV_NAME);
1495 if (err < 0) {
1496 printk(KERN_ERR DRV_NAME "(%s): request regions failed\n",
1497 pci_name(pdev));
1498 goto out_scsi_host_put;
1499 }
1500
25729a7f 1501 hba->mmio_base = pci_ioremap_bar(pdev, 0);
5a25ba16
JG		 1502 if ( !hba->mmio_base) {
1503 printk(KERN_ERR DRV_NAME "(%s): memory map failed\n",
1504 pci_name(pdev));
1505 err = -ENOMEM;
1506 goto out_release_regions;
1507 }
1508
1509 err = stex_set_dma_mask(pdev);
1510 if (err) {
1511 printk(KERN_ERR DRV_NAME "(%s): set dma mask failed\n",
1512 pci_name(pdev));
1513 goto out_iounmap;
1514 }
1515
94e9108b 1516 hba->cardtype = (unsigned int) id->driver_data;
591a3a5f 1517 ci = &stex_card_info[hba->cardtype];
0f3f6ee6
EL		 1518 sts_offset = scratch_offset = (ci->rq_count+1) * ci->rq_size;
1519 if (hba->cardtype == st_yel)
1520 sts_offset += (ci->sts_count+1) * sizeof(u32);
591a3a5f
EL		 1521 cp_offset = sts_offset + (ci->sts_count+1) * sizeof(struct status_msg);
1522 hba->dma_size = cp_offset + sizeof(struct st_frame);
1523 if (hba->cardtype == st_seq ||
1524 (hba->cardtype == st_vsc && (pdev->subsystem_device & 1))) {
1525 hba->extra_offset = hba->dma_size;
1526 hba->dma_size += ST_ADDITIONAL_MEM;
1527 }
5a25ba16 1528 hba->dma_mem = dma_alloc_coherent(&pdev->dev,
94e9108b 1529 hba->dma_size, &hba->dma_handle, GFP_KERNEL);
5a25ba16
JG		 1530 if (!hba->dma_mem) {
1531 err = -ENOMEM;
1532 printk(KERN_ERR DRV_NAME "(%s): dma mem alloc failed\n",
1533 pci_name(pdev));
1534 goto out_iounmap;
1535 }
1536
591a3a5f
EL		 1537 hba->ccb = kcalloc(ci->rq_count, sizeof(struct st_ccb), GFP_KERNEL);
1538 if (!hba->ccb) {
1539 err = -ENOMEM;
1540 printk(KERN_ERR DRV_NAME "(%s): ccb alloc failed\n",
1541 pci_name(pdev));
1542 goto out_pci_free;
1543 }
1544
0f3f6ee6
EL		 1545 if (hba->cardtype == st_yel)
1546 hba->scratch = (__le32 *)(hba->dma_mem + scratch_offset);
591a3a5f
EL		 1547 hba->status_buffer = (struct status_msg *)(hba->dma_mem + sts_offset);
1548 hba->copy_buffer = hba->dma_mem + cp_offset;
1549 hba->rq_count = ci->rq_count;
1550 hba->rq_size = ci->rq_size;
1551 hba->sts_count = ci->sts_count;
0f3f6ee6
EL		 1552 hba->alloc_rq = ci->alloc_rq;
1553 hba->map_sg = ci->map_sg;
1554 hba->send = ci->send;
5a25ba16
JG		 1555 hba->mu_status = MU_STATE_STARTING;
1556
0f3f6ee6
EL		 1557 if (hba->cardtype == st_yel)
1558 host->sg_tablesize = 38;
1559 else
1560 host->sg_tablesize = 32;
591a3a5f
EL		 1561 host->can_queue = ci->rq_count;
1562 host->cmd_per_lun = ci->rq_count;
1563 host->max_id = ci->max_id;
1564 host->max_lun = ci->max_lun;
1565 host->max_channel = ci->max_channel;
5a25ba16
JG		 1566 host->unique_id = host->host_no;
1567 host->max_cmd_len = STEX_CDB_LENGTH;
1568
1569 hba->host = host;
1570 hba->pdev = pdev;
5a25ba16 1571
99946f81 1572 err = stex_request_irq(hba);
5a25ba16
JG		 1573 if (err) {
1574 printk(KERN_ERR DRV_NAME "(%s): request irq failed\n",
1575 pci_name(pdev));
591a3a5f 1576 goto out_ccb_free;
5a25ba16
JG		 1577 }
1578
1579 err = stex_handshake(hba);
1580 if (err)
1581 goto out_free_irq;
1582
529e7a62 1583 err = scsi_init_shared_tag_map(host, host->can_queue);
deb81d80 1584 if (err) {
cf355883
EL		 1585 printk(KERN_ERR DRV_NAME "(%s): init shared queue failed\n",
1586 pci_name(pdev));
1587 goto out_free_irq;
1588 }
1589
5a25ba16
JG		 1590 pci_set_drvdata(pdev, hba);
1591
1592 err = scsi_add_host(host, &pdev->dev);
1593 if (err) {
1594 printk(KERN_ERR DRV_NAME "(%s): scsi_add_host failed\n",
1595 pci_name(pdev));
1596 goto out_free_irq;
1597 }
1598
1599 scsi_scan_host(host);
1600
1601 return 0;
1602
1603out_free_irq:
99946f81 1604 stex_free_irq(hba);
591a3a5f
EL		 1605out_ccb_free:
1606 kfree(hba->ccb);
5a25ba16 1607out_pci_free:
94e9108b 1608 dma_free_coherent(&pdev->dev, hba->dma_size,
5a25ba16
JG		 1609 hba->dma_mem, hba->dma_handle);
1610out_iounmap:
1611 iounmap(hba->mmio_base);
1612out_release_regions:
1613 pci_release_regions(pdev);
1614out_scsi_host_put:
1615 scsi_host_put(host);
1616out_disable:
1617 pci_disable_device(pdev);
1618
1619 return err;
1620}
1621
1622static void stex_hba_stop(struct st_hba *hba)
1623{
1624 struct req_msg *req;
0f3f6ee6 1625 struct st_msg_header *msg_h;
5a25ba16
JG		 1626 unsigned long flags;
1627 unsigned long before;
cf355883 1628 u16 tag = 0;
5a25ba16
JG		 1629
1630 spin_lock_irqsave(hba->host->host_lock, flags);
0f3f6ee6
EL		 1631 req = hba->alloc_rq(hba);
1632 if (hba->cardtype == st_yel) {
1633 msg_h = (struct st_msg_header *)req - 1;
1634 memset(msg_h, 0, hba->rq_size);
1635 } else
1636 memset(req, 0, hba->rq_size);
5a25ba16 1637
0f3f6ee6 1638 if (hba->cardtype == st_yosemite || hba->cardtype == st_yel) {
fb4f66be
EL		 1639 req->cdb[0] = MGT_CMD;
1640 req->cdb[1] = MGT_CMD_SIGNATURE;
1641 req->cdb[2] = CTLR_CONFIG_CMD;
1642 req->cdb[3] = CTLR_SHUTDOWN;
1643 } else {
1644 req->cdb[0] = CONTROLLER_CMD;
1645 req->cdb[1] = CTLR_POWER_STATE_CHANGE;
1646 req->cdb[2] = CTLR_POWER_SAVING;
1647 }
5a25ba16
JG		 1648
1649 hba->ccb[tag].cmd = NULL;
1650 hba->ccb[tag].sg_count = 0;
1651 hba->ccb[tag].sense_bufflen = 0;
1652 hba->ccb[tag].sense_buffer = NULL;
f1498161 1653 hba->ccb[tag].req_type = PASSTHRU_REQ_TYPE;
5a25ba16 1654
0f3f6ee6 1655 hba->send(hba, req, tag);
5a25ba16
JG		 1656 spin_unlock_irqrestore(hba->host->host_lock, flags);
1657
cf355883
EL		 1658 before = jiffies;
1659 while (hba->ccb[tag].req_type & PASSTHRU_REQ_TYPE) {
f1498161
EL		 1660 if (time_after(jiffies, before + ST_INTERNAL_TIMEOUT * HZ)) {
1661 hba->ccb[tag].req_type = 0;
cf355883 1662 return;
f1498161
EL		 1663 }
1664 msleep(1);
cf355883 1665 }
5a25ba16
JG		 1666}
1667
1668static void stex_hba_free(struct st_hba *hba)
1669{
99946f81 1670 stex_free_irq(hba);
5a25ba16
JG		 1671
1672 iounmap(hba->mmio_base);
1673
1674 pci_release_regions(hba->pdev);
1675
591a3a5f
EL		 1676 kfree(hba->ccb);
1677
94e9108b 1678 dma_free_coherent(&hba->pdev->dev, hba->dma_size,
5a25ba16
JG		 1679 hba->dma_mem, hba->dma_handle);
1680}
1681
1682static void stex_remove(struct pci_dev *pdev)
1683{
1684 struct st_hba *hba = pci_get_drvdata(pdev);
1685
1686 scsi_remove_host(hba->host);
1687
1688 pci_set_drvdata(pdev, NULL);
1689
1690 stex_hba_stop(hba);
1691
1692 stex_hba_free(hba);
1693
1694 scsi_host_put(hba->host);
1695
1696 pci_disable_device(pdev);
1697}
1698
1699static void stex_shutdown(struct pci_dev *pdev)
1700{
1701 struct st_hba *hba = pci_get_drvdata(pdev);
1702
1703 stex_hba_stop(hba);
1704}
1705
5a25ba16
JG		 1706MODULE_DEVICE_TABLE(pci, stex_pci_tbl);
1707
1708static struct pci_driver stex_pci_driver = {
1709 .name = DRV_NAME,
1710 .id_table = stex_pci_tbl,
1711 .probe = stex_probe,
1712 .remove = __devexit_p(stex_remove),
1713 .shutdown = stex_shutdown,
1714};
1715
1716static int __init stex_init(void)
1717{
1718 printk(KERN_INFO DRV_NAME
1719 ": Promise SuperTrak EX Driver version: %s\n",
1720 ST_DRIVER_VERSION);
1721
1722 return pci_register_driver(&stex_pci_driver);
1723}
1724
1725static void __exit stex_exit(void)
1726{
1727 pci_unregister_driver(&stex_pci_driver);
1728}
1729
1730module_init(stex_init);
1731module_exit(stex_exit);
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