[net-next-2.6.git] / drivers / scsi / sata_sis.c

/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware documentation available under NDA.
 *
 */

#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include "scsi.h"
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"0.5"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS_SATA1_OFS		= 0x10, /* offset from sata0->sata1 phy regs */

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);

static struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	{ PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	{ }	/* terminate list */
};


static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
};

static Scsi_Host_Template sis_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.eh_strategy_handler	= ata_scsi_error,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= ATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
	.ordered_flush		= 1,
};

static struct ata_port_operations sis_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.dev_select		= ata_std_dev_select,
	.phy_reset		= sata_phy_reset,
	.bmdma_setup            = ata_bmdma_setup,
	.bmdma_start            = ata_bmdma_start,
	.bmdma_stop		= ata_bmdma_stop,
	.bmdma_status		= ata_bmdma_status,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.eng_timeout		= ata_eng_timeout,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static struct ata_port_info sis_port_info = {
	.sht		= &sis_sht,
	.host_flags	= ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
			  ATA_FLAG_NO_LEGACY,
	.pio_mask	= 0x1f,
	.mwdma_mask	= 0x7,
	.udma_mask	= 0x7f,
	.port_ops	= &sis_ops,
};


MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
{
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);

	if (port_no)
		addr += SIS_SATA1_OFS;
	return addr;
}

static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
{
	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
	u32 val;

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return 0xffffffff;
	pci_read_config_dword(pdev, cfg_addr, &val);
	return val;
}

static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);

	if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return;
	pci_write_config_dword(pdev, cfg_addr, val);
}

static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
	if (sc_reg > SCR_CONTROL)
		return 0xffffffffU;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(ap, sc_reg);
	return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
}

static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return;

	if (ap->flags & SIS_FLAG_CFGSCR)
		sis_scr_cfg_write(ap, sc_reg, val);
	else
		outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
}

/* move to PCI layer, integrate w/ MSI stuff */
static void pci_enable_intx(struct pci_dev *pdev)
{
	u16 pci_command;

	pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
	if (pci_command & PCI_COMMAND_INTX_DISABLE) {
		pci_command &= ~PCI_COMMAND_INTX_DISABLE;
		pci_write_config_word(pdev, PCI_COMMAND, pci_command);
	}
}

static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct ata_probe_ent *probe_ent = NULL;
	int rc;
	u32 genctl;
	struct ata_port_info *ppi;
	int pci_dev_busy = 0;

	rc = pci_enable_device(pdev);
	if (rc)
		return rc;

	rc = pci_request_regions(pdev, DRV_NAME);
	if (rc) {
		pci_dev_busy = 1;
		goto err_out;
	}

	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		goto err_out_regions;

	ppi = &sis_port_info;
	probe_ent = ata_pci_init_native_mode(pdev, &ppi);
	if (!probe_ent) {
		rc = -ENOMEM;
		goto err_out_regions;
	}

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		probe_ent->host_flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		probe_ent->host_flags |= SIS_FLAG_CFGSCR;
	}

	if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
		probe_ent->port[0].scr_addr =
			pci_resource_start(pdev, SIS_SCR_PCI_BAR);
		probe_ent->port[1].scr_addr =
			pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
	}

	pci_set_master(pdev);
	pci_enable_intx(pdev);

	/* FIXME: check ata_device_add return value */
	ata_device_add(probe_ent);
	kfree(probe_ent);

	return 0;

err_out_regions:
	pci_release_regions(pdev);

err_out:
	if (!pci_dev_busy)
		pci_disable_device(pdev);
	return rc;

}

static int __init sis_init(void)
{
	return pci_module_init(&sis_pci_driver);
}

static void __exit sis_exit(void)
{
	pci_unregister_driver(&sis_pci_driver);
}

module_init(sis_init);
module_exit(sis_exit);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* sata_sis.c - Silicon Integrated Systems SATA
	3	*
	4	* Maintained by: Uwe Koziolek
	5	* Please ALWAYS copy linux-ide@vger.kernel.org
	6	* on emails.
	7	*
	8	* Copyright 2004 Uwe Koziolek
	9	*
af36d7f0 JG	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2, or (at your option)
	14	* any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; see the file COPYING. If not, write to
	23	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	24	*
	25	*
	26	* libata documentation is available via 'make {ps\|pdf}docs',
	27	* as Documentation/DocBook/libata.*
	28	*
	29	* Hardware documentation available under NDA.
1da177e4 LT	30	*
	31	*/
	32
	33	#include <linux/config.h>
	34	#include <linux/kernel.h>
	35	#include <linux/module.h>
	36	#include <linux/pci.h>
	37	#include <linux/init.h>
	38	#include <linux/blkdev.h>
	39	#include <linux/delay.h>
	40	#include <linux/interrupt.h>
	41	#include "scsi.h"
	42	#include <scsi/scsi_host.h>
	43	#include <linux/libata.h>
	44
	45	#define DRV_NAME "sata_sis"
	46	#define DRV_VERSION "0.5"
	47
	48	enum {
	49	sis_180 = 0,
	50	SIS_SCR_PCI_BAR = 5,
	51
	52	/* PCI configuration registers */
	53	SIS_GENCTL = 0x54, /* IDE General Control register */
	54	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
	55	SIS_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	56
	57	/* random bits */
	58	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	59
	60	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	61	};
	62
	63	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent);
	64	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
	65	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
	66
	67	static struct pci_device_id sis_pci_tbl[] = {
	68	{ PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	69	{ PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
	70	{ } /* terminate list */
	71	};
	72
	73
	74	static struct pci_driver sis_pci_driver = {
	75	.name = DRV_NAME,
	76	.id_table = sis_pci_tbl,
	77	.probe = sis_init_one,
	78	.remove = ata_pci_remove_one,
	79	};
	80
	81	static Scsi_Host_Template sis_sht = {
	82	.module = THIS_MODULE,
	83	.name = DRV_NAME,
	84	.ioctl = ata_scsi_ioctl,
	85	.queuecommand = ata_scsi_queuecmd,
	86	.eh_strategy_handler = ata_scsi_error,
	87	.can_queue = ATA_DEF_QUEUE,
	88	.this_id = ATA_SHT_THIS_ID,
	89	.sg_tablesize = ATA_MAX_PRD,
	90	.max_sectors = ATA_MAX_SECTORS,
	91	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	92	.emulated = ATA_SHT_EMULATED,
	93	.use_clustering = ATA_SHT_USE_CLUSTERING,
94	.proc_name = DRV_NAME,
95	.dma_boundary = ATA_DMA_BOUNDARY,
96	.slave_configure = ata_scsi_slave_config,
97	.bios_param = ata_std_bios_param,
98	.ordered_flush = 1,
99	};
100
101	static struct ata_port_operations sis_ops = {
102	.port_disable = ata_port_disable,
103	.tf_load = ata_tf_load,
104	.tf_read = ata_tf_read,
105	.check_status = ata_check_status,
106	.exec_command = ata_exec_command,
107	.dev_select = ata_std_dev_select,
108	.phy_reset = sata_phy_reset,
109	.bmdma_setup = ata_bmdma_setup,
110	.bmdma_start = ata_bmdma_start,
111	.bmdma_stop = ata_bmdma_stop,
112	.bmdma_status = ata_bmdma_status,
113	.qc_prep = ata_qc_prep,
114	.qc_issue = ata_qc_issue_prot,
115	.eng_timeout = ata_eng_timeout,
116	.irq_handler = ata_interrupt,
117	.irq_clear = ata_bmdma_irq_clear,
118	.scr_read = sis_scr_read,
119	.scr_write = sis_scr_write,
120	.port_start = ata_port_start,
121	.port_stop = ata_port_stop,
aa8f0dc6	122	.host_stop = ata_host_stop,
1da177e4 LT	123	};
	124
	125	static struct ata_port_info sis_port_info = {
	126	.sht = &sis_sht,
	127	.host_flags = ATA_FLAG_SATA \| ATA_FLAG_SATA_RESET \|
	128	ATA_FLAG_NO_LEGACY,
	129	.pio_mask = 0x1f,
	130	.mwdma_mask = 0x7,
	131	.udma_mask = 0x7f,
	132	.port_ops = &sis_ops,
	133	};
	134
	135
	136	MODULE_AUTHOR("Uwe Koziolek");
	137	MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
	138	MODULE_LICENSE("GPL");
	139	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	140	MODULE_VERSION(DRV_VERSION);
	141
	142	static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg)
	143	{
	144	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	145
	146	if (port_no)
	147	addr += SIS_SATA1_OFS;
	148	return addr;
	149	}
	150
	151	static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
	152	{
	153	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	154	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg);
	155	u32 val;
	156
	157	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
	158	return 0xffffffff;
	159	pci_read_config_dword(pdev, cfg_addr, &val);
	160	return val;
	161	}
	162
	163	static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
	164	{
	165	struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
	166	unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr);
	167
	168	if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
	169	return;
	170	pci_write_config_dword(pdev, cfg_addr, val);
	171	}
	172
	173	static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
	174	{
	175	if (sc_reg > SCR_CONTROL)
	176	return 0xffffffffU;
	177
	178	if (ap->flags & SIS_FLAG_CFGSCR)
	179	return sis_scr_cfg_read(ap, sc_reg);
	180	return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
	181	}
	182
	183	static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
	184	{
	185	if (sc_reg > SCR_CONTROL)
	186	return;
187
188	if (ap->flags & SIS_FLAG_CFGSCR)
189	sis_scr_cfg_write(ap, sc_reg, val);
190	else
191	outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
192	}
193
194	/* move to PCI layer, integrate w/ MSI stuff */
195	static void pci_enable_intx(struct pci_dev *pdev)
196	{
197	u16 pci_command;
198
199	pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
200	if (pci_command & PCI_COMMAND_INTX_DISABLE) {
201	pci_command &= ~PCI_COMMAND_INTX_DISABLE;
202	pci_write_config_word(pdev, PCI_COMMAND, pci_command);
203	}
204	}
205
206	static int sis_init_one (struct pci_dev pdev, const struct pci_device_id ent)
207	{
208	struct ata_probe_ent *probe_ent = NULL;
209	int rc;
210	u32 genctl;
211	struct ata_port_info *ppi;
212	int pci_dev_busy = 0;
213
214	rc = pci_enable_device(pdev);
215	if (rc)
216	return rc;
217
218	rc = pci_request_regions(pdev, DRV_NAME);
219	if (rc) {
220	pci_dev_busy = 1;
221	goto err_out;
222	}
223
224	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
225	if (rc)
226	goto err_out_regions;
227	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
228	if (rc)
229	goto err_out_regions;
230
231	ppi = &sis_port_info;
232	probe_ent = ata_pci_init_native_mode(pdev, &ppi);
233	if (!probe_ent) {
234	rc = -ENOMEM;
235	goto err_out_regions;
236	}
237
238	/* check and see if the SCRs are in IO space or PCI cfg space */
239	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
240	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
241	probe_ent->host_flags \|= SIS_FLAG_CFGSCR;
8a60a071	242
1da177e4 LT	243	/* if hardware thinks SCRs are in IO space, but there are
	244	* no IO resources assigned, change to PCI cfg space.
	245	*/
	246	if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
	247	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	248	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	249	genctl &= ~GENCTL_IOMAPPED_SCR;
	250	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
	251	probe_ent->host_flags \|= SIS_FLAG_CFGSCR;
	252	}
	253
	254	if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
	255	probe_ent->port[0].scr_addr =
	256	pci_resource_start(pdev, SIS_SCR_PCI_BAR);
	257	probe_ent->port[1].scr_addr =
	258	pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64;
	259	}
	260
	261	pci_set_master(pdev);
	262	pci_enable_intx(pdev);
	263
	264	/* FIXME: check ata_device_add return value */
	265	ata_device_add(probe_ent);
	266	kfree(probe_ent);
	267
	268	return 0;
	269
	270	err_out_regions:
	271	pci_release_regions(pdev);
	272
	273	err_out:
	274	if (!pci_dev_busy)
	275	pci_disable_device(pdev);
	276	return rc;
	277
	278	}
	279
	280	static int __init sis_init(void)
	281	{
	282	return pci_module_init(&sis_pci_driver);
	283	}
	284
	285	static void __exit sis_exit(void)
	286	{
	287	pci_unregister_driver(&sis_pci_driver);
	288	}
	289
	290	module_init(sis_init);
	291	module_exit(sis_exit);
	292