]>
Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
10 | * The contents of this file are subject to the Open | |
11 | * Software License version 1.1 that can be found at | |
12 | * http://www.opensource.org/licenses/osl-1.1.txt and is included herein | |
13 | * by reference. | |
14 | * | |
15 | * Alternatively, the contents of this file may be used under the terms | |
16 | * of the GNU General Public License version 2 (the "GPL") as distributed | |
17 | * in the kernel source COPYING file, in which case the provisions of | |
18 | * the GPL are applicable instead of the above. If you wish to allow | |
19 | * the use of your version of this file only under the terms of the | |
20 | * GPL and not to allow others to use your version of this file under | |
21 | * the OSL, indicate your decision by deleting the provisions above and | |
22 | * replace them with the notice and other provisions required by the GPL. | |
23 | * If you do not delete the provisions above, a recipient may use your | |
24 | * version of this file under either the OSL or the GPL. | |
25 | * | |
26 | */ | |
27 | ||
28 | #include <linux/config.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/pci.h> | |
32 | #include <linux/init.h> | |
33 | #include <linux/blkdev.h> | |
34 | #include <linux/delay.h> | |
35 | #include <linux/interrupt.h> | |
36 | #include "scsi.h" | |
37 | #include <scsi/scsi_host.h> | |
38 | #include <linux/libata.h> | |
39 | ||
40 | #define DRV_NAME "sata_sis" | |
41 | #define DRV_VERSION "0.5" | |
42 | ||
43 | enum { | |
44 | sis_180 = 0, | |
45 | SIS_SCR_PCI_BAR = 5, | |
46 | ||
47 | /* PCI configuration registers */ | |
48 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
49 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
50 | SIS_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ | |
51 | ||
52 | /* random bits */ | |
53 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
54 | ||
55 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
56 | }; | |
57 | ||
58 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
59 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
60 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
61 | ||
62 | static struct pci_device_id sis_pci_tbl[] = { | |
63 | { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, | |
64 | { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 }, | |
65 | { } /* terminate list */ | |
66 | }; | |
67 | ||
68 | ||
69 | static struct pci_driver sis_pci_driver = { | |
70 | .name = DRV_NAME, | |
71 | .id_table = sis_pci_tbl, | |
72 | .probe = sis_init_one, | |
73 | .remove = ata_pci_remove_one, | |
74 | }; | |
75 | ||
76 | static Scsi_Host_Template sis_sht = { | |
77 | .module = THIS_MODULE, | |
78 | .name = DRV_NAME, | |
79 | .ioctl = ata_scsi_ioctl, | |
80 | .queuecommand = ata_scsi_queuecmd, | |
81 | .eh_strategy_handler = ata_scsi_error, | |
82 | .can_queue = ATA_DEF_QUEUE, | |
83 | .this_id = ATA_SHT_THIS_ID, | |
84 | .sg_tablesize = ATA_MAX_PRD, | |
85 | .max_sectors = ATA_MAX_SECTORS, | |
86 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
87 | .emulated = ATA_SHT_EMULATED, | |
88 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
89 | .proc_name = DRV_NAME, | |
90 | .dma_boundary = ATA_DMA_BOUNDARY, | |
91 | .slave_configure = ata_scsi_slave_config, | |
92 | .bios_param = ata_std_bios_param, | |
93 | .ordered_flush = 1, | |
94 | }; | |
95 | ||
96 | static struct ata_port_operations sis_ops = { | |
97 | .port_disable = ata_port_disable, | |
98 | .tf_load = ata_tf_load, | |
99 | .tf_read = ata_tf_read, | |
100 | .check_status = ata_check_status, | |
101 | .exec_command = ata_exec_command, | |
102 | .dev_select = ata_std_dev_select, | |
103 | .phy_reset = sata_phy_reset, | |
104 | .bmdma_setup = ata_bmdma_setup, | |
105 | .bmdma_start = ata_bmdma_start, | |
106 | .bmdma_stop = ata_bmdma_stop, | |
107 | .bmdma_status = ata_bmdma_status, | |
108 | .qc_prep = ata_qc_prep, | |
109 | .qc_issue = ata_qc_issue_prot, | |
110 | .eng_timeout = ata_eng_timeout, | |
111 | .irq_handler = ata_interrupt, | |
112 | .irq_clear = ata_bmdma_irq_clear, | |
113 | .scr_read = sis_scr_read, | |
114 | .scr_write = sis_scr_write, | |
115 | .port_start = ata_port_start, | |
116 | .port_stop = ata_port_stop, | |
aa8f0dc6 | 117 | .host_stop = ata_host_stop, |
1da177e4 LT |
118 | }; |
119 | ||
120 | static struct ata_port_info sis_port_info = { | |
121 | .sht = &sis_sht, | |
122 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET | | |
123 | ATA_FLAG_NO_LEGACY, | |
124 | .pio_mask = 0x1f, | |
125 | .mwdma_mask = 0x7, | |
126 | .udma_mask = 0x7f, | |
127 | .port_ops = &sis_ops, | |
128 | }; | |
129 | ||
130 | ||
131 | MODULE_AUTHOR("Uwe Koziolek"); | |
132 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
133 | MODULE_LICENSE("GPL"); | |
134 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
135 | MODULE_VERSION(DRV_VERSION); | |
136 | ||
137 | static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg) | |
138 | { | |
139 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); | |
140 | ||
141 | if (port_no) | |
142 | addr += SIS_SATA1_OFS; | |
143 | return addr; | |
144 | } | |
145 | ||
146 | static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |
147 | { | |
148 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
149 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg); | |
150 | u32 val; | |
151 | ||
152 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
153 | return 0xffffffff; | |
154 | pci_read_config_dword(pdev, cfg_addr, &val); | |
155 | return val; | |
156 | } | |
157 | ||
158 | static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val) | |
159 | { | |
160 | struct pci_dev *pdev = to_pci_dev(ap->host_set->dev); | |
161 | unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr); | |
162 | ||
163 | if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
164 | return; | |
165 | pci_write_config_dword(pdev, cfg_addr, val); | |
166 | } | |
167 | ||
168 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
169 | { | |
170 | if (sc_reg > SCR_CONTROL) | |
171 | return 0xffffffffU; | |
172 | ||
173 | if (ap->flags & SIS_FLAG_CFGSCR) | |
174 | return sis_scr_cfg_read(ap, sc_reg); | |
175 | return inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
176 | } | |
177 | ||
178 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
179 | { | |
180 | if (sc_reg > SCR_CONTROL) | |
181 | return; | |
182 | ||
183 | if (ap->flags & SIS_FLAG_CFGSCR) | |
184 | sis_scr_cfg_write(ap, sc_reg, val); | |
185 | else | |
186 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); | |
187 | } | |
188 | ||
189 | /* move to PCI layer, integrate w/ MSI stuff */ | |
190 | static void pci_enable_intx(struct pci_dev *pdev) | |
191 | { | |
192 | u16 pci_command; | |
193 | ||
194 | pci_read_config_word(pdev, PCI_COMMAND, &pci_command); | |
195 | if (pci_command & PCI_COMMAND_INTX_DISABLE) { | |
196 | pci_command &= ~PCI_COMMAND_INTX_DISABLE; | |
197 | pci_write_config_word(pdev, PCI_COMMAND, pci_command); | |
198 | } | |
199 | } | |
200 | ||
201 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
202 | { | |
203 | struct ata_probe_ent *probe_ent = NULL; | |
204 | int rc; | |
205 | u32 genctl; | |
206 | struct ata_port_info *ppi; | |
207 | int pci_dev_busy = 0; | |
208 | ||
209 | rc = pci_enable_device(pdev); | |
210 | if (rc) | |
211 | return rc; | |
212 | ||
213 | rc = pci_request_regions(pdev, DRV_NAME); | |
214 | if (rc) { | |
215 | pci_dev_busy = 1; | |
216 | goto err_out; | |
217 | } | |
218 | ||
219 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
220 | if (rc) | |
221 | goto err_out_regions; | |
222 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
223 | if (rc) | |
224 | goto err_out_regions; | |
225 | ||
226 | ppi = &sis_port_info; | |
227 | probe_ent = ata_pci_init_native_mode(pdev, &ppi); | |
228 | if (!probe_ent) { | |
229 | rc = -ENOMEM; | |
230 | goto err_out_regions; | |
231 | } | |
232 | ||
233 | /* check and see if the SCRs are in IO space or PCI cfg space */ | |
234 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
235 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
236 | probe_ent->host_flags |= SIS_FLAG_CFGSCR; | |
237 | ||
238 | /* if hardware thinks SCRs are in IO space, but there are | |
239 | * no IO resources assigned, change to PCI cfg space. | |
240 | */ | |
241 | if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) && | |
242 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || | |
243 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
244 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
245 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
246 | probe_ent->host_flags |= SIS_FLAG_CFGSCR; | |
247 | } | |
248 | ||
249 | if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) { | |
250 | probe_ent->port[0].scr_addr = | |
251 | pci_resource_start(pdev, SIS_SCR_PCI_BAR); | |
252 | probe_ent->port[1].scr_addr = | |
253 | pci_resource_start(pdev, SIS_SCR_PCI_BAR) + 64; | |
254 | } | |
255 | ||
256 | pci_set_master(pdev); | |
257 | pci_enable_intx(pdev); | |
258 | ||
259 | /* FIXME: check ata_device_add return value */ | |
260 | ata_device_add(probe_ent); | |
261 | kfree(probe_ent); | |
262 | ||
263 | return 0; | |
264 | ||
265 | err_out_regions: | |
266 | pci_release_regions(pdev); | |
267 | ||
268 | err_out: | |
269 | if (!pci_dev_busy) | |
270 | pci_disable_device(pdev); | |
271 | return rc; | |
272 | ||
273 | } | |
274 | ||
275 | static int __init sis_init(void) | |
276 | { | |
277 | return pci_module_init(&sis_pci_driver); | |
278 | } | |
279 | ||
280 | static void __exit sis_exit(void) | |
281 | { | |
282 | pci_unregister_driver(&sis_pci_driver); | |
283 | } | |
284 | ||
285 | module_init(sis_init); | |
286 | module_exit(sis_exit); | |
287 |