]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/scsi/sata_sil24.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[PATCH] sata_sil: new interrupt handler
[net-next-2.6.git] / drivers / scsi / sata_sil24.c
CommitLineData
edb33667
TH		 1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
edb33667
TH		 8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/pci.h>
23#include <linux/blkdev.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
a9524a76 27#include <linux/device.h>
edb33667 28#include <scsi/scsi_host.h>
193515d5 29#include <scsi/scsi_cmnd.h>
edb33667
TH		 30#include <linux/libata.h>
31#include <asm/io.h>
32
33#define DRV_NAME "sata_sil24"
af64371a 34#define DRV_VERSION "0.24"
edb33667 35
edb33667
TH		 36/*
37 * Port request block (PRB) 32 bytes
38 */
39struct sil24_prb {
40 u16 ctrl;
41 u16 prot;
42 u32 rx_cnt;
43 u8 fis[6 * 4];
44};
45
46/*
47 * Scatter gather entry (SGE) 16 bytes
48 */
49struct sil24_sge {
50 u64 addr;
51 u32 cnt;
52 u32 flags;
53};
54
55/*
56 * Port multiplier
57 */
58struct sil24_port_multiplier {
59 u32 diag;
60 u32 sactive;
61};
62
63enum {
64 /*
65 * Global controller registers (128 bytes @ BAR0)
66 */
67 /* 32 bit regs */
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
69 HOST_CTRL = 0x40,
70 HOST_IRQ_STAT = 0x44,
71 HOST_PHY_CFG = 0x48,
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
77 /* 8 bit regs */
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
82 HOST_I2C_DATA = 0x7c,
83 HOST_I2C_XFER_CNT = 0x7e,
84 HOST_I2C_CTRL = 0x7f,
85
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
88
7dafc3fd
TH		 89 /* HOST_CTRL bits */
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95
edb33667
TH		 96 /*
97 * Port registers
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
99 */
100 PORT_REGS_SIZE = 0x2000,
101 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
edb33667
TH		 102
103 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
104 /* 32 bit regs */
83bbecc9
TH		 105 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
106 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
107 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
108 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
109 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
edb33667 110 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
83bbecc9
TH		 111 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
112 PORT_CMD_ERR = 0x1024, /* command error number */
edb33667
TH		 113 PORT_FIS_CFG = 0x1028,
114 PORT_FIFO_THRES = 0x102c,
115 /* 16 bit regs */
116 PORT_DECODE_ERR_CNT = 0x1040,
117 PORT_DECODE_ERR_THRESH = 0x1042,
118 PORT_CRC_ERR_CNT = 0x1044,
119 PORT_CRC_ERR_THRESH = 0x1046,
120 PORT_HSHK_ERR_CNT = 0x1048,
121 PORT_HSHK_ERR_THRESH = 0x104a,
122 /* 32 bit regs */
123 PORT_PHY_CFG = 0x1050,
124 PORT_SLOT_STAT = 0x1800,
125 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
126 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
127 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
128 PORT_SCONTROL = 0x1f00,
129 PORT_SSTATUS = 0x1f04,
130 PORT_SERROR = 0x1f08,
131 PORT_SACTIVE = 0x1f0c,
132
133 /* PORT_CTRL_STAT bits */
134 PORT_CS_PORT_RST = (1 << 0), /* port reset */
135 PORT_CS_DEV_RST = (1 << 1), /* device reset */
136 PORT_CS_INIT = (1 << 2), /* port initialize */
137 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
d10cb35a 138 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
e382eb1d
TH		 139 PORT_CS_RESUME = (1 << 6), /* port resume */
140 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
141 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
142 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
edb33667
TH		 143
144 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
145 /* bits[11:0] are masked */
146 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
147 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
148 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
149 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
150 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
151 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
7dafc3fd
TH		 152 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
153 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
154 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
155 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
156 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
3b9f1d0f 157 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
edb33667 158
88ce7550
TH		 159 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
160 PORT_IRQ_DEV_XCHG | PORT_IRQ_UNK_FIS,
161
edb33667
TH		 162 /* bits[27:16] are unmasked (raw) */
163 PORT_IRQ_RAW_SHIFT = 16,
164 PORT_IRQ_MASKED_MASK = 0x7ff,
165 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
166
167 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
168 PORT_IRQ_STEER_SHIFT = 30,
169 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
170
171 /* PORT_CMD_ERR constants */
172 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
173 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
174 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
175 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
176 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
177 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
178 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
179 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
180 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
181 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
182 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
183 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
184 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
185 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
186 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
187 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
188 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
189 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
190 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
64008802 191 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
edb33667 192 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
83bbecc9 193 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
edb33667 194
d10cb35a
TH		 195 /* bits of PRB control field */
196 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
197 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
198 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
199 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
200 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
201
202 /* PRB protocol field */
203 PRB_PROT_PACKET = (1 << 0),
204 PRB_PROT_TCQ = (1 << 1),
205 PRB_PROT_NCQ = (1 << 2),
206 PRB_PROT_READ = (1 << 3),
207 PRB_PROT_WRITE = (1 << 4),
208 PRB_PROT_TRANSPARENT = (1 << 5),
209
edb33667
TH		 210 /*
211 * Other constants
212 */
213 SGE_TRM = (1 << 31), /* Last SGE in chain */
d10cb35a
TH		 214 SGE_LNK = (1 << 30), /* linked list
215 Points to SGT, not SGE */
216 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
217 data address ignored */
edb33667 218
aee10a03
TH		 219 SIL24_MAX_CMDS = 31,
220
edb33667
TH		 221 /* board id */
222 BID_SIL3124 = 0,
223 BID_SIL3132 = 1,
042c21fd 224 BID_SIL3131 = 2,
edb33667 225
9466d85b
TH		 226 /* host flags */
227 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
aee10a03
TH		 228 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
229 ATA_FLAG_NCQ,
37024e8e 230 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
9466d85b 231
edb33667
TH		 232 IRQ_STAT_4PORTS = 0xf,
233};
234
69ad185f 235struct sil24_ata_block {
edb33667
TH		 236 struct sil24_prb prb;
237 struct sil24_sge sge[LIBATA_MAX_PRD];
238};
239
69ad185f
TH		 240struct sil24_atapi_block {
241 struct sil24_prb prb;
242 u8 cdb[16];
243 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
244};
245
246union sil24_cmd_block {
247 struct sil24_ata_block ata;
248 struct sil24_atapi_block atapi;
249};
250
88ce7550
TH		 251static struct sil24_cerr_info {
252 unsigned int err_mask, action;
253 const char *desc;
254} sil24_cerr_db[] = {
255 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
256 "device error" },
257 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
258 "device error via D2H FIS" },
259 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
260 "device error via SDB FIS" },
261 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
262 "error in data FIS" },
263 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
264 "failed to transmit command FIS" },
265 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
266 "protocol mismatch" },
267 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
268 "data directon mismatch" },
269 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
270 "ran out of SGEs while writing" },
271 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
272 "ran out of SGEs while reading" },
273 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
274 "invalid data directon for ATAPI CDB" },
275 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
276 "SGT no on qword boundary" },
277 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
278 "PCI target abort while fetching SGT" },
279 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
280 "PCI master abort while fetching SGT" },
281 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
282 "PCI parity error while fetching SGT" },
283 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
284 "PRB not on qword boundary" },
285 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
286 "PCI target abort while fetching PRB" },
287 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
288 "PCI master abort while fetching PRB" },
289 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI parity error while fetching PRB" },
291 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "undefined error while transferring data" },
293 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "PCI target abort while transferring data" },
295 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
296 "PCI master abort while transferring data" },
297 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI parity error while transferring data" },
299 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
300 "FIS received while sending service FIS" },
301};
302
edb33667
TH		 303/*
304 * ap->private_data
305 *
306 * The preview driver always returned 0 for status. We emulate it
307 * here from the previous interrupt.
308 */
309struct sil24_port_priv {
69ad185f 310 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
edb33667 311 dma_addr_t cmd_block_dma; /* DMA base addr for them */
6a575fa9 312 struct ata_taskfile tf; /* Cached taskfile registers */
edb33667
TH		 313};
314
315/* ap->host_set->private_data */
316struct sil24_host_priv {
4b4a5eae
AV		 317 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
318 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
edb33667
TH		 319};
320
69ad185f 321static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
edb33667 322static u8 sil24_check_status(struct ata_port *ap);
edb33667
TH		 323static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
324static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
7f726d12 325static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
07b73470 326static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
edb33667 327static void sil24_qc_prep(struct ata_queued_cmd *qc);
9a3d9eb0 328static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
edb33667 329static void sil24_irq_clear(struct ata_port *ap);
edb33667 330static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
88ce7550
TH		 331static void sil24_freeze(struct ata_port *ap);
332static void sil24_thaw(struct ata_port *ap);
333static void sil24_error_handler(struct ata_port *ap);
334static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
edb33667
TH		 335static int sil24_port_start(struct ata_port *ap);
336static void sil24_port_stop(struct ata_port *ap);
337static void sil24_host_stop(struct ata_host_set *host_set);
338static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
339
3b7d697d 340static const struct pci_device_id sil24_pci_tbl[] = {
edb33667 341 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
4b9d7e04 342 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
edb33667 343 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
042c21fd
TH		 344 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
345 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
1fcce839 346 { } /* terminate list */
edb33667
TH		 347};
348
349static struct pci_driver sil24_pci_driver = {
350 .name = DRV_NAME,
351 .id_table = sil24_pci_tbl,
352 .probe = sil24_init_one,
353 .remove = ata_pci_remove_one, /* safe? */
354};
355
193515d5 356static struct scsi_host_template sil24_sht = {
edb33667
TH		 357 .module = THIS_MODULE,
358 .name = DRV_NAME,
359 .ioctl = ata_scsi_ioctl,
360 .queuecommand = ata_scsi_queuecmd,
aee10a03
TH		 361 .change_queue_depth = ata_scsi_change_queue_depth,
362 .can_queue = SIL24_MAX_CMDS,
edb33667
TH		 363 .this_id = ATA_SHT_THIS_ID,
364 .sg_tablesize = LIBATA_MAX_PRD,
edb33667
TH		 365 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
366 .emulated = ATA_SHT_EMULATED,
367 .use_clustering = ATA_SHT_USE_CLUSTERING,
368 .proc_name = DRV_NAME,
369 .dma_boundary = ATA_DMA_BOUNDARY,
370 .slave_configure = ata_scsi_slave_config,
371 .bios_param = ata_std_bios_param,
edb33667
TH		 372};
373
057ace5e 374static const struct ata_port_operations sil24_ops = {
edb33667
TH		 375 .port_disable = ata_port_disable,
376
69ad185f
TH		 377 .dev_config = sil24_dev_config,
378
edb33667
TH		 379 .check_status = sil24_check_status,
380 .check_altstatus = sil24_check_status,
edb33667
TH		 381 .dev_select = ata_noop_dev_select,
382
7f726d12
TH		 383 .tf_read = sil24_tf_read,
384
07b73470 385 .probe_reset = sil24_probe_reset,
edb33667
TH		 386
387 .qc_prep = sil24_qc_prep,
388 .qc_issue = sil24_qc_issue,
389
edb33667
TH		 390 .irq_handler = sil24_interrupt,
391 .irq_clear = sil24_irq_clear,
392
393 .scr_read = sil24_scr_read,
394 .scr_write = sil24_scr_write,
395
88ce7550
TH		 396 .freeze = sil24_freeze,
397 .thaw = sil24_thaw,
398 .error_handler = sil24_error_handler,
399 .post_internal_cmd = sil24_post_internal_cmd,
400
edb33667
TH		 401 .port_start = sil24_port_start,
402 .port_stop = sil24_port_stop,
403 .host_stop = sil24_host_stop,
404};
405
042c21fd
TH		 406/*
407 * Use bits 30-31 of host_flags to encode available port numbers.
408 * Current maxium is 4.
409 */
410#define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
411#define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
412
edb33667
TH		 413static struct ata_port_info sil24_port_info[] = {
414 /* sil_3124 */
415 {
416 .sht = &sil24_sht,
37024e8e
TH		 417 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
418 SIL24_FLAG_PCIX_IRQ_WOC,
edb33667
TH		 419 .pio_mask = 0x1f, /* pio0-4 */
420 .mwdma_mask = 0x07, /* mwdma0-2 */
421 .udma_mask = 0x3f, /* udma0-5 */
422 .port_ops = &sil24_ops,
423 },
2e9edbf8 424 /* sil_3132 */
edb33667
TH		 425 {
426 .sht = &sil24_sht,
9466d85b 427 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
042c21fd
TH		 428 .pio_mask = 0x1f, /* pio0-4 */
429 .mwdma_mask = 0x07, /* mwdma0-2 */
430 .udma_mask = 0x3f, /* udma0-5 */
431 .port_ops = &sil24_ops,
432 },
433 /* sil_3131/sil_3531 */
434 {
435 .sht = &sil24_sht,
9466d85b 436 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
edb33667
TH		 437 .pio_mask = 0x1f, /* pio0-4 */
438 .mwdma_mask = 0x07, /* mwdma0-2 */
439 .udma_mask = 0x3f, /* udma0-5 */
440 .port_ops = &sil24_ops,
441 },
442};
443
aee10a03
TH		 444static int sil24_tag(int tag)
445{
446 if (unlikely(ata_tag_internal(tag)))
447 return 0;
448 return tag;
449}
450
69ad185f
TH		 451static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
452{
453 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
454
6e7846e9 455 if (dev->cdb_len == 16)
69ad185f
TH		 456 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
457 else
458 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
459}
460
6a575fa9
TH		 461static inline void sil24_update_tf(struct ata_port *ap)
462{
463 struct sil24_port_priv *pp = ap->private_data;
4b4a5eae
AV		 464 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
465 struct sil24_prb __iomem *prb = port;
466 u8 fis[6 * 4];
6a575fa9 467
4b4a5eae
AV		 468 memcpy_fromio(fis, prb->fis, 6 * 4);
469 ata_tf_from_fis(fis, &pp->tf);
6a575fa9
TH		 470}
471
edb33667
TH		 472static u8 sil24_check_status(struct ata_port *ap)
473{
6a575fa9
TH		 474 struct sil24_port_priv *pp = ap->private_data;
475 return pp->tf.command;
edb33667
TH		 476}
477
edb33667
TH		 478static int sil24_scr_map[] = {
479 [SCR_CONTROL] = 0,
480 [SCR_STATUS] = 1,
481 [SCR_ERROR] = 2,
482 [SCR_ACTIVE] = 3,
483};
484
485static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
486{
4b4a5eae 487 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 488 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 489 void __iomem *addr;
edb33667
TH		 490 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
491 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
492 }
493 return 0xffffffffU;
494}
495
496static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
497{
4b4a5eae 498 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
edb33667 499 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
4b4a5eae 500 void __iomem *addr;
edb33667
TH		 501 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
502 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
503 }
504}
505
7f726d12
TH		 506static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
507{
508 struct sil24_port_priv *pp = ap->private_data;
509 *tf = pp->tf;
510}
511
b5bc421c
TH		 512static int sil24_init_port(struct ata_port *ap)
513{
514 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
515 u32 tmp;
516
517 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
518 ata_wait_register(port + PORT_CTRL_STAT,
519 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
520 tmp = ata_wait_register(port + PORT_CTRL_STAT,
521 PORT_CS_RDY, 0, 10, 100);
522
523 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
524 return -EIO;
525 return 0;
526}
527
2bf2cb26 528static int sil24_softreset(struct ata_port *ap, unsigned int *class)
edb33667 529{
ca45160d
TH		 530 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
531 struct sil24_port_priv *pp = ap->private_data;
69ad185f 532 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
ca45160d 533 dma_addr_t paddr = pp->cmd_block_dma;
88ce7550 534 u32 mask, irq_stat;
643be977 535 const char *reason;
ca45160d 536
07b73470
TH		 537 DPRINTK("ENTER\n");
538
81952c54 539 if (ata_port_offline(ap)) {
10d996ad
TH		 540 DPRINTK("PHY reports no device\n");
541 *class = ATA_DEV_NONE;
542 goto out;
543 }
544
2555d6c2
TH		 545 /* put the port into known state */
546 if (sil24_init_port(ap)) {
547 reason ="port not ready";
548 goto err;
549 }
550
0eaa6058 551 /* do SRST */
bad28a37 552 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
ca45160d
TH		 553 prb->fis[1] = 0; /* no PM yet */
554
555 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
26ec634c 556 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
ca45160d 557
7dd29dd6
TH		 558 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
559 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
560 100, ATA_TMOUT_BOOT / HZ * 1000);
ca45160d 561
7dd29dd6
TH		 562 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
563 irq_stat >>= PORT_IRQ_RAW_SHIFT;
ca45160d 564
10d996ad 565 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
643be977
TH		 566 if (irq_stat & PORT_IRQ_ERROR)
567 reason = "SRST command error";
568 else
569 reason = "timeout";
570 goto err;
07b73470 571 }
10d996ad
TH		 572
573 sil24_update_tf(ap);
574 *class = ata_dev_classify(&pp->tf);
575
07b73470
TH		 576 if (*class == ATA_DEV_UNKNOWN)
577 *class = ATA_DEV_NONE;
ca45160d 578
10d996ad 579 out:
07b73470 580 DPRINTK("EXIT, class=%u\n", *class);
ca45160d 581 return 0;
643be977
TH		 582
583 err:
f15a1daf 584 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
643be977 585 return -EIO;
ca45160d
TH		 586}
587
2bf2cb26 588static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
489ff4c7 589{
ecc2e2b9
TH		 590 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
591 const char *reason;
592 int tout_msec;
593 u32 tmp;
594
595 /* sil24 does the right thing(tm) without any protection */
3c567b7d 596 sata_set_spd(ap);
ecc2e2b9
TH		 597
598 tout_msec = 100;
81952c54 599 if (ata_port_online(ap))
ecc2e2b9
TH		 600 tout_msec = 5000;
601
602 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
603 tmp = ata_wait_register(port + PORT_CTRL_STAT,
604 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
605
606 /* SStatus oscillates between zero and valid status for short
607 * duration after DEV_RST, give it time to settle.
608 */
609 msleep(100);
610
611 if (tmp & PORT_CS_DEV_RST) {
81952c54 612 if (ata_port_offline(ap))
ecc2e2b9
TH		 613 return 0;
614 reason = "link not ready";
615 goto err;
616 }
617
618 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
619 reason = "device not ready";
620 goto err;
621 }
489ff4c7 622
ecc2e2b9
TH		 623 /* sil24 doesn't report device class code after hardreset,
624 * leave *class alone.
625 */
626 return 0;
627
628 err:
f15a1daf 629 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
ecc2e2b9 630 return -EIO;
489ff4c7
TH		 631}
632
07b73470 633static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
ca45160d 634{
07b73470 635 return ata_drive_probe_reset(ap, ata_std_probeinit,
489ff4c7 636 sil24_softreset, sil24_hardreset,
07b73470 637 ata_std_postreset, classes);
edb33667
TH		 638}
639
640static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
69ad185f 641 struct sil24_sge *sge)
edb33667 642{
972c26bd
JG		 643 struct scatterlist *sg;
644 unsigned int idx = 0;
edb33667 645
972c26bd 646 ata_for_each_sg(sg, qc) {
edb33667
TH		 647 sge->addr = cpu_to_le64(sg_dma_address(sg));
648 sge->cnt = cpu_to_le32(sg_dma_len(sg));
972c26bd
JG		 649 if (ata_sg_is_last(sg, qc))
650 sge->flags = cpu_to_le32(SGE_TRM);
651 else
652 sge->flags = 0;
653
654 sge++;
655 idx++;
edb33667
TH		 656 }
657}
658
659static void sil24_qc_prep(struct ata_queued_cmd *qc)
660{
661 struct ata_port *ap = qc->ap;
662 struct sil24_port_priv *pp = ap->private_data;
aee10a03 663 union sil24_cmd_block *cb;
69ad185f
TH		 664 struct sil24_prb *prb;
665 struct sil24_sge *sge;
bad28a37 666 u16 ctrl = 0;
edb33667 667
aee10a03
TH		 668 cb = &pp->cmd_block[sil24_tag(qc->tag)];
669
edb33667
TH		 670 switch (qc->tf.protocol) {
671 case ATA_PROT_PIO:
672 case ATA_PROT_DMA:
aee10a03 673 case ATA_PROT_NCQ:
edb33667 674 case ATA_PROT_NODATA:
69ad185f
TH		 675 prb = &cb->ata.prb;
676 sge = cb->ata.sge;
edb33667 677 break;
69ad185f
TH		 678
679 case ATA_PROT_ATAPI:
680 case ATA_PROT_ATAPI_DMA:
681 case ATA_PROT_ATAPI_NODATA:
682 prb = &cb->atapi.prb;
683 sge = cb->atapi.sge;
684 memset(cb->atapi.cdb, 0, 32);
6e7846e9 685 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
69ad185f
TH		 686
687 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
688 if (qc->tf.flags & ATA_TFLAG_WRITE)
bad28a37 689 ctrl = PRB_CTRL_PACKET_WRITE;
69ad185f 690 else
bad28a37
TH		 691 ctrl = PRB_CTRL_PACKET_READ;
692 }
69ad185f
TH		 693 break;
694
edb33667 695 default:
69ad185f
TH		 696 prb = NULL; /* shut up, gcc */
697 sge = NULL;
edb33667
TH		 698 BUG();
699 }
700
bad28a37 701 prb->ctrl = cpu_to_le16(ctrl);
edb33667
TH		 702 ata_tf_to_fis(&qc->tf, prb->fis, 0);
703
704 if (qc->flags & ATA_QCFLAG_DMAMAP)
69ad185f 705 sil24_fill_sg(qc, sge);
edb33667
TH		 706}
707
9a3d9eb0 708static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
edb33667
TH		 709{
710 struct ata_port *ap = qc->ap;
711 struct sil24_port_priv *pp = ap->private_data;
aee10a03
TH		 712 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
713 unsigned int tag = sil24_tag(qc->tag);
714 dma_addr_t paddr;
715 void __iomem *activate;
edb33667 716
aee10a03
TH		 717 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
718 activate = port + PORT_CMD_ACTIVATE + tag * 8;
719
720 writel((u32)paddr, activate);
721 writel((u64)paddr >> 32, activate + 4);
26ec634c 722
edb33667
TH		 723 return 0;
724}
725
726static void sil24_irq_clear(struct ata_port *ap)
727{
728 /* unused */
729}
730
88ce7550 731static void sil24_freeze(struct ata_port *ap)
7d1ce682 732{
88ce7550 733 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
7d1ce682 734
88ce7550
TH		 735 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
736 * PORT_IRQ_ENABLE instead.
737 */
738 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
7d1ce682
TH		 739}
740
88ce7550 741static void sil24_thaw(struct ata_port *ap)
edb33667 742{
88ce7550 743 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
edb33667
TH		 744 u32 tmp;
745
88ce7550
TH		 746 /* clear IRQ */
747 tmp = readl(port + PORT_IRQ_STAT);
748 writel(tmp, port + PORT_IRQ_STAT);
edb33667 749
88ce7550
TH		 750 /* turn IRQ back on */
751 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
edb33667
TH		 752}
753
88ce7550 754static void sil24_error_intr(struct ata_port *ap)
8746618d 755{
4b4a5eae 756 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
88ce7550
TH		 757 struct ata_eh_info *ehi = &ap->eh_info;
758 int freeze = 0;
759 u32 irq_stat;
8746618d 760
88ce7550 761 /* on error, we need to clear IRQ explicitly */
8746618d 762 irq_stat = readl(port + PORT_IRQ_STAT);
88ce7550 763 writel(irq_stat, port + PORT_IRQ_STAT);
ad6e90f6 764
88ce7550
TH		 765 /* first, analyze and record host port events */
766 ata_ehi_clear_desc(ehi);
ad6e90f6 767
88ce7550 768 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
8746618d 769
88ce7550
TH		 770 if (irq_stat & PORT_IRQ_DEV_XCHG) {
771 ehi->err_mask |= AC_ERR_ATA_BUS;
772 /* sil24 doesn't recover very well from phy
773 * disconnection with a softreset. Force hardreset.
6a575fa9 774 */
88ce7550
TH		 775 ehi->action |= ATA_EH_HARDRESET;
776 ata_ehi_push_desc(ehi, ", device_exchanged");
777 freeze = 1;
6a575fa9
TH		 778 }
779
88ce7550
TH		 780 if (irq_stat & PORT_IRQ_UNK_FIS) {
781 ehi->err_mask |= AC_ERR_HSM;
782 ehi->action |= ATA_EH_SOFTRESET;
783 ata_ehi_push_desc(ehi , ", unknown FIS");
784 freeze = 1;
785 }
786
787 /* deal with command error */
788 if (irq_stat & PORT_IRQ_ERROR) {
789 struct sil24_cerr_info *ci = NULL;
790 unsigned int err_mask = 0, action = 0;
791 struct ata_queued_cmd *qc;
792 u32 cerr;
793
794 /* analyze CMD_ERR */
795 cerr = readl(port + PORT_CMD_ERR);
796 if (cerr < ARRAY_SIZE(sil24_cerr_db))
797 ci = &sil24_cerr_db[cerr];
798
799 if (ci && ci->desc) {
800 err_mask |= ci->err_mask;
801 action |= ci->action;
802 ata_ehi_push_desc(ehi, ", %s", ci->desc);
803 } else {
804 err_mask |= AC_ERR_OTHER;
805 action |= ATA_EH_SOFTRESET;
806 ata_ehi_push_desc(ehi, ", unknown command error %d",
807 cerr);
808 }
809
810 /* record error info */
811 qc = ata_qc_from_tag(ap, ap->active_tag);
812 if (qc) {
88ce7550
TH		 813 sil24_update_tf(ap);
814 qc->err_mask |= err_mask;
815 } else
816 ehi->err_mask |= err_mask;
817
818 ehi->action |= action;
a22e2eb0 819 }
88ce7550
TH		 820
821 /* freeze or abort */
822 if (freeze)
823 ata_port_freeze(ap);
824 else
825 ata_port_abort(ap);
8746618d
TH		 826}
827
aee10a03
TH		 828static void sil24_finish_qc(struct ata_queued_cmd *qc)
829{
830 if (qc->flags & ATA_QCFLAG_RESULT_TF)
831 sil24_update_tf(qc->ap);
832}
833
edb33667
TH		 834static inline void sil24_host_intr(struct ata_port *ap)
835{
4b4a5eae 836 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
aee10a03
TH		 837 u32 slot_stat, qc_active;
838 int rc;
edb33667
TH		 839
840 slot_stat = readl(port + PORT_SLOT_STAT);
37024e8e 841
88ce7550
TH		 842 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
843 sil24_error_intr(ap);
844 return;
845 }
846
847 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
848 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
37024e8e 849
aee10a03
TH		 850 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
851 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
852 if (rc > 0)
853 return;
854 if (rc < 0) {
855 struct ata_eh_info *ehi = &ap->eh_info;
856 ehi->err_mask |= AC_ERR_HSM;
857 ehi->action |= ATA_EH_SOFTRESET;
858 ata_port_freeze(ap);
88ce7550
TH		 859 return;
860 }
861
862 if (ata_ratelimit())
863 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
aee10a03
TH		 864 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
865 slot_stat, ap->active_tag, ap->sactive);
edb33667
TH		 866}
867
868static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
869{
870 struct ata_host_set *host_set = dev_instance;
871 struct sil24_host_priv *hpriv = host_set->private_data;
872 unsigned handled = 0;
873 u32 status;
874 int i;
875
876 status = readl(hpriv->host_base + HOST_IRQ_STAT);
877
06460aea
TH		 878 if (status == 0xffffffff) {
879 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
880 "PCI fault or device removal?\n");
881 goto out;
882 }
883
edb33667
TH		 884 if (!(status & IRQ_STAT_4PORTS))
885 goto out;
886
887 spin_lock(&host_set->lock);
888
889 for (i = 0; i < host_set->n_ports; i++)
890 if (status & (1 << i)) {
891 struct ata_port *ap = host_set->ports[i];
198e0fed 892 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
edb33667 893 sil24_host_intr(host_set->ports[i]);
3cc4571c
TH		 894 handled++;
895 } else
896 printk(KERN_ERR DRV_NAME
897 ": interrupt from disabled port %d\n", i);
edb33667
TH		 898 }
899
900 spin_unlock(&host_set->lock);
901 out:
902 return IRQ_RETVAL(handled);
903}
904
88ce7550
TH		 905static void sil24_error_handler(struct ata_port *ap)
906{
907 struct ata_eh_context *ehc = &ap->eh_context;
908
909 if (sil24_init_port(ap)) {
910 ata_eh_freeze_port(ap);
911 ehc->i.action |= ATA_EH_HARDRESET;
912 }
913
914 /* perform recovery */
f5914a46
TH		 915 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
916 ata_std_postreset);
88ce7550
TH		 917}
918
919static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
920{
921 struct ata_port *ap = qc->ap;
922
923 if (qc->flags & ATA_QCFLAG_FAILED)
924 qc->err_mask |= AC_ERR_OTHER;
925
926 /* make DMA engine forget about the failed command */
927 if (qc->err_mask)
928 sil24_init_port(ap);
929}
930
6037d6bb
JG		 931static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
932{
aee10a03 933 const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
6037d6bb
JG		 934
935 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
936}
937
edb33667
TH		 938static int sil24_port_start(struct ata_port *ap)
939{
940 struct device *dev = ap->host_set->dev;
edb33667 941 struct sil24_port_priv *pp;
69ad185f 942 union sil24_cmd_block *cb;
aee10a03 943 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
edb33667 944 dma_addr_t cb_dma;
6037d6bb 945 int rc = -ENOMEM;
edb33667 946
6037d6bb 947 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
edb33667 948 if (!pp)
6037d6bb 949 goto err_out;
edb33667 950
6a575fa9
TH		 951 pp->tf.command = ATA_DRDY;
952
edb33667 953 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
6037d6bb
JG		 954 if (!cb)
955 goto err_out_pp;
edb33667
TH		 956 memset(cb, 0, cb_size);
957
6037d6bb
JG		 958 rc = ata_pad_alloc(ap, dev);
959 if (rc)
960 goto err_out_pad;
961
edb33667
TH		 962 pp->cmd_block = cb;
963 pp->cmd_block_dma = cb_dma;
964
965 ap->private_data = pp;
966
967 return 0;
6037d6bb
JG		 968
969err_out_pad:
970 sil24_cblk_free(pp, dev);
971err_out_pp:
972 kfree(pp);
973err_out:
974 return rc;
edb33667
TH		 975}
976
977static void sil24_port_stop(struct ata_port *ap)
978{
979 struct device *dev = ap->host_set->dev;
980 struct sil24_port_priv *pp = ap->private_data;
edb33667 981
6037d6bb 982 sil24_cblk_free(pp, dev);
e9c05afa 983 ata_pad_free(ap, dev);
edb33667
TH		 984 kfree(pp);
985}
986
987static void sil24_host_stop(struct ata_host_set *host_set)
988{
989 struct sil24_host_priv *hpriv = host_set->private_data;
142877b0 990 struct pci_dev *pdev = to_pci_dev(host_set->dev);
edb33667 991
142877b0
JG		 992 pci_iounmap(pdev, hpriv->host_base);
993 pci_iounmap(pdev, hpriv->port_base);
edb33667
TH		 994 kfree(hpriv);
995}
996
997static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
998{
999 static int printed_version = 0;
1000 unsigned int board_id = (unsigned int)ent->driver_data;
042c21fd 1001 struct ata_port_info *pinfo = &sil24_port_info[board_id];
edb33667
TH		 1002 struct ata_probe_ent *probe_ent = NULL;
1003 struct sil24_host_priv *hpriv = NULL;
4b4a5eae
AV		 1004 void __iomem *host_base = NULL;
1005 void __iomem *port_base = NULL;
edb33667 1006 int i, rc;
37024e8e 1007 u32 tmp;
edb33667
TH		 1008
1009 if (!printed_version++)
a9524a76 1010 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
edb33667
TH		 1011
1012 rc = pci_enable_device(pdev);
1013 if (rc)
1014 return rc;
1015
1016 rc = pci_request_regions(pdev, DRV_NAME);
1017 if (rc)
1018 goto out_disable;
1019
1020 rc = -ENOMEM;
142877b0
JG		 1021 /* map mmio registers */
1022 host_base = pci_iomap(pdev, 0, 0);
edb33667
TH		 1023 if (!host_base)
1024 goto out_free;
142877b0 1025 port_base = pci_iomap(pdev, 2, 0);
edb33667
TH		 1026 if (!port_base)
1027 goto out_free;
1028
1029 /* allocate & init probe_ent and hpriv */
142877b0 1030 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
edb33667
TH		 1031 if (!probe_ent)
1032 goto out_free;
1033
142877b0 1034 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
edb33667
TH		 1035 if (!hpriv)
1036 goto out_free;
1037
edb33667
TH		 1038 probe_ent->dev = pci_dev_to_dev(pdev);
1039 INIT_LIST_HEAD(&probe_ent->node);
1040
042c21fd
TH		 1041 probe_ent->sht = pinfo->sht;
1042 probe_ent->host_flags = pinfo->host_flags;
1043 probe_ent->pio_mask = pinfo->pio_mask;
fbfda6e7 1044 probe_ent->mwdma_mask = pinfo->mwdma_mask;
042c21fd
TH		 1045 probe_ent->udma_mask = pinfo->udma_mask;
1046 probe_ent->port_ops = pinfo->port_ops;
1047 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
edb33667
TH		 1048
1049 probe_ent->irq = pdev->irq;
1050 probe_ent->irq_flags = SA_SHIRQ;
1051 probe_ent->mmio_base = port_base;
1052 probe_ent->private_data = hpriv;
1053
edb33667
TH		 1054 hpriv->host_base = host_base;
1055 hpriv->port_base = port_base;
1056
1057 /*
1058 * Configure the device
1059 */
26ec634c
TH		 1060 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1061 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1062 if (rc) {
1063 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1064 if (rc) {
1065 dev_printk(KERN_ERR, &pdev->dev,
1066 "64-bit DMA enable failed\n");
1067 goto out_free;
1068 }
1069 }
1070 } else {
1071 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1072 if (rc) {
1073 dev_printk(KERN_ERR, &pdev->dev,
1074 "32-bit DMA enable failed\n");
1075 goto out_free;
1076 }
1077 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1078 if (rc) {
1079 dev_printk(KERN_ERR, &pdev->dev,
1080 "32-bit consistent DMA enable failed\n");
1081 goto out_free;
1082 }
edb33667
TH		 1083 }
1084
1085 /* GPIO off */
1086 writel(0, host_base + HOST_FLASH_CMD);
1087
37024e8e
TH		 1088 /* Apply workaround for completion IRQ loss on PCI-X errata */
1089 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1090 tmp = readl(host_base + HOST_CTRL);
1091 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1092 dev_printk(KERN_INFO, &pdev->dev,
1093 "Applying completion IRQ loss on PCI-X "
1094 "errata fix\n");
1095 else
1096 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1097 }
1098
7dd29dd6 1099 /* clear global reset & mask interrupts during initialization */
edb33667
TH		 1100 writel(0, host_base + HOST_CTRL);
1101
1102 for (i = 0; i < probe_ent->n_ports; i++) {
4b4a5eae 1103 void __iomem *port = port_base + i * PORT_REGS_SIZE;
edb33667 1104 unsigned long portu = (unsigned long)port;
edb33667 1105
4f50c3cb 1106 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
edb33667
TH		 1107 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1108
1109 ata_std_ports(&probe_ent->port[i]);
1110
1111 /* Initial PHY setting */
1112 writel(0x20c, port + PORT_PHY_CFG);
1113
1114 /* Clear port RST */
1115 tmp = readl(port + PORT_CTRL_STAT);
1116 if (tmp & PORT_CS_PORT_RST) {
1117 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
7dd29dd6
TH		 1118 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1119 PORT_CS_PORT_RST,
1120 PORT_CS_PORT_RST, 10, 100);
edb33667 1121 if (tmp & PORT_CS_PORT_RST)
a9524a76
JG		 1122 dev_printk(KERN_ERR, &pdev->dev,
1123 "failed to clear port RST\n");
edb33667
TH		 1124 }
1125
37024e8e
TH		 1126 /* Configure IRQ WoC */
1127 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1128 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1129 else
1130 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1131
edb33667
TH		 1132 /* Zero error counters. */
1133 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1134 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1135 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1136 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1137 writel(0x0000, port + PORT_CRC_ERR_CNT);
1138 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1139
26ec634c
TH		 1140 /* Always use 64bit activation */
1141 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
edb33667 1142
923f1225
TH		 1143 /* Clear port multiplier enable and resume bits */
1144 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
edb33667
TH		 1145 }
1146
1147 /* Turn on interrupts */
1148 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1149
1150 pci_set_master(pdev);
1151
1483467f 1152 /* FIXME: check ata_device_add return value */
edb33667
TH		 1153 ata_device_add(probe_ent);
1154
1155 kfree(probe_ent);
1156 return 0;
1157
1158 out_free:
1159 if (host_base)
142877b0 1160 pci_iounmap(pdev, host_base);
edb33667 1161 if (port_base)
142877b0 1162 pci_iounmap(pdev, port_base);
edb33667
TH		 1163 kfree(probe_ent);
1164 kfree(hpriv);
1165 pci_release_regions(pdev);
1166 out_disable:
1167 pci_disable_device(pdev);
1168 return rc;
1169}
1170
1171static int __init sil24_init(void)
1172{
1173 return pci_module_init(&sil24_pci_driver);
1174}
1175
1176static void __exit sil24_exit(void)
1177{
1178 pci_unregister_driver(&sil24_pci_driver);
1179}
1180
1181MODULE_AUTHOR("Tejun Heo");
1182MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1183MODULE_LICENSE("GPL");
1184MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1185
1186module_init(sil24_init);
1187module_exit(sil24_exit);
Clone of davem's net-next-2.6 tree