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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dma-mapping.h> | |
a9524a76 | 27 | #include <linux/device.h> |
edb33667 | 28 | #include <scsi/scsi_host.h> |
193515d5 | 29 | #include <scsi/scsi_cmnd.h> |
edb33667 TH |
30 | #include <linux/libata.h> |
31 | #include <asm/io.h> | |
32 | ||
33 | #define DRV_NAME "sata_sil24" | |
69ad185f | 34 | #define DRV_VERSION "0.23" |
edb33667 | 35 | |
edb33667 TH |
36 | /* |
37 | * Port request block (PRB) 32 bytes | |
38 | */ | |
39 | struct sil24_prb { | |
40 | u16 ctrl; | |
41 | u16 prot; | |
42 | u32 rx_cnt; | |
43 | u8 fis[6 * 4]; | |
44 | }; | |
45 | ||
46 | /* | |
47 | * Scatter gather entry (SGE) 16 bytes | |
48 | */ | |
49 | struct sil24_sge { | |
50 | u64 addr; | |
51 | u32 cnt; | |
52 | u32 flags; | |
53 | }; | |
54 | ||
55 | /* | |
56 | * Port multiplier | |
57 | */ | |
58 | struct sil24_port_multiplier { | |
59 | u32 diag; | |
60 | u32 sactive; | |
61 | }; | |
62 | ||
63 | enum { | |
64 | /* | |
65 | * Global controller registers (128 bytes @ BAR0) | |
66 | */ | |
67 | /* 32 bit regs */ | |
68 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
69 | HOST_CTRL = 0x40, | |
70 | HOST_IRQ_STAT = 0x44, | |
71 | HOST_PHY_CFG = 0x48, | |
72 | HOST_BIST_CTRL = 0x50, | |
73 | HOST_BIST_PTRN = 0x54, | |
74 | HOST_BIST_STAT = 0x58, | |
75 | HOST_MEM_BIST_STAT = 0x5c, | |
76 | HOST_FLASH_CMD = 0x70, | |
77 | /* 8 bit regs */ | |
78 | HOST_FLASH_DATA = 0x74, | |
79 | HOST_TRANSITION_DETECT = 0x75, | |
80 | HOST_GPIO_CTRL = 0x76, | |
81 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
82 | HOST_I2C_DATA = 0x7c, | |
83 | HOST_I2C_XFER_CNT = 0x7e, | |
84 | HOST_I2C_CTRL = 0x7f, | |
85 | ||
86 | /* HOST_SLOT_STAT bits */ | |
87 | HOST_SSTAT_ATTN = (1 << 31), | |
88 | ||
89 | /* | |
90 | * Port registers | |
91 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
92 | */ | |
93 | PORT_REGS_SIZE = 0x2000, | |
94 | PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */ | |
edb33667 TH |
95 | |
96 | PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */ | |
97 | /* 32 bit regs */ | |
83bbecc9 TH |
98 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
99 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
100 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
101 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
102 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 103 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
104 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
105 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
106 | PORT_FIS_CFG = 0x1028, |
107 | PORT_FIFO_THRES = 0x102c, | |
108 | /* 16 bit regs */ | |
109 | PORT_DECODE_ERR_CNT = 0x1040, | |
110 | PORT_DECODE_ERR_THRESH = 0x1042, | |
111 | PORT_CRC_ERR_CNT = 0x1044, | |
112 | PORT_CRC_ERR_THRESH = 0x1046, | |
113 | PORT_HSHK_ERR_CNT = 0x1048, | |
114 | PORT_HSHK_ERR_THRESH = 0x104a, | |
115 | /* 32 bit regs */ | |
116 | PORT_PHY_CFG = 0x1050, | |
117 | PORT_SLOT_STAT = 0x1800, | |
118 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
119 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ | |
120 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
121 | PORT_SCONTROL = 0x1f00, | |
122 | PORT_SSTATUS = 0x1f04, | |
123 | PORT_SERROR = 0x1f08, | |
124 | PORT_SACTIVE = 0x1f0c, | |
125 | ||
126 | /* PORT_CTRL_STAT bits */ | |
127 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
128 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
129 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
130 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 131 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
e382eb1d TH |
132 | PORT_CS_RESUME = (1 << 6), /* port resume */ |
133 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ | |
134 | PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */ | |
135 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ | |
edb33667 TH |
136 | |
137 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
138 | /* bits[11:0] are masked */ | |
139 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
140 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
141 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
142 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
143 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
144 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
145 | PORT_IRQ_UNK_FIS = (1 << 6), /* Unknown FIS received */ | |
146 | PORT_IRQ_SDB_FIS = (1 << 11), /* SDB FIS received */ | |
147 | ||
148 | /* bits[27:16] are unmasked (raw) */ | |
149 | PORT_IRQ_RAW_SHIFT = 16, | |
150 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
151 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
152 | ||
153 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
154 | PORT_IRQ_STEER_SHIFT = 30, | |
155 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
156 | ||
157 | /* PORT_CMD_ERR constants */ | |
158 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
159 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
160 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
161 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
162 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
163 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
164 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
165 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
166 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
167 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
168 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
169 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
170 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
171 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
172 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
173 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
174 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
175 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
176 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
177 | PORT_CERR_XFR_MSGABRT = 34, /* PSD ecode 10 - master abort */ | |
178 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ | |
83bbecc9 | 179 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 180 | |
d10cb35a TH |
181 | /* bits of PRB control field */ |
182 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
183 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
184 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
185 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
186 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
187 | ||
188 | /* PRB protocol field */ | |
189 | PRB_PROT_PACKET = (1 << 0), | |
190 | PRB_PROT_TCQ = (1 << 1), | |
191 | PRB_PROT_NCQ = (1 << 2), | |
192 | PRB_PROT_READ = (1 << 3), | |
193 | PRB_PROT_WRITE = (1 << 4), | |
194 | PRB_PROT_TRANSPARENT = (1 << 5), | |
195 | ||
edb33667 TH |
196 | /* |
197 | * Other constants | |
198 | */ | |
199 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
200 | SGE_LNK = (1 << 30), /* linked list |
201 | Points to SGT, not SGE */ | |
202 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
203 | data address ignored */ | |
edb33667 TH |
204 | |
205 | /* board id */ | |
206 | BID_SIL3124 = 0, | |
207 | BID_SIL3132 = 1, | |
042c21fd | 208 | BID_SIL3131 = 2, |
edb33667 TH |
209 | |
210 | IRQ_STAT_4PORTS = 0xf, | |
211 | }; | |
212 | ||
69ad185f | 213 | struct sil24_ata_block { |
edb33667 TH |
214 | struct sil24_prb prb; |
215 | struct sil24_sge sge[LIBATA_MAX_PRD]; | |
216 | }; | |
217 | ||
69ad185f TH |
218 | struct sil24_atapi_block { |
219 | struct sil24_prb prb; | |
220 | u8 cdb[16]; | |
221 | struct sil24_sge sge[LIBATA_MAX_PRD - 1]; | |
222 | }; | |
223 | ||
224 | union sil24_cmd_block { | |
225 | struct sil24_ata_block ata; | |
226 | struct sil24_atapi_block atapi; | |
227 | }; | |
228 | ||
edb33667 TH |
229 | /* |
230 | * ap->private_data | |
231 | * | |
232 | * The preview driver always returned 0 for status. We emulate it | |
233 | * here from the previous interrupt. | |
234 | */ | |
235 | struct sil24_port_priv { | |
69ad185f | 236 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 237 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
6a575fa9 | 238 | struct ata_taskfile tf; /* Cached taskfile registers */ |
edb33667 TH |
239 | }; |
240 | ||
241 | /* ap->host_set->private_data */ | |
242 | struct sil24_host_priv { | |
4b4a5eae AV |
243 | void __iomem *host_base; /* global controller control (128 bytes @BAR0) */ |
244 | void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */ | |
edb33667 TH |
245 | }; |
246 | ||
69ad185f | 247 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev); |
edb33667 | 248 | static u8 sil24_check_status(struct ata_port *ap); |
edb33667 TH |
249 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg); |
250 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val); | |
7f726d12 | 251 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf); |
edb33667 TH |
252 | static void sil24_phy_reset(struct ata_port *ap); |
253 | static void sil24_qc_prep(struct ata_queued_cmd *qc); | |
9a3d9eb0 | 254 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
edb33667 TH |
255 | static void sil24_irq_clear(struct ata_port *ap); |
256 | static void sil24_eng_timeout(struct ata_port *ap); | |
257 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs); | |
258 | static int sil24_port_start(struct ata_port *ap); | |
259 | static void sil24_port_stop(struct ata_port *ap); | |
260 | static void sil24_host_stop(struct ata_host_set *host_set); | |
261 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); | |
262 | ||
3b7d697d | 263 | static const struct pci_device_id sil24_pci_tbl[] = { |
edb33667 TH |
264 | { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 }, |
265 | { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 }, | |
042c21fd TH |
266 | { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, |
267 | { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 }, | |
1fcce839 | 268 | { } /* terminate list */ |
edb33667 TH |
269 | }; |
270 | ||
271 | static struct pci_driver sil24_pci_driver = { | |
272 | .name = DRV_NAME, | |
273 | .id_table = sil24_pci_tbl, | |
274 | .probe = sil24_init_one, | |
275 | .remove = ata_pci_remove_one, /* safe? */ | |
276 | }; | |
277 | ||
193515d5 | 278 | static struct scsi_host_template sil24_sht = { |
edb33667 TH |
279 | .module = THIS_MODULE, |
280 | .name = DRV_NAME, | |
281 | .ioctl = ata_scsi_ioctl, | |
282 | .queuecommand = ata_scsi_queuecmd, | |
35daeb8f | 283 | .eh_timed_out = ata_scsi_timed_out, |
edb33667 TH |
284 | .eh_strategy_handler = ata_scsi_error, |
285 | .can_queue = ATA_DEF_QUEUE, | |
286 | .this_id = ATA_SHT_THIS_ID, | |
287 | .sg_tablesize = LIBATA_MAX_PRD, | |
288 | .max_sectors = ATA_MAX_SECTORS, | |
289 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, | |
290 | .emulated = ATA_SHT_EMULATED, | |
291 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
292 | .proc_name = DRV_NAME, | |
293 | .dma_boundary = ATA_DMA_BOUNDARY, | |
294 | .slave_configure = ata_scsi_slave_config, | |
295 | .bios_param = ata_std_bios_param, | |
edb33667 TH |
296 | }; |
297 | ||
057ace5e | 298 | static const struct ata_port_operations sil24_ops = { |
edb33667 TH |
299 | .port_disable = ata_port_disable, |
300 | ||
69ad185f TH |
301 | .dev_config = sil24_dev_config, |
302 | ||
edb33667 TH |
303 | .check_status = sil24_check_status, |
304 | .check_altstatus = sil24_check_status, | |
edb33667 TH |
305 | .dev_select = ata_noop_dev_select, |
306 | ||
7f726d12 TH |
307 | .tf_read = sil24_tf_read, |
308 | ||
edb33667 TH |
309 | .phy_reset = sil24_phy_reset, |
310 | ||
311 | .qc_prep = sil24_qc_prep, | |
312 | .qc_issue = sil24_qc_issue, | |
313 | ||
314 | .eng_timeout = sil24_eng_timeout, | |
315 | ||
316 | .irq_handler = sil24_interrupt, | |
317 | .irq_clear = sil24_irq_clear, | |
318 | ||
319 | .scr_read = sil24_scr_read, | |
320 | .scr_write = sil24_scr_write, | |
321 | ||
322 | .port_start = sil24_port_start, | |
323 | .port_stop = sil24_port_stop, | |
324 | .host_stop = sil24_host_stop, | |
325 | }; | |
326 | ||
042c21fd TH |
327 | /* |
328 | * Use bits 30-31 of host_flags to encode available port numbers. | |
329 | * Current maxium is 4. | |
330 | */ | |
331 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
332 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
333 | ||
edb33667 TH |
334 | static struct ata_port_info sil24_port_info[] = { |
335 | /* sil_3124 */ | |
336 | { | |
337 | .sht = &sil24_sht, | |
338 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
ca45160d | 339 | ATA_FLAG_SRST | ATA_FLAG_MMIO | |
042c21fd | 340 | ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(4), |
edb33667 TH |
341 | .pio_mask = 0x1f, /* pio0-4 */ |
342 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
343 | .udma_mask = 0x3f, /* udma0-5 */ | |
344 | .port_ops = &sil24_ops, | |
345 | }, | |
346 | /* sil_3132 */ | |
347 | { | |
348 | .sht = &sil24_sht, | |
349 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
ca45160d | 350 | ATA_FLAG_SRST | ATA_FLAG_MMIO | |
042c21fd TH |
351 | ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(2), |
352 | .pio_mask = 0x1f, /* pio0-4 */ | |
353 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
354 | .udma_mask = 0x3f, /* udma0-5 */ | |
355 | .port_ops = &sil24_ops, | |
356 | }, | |
357 | /* sil_3131/sil_3531 */ | |
358 | { | |
359 | .sht = &sil24_sht, | |
360 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
ca45160d | 361 | ATA_FLAG_SRST | ATA_FLAG_MMIO | |
042c21fd | 362 | ATA_FLAG_PIO_DMA | SIL24_NPORTS2FLAG(1), |
edb33667 TH |
363 | .pio_mask = 0x1f, /* pio0-4 */ |
364 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
365 | .udma_mask = 0x3f, /* udma0-5 */ | |
366 | .port_ops = &sil24_ops, | |
367 | }, | |
368 | }; | |
369 | ||
69ad185f TH |
370 | static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev) |
371 | { | |
372 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; | |
373 | ||
374 | if (ap->cdb_len == 16) | |
375 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); | |
376 | else | |
377 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
378 | } | |
379 | ||
6a575fa9 TH |
380 | static inline void sil24_update_tf(struct ata_port *ap) |
381 | { | |
382 | struct sil24_port_priv *pp = ap->private_data; | |
4b4a5eae AV |
383 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
384 | struct sil24_prb __iomem *prb = port; | |
385 | u8 fis[6 * 4]; | |
6a575fa9 | 386 | |
4b4a5eae AV |
387 | memcpy_fromio(fis, prb->fis, 6 * 4); |
388 | ata_tf_from_fis(fis, &pp->tf); | |
6a575fa9 TH |
389 | } |
390 | ||
edb33667 TH |
391 | static u8 sil24_check_status(struct ata_port *ap) |
392 | { | |
6a575fa9 TH |
393 | struct sil24_port_priv *pp = ap->private_data; |
394 | return pp->tf.command; | |
edb33667 TH |
395 | } |
396 | ||
edb33667 TH |
397 | static int sil24_scr_map[] = { |
398 | [SCR_CONTROL] = 0, | |
399 | [SCR_STATUS] = 1, | |
400 | [SCR_ERROR] = 2, | |
401 | [SCR_ACTIVE] = 3, | |
402 | }; | |
403 | ||
404 | static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg) | |
405 | { | |
4b4a5eae | 406 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 407 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 408 | void __iomem *addr; |
edb33667 TH |
409 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
410 | return readl(scr_addr + sil24_scr_map[sc_reg] * 4); | |
411 | } | |
412 | return 0xffffffffU; | |
413 | } | |
414 | ||
415 | static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val) | |
416 | { | |
4b4a5eae | 417 | void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr; |
edb33667 | 418 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 419 | void __iomem *addr; |
edb33667 TH |
420 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
421 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
422 | } | |
423 | } | |
424 | ||
7f726d12 TH |
425 | static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf) |
426 | { | |
427 | struct sil24_port_priv *pp = ap->private_data; | |
428 | *tf = pp->tf; | |
429 | } | |
430 | ||
ca45160d | 431 | static int sil24_issue_SRST(struct ata_port *ap) |
edb33667 | 432 | { |
ca45160d TH |
433 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
434 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f | 435 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d TH |
436 | dma_addr_t paddr = pp->cmd_block_dma; |
437 | u32 irq_enable, irq_stat; | |
438 | int cnt; | |
439 | ||
440 | /* temporarily turn off IRQs during SRST */ | |
441 | irq_enable = readl(port + PORT_IRQ_ENABLE_SET); | |
442 | writel(irq_enable, port + PORT_IRQ_ENABLE_CLR); | |
443 | ||
edb33667 | 444 | /* |
ca45160d TH |
445 | * XXX: Not sure whether the following sleep is needed or not. |
446 | * The original driver had it. So.... | |
edb33667 | 447 | */ |
ca45160d TH |
448 | msleep(10); |
449 | ||
450 | prb->ctrl = PRB_CTRL_SRST; | |
451 | prb->fis[1] = 0; /* no PM yet */ | |
452 | ||
453 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | |
454 | ||
455 | for (cnt = 0; cnt < 100; cnt++) { | |
456 | irq_stat = readl(port + PORT_IRQ_STAT); | |
457 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ | |
458 | ||
459 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
460 | if (irq_stat & (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR)) | |
461 | break; | |
462 | ||
463 | msleep(1); | |
464 | } | |
465 | ||
466 | /* restore IRQs */ | |
467 | writel(irq_enable, port + PORT_IRQ_ENABLE_SET); | |
468 | ||
469 | if (!(irq_stat & PORT_IRQ_COMPLETE)) | |
470 | return -1; | |
471 | ||
472 | /* update TF */ | |
473 | sil24_update_tf(ap); | |
474 | return 0; | |
475 | } | |
476 | ||
477 | static void sil24_phy_reset(struct ata_port *ap) | |
478 | { | |
479 | struct sil24_port_priv *pp = ap->private_data; | |
480 | ||
481 | __sata_phy_reset(ap); | |
482 | if (ap->flags & ATA_FLAG_PORT_DISABLED) | |
483 | return; | |
484 | ||
485 | if (sil24_issue_SRST(ap) < 0) { | |
486 | printk(KERN_ERR DRV_NAME | |
487 | " ata%u: SRST failed, disabling port\n", ap->id); | |
488 | ap->ops->port_disable(ap); | |
489 | return; | |
490 | } | |
491 | ||
492 | ap->device->class = ata_dev_classify(&pp->tf); | |
edb33667 TH |
493 | } |
494 | ||
495 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, | |
69ad185f | 496 | struct sil24_sge *sge) |
edb33667 | 497 | { |
972c26bd JG |
498 | struct scatterlist *sg; |
499 | unsigned int idx = 0; | |
edb33667 | 500 | |
972c26bd | 501 | ata_for_each_sg(sg, qc) { |
edb33667 TH |
502 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
503 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
972c26bd JG |
504 | if (ata_sg_is_last(sg, qc)) |
505 | sge->flags = cpu_to_le32(SGE_TRM); | |
506 | else | |
507 | sge->flags = 0; | |
508 | ||
509 | sge++; | |
510 | idx++; | |
edb33667 TH |
511 | } |
512 | } | |
513 | ||
514 | static void sil24_qc_prep(struct ata_queued_cmd *qc) | |
515 | { | |
516 | struct ata_port *ap = qc->ap; | |
517 | struct sil24_port_priv *pp = ap->private_data; | |
69ad185f TH |
518 | union sil24_cmd_block *cb = pp->cmd_block + qc->tag; |
519 | struct sil24_prb *prb; | |
520 | struct sil24_sge *sge; | |
edb33667 TH |
521 | |
522 | switch (qc->tf.protocol) { | |
523 | case ATA_PROT_PIO: | |
524 | case ATA_PROT_DMA: | |
525 | case ATA_PROT_NODATA: | |
69ad185f TH |
526 | prb = &cb->ata.prb; |
527 | sge = cb->ata.sge; | |
528 | prb->ctrl = 0; | |
edb33667 | 529 | break; |
69ad185f TH |
530 | |
531 | case ATA_PROT_ATAPI: | |
532 | case ATA_PROT_ATAPI_DMA: | |
533 | case ATA_PROT_ATAPI_NODATA: | |
534 | prb = &cb->atapi.prb; | |
535 | sge = cb->atapi.sge; | |
536 | memset(cb->atapi.cdb, 0, 32); | |
537 | memcpy(cb->atapi.cdb, qc->cdb, ap->cdb_len); | |
538 | ||
539 | if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) { | |
540 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
541 | prb->ctrl = PRB_CTRL_PACKET_WRITE; | |
542 | else | |
543 | prb->ctrl = PRB_CTRL_PACKET_READ; | |
544 | } else | |
545 | prb->ctrl = 0; | |
546 | ||
547 | break; | |
548 | ||
edb33667 | 549 | default: |
69ad185f TH |
550 | prb = NULL; /* shut up, gcc */ |
551 | sge = NULL; | |
edb33667 TH |
552 | BUG(); |
553 | } | |
554 | ||
555 | ata_tf_to_fis(&qc->tf, prb->fis, 0); | |
556 | ||
557 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 558 | sil24_fill_sg(qc, sge); |
edb33667 TH |
559 | } |
560 | ||
9a3d9eb0 | 561 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
562 | { |
563 | struct ata_port *ap = qc->ap; | |
4b4a5eae | 564 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
565 | struct sil24_port_priv *pp = ap->private_data; |
566 | dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block); | |
567 | ||
4f50c3cb | 568 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); |
edb33667 TH |
569 | return 0; |
570 | } | |
571 | ||
572 | static void sil24_irq_clear(struct ata_port *ap) | |
573 | { | |
574 | /* unused */ | |
575 | } | |
576 | ||
7d1ce682 TH |
577 | static int __sil24_restart_controller(void __iomem *port) |
578 | { | |
579 | u32 tmp; | |
580 | int cnt; | |
581 | ||
582 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); | |
583 | ||
584 | /* Max ~10ms */ | |
585 | for (cnt = 0; cnt < 10000; cnt++) { | |
586 | tmp = readl(port + PORT_CTRL_STAT); | |
587 | if (tmp & PORT_CS_RDY) | |
588 | return 0; | |
589 | udelay(1); | |
590 | } | |
591 | ||
592 | return -1; | |
593 | } | |
594 | ||
595 | static void sil24_restart_controller(struct ata_port *ap) | |
596 | { | |
597 | if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr)) | |
598 | printk(KERN_ERR DRV_NAME | |
599 | " ata%u: failed to restart controller\n", ap->id); | |
600 | } | |
601 | ||
4b4a5eae | 602 | static int __sil24_reset_controller(void __iomem *port) |
edb33667 | 603 | { |
edb33667 TH |
604 | int cnt; |
605 | u32 tmp; | |
606 | ||
edb33667 TH |
607 | /* Reset controller state. Is this correct? */ |
608 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
609 | readl(port + PORT_CTRL_STAT); /* sync */ | |
610 | ||
611 | /* Max ~100ms */ | |
612 | for (cnt = 0; cnt < 1000; cnt++) { | |
613 | udelay(100); | |
614 | tmp = readl(port + PORT_CTRL_STAT); | |
615 | if (!(tmp & PORT_CS_DEV_RST)) | |
616 | break; | |
617 | } | |
923f1225 | 618 | |
edb33667 | 619 | if (tmp & PORT_CS_DEV_RST) |
923f1225 | 620 | return -1; |
7d1ce682 TH |
621 | |
622 | if (tmp & PORT_CS_RDY) | |
623 | return 0; | |
624 | ||
625 | return __sil24_restart_controller(port); | |
923f1225 TH |
626 | } |
627 | ||
628 | static void sil24_reset_controller(struct ata_port *ap) | |
629 | { | |
630 | printk(KERN_NOTICE DRV_NAME | |
631 | " ata%u: resetting controller...\n", ap->id); | |
4b4a5eae | 632 | if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr)) |
923f1225 TH |
633 | printk(KERN_ERR DRV_NAME |
634 | " ata%u: failed to reset controller\n", ap->id); | |
edb33667 TH |
635 | } |
636 | ||
637 | static void sil24_eng_timeout(struct ata_port *ap) | |
638 | { | |
639 | struct ata_queued_cmd *qc; | |
640 | ||
641 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
edb33667 | 642 | |
edb33667 | 643 | printk(KERN_ERR "ata%u: command timeout\n", ap->id); |
11a56d24 | 644 | qc->err_mask |= AC_ERR_TIMEOUT; |
a72ec4ce | 645 | ata_eh_qc_complete(qc); |
edb33667 TH |
646 | |
647 | sil24_reset_controller(ap); | |
648 | } | |
649 | ||
8746618d TH |
650 | static void sil24_error_intr(struct ata_port *ap, u32 slot_stat) |
651 | { | |
652 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
6a575fa9 | 653 | struct sil24_port_priv *pp = ap->private_data; |
4b4a5eae | 654 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
8746618d | 655 | u32 irq_stat, cmd_err, sstatus, serror; |
a7dac447 | 656 | unsigned int err_mask; |
8746618d TH |
657 | |
658 | irq_stat = readl(port + PORT_IRQ_STAT); | |
ad6e90f6 TH |
659 | writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */ |
660 | ||
661 | if (!(irq_stat & PORT_IRQ_ERROR)) { | |
662 | /* ignore non-completion, non-error irqs for now */ | |
663 | printk(KERN_WARNING DRV_NAME | |
664 | "ata%u: non-error exception irq (irq_stat %x)\n", | |
665 | ap->id, irq_stat); | |
666 | return; | |
667 | } | |
668 | ||
8746618d TH |
669 | cmd_err = readl(port + PORT_CMD_ERR); |
670 | sstatus = readl(port + PORT_SSTATUS); | |
671 | serror = readl(port + PORT_SERROR); | |
8746618d TH |
672 | if (serror) |
673 | writel(serror, port + PORT_SERROR); | |
674 | ||
c0ab4242 TH |
675 | /* |
676 | * Don't log ATAPI device errors. They're supposed to happen | |
677 | * and any serious errors will be logged using sense data by | |
678 | * the SCSI layer. | |
679 | */ | |
680 | if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB) | |
681 | printk("ata%u: error interrupt on port%d\n" | |
682 | " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n", | |
683 | ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror); | |
8746618d | 684 | |
6a575fa9 TH |
685 | if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) { |
686 | /* | |
687 | * Device is reporting error, tf registers are valid. | |
688 | */ | |
689 | sil24_update_tf(ap); | |
a7dac447 | 690 | err_mask = ac_err_mask(pp->tf.command); |
7d1ce682 | 691 | sil24_restart_controller(ap); |
6a575fa9 TH |
692 | } else { |
693 | /* | |
694 | * Other errors. libata currently doesn't have any | |
695 | * mechanism to report these errors. Just turn on | |
696 | * ATA_ERR. | |
697 | */ | |
a7dac447 | 698 | err_mask = AC_ERR_OTHER; |
7d1ce682 | 699 | sil24_reset_controller(ap); |
6a575fa9 TH |
700 | } |
701 | ||
a22e2eb0 AL |
702 | if (qc) { |
703 | qc->err_mask |= err_mask; | |
704 | ata_qc_complete(qc); | |
705 | } | |
8746618d TH |
706 | } |
707 | ||
edb33667 TH |
708 | static inline void sil24_host_intr(struct ata_port *ap) |
709 | { | |
710 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
4b4a5eae | 711 | void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr; |
edb33667 TH |
712 | u32 slot_stat; |
713 | ||
714 | slot_stat = readl(port + PORT_SLOT_STAT); | |
715 | if (!(slot_stat & HOST_SSTAT_ATTN)) { | |
6a575fa9 TH |
716 | struct sil24_port_priv *pp = ap->private_data; |
717 | /* | |
718 | * !HOST_SSAT_ATTN guarantees successful completion, | |
719 | * so reading back tf registers is unnecessary for | |
720 | * most commands. TODO: read tf registers for | |
721 | * commands which require these values on successful | |
722 | * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER, | |
723 | * DEVICE RESET and READ PORT MULTIPLIER (any more?). | |
724 | */ | |
725 | sil24_update_tf(ap); | |
726 | ||
a22e2eb0 AL |
727 | if (qc) { |
728 | qc->err_mask |= ac_err_mask(pp->tf.command); | |
729 | ata_qc_complete(qc); | |
730 | } | |
8746618d TH |
731 | } else |
732 | sil24_error_intr(ap, slot_stat); | |
edb33667 TH |
733 | } |
734 | ||
735 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs) | |
736 | { | |
737 | struct ata_host_set *host_set = dev_instance; | |
738 | struct sil24_host_priv *hpriv = host_set->private_data; | |
739 | unsigned handled = 0; | |
740 | u32 status; | |
741 | int i; | |
742 | ||
743 | status = readl(hpriv->host_base + HOST_IRQ_STAT); | |
744 | ||
06460aea TH |
745 | if (status == 0xffffffff) { |
746 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
747 | "PCI fault or device removal?\n"); | |
748 | goto out; | |
749 | } | |
750 | ||
edb33667 TH |
751 | if (!(status & IRQ_STAT_4PORTS)) |
752 | goto out; | |
753 | ||
754 | spin_lock(&host_set->lock); | |
755 | ||
756 | for (i = 0; i < host_set->n_ports; i++) | |
757 | if (status & (1 << i)) { | |
758 | struct ata_port *ap = host_set->ports[i]; | |
3cc4571c | 759 | if (ap && !(ap->flags & ATA_FLAG_PORT_DISABLED)) { |
edb33667 | 760 | sil24_host_intr(host_set->ports[i]); |
3cc4571c TH |
761 | handled++; |
762 | } else | |
763 | printk(KERN_ERR DRV_NAME | |
764 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
765 | } |
766 | ||
767 | spin_unlock(&host_set->lock); | |
768 | out: | |
769 | return IRQ_RETVAL(handled); | |
770 | } | |
771 | ||
6037d6bb JG |
772 | static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev) |
773 | { | |
774 | const size_t cb_size = sizeof(*pp->cmd_block); | |
775 | ||
776 | dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma); | |
777 | } | |
778 | ||
edb33667 TH |
779 | static int sil24_port_start(struct ata_port *ap) |
780 | { | |
781 | struct device *dev = ap->host_set->dev; | |
edb33667 | 782 | struct sil24_port_priv *pp; |
69ad185f | 783 | union sil24_cmd_block *cb; |
edb33667 TH |
784 | size_t cb_size = sizeof(*cb); |
785 | dma_addr_t cb_dma; | |
6037d6bb | 786 | int rc = -ENOMEM; |
edb33667 | 787 | |
6037d6bb | 788 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); |
edb33667 | 789 | if (!pp) |
6037d6bb | 790 | goto err_out; |
edb33667 | 791 | |
6a575fa9 TH |
792 | pp->tf.command = ATA_DRDY; |
793 | ||
edb33667 | 794 | cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb JG |
795 | if (!cb) |
796 | goto err_out_pp; | |
edb33667 TH |
797 | memset(cb, 0, cb_size); |
798 | ||
6037d6bb JG |
799 | rc = ata_pad_alloc(ap, dev); |
800 | if (rc) | |
801 | goto err_out_pad; | |
802 | ||
edb33667 TH |
803 | pp->cmd_block = cb; |
804 | pp->cmd_block_dma = cb_dma; | |
805 | ||
806 | ap->private_data = pp; | |
807 | ||
808 | return 0; | |
6037d6bb JG |
809 | |
810 | err_out_pad: | |
811 | sil24_cblk_free(pp, dev); | |
812 | err_out_pp: | |
813 | kfree(pp); | |
814 | err_out: | |
815 | return rc; | |
edb33667 TH |
816 | } |
817 | ||
818 | static void sil24_port_stop(struct ata_port *ap) | |
819 | { | |
820 | struct device *dev = ap->host_set->dev; | |
821 | struct sil24_port_priv *pp = ap->private_data; | |
edb33667 | 822 | |
6037d6bb | 823 | sil24_cblk_free(pp, dev); |
e9c05afa | 824 | ata_pad_free(ap, dev); |
edb33667 TH |
825 | kfree(pp); |
826 | } | |
827 | ||
828 | static void sil24_host_stop(struct ata_host_set *host_set) | |
829 | { | |
830 | struct sil24_host_priv *hpriv = host_set->private_data; | |
831 | ||
832 | iounmap(hpriv->host_base); | |
833 | iounmap(hpriv->port_base); | |
834 | kfree(hpriv); | |
835 | } | |
836 | ||
837 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) | |
838 | { | |
839 | static int printed_version = 0; | |
840 | unsigned int board_id = (unsigned int)ent->driver_data; | |
042c21fd | 841 | struct ata_port_info *pinfo = &sil24_port_info[board_id]; |
edb33667 TH |
842 | struct ata_probe_ent *probe_ent = NULL; |
843 | struct sil24_host_priv *hpriv = NULL; | |
4b4a5eae AV |
844 | void __iomem *host_base = NULL; |
845 | void __iomem *port_base = NULL; | |
edb33667 TH |
846 | int i, rc; |
847 | ||
848 | if (!printed_version++) | |
a9524a76 | 849 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 TH |
850 | |
851 | rc = pci_enable_device(pdev); | |
852 | if (rc) | |
853 | return rc; | |
854 | ||
855 | rc = pci_request_regions(pdev, DRV_NAME); | |
856 | if (rc) | |
857 | goto out_disable; | |
858 | ||
859 | rc = -ENOMEM; | |
860 | /* ioremap mmio registers */ | |
861 | host_base = ioremap(pci_resource_start(pdev, 0), | |
862 | pci_resource_len(pdev, 0)); | |
863 | if (!host_base) | |
864 | goto out_free; | |
865 | port_base = ioremap(pci_resource_start(pdev, 2), | |
866 | pci_resource_len(pdev, 2)); | |
867 | if (!port_base) | |
868 | goto out_free; | |
869 | ||
870 | /* allocate & init probe_ent and hpriv */ | |
871 | probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL); | |
872 | if (!probe_ent) | |
873 | goto out_free; | |
874 | ||
875 | hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL); | |
876 | if (!hpriv) | |
877 | goto out_free; | |
878 | ||
879 | memset(probe_ent, 0, sizeof(*probe_ent)); | |
880 | probe_ent->dev = pci_dev_to_dev(pdev); | |
881 | INIT_LIST_HEAD(&probe_ent->node); | |
882 | ||
042c21fd TH |
883 | probe_ent->sht = pinfo->sht; |
884 | probe_ent->host_flags = pinfo->host_flags; | |
885 | probe_ent->pio_mask = pinfo->pio_mask; | |
886 | probe_ent->udma_mask = pinfo->udma_mask; | |
887 | probe_ent->port_ops = pinfo->port_ops; | |
888 | probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags); | |
edb33667 TH |
889 | |
890 | probe_ent->irq = pdev->irq; | |
891 | probe_ent->irq_flags = SA_SHIRQ; | |
892 | probe_ent->mmio_base = port_base; | |
893 | probe_ent->private_data = hpriv; | |
894 | ||
895 | memset(hpriv, 0, sizeof(*hpriv)); | |
896 | hpriv->host_base = host_base; | |
897 | hpriv->port_base = port_base; | |
898 | ||
899 | /* | |
900 | * Configure the device | |
901 | */ | |
902 | /* | |
903 | * FIXME: This device is certainly 64-bit capable. We just | |
904 | * don't know how to use it. After fixing 32bit activation in | |
905 | * this function, enable 64bit masks here. | |
906 | */ | |
907 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
908 | if (rc) { | |
a9524a76 JG |
909 | dev_printk(KERN_ERR, &pdev->dev, |
910 | "32-bit DMA enable failed\n"); | |
edb33667 TH |
911 | goto out_free; |
912 | } | |
913 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
914 | if (rc) { | |
a9524a76 JG |
915 | dev_printk(KERN_ERR, &pdev->dev, |
916 | "32-bit consistent DMA enable failed\n"); | |
edb33667 TH |
917 | goto out_free; |
918 | } | |
919 | ||
920 | /* GPIO off */ | |
921 | writel(0, host_base + HOST_FLASH_CMD); | |
922 | ||
923 | /* Mask interrupts during initialization */ | |
924 | writel(0, host_base + HOST_CTRL); | |
925 | ||
926 | for (i = 0; i < probe_ent->n_ports; i++) { | |
4b4a5eae | 927 | void __iomem *port = port_base + i * PORT_REGS_SIZE; |
edb33667 TH |
928 | unsigned long portu = (unsigned long)port; |
929 | u32 tmp; | |
930 | int cnt; | |
931 | ||
4f50c3cb | 932 | probe_ent->port[i].cmd_addr = portu + PORT_PRB; |
edb33667 TH |
933 | probe_ent->port[i].scr_addr = portu + PORT_SCONTROL; |
934 | ||
935 | ata_std_ports(&probe_ent->port[i]); | |
936 | ||
937 | /* Initial PHY setting */ | |
938 | writel(0x20c, port + PORT_PHY_CFG); | |
939 | ||
940 | /* Clear port RST */ | |
941 | tmp = readl(port + PORT_CTRL_STAT); | |
942 | if (tmp & PORT_CS_PORT_RST) { | |
943 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
944 | readl(port + PORT_CTRL_STAT); /* sync */ | |
945 | for (cnt = 0; cnt < 10; cnt++) { | |
946 | msleep(10); | |
947 | tmp = readl(port + PORT_CTRL_STAT); | |
948 | if (!(tmp & PORT_CS_PORT_RST)) | |
949 | break; | |
950 | } | |
951 | if (tmp & PORT_CS_PORT_RST) | |
a9524a76 JG |
952 | dev_printk(KERN_ERR, &pdev->dev, |
953 | "failed to clear port RST\n"); | |
edb33667 TH |
954 | } |
955 | ||
956 | /* Zero error counters. */ | |
957 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
958 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
959 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
960 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
961 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
962 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
963 | ||
964 | /* FIXME: 32bit activation? */ | |
965 | writel(0, port + PORT_ACTIVATE_UPPER_ADDR); | |
966 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT); | |
967 | ||
968 | /* Configure interrupts */ | |
969 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
970 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | PORT_IRQ_SDB_FIS, | |
971 | port + PORT_IRQ_ENABLE_SET); | |
972 | ||
973 | /* Clear interrupts */ | |
974 | writel(0x0fff0fff, port + PORT_IRQ_STAT); | |
975 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
923f1225 TH |
976 | |
977 | /* Clear port multiplier enable and resume bits */ | |
978 | writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR); | |
979 | ||
980 | /* Reset itself */ | |
981 | if (__sil24_reset_controller(port)) | |
a9524a76 JG |
982 | dev_printk(KERN_ERR, &pdev->dev, |
983 | "failed to reset controller\n"); | |
edb33667 TH |
984 | } |
985 | ||
986 | /* Turn on interrupts */ | |
987 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
988 | ||
989 | pci_set_master(pdev); | |
990 | ||
1483467f | 991 | /* FIXME: check ata_device_add return value */ |
edb33667 TH |
992 | ata_device_add(probe_ent); |
993 | ||
994 | kfree(probe_ent); | |
995 | return 0; | |
996 | ||
997 | out_free: | |
998 | if (host_base) | |
999 | iounmap(host_base); | |
1000 | if (port_base) | |
1001 | iounmap(port_base); | |
1002 | kfree(probe_ent); | |
1003 | kfree(hpriv); | |
1004 | pci_release_regions(pdev); | |
1005 | out_disable: | |
1006 | pci_disable_device(pdev); | |
1007 | return rc; | |
1008 | } | |
1009 | ||
1010 | static int __init sil24_init(void) | |
1011 | { | |
1012 | return pci_module_init(&sil24_pci_driver); | |
1013 | } | |
1014 | ||
1015 | static void __exit sil24_exit(void) | |
1016 | { | |
1017 | pci_unregister_driver(&sil24_pci_driver); | |
1018 | } | |
1019 | ||
1020 | MODULE_AUTHOR("Tejun Heo"); | |
1021 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1022 | MODULE_LICENSE("GPL"); | |
1023 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
1024 | ||
1025 | module_init(sil24_init); | |
1026 | module_exit(sil24_exit); |