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1da177e4 LT |
1 | /* |
2 | * sata_nv.c - NVIDIA nForce SATA | |
3 | * | |
4 | * Copyright 2004 NVIDIA Corp. All rights reserved. | |
5 | * Copyright 2004 Andrew Chew | |
6 | * | |
aa7e16d6 JG |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
1da177e4 | 21 | * |
af36d7f0 JG |
22 | * |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
25 | * | |
26 | * No hardware documentation available outside of NVIDIA. | |
27 | * This driver programs the NVIDIA SATA controller in a similar | |
28 | * fashion as with other PCI IDE BMDMA controllers, with a few | |
29 | * NV-specific details such as register offsets, SATA phy location, | |
30 | * hotplug info, etc. | |
31 | * | |
1da177e4 LT |
32 | */ |
33 | ||
34 | #include <linux/config.h> | |
35 | #include <linux/kernel.h> | |
36 | #include <linux/module.h> | |
37 | #include <linux/pci.h> | |
38 | #include <linux/init.h> | |
39 | #include <linux/blkdev.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/interrupt.h> | |
a9524a76 | 42 | #include <linux/device.h> |
1da177e4 LT |
43 | #include <scsi/scsi_host.h> |
44 | #include <linux/libata.h> | |
45 | ||
46 | #define DRV_NAME "sata_nv" | |
af64371a | 47 | #define DRV_VERSION "0.9" |
1da177e4 | 48 | |
10ad05df JG |
49 | enum { |
50 | NV_PORTS = 2, | |
51 | NV_PIO_MASK = 0x1f, | |
52 | NV_MWDMA_MASK = 0x07, | |
53 | NV_UDMA_MASK = 0x7f, | |
54 | NV_PORT0_SCR_REG_OFFSET = 0x00, | |
55 | NV_PORT1_SCR_REG_OFFSET = 0x40, | |
1da177e4 | 56 | |
27e4b274 | 57 | /* INT_STATUS/ENABLE */ |
10ad05df | 58 | NV_INT_STATUS = 0x10, |
10ad05df | 59 | NV_INT_ENABLE = 0x11, |
27e4b274 | 60 | NV_INT_STATUS_CK804 = 0x440, |
10ad05df | 61 | NV_INT_ENABLE_CK804 = 0x441, |
1da177e4 | 62 | |
27e4b274 TH |
63 | /* INT_STATUS/ENABLE bits */ |
64 | NV_INT_DEV = 0x01, | |
65 | NV_INT_PM = 0x02, | |
66 | NV_INT_ADDED = 0x04, | |
67 | NV_INT_REMOVED = 0x08, | |
68 | ||
69 | NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */ | |
70 | ||
39f87582 TH |
71 | NV_INT_ALL = 0x0f, |
72 | NV_INT_MASK = NV_INT_DEV, | |
73 | ||
27e4b274 | 74 | /* INT_CONFIG */ |
10ad05df JG |
75 | NV_INT_CONFIG = 0x12, |
76 | NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI | |
1da177e4 | 77 | |
10ad05df JG |
78 | // For PCI config register 20 |
79 | NV_MCP_SATA_CFG_20 = 0x50, | |
80 | NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04, | |
81 | }; | |
1da177e4 LT |
82 | |
83 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
ada364e8 TH |
84 | static void nv_ck804_host_stop(struct ata_host_set *host_set); |
85 | static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance, | |
86 | struct pt_regs *regs); | |
87 | static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance, | |
88 | struct pt_regs *regs); | |
89 | static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance, | |
90 | struct pt_regs *regs); | |
1da177e4 LT |
91 | static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg); |
92 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 93 | |
39f87582 TH |
94 | static void nv_nf2_freeze(struct ata_port *ap); |
95 | static void nv_nf2_thaw(struct ata_port *ap); | |
96 | static void nv_ck804_freeze(struct ata_port *ap); | |
97 | static void nv_ck804_thaw(struct ata_port *ap); | |
98 | static void nv_error_handler(struct ata_port *ap); | |
99 | ||
1da177e4 LT |
100 | enum nv_host_type |
101 | { | |
102 | GENERIC, | |
103 | NFORCE2, | |
27e4b274 | 104 | NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ |
e710245b | 105 | CK804 |
1da177e4 LT |
106 | }; |
107 | ||
3b7d697d | 108 | static const struct pci_device_id nv_pci_tbl[] = { |
1da177e4 LT |
109 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, |
110 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 }, | |
111 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, | |
112 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 }, | |
113 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, | |
114 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 }, | |
115 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA, | |
116 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
117 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2, | |
118 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
119 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA, | |
120 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
121 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2, | |
122 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 }, | |
541134cf | 123 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA, |
e710245b | 124 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
541134cf | 125 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2, |
e710245b | 126 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
541134cf | 127 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA, |
e710245b | 128 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
e86ee668 | 129 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2, |
e710245b | 130 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, |
4c5c8161 AC |
131 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA, |
132 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, | |
133 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2, | |
134 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, | |
135 | { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3, | |
136 | PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC }, | |
1da177e4 LT |
137 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
138 | PCI_ANY_ID, PCI_ANY_ID, | |
139 | PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC }, | |
541134cf DD |
140 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
141 | PCI_ANY_ID, PCI_ANY_ID, | |
142 | PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC }, | |
1da177e4 LT |
143 | { 0, } /* terminate list */ |
144 | }; | |
145 | ||
1da177e4 LT |
146 | static struct pci_driver nv_pci_driver = { |
147 | .name = DRV_NAME, | |
148 | .id_table = nv_pci_tbl, | |
149 | .probe = nv_init_one, | |
150 | .remove = ata_pci_remove_one, | |
151 | }; | |
152 | ||
193515d5 | 153 | static struct scsi_host_template nv_sht = { |
1da177e4 LT |
154 | .module = THIS_MODULE, |
155 | .name = DRV_NAME, | |
156 | .ioctl = ata_scsi_ioctl, | |
157 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
158 | .can_queue = ATA_DEF_QUEUE, |
159 | .this_id = ATA_SHT_THIS_ID, | |
160 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
161 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
162 | .emulated = ATA_SHT_EMULATED, | |
163 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
164 | .proc_name = DRV_NAME, | |
165 | .dma_boundary = ATA_DMA_BOUNDARY, | |
166 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 167 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 168 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
169 | }; |
170 | ||
ada364e8 | 171 | static const struct ata_port_operations nv_generic_ops = { |
1da177e4 LT |
172 | .port_disable = ata_port_disable, |
173 | .tf_load = ata_tf_load, | |
174 | .tf_read = ata_tf_read, | |
175 | .exec_command = ata_exec_command, | |
176 | .check_status = ata_check_status, | |
177 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
178 | .bmdma_setup = ata_bmdma_setup, |
179 | .bmdma_start = ata_bmdma_start, | |
180 | .bmdma_stop = ata_bmdma_stop, | |
181 | .bmdma_status = ata_bmdma_status, | |
182 | .qc_prep = ata_qc_prep, | |
183 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
184 | .freeze = ata_bmdma_freeze, |
185 | .thaw = ata_bmdma_thaw, | |
186 | .error_handler = nv_error_handler, | |
187 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a6b2c5d4 | 188 | .data_xfer = ata_pio_data_xfer, |
ada364e8 | 189 | .irq_handler = nv_generic_interrupt, |
1da177e4 LT |
190 | .irq_clear = ata_bmdma_irq_clear, |
191 | .scr_read = nv_scr_read, | |
192 | .scr_write = nv_scr_write, | |
193 | .port_start = ata_port_start, | |
194 | .port_stop = ata_port_stop, | |
e6faf082 | 195 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
196 | }; |
197 | ||
ada364e8 TH |
198 | static const struct ata_port_operations nv_nf2_ops = { |
199 | .port_disable = ata_port_disable, | |
200 | .tf_load = ata_tf_load, | |
201 | .tf_read = ata_tf_read, | |
202 | .exec_command = ata_exec_command, | |
203 | .check_status = ata_check_status, | |
204 | .dev_select = ata_std_dev_select, | |
ada364e8 TH |
205 | .bmdma_setup = ata_bmdma_setup, |
206 | .bmdma_start = ata_bmdma_start, | |
207 | .bmdma_stop = ata_bmdma_stop, | |
208 | .bmdma_status = ata_bmdma_status, | |
209 | .qc_prep = ata_qc_prep, | |
210 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
211 | .freeze = nv_nf2_freeze, |
212 | .thaw = nv_nf2_thaw, | |
213 | .error_handler = nv_error_handler, | |
214 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
ada364e8 TH |
215 | .data_xfer = ata_pio_data_xfer, |
216 | .irq_handler = nv_nf2_interrupt, | |
217 | .irq_clear = ata_bmdma_irq_clear, | |
218 | .scr_read = nv_scr_read, | |
219 | .scr_write = nv_scr_write, | |
220 | .port_start = ata_port_start, | |
221 | .port_stop = ata_port_stop, | |
222 | .host_stop = ata_pci_host_stop, | |
223 | }; | |
224 | ||
225 | static const struct ata_port_operations nv_ck804_ops = { | |
226 | .port_disable = ata_port_disable, | |
227 | .tf_load = ata_tf_load, | |
228 | .tf_read = ata_tf_read, | |
229 | .exec_command = ata_exec_command, | |
230 | .check_status = ata_check_status, | |
231 | .dev_select = ata_std_dev_select, | |
ada364e8 TH |
232 | .bmdma_setup = ata_bmdma_setup, |
233 | .bmdma_start = ata_bmdma_start, | |
234 | .bmdma_stop = ata_bmdma_stop, | |
235 | .bmdma_status = ata_bmdma_status, | |
236 | .qc_prep = ata_qc_prep, | |
237 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
238 | .freeze = nv_ck804_freeze, |
239 | .thaw = nv_ck804_thaw, | |
240 | .error_handler = nv_error_handler, | |
241 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
ada364e8 TH |
242 | .data_xfer = ata_pio_data_xfer, |
243 | .irq_handler = nv_ck804_interrupt, | |
244 | .irq_clear = ata_bmdma_irq_clear, | |
245 | .scr_read = nv_scr_read, | |
246 | .scr_write = nv_scr_write, | |
247 | .port_start = ata_port_start, | |
248 | .port_stop = ata_port_stop, | |
249 | .host_stop = nv_ck804_host_stop, | |
250 | }; | |
251 | ||
ada364e8 TH |
252 | static struct ata_port_info nv_port_info[] = { |
253 | /* generic */ | |
254 | { | |
255 | .sht = &nv_sht, | |
39f87582 | 256 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
ada364e8 TH |
257 | .pio_mask = NV_PIO_MASK, |
258 | .mwdma_mask = NV_MWDMA_MASK, | |
259 | .udma_mask = NV_UDMA_MASK, | |
260 | .port_ops = &nv_generic_ops, | |
261 | }, | |
262 | /* nforce2/3 */ | |
263 | { | |
264 | .sht = &nv_sht, | |
39f87582 | 265 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
ada364e8 TH |
266 | .pio_mask = NV_PIO_MASK, |
267 | .mwdma_mask = NV_MWDMA_MASK, | |
268 | .udma_mask = NV_UDMA_MASK, | |
269 | .port_ops = &nv_nf2_ops, | |
270 | }, | |
271 | /* ck804 */ | |
272 | { | |
273 | .sht = &nv_sht, | |
39f87582 | 274 | .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
ada364e8 TH |
275 | .pio_mask = NV_PIO_MASK, |
276 | .mwdma_mask = NV_MWDMA_MASK, | |
277 | .udma_mask = NV_UDMA_MASK, | |
278 | .port_ops = &nv_ck804_ops, | |
279 | }, | |
1da177e4 LT |
280 | }; |
281 | ||
282 | MODULE_AUTHOR("NVIDIA"); | |
283 | MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); | |
284 | MODULE_LICENSE("GPL"); | |
285 | MODULE_DEVICE_TABLE(pci, nv_pci_tbl); | |
286 | MODULE_VERSION(DRV_VERSION); | |
287 | ||
ada364e8 TH |
288 | static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance, |
289 | struct pt_regs *regs) | |
1da177e4 LT |
290 | { |
291 | struct ata_host_set *host_set = dev_instance; | |
1da177e4 LT |
292 | unsigned int i; |
293 | unsigned int handled = 0; | |
294 | unsigned long flags; | |
295 | ||
296 | spin_lock_irqsave(&host_set->lock, flags); | |
297 | ||
298 | for (i = 0; i < host_set->n_ports; i++) { | |
299 | struct ata_port *ap; | |
300 | ||
301 | ap = host_set->ports[i]; | |
c1389503 | 302 | if (ap && |
029f5468 | 303 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
304 | struct ata_queued_cmd *qc; |
305 | ||
306 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 307 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 | 308 | handled += ata_host_intr(ap, qc); |
b887030a AC |
309 | else |
310 | // No request pending? Clear interrupt status | |
311 | // anyway, in case there's one pending. | |
312 | ap->ops->check_status(ap); | |
1da177e4 LT |
313 | } |
314 | ||
315 | } | |
316 | ||
1da177e4 LT |
317 | spin_unlock_irqrestore(&host_set->lock, flags); |
318 | ||
319 | return IRQ_RETVAL(handled); | |
320 | } | |
321 | ||
ada364e8 TH |
322 | static int nv_host_intr(struct ata_port *ap, u8 irq_stat) |
323 | { | |
324 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
325 | int handled; | |
326 | ||
327 | /* bail out if not our interrupt */ | |
328 | if (!(irq_stat & NV_INT_DEV)) | |
329 | return 0; | |
330 | ||
331 | /* DEV interrupt w/ no active qc? */ | |
332 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
333 | ata_check_status(ap); | |
334 | return 1; | |
335 | } | |
336 | ||
337 | /* handle interrupt */ | |
338 | handled = ata_host_intr(ap, qc); | |
339 | if (unlikely(!handled)) { | |
340 | /* spurious, clear it */ | |
341 | ata_check_status(ap); | |
342 | } | |
343 | ||
344 | return 1; | |
345 | } | |
346 | ||
347 | static irqreturn_t nv_do_interrupt(struct ata_host_set *host_set, u8 irq_stat) | |
348 | { | |
349 | int i, handled = 0; | |
350 | ||
351 | for (i = 0; i < host_set->n_ports; i++) { | |
352 | struct ata_port *ap = host_set->ports[i]; | |
353 | ||
354 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) | |
355 | handled += nv_host_intr(ap, irq_stat); | |
356 | ||
357 | irq_stat >>= NV_INT_PORT_SHIFT; | |
358 | } | |
359 | ||
360 | return IRQ_RETVAL(handled); | |
361 | } | |
362 | ||
363 | static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance, | |
364 | struct pt_regs *regs) | |
365 | { | |
366 | struct ata_host_set *host_set = dev_instance; | |
367 | unsigned long flags; | |
368 | u8 irq_stat; | |
369 | irqreturn_t ret; | |
370 | ||
371 | spin_lock_irqsave(&host_set->lock, flags); | |
372 | irq_stat = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); | |
373 | ret = nv_do_interrupt(host_set, irq_stat); | |
374 | spin_unlock_irqrestore(&host_set->lock, flags); | |
375 | ||
376 | return ret; | |
377 | } | |
378 | ||
379 | static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance, | |
380 | struct pt_regs *regs) | |
381 | { | |
382 | struct ata_host_set *host_set = dev_instance; | |
383 | unsigned long flags; | |
384 | u8 irq_stat; | |
385 | irqreturn_t ret; | |
386 | ||
387 | spin_lock_irqsave(&host_set->lock, flags); | |
388 | irq_stat = readb(host_set->mmio_base + NV_INT_STATUS_CK804); | |
389 | ret = nv_do_interrupt(host_set, irq_stat); | |
390 | spin_unlock_irqrestore(&host_set->lock, flags); | |
391 | ||
392 | return ret; | |
393 | } | |
394 | ||
1da177e4 LT |
395 | static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg) |
396 | { | |
1da177e4 LT |
397 | if (sc_reg > SCR_CONTROL) |
398 | return 0xffffffffU; | |
399 | ||
02cbd926 | 400 | return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
401 | } |
402 | ||
403 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
404 | { | |
1da177e4 LT |
405 | if (sc_reg > SCR_CONTROL) |
406 | return; | |
407 | ||
02cbd926 | 408 | iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
409 | } |
410 | ||
39f87582 TH |
411 | static void nv_nf2_freeze(struct ata_port *ap) |
412 | { | |
413 | unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr; | |
414 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | |
415 | u8 mask; | |
416 | ||
417 | mask = inb(scr_addr + NV_INT_ENABLE); | |
418 | mask &= ~(NV_INT_ALL << shift); | |
419 | outb(mask, scr_addr + NV_INT_ENABLE); | |
420 | } | |
421 | ||
422 | static void nv_nf2_thaw(struct ata_port *ap) | |
423 | { | |
424 | unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr; | |
425 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | |
426 | u8 mask; | |
427 | ||
428 | outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); | |
429 | ||
430 | mask = inb(scr_addr + NV_INT_ENABLE); | |
431 | mask |= (NV_INT_MASK << shift); | |
432 | outb(mask, scr_addr + NV_INT_ENABLE); | |
433 | } | |
434 | ||
435 | static void nv_ck804_freeze(struct ata_port *ap) | |
436 | { | |
437 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
438 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | |
439 | u8 mask; | |
440 | ||
441 | mask = readb(mmio_base + NV_INT_ENABLE_CK804); | |
442 | mask &= ~(NV_INT_ALL << shift); | |
443 | writeb(mask, mmio_base + NV_INT_ENABLE_CK804); | |
444 | } | |
445 | ||
446 | static void nv_ck804_thaw(struct ata_port *ap) | |
447 | { | |
448 | void __iomem *mmio_base = ap->host_set->mmio_base; | |
449 | int shift = ap->port_no * NV_INT_PORT_SHIFT; | |
450 | u8 mask; | |
451 | ||
452 | writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804); | |
453 | ||
454 | mask = readb(mmio_base + NV_INT_ENABLE_CK804); | |
455 | mask |= (NV_INT_MASK << shift); | |
456 | writeb(mask, mmio_base + NV_INT_ENABLE_CK804); | |
457 | } | |
458 | ||
459 | static int nv_hardreset(struct ata_port *ap, unsigned int *class) | |
460 | { | |
461 | unsigned int dummy; | |
462 | ||
463 | /* SATA hardreset fails to retrieve proper device signature on | |
464 | * some controllers. Don't classify on hardreset. For more | |
465 | * info, see http://bugme.osdl.org/show_bug.cgi?id=3352 | |
466 | */ | |
467 | return sata_std_hardreset(ap, &dummy); | |
468 | } | |
469 | ||
470 | static void nv_error_handler(struct ata_port *ap) | |
471 | { | |
472 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, | |
473 | nv_hardreset, ata_std_postreset); | |
474 | } | |
475 | ||
1da177e4 LT |
476 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
477 | { | |
478 | static int printed_version = 0; | |
1da177e4 LT |
479 | struct ata_port_info *ppi; |
480 | struct ata_probe_ent *probe_ent; | |
481 | int pci_dev_busy = 0; | |
482 | int rc; | |
483 | u32 bar; | |
02cbd926 | 484 | unsigned long base; |
1da177e4 LT |
485 | |
486 | // Make sure this is a SATA controller by counting the number of bars | |
487 | // (NVIDIA SATA controllers will always have six bars). Otherwise, | |
488 | // it's an IDE controller and we ignore it. | |
489 | for (bar=0; bar<6; bar++) | |
490 | if (pci_resource_start(pdev, bar) == 0) | |
491 | return -ENODEV; | |
492 | ||
493 | if (!printed_version++) | |
a9524a76 | 494 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
495 | |
496 | rc = pci_enable_device(pdev); | |
497 | if (rc) | |
498 | goto err_out; | |
499 | ||
500 | rc = pci_request_regions(pdev, DRV_NAME); | |
501 | if (rc) { | |
502 | pci_dev_busy = 1; | |
503 | goto err_out_disable; | |
504 | } | |
505 | ||
506 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
507 | if (rc) | |
508 | goto err_out_regions; | |
509 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
510 | if (rc) | |
511 | goto err_out_regions; | |
512 | ||
513 | rc = -ENOMEM; | |
514 | ||
ada364e8 | 515 | ppi = &nv_port_info[ent->driver_data]; |
47a86593 | 516 | probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
1da177e4 LT |
517 | if (!probe_ent) |
518 | goto err_out_regions; | |
519 | ||
02cbd926 JG |
520 | probe_ent->mmio_base = pci_iomap(pdev, 5, 0); |
521 | if (!probe_ent->mmio_base) { | |
522 | rc = -EIO; | |
e6faf082 | 523 | goto err_out_free_ent; |
02cbd926 | 524 | } |
1da177e4 | 525 | |
02cbd926 | 526 | base = (unsigned long)probe_ent->mmio_base; |
1da177e4 | 527 | |
02cbd926 JG |
528 | probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET; |
529 | probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET; | |
1da177e4 | 530 | |
ada364e8 TH |
531 | /* enable SATA space for CK804 */ |
532 | if (ent->driver_data == CK804) { | |
533 | u8 regval; | |
534 | ||
535 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
536 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
537 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
538 | } | |
539 | ||
1da177e4 LT |
540 | pci_set_master(pdev); |
541 | ||
542 | rc = ata_device_add(probe_ent); | |
543 | if (rc != NV_PORTS) | |
544 | goto err_out_iounmap; | |
545 | ||
1da177e4 LT |
546 | kfree(probe_ent); |
547 | ||
548 | return 0; | |
549 | ||
550 | err_out_iounmap: | |
02cbd926 | 551 | pci_iounmap(pdev, probe_ent->mmio_base); |
1da177e4 LT |
552 | err_out_free_ent: |
553 | kfree(probe_ent); | |
554 | err_out_regions: | |
555 | pci_release_regions(pdev); | |
556 | err_out_disable: | |
557 | if (!pci_dev_busy) | |
558 | pci_disable_device(pdev); | |
559 | err_out: | |
560 | return rc; | |
561 | } | |
562 | ||
ada364e8 TH |
563 | static void nv_ck804_host_stop(struct ata_host_set *host_set) |
564 | { | |
565 | struct pci_dev *pdev = to_pci_dev(host_set->dev); | |
566 | u8 regval; | |
567 | ||
568 | /* disable SATA space for CK804 */ | |
569 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
570 | regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
571 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
572 | ||
573 | ata_pci_host_stop(host_set); | |
574 | } | |
575 | ||
1da177e4 LT |
576 | static int __init nv_init(void) |
577 | { | |
578 | return pci_module_init(&nv_pci_driver); | |
579 | } | |
580 | ||
581 | static void __exit nv_exit(void) | |
582 | { | |
583 | pci_unregister_driver(&nv_pci_driver); | |
584 | } | |
585 | ||
586 | module_init(nv_init); | |
587 | module_exit(nv_exit); |