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Merge git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi-misc-2.6
[net-next-2.6.git] / drivers / scsi / qla4xxx / ql4_def.h
CommitLineData
afaf5a2d
DS		 1/*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8#ifndef __QL4_DEF_H
9#define __QL4_DEF_H
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/types.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/pci.h>
17#include <linux/dma-mapping.h>
18#include <linux/sched.h>
19#include <linux/slab.h>
20#include <linux/dmapool.h>
21#include <linux/mempool.h>
22#include <linux/spinlock.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/interrupt.h>
26#include <linux/mutex.h>
7b3595df 27#include <linux/aer.h>
afaf5a2d
DS		 28
29#include <net/tcp.h>
30#include <scsi/scsi.h>
31#include <scsi/scsi_host.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_cmnd.h>
34#include <scsi/scsi_transport.h>
35#include <scsi/scsi_transport_iscsi.h>
36
f4f5df23
VC		 37#include "ql4_dbg.h"
38#include "ql4_nx.h"
afaf5a2d
DS		 39
40#ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
41#define PCI_DEVICE_ID_QLOGIC_ISP4010 0x4010
42#endif
43
44#ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
45#define PCI_DEVICE_ID_QLOGIC_ISP4022 0x4022
d915058f
DS		 46#endif
47
48#ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
49#define PCI_DEVICE_ID_QLOGIC_ISP4032 0x4032
50#endif
afaf5a2d 51
f4f5df23
VC		 52#ifndef PCI_DEVICE_ID_QLOGIC_ISP8022
53#define PCI_DEVICE_ID_QLOGIC_ISP8022 0x8022
54#endif
55
afaf5a2d
DS		 56#define QLA_SUCCESS 0
57#define QLA_ERROR 1
58
59/*
60 * Data bit definitions
61 */
62#define BIT_0 0x1
63#define BIT_1 0x2
64#define BIT_2 0x4
65#define BIT_3 0x8
66#define BIT_4 0x10
67#define BIT_5 0x20
68#define BIT_6 0x40
69#define BIT_7 0x80
70#define BIT_8 0x100
71#define BIT_9 0x200
72#define BIT_10 0x400
73#define BIT_11 0x800
74#define BIT_12 0x1000
75#define BIT_13 0x2000
76#define BIT_14 0x4000
77#define BIT_15 0x8000
78#define BIT_16 0x10000
79#define BIT_17 0x20000
80#define BIT_18 0x40000
81#define BIT_19 0x80000
82#define BIT_20 0x100000
83#define BIT_21 0x200000
84#define BIT_22 0x400000
85#define BIT_23 0x800000
86#define BIT_24 0x1000000
87#define BIT_25 0x2000000
88#define BIT_26 0x4000000
89#define BIT_27 0x8000000
90#define BIT_28 0x10000000
91#define BIT_29 0x20000000
92#define BIT_30 0x40000000
93#define BIT_31 0x80000000
94
f4f5df23
VC		 95/**
96 * Macros to help code, maintain, etc.
97 **/
98#define ql4_printk(level, ha, format, arg...) \
99 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
100
101
afaf5a2d
DS		 102/*
103 * Host adapter default definitions
104 ***********************************/
105#define MAX_HBAS 16
106#define MAX_BUSES 1
f4f5df23 107#define MAX_TARGETS MAX_DEV_DB_ENTRIES
afaf5a2d
DS		 108#define MAX_LUNS 0xffff
109#define MAX_AEN_ENTRIES 256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
f4f5df23 110#define MAX_DDB_ENTRIES MAX_DEV_DB_ENTRIES
afaf5a2d
DS		 111#define MAX_PDU_ENTRIES 32
112#define INVALID_ENTRY 0xFFFF
113#define MAX_CMDS_TO_RISC 1024
114#define MAX_SRBS MAX_CMDS_TO_RISC
115#define MBOX_AEN_REG_COUNT 5
116#define MAX_INIT_RETRIES 5
afaf5a2d
DS		 117
118/*
119 * Buffer sizes
120 */
121#define REQUEST_QUEUE_DEPTH MAX_CMDS_TO_RISC
122#define RESPONSE_QUEUE_DEPTH 64
123#define QUEUE_SIZE 64
124#define DMA_BUFFER_SIZE 512
125
126/*
127 * Misc
128 */
129#define MAC_ADDR_LEN 6 /* in bytes */
130#define IP_ADDR_LEN 4 /* in bytes */
2a49a78e 131#define IPv6_ADDR_LEN 16 /* IPv6 address size */
afaf5a2d
DS		 132#define DRIVER_NAME "qla4xxx"
133
134#define MAX_LINKED_CMDS_PER_LUN 3
dbaf82ec 135#define MAX_REQS_SERVICED_PER_INTR 1
afaf5a2d
DS		 136
137#define ISCSI_IPADDR_SIZE 4 /* IP address size */
b1c11812 138#define ISCSI_ALIAS_SIZE 32 /* ISCSI Alias name size */
5c8bfc94 139#define ISCSI_NAME_SIZE 0xE0 /* ISCSI Name size */
afaf5a2d 140
3013cea8
VC		 141#define QL4_SESS_RECOVERY_TMO 30 /* iSCSI session */
142 /* recovery timeout */
143
afaf5a2d
DS		 144#define LSDW(x) ((u32)((u64)(x)))
145#define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
146
147/*
148 * Retry & Timeout Values
149 */
150#define MBOX_TOV 60
151#define SOFT_RESET_TOV 30
152#define RESET_INTR_TOV 3
153#define SEMAPHORE_TOV 10
f4f5df23 154#define ADAPTER_INIT_TOV 30
afaf5a2d
DS		 155#define ADAPTER_RESET_TOV 180
156#define EXTEND_CMD_TOV 60
157#define WAIT_CMD_TOV 30
158#define EH_WAIT_CMD_TOV 120
159#define FIRMWARE_UP_TOV 60
160#define RESET_FIRMWARE_TOV 30
161#define LOGOUT_TOV 10
162#define IOCB_TOV_MARGIN 10
163#define RELOGIN_TOV 18
164#define ISNS_DEREG_TOV 5
f581a3f7 165#define HBA_ONLINE_TOV 30
afaf5a2d
DS		 166
167#define MAX_RESET_HA_RETRIES 2
168
5369887a
VC		 169#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
170
afaf5a2d
DS		 171/*
172 * SCSI Request Block structure (srb) that is placed
173 * on cmd->SCp location of every I/O [We have 22 bytes available]
174 */
175struct srb {
176 struct list_head list; /* (8) */
177 struct scsi_qla_host *ha; /* HA the SP is queued on */
178 struct ddb_entry *ddb;
179 uint16_t flags; /* (1) Status flags. */
180
181#define SRB_DMA_VALID BIT_3 /* DMA Buffer mapped. */
182#define SRB_GOT_SENSE BIT_4 /* sense data recieved. */
183 uint8_t state; /* (1) Status flags. */
184
185#define SRB_NO_QUEUE_STATE 0 /* Request is in between states */
186#define SRB_FREE_STATE 1
187#define SRB_ACTIVE_STATE 3
188#define SRB_ACTIVE_TIMEOUT_STATE 4
189#define SRB_SUSPENDED_STATE 7 /* Request in suspended state */
190
191 struct scsi_cmnd *cmd; /* (4) SCSI command block */
192 dma_addr_t dma_handle; /* (4) for unmap of single transfers */
09a0f719 193 struct kref srb_ref; /* reference count for this srb */
afaf5a2d
DS		 194 uint32_t fw_ddb_index;
195 uint8_t err_id; /* error id */
196#define SRB_ERR_PORT 1 /* Request failed because "port down" */
197#define SRB_ERR_LOOP 2 /* Request failed because "loop down" */
198#define SRB_ERR_DEVICE 3 /* Request failed because "device error" */
199#define SRB_ERR_OTHER 4
200
201 uint16_t reserved;
202 uint16_t iocb_tov;
203 uint16_t iocb_cnt; /* Number of used iocbs */
204 uint16_t cc_stat;
94bced3c
KH		 205
206 /* Used for extended sense / status continuation */
207 uint8_t *req_sense_ptr;
208 uint16_t req_sense_len;
209 uint16_t reserved2;
afaf5a2d
DS		 210};
211
5c8bfc94
DS		 212/*
213 * Asynchronous Event Queue structure
214 */
215struct aen {
216 uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
217};
218
219struct ql4_aen_log {
220 int count;
221 struct aen entry[MAX_AEN_ENTRIES];
222};
223
224/*
225 * Device Database (DDB) structure
226 */
afaf5a2d
DS		 227struct ddb_entry {
228 struct list_head list; /* ddb list */
229 struct scsi_qla_host *ha;
230 struct iscsi_cls_session *sess;
231 struct iscsi_cls_conn *conn;
232
233 atomic_t state; /* DDB State */
234
235 unsigned long flags; /* DDB Flags */
236
237 unsigned long dev_scan_wait_to_start_relogin;
238 unsigned long dev_scan_wait_to_complete_relogin;
239
afaf5a2d 240 uint16_t fw_ddb_index; /* DDB firmware index */
2a49a78e 241 uint16_t options;
afaf5a2d
DS		 242 uint32_t fw_ddb_device_state; /* F/W Device State -- see ql4_fw.h */
243
244 uint32_t CmdSn;
245 uint16_t target_session_id;
246 uint16_t connection_id;
247 uint16_t exe_throttle; /* Max mumber of cmds outstanding
248 * simultaneously */
249 uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
250 * complete */
251 uint16_t default_relogin_timeout; /* Max time to wait for
252 * relogin to complete */
253 uint16_t tcp_source_port_num;
254 uint32_t default_time2wait; /* Default Min time between
255 * relogins (+aens) */
256
afaf5a2d
DS		 257 atomic_t retry_relogin_timer; /* Min Time between relogins
258 * (4000 only) */
259 atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
260 atomic_t relogin_retry_count; /* Num of times relogin has been
261 * retried */
262
263 uint16_t port;
264 uint32_t tpgt;
2a49a78e 265 uint8_t ip_addr[IP_ADDR_LEN];
afaf5a2d
DS		 266 uint8_t iscsi_name[ISCSI_NAME_SIZE]; /* 72 x48 */
267 uint8_t iscsi_alias[0x20];
41bbdbeb 268 uint8_t isid[6];
2a49a78e
VC		 269 uint16_t iscsi_max_burst_len;
270 uint16_t iscsi_max_outsnd_r2t;
271 uint16_t iscsi_first_burst_len;
272 uint16_t iscsi_max_rcv_data_seg_len;
273 uint16_t iscsi_max_snd_data_seg_len;
274
275 struct in6_addr remote_ipv6_addr;
276 struct in6_addr link_local_ipv6_addr;
afaf5a2d
DS		 277};
278
279/*
280 * DDB states.
281 */
282#define DDB_STATE_DEAD 0 /* We can no longer talk to
283 * this device */
284#define DDB_STATE_ONLINE 1 /* Device ready to accept
285 * commands */
286#define DDB_STATE_MISSING 2 /* Device logged off, trying
287 * to re-login */
288
289/*
290 * DDB flags.
291 */
292#define DF_RELOGIN 0 /* Relogin to device */
293#define DF_NO_RELOGIN 1 /* Do not relogin if IOCTL
294 * logged it out */
295#define DF_ISNS_DISCOVERED 2 /* Device was discovered via iSNS */
296#define DF_FO_MASKED 3
297
afaf5a2d
DS		 298
299#include "ql4_fw.h"
300#include "ql4_nvram.h"
301
f4f5df23
VC		 302struct ql82xx_hw_data {
303 /* Offsets for flash/nvram access (set to ~0 if not used). */
304 uint32_t flash_conf_off;
305 uint32_t flash_data_off;
306
307 uint32_t fdt_wrt_disable;
308 uint32_t fdt_erase_cmd;
309 uint32_t fdt_block_size;
310 uint32_t fdt_unprotect_sec_cmd;
311 uint32_t fdt_protect_sec_cmd;
312
313 uint32_t flt_region_flt;
314 uint32_t flt_region_fdt;
315 uint32_t flt_region_boot;
316 uint32_t flt_region_bootload;
317 uint32_t flt_region_fw;
318 uint32_t reserved;
319};
320
321struct qla4_8xxx_legacy_intr_set {
322 uint32_t int_vec_bit;
323 uint32_t tgt_status_reg;
324 uint32_t tgt_mask_reg;
325 uint32_t pci_int_reg;
326};
327
328/* MSI-X Support */
329
330#define QLA_MSIX_DEFAULT 0x00
331#define QLA_MSIX_RSP_Q 0x01
332
333#define QLA_MSIX_ENTRIES 2
334#define QLA_MIDX_DEFAULT 0
335#define QLA_MIDX_RSP_Q 1
336
337struct ql4_msix_entry {
338 int have_irq;
339 uint16_t msix_vector;
340 uint16_t msix_entry;
341};
342
343/*
344 * ISP Operations
345 */
346struct isp_operations {
347 int (*iospace_config) (struct scsi_qla_host *ha);
348 void (*pci_config) (struct scsi_qla_host *);
349 void (*disable_intrs) (struct scsi_qla_host *);
350 void (*enable_intrs) (struct scsi_qla_host *);
351 int (*start_firmware) (struct scsi_qla_host *);
352 irqreturn_t (*intr_handler) (int , void *);
353 void (*interrupt_service_routine) (struct scsi_qla_host *, uint32_t);
354 int (*reset_chip) (struct scsi_qla_host *);
355 int (*reset_firmware) (struct scsi_qla_host *);
356 void (*queue_iocb) (struct scsi_qla_host *);
357 void (*complete_iocb) (struct scsi_qla_host *);
358 uint16_t (*rd_shdw_req_q_out) (struct scsi_qla_host *);
359 uint16_t (*rd_shdw_rsp_q_in) (struct scsi_qla_host *);
360 int (*get_sys_info) (struct scsi_qla_host *);
361};
362
afaf5a2d
DS		 363/*
364 * Linux Host Adapter structure
365 */
366struct scsi_qla_host {
367 /* Linux adapter configuration data */
afaf5a2d
DS		 368 unsigned long flags;
369
5c8bfc94
DS		 370#define AF_ONLINE 0 /* 0x00000001 */
371#define AF_INIT_DONE 1 /* 0x00000002 */
372#define AF_MBOX_COMMAND 2 /* 0x00000004 */
373#define AF_MBOX_COMMAND_DONE 3 /* 0x00000008 */
f4f5df23 374#define AF_DPC_SCHEDULED 5 /* 0x00000020 */
5c8bfc94
DS		 375#define AF_INTERRUPTS_ON 6 /* 0x00000040 */
376#define AF_GET_CRASH_RECORD 7 /* 0x00000080 */
377#define AF_LINK_UP 8 /* 0x00000100 */
378#define AF_IRQ_ATTACHED 10 /* 0x00000400 */
379#define AF_DISABLE_ACB_COMPLETE 11 /* 0x00000800 */
f4f5df23
VC		 380#define AF_HBA_GOING_AWAY 12 /* 0x00001000 */
381#define AF_INTx_ENABLED 15 /* 0x00008000 */
382#define AF_MSI_ENABLED 16 /* 0x00010000 */
383#define AF_MSIX_ENABLED 17 /* 0x00020000 */
384#define AF_MBOX_COMMAND_NOPOLL 18 /* 0x00040000 */
21033639 385#define AF_FW_RECOVERY 19 /* 0x00080000 */
2232be0d
LC		 386#define AF_EEH_BUSY 20 /* 0x00100000 */
387#define AF_PCI_CHANNEL_IO_PERM_FAILURE 21 /* 0x00200000 */
afaf5a2d
DS		 388
389 unsigned long dpc_flags;
390
5c8bfc94
DS		 391#define DPC_RESET_HA 1 /* 0x00000002 */
392#define DPC_RETRY_RESET_HA 2 /* 0x00000004 */
393#define DPC_RELOGIN_DEVICE 3 /* 0x00000008 */
f4f5df23 394#define DPC_RESET_HA_FW_CONTEXT 4 /* 0x00000010 */
5c8bfc94
DS		 395#define DPC_RESET_HA_INTR 5 /* 0x00000020 */
396#define DPC_ISNS_RESTART 7 /* 0x00000080 */
397#define DPC_AEN 9 /* 0x00000200 */
398#define DPC_GET_DHCP_IP_ADDR 15 /* 0x00008000 */
065aa1b4 399#define DPC_LINK_CHANGED 18 /* 0x00040000 */
f4f5df23
VC		 400#define DPC_RESET_ACTIVE 20 /* 0x00040000 */
401#define DPC_HA_UNRECOVERABLE 21 /* 0x00080000 ISP-82xx only*/
402#define DPC_HA_NEED_QUIESCENT 22 /* 0x00100000 ISP-82xx only*/
403
5c8bfc94
DS		 404
405 struct Scsi_Host *host; /* pointer to host data */
406 uint32_t tot_ddbs;
afaf5a2d 407
f4f5df23 408 uint16_t iocb_cnt;
afaf5a2d
DS		 409
410 /* SRB cache. */
411#define SRB_MIN_REQ 128
412 mempool_t *srb_mempool;
413
414 /* pci information */
415 struct pci_dev *pdev;
416
417 struct isp_reg __iomem *reg; /* Base I/O address */
418 unsigned long pio_address;
419 unsigned long pio_length;
420#define MIN_IOBASE_LEN 0x100
421
422 uint16_t req_q_count;
afaf5a2d
DS		 423
424 unsigned long host_no;
425
426 /* NVRAM registers */
427 struct eeprom_data *nvram;
428 spinlock_t hardware_lock ____cacheline_aligned;
f4f5df23 429 uint32_t eeprom_cmd_data;
afaf5a2d
DS		 430
431 /* Counters for general statistics */
d915058f 432 uint64_t isr_count;
afaf5a2d
DS		 433 uint64_t adapter_error_count;
434 uint64_t device_error_count;
435 uint64_t total_io_count;
436 uint64_t total_mbytes_xferred;
437 uint64_t link_failure_count;
438 uint64_t invalid_crc_count;
d915058f 439 uint32_t bytes_xfered;
afaf5a2d
DS		 440 uint32_t spurious_int_count;
441 uint32_t aborted_io_count;
442 uint32_t io_timeout_count;
443 uint32_t mailbox_timeout_count;
444 uint32_t seconds_since_last_intr;
445 uint32_t seconds_since_last_heartbeat;
446 uint32_t mac_index;
447
448 /* Info Needed for Management App */
449 /* --- From GetFwVersion --- */
450 uint32_t firmware_version[2];
451 uint32_t patch_number;
452 uint32_t build_number;
5c8bfc94 453 uint32_t board_id;
afaf5a2d
DS		 454
455 /* --- From Init_FW --- */
456 /* init_cb_t *init_cb; */
457 uint16_t firmware_options;
458 uint16_t tcp_options;
459 uint8_t ip_address[IP_ADDR_LEN];
460 uint8_t subnet_mask[IP_ADDR_LEN];
461 uint8_t gateway[IP_ADDR_LEN];
462 uint8_t alias[32];
463 uint8_t name_string[256];
464 uint8_t heartbeat_interval;
afaf5a2d
DS		 465
466 /* --- From FlashSysInfo --- */
467 uint8_t my_mac[MAC_ADDR_LEN];
468 uint8_t serial_number[16];
469
470 /* --- From GetFwState --- */
471 uint32_t firmware_state;
afaf5a2d
DS		 472 uint32_t addl_fw_state;
473
474 /* Linux kernel thread */
475 struct workqueue_struct *dpc_thread;
476 struct work_struct dpc_work;
477
478 /* Linux timer thread */
479 struct timer_list timer;
480 uint32_t timer_active;
481
482 /* Recovery Timers */
afaf5a2d
DS		 483 uint32_t discovery_wait;
484 atomic_t check_relogin_timeouts;
485 uint32_t retry_reset_ha_cnt;
486 uint32_t isp_reset_timer; /* reset test timer */
487 uint32_t nic_reset_timer; /* simulated nic reset test timer */
488 int eh_start;
489 struct list_head free_srb_q;
490 uint16_t free_srb_q_count;
491 uint16_t num_srbs_allocated;
492
493 /* DMA Memory Block */
494 void *queues;
495 dma_addr_t queues_dma;
496 unsigned long queues_len;
497
498#define MEM_ALIGN_VALUE \
499 ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
500 sizeof(struct queue_entry))
501 /* request and response queue variables */
502 dma_addr_t request_dma;
503 struct queue_entry *request_ring;
504 struct queue_entry *request_ptr;
505 dma_addr_t response_dma;
506 struct queue_entry *response_ring;
507 struct queue_entry *response_ptr;
508 dma_addr_t shadow_regs_dma;
509 struct shadow_regs *shadow_regs;
510 uint16_t request_in; /* Current indexes. */
511 uint16_t request_out;
512 uint16_t response_in;
513 uint16_t response_out;
514
515 /* aen queue variables */
516 uint16_t aen_q_count; /* Number of available aen_q entries */
517 uint16_t aen_in; /* Current indexes */
518 uint16_t aen_out;
519 struct aen aen_q[MAX_AEN_ENTRIES];
520
5c8bfc94
DS		 521 struct ql4_aen_log aen_log;/* tracks all aens */
522
afaf5a2d
DS		 523 /* This mutex protects several threads to do mailbox commands
524 * concurrently.
525 */
526 struct mutex mbox_sem;
afaf5a2d
DS		 527
528 /* temporary mailbox status registers */
529 volatile uint8_t mbox_status_count;
530 volatile uint32_t mbox_status[MBOX_REG_COUNT];
531
532 /* local device database list (contains internal ddb entries) */
533 struct list_head ddb_list;
534
535 /* Map ddb_list entry by FW ddb index */
536 struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
537
94bced3c
KH		 538 /* Saved srb for status continuation entry processing */
539 struct srb *status_srb;
2a49a78e
VC		 540
541 /* IPv6 support info from InitFW */
542 uint8_t acb_version;
543 uint8_t ipv4_addr_state;
544 uint16_t ipv4_options;
545
546 uint32_t resvd2;
547 uint32_t ipv6_options;
548 uint32_t ipv6_addl_options;
549 uint8_t ipv6_link_local_state;
550 uint8_t ipv6_addr0_state;
551 uint8_t ipv6_addr1_state;
552 uint8_t ipv6_default_router_state;
553 struct in6_addr ipv6_link_local_addr;
554 struct in6_addr ipv6_addr0;
555 struct in6_addr ipv6_addr1;
556 struct in6_addr ipv6_default_router_addr;
f4f5df23
VC		 557
558 /* qla82xx specific fields */
559 struct device_reg_82xx __iomem *qla4_8xxx_reg; /* Base I/O address */
560 unsigned long nx_pcibase; /* Base I/O address */
561 uint8_t *nx_db_rd_ptr; /* Doorbell read pointer */
562 unsigned long nx_db_wr_ptr; /* Door bell write pointer */
563 unsigned long first_page_group_start;
564 unsigned long first_page_group_end;
565
566 uint32_t crb_win;
567 uint32_t curr_window;
568 uint32_t ddr_mn_window;
569 unsigned long mn_win_crb;
570 unsigned long ms_win_crb;
571 int qdr_sn_window;
572 rwlock_t hw_lock;
573 uint16_t func_num;
574 int link_width;
575
576 struct qla4_8xxx_legacy_intr_set nx_legacy_intr;
577 u32 nx_crb_mask;
578
579 uint8_t revision_id;
580 uint32_t fw_heartbeat_counter;
581
582 struct isp_operations *isp_ops;
583 struct ql82xx_hw_data hw;
584
585 struct ql4_msix_entry msix_entries[QLA_MSIX_ENTRIES];
586
587 uint32_t nx_dev_init_timeout;
588 uint32_t nx_reset_timeout;
589
590 struct completion mbx_intr_comp;
afaf5a2d
DS		 591};
592
2a49a78e
VC		 593static inline int is_ipv4_enabled(struct scsi_qla_host *ha)
594{
595 return ((ha->ipv4_options & IPOPT_IPv4_PROTOCOL_ENABLE) != 0);
596}
597
598static inline int is_ipv6_enabled(struct scsi_qla_host *ha)
599{
600 return ((ha->ipv6_options & IPV6_OPT_IPV6_PROTOCOL_ENABLE) != 0);
601}
602
afaf5a2d
DS		 603static inline int is_qla4010(struct scsi_qla_host *ha)
604{
605 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
606}
607
608static inline int is_qla4022(struct scsi_qla_host *ha)
609{
610 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
611}
612
d915058f
DS		 613static inline int is_qla4032(struct scsi_qla_host *ha)
614{
615 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
616}
617
f4f5df23
VC		 618static inline int is_qla8022(struct scsi_qla_host *ha)
619{
620 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
621}
622
2232be0d
LC		 623/* Note: Currently AER/EEH is now supported only for 8022 cards
624 * This function needs to be updated when AER/EEH is enabled
625 * for other cards.
626 */
627static inline int is_aer_supported(struct scsi_qla_host *ha)
628{
629 return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8022;
630}
631
afaf5a2d
DS		 632static inline int adapter_up(struct scsi_qla_host *ha)
633{
634 return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
635 (test_bit(AF_LINK_UP, &ha->flags) != 0);
636}
637
638static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
639{
640 return (struct scsi_qla_host *)shost->hostdata;
641}
642
643static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
644{
d915058f
DS		 645 return (is_qla4010(ha) ?
646 &ha->reg->u1.isp4010.nvram :
647 &ha->reg->u1.isp4022.semaphore);
afaf5a2d
DS		 648}
649
650static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
651{
d915058f
DS		 652 return (is_qla4010(ha) ?
653 &ha->reg->u1.isp4010.nvram :
654 &ha->reg->u1.isp4022.nvram);
afaf5a2d
DS		 655}
656
657static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
658{
d915058f
DS		 659 return (is_qla4010(ha) ?
660 &ha->reg->u2.isp4010.ext_hw_conf :
661 &ha->reg->u2.isp4022.p0.ext_hw_conf);
afaf5a2d
DS		 662}
663
664static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
665{
d915058f
DS		 666 return (is_qla4010(ha) ?
667 &ha->reg->u2.isp4010.port_status :
668 &ha->reg->u2.isp4022.p0.port_status);
afaf5a2d
DS		 669}
670
671static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
672{
d915058f
DS		 673 return (is_qla4010(ha) ?
674 &ha->reg->u2.isp4010.port_ctrl :
675 &ha->reg->u2.isp4022.p0.port_ctrl);
afaf5a2d
DS		 676}
677
678static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
679{
d915058f
DS		 680 return (is_qla4010(ha) ?
681 &ha->reg->u2.isp4010.port_err_status :
682 &ha->reg->u2.isp4022.p0.port_err_status);
afaf5a2d
DS		 683}
684
685static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
686{
d915058f
DS		 687 return (is_qla4010(ha) ?
688 &ha->reg->u2.isp4010.gp_out :
689 &ha->reg->u2.isp4022.p0.gp_out);
afaf5a2d
DS		 690}
691
692static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
693{
d915058f
DS		 694 return (is_qla4010(ha) ?
695 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
696 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
afaf5a2d
DS		 697}
698
699int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
700void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
701int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
702
703static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
704{
d915058f
DS		 705 if (is_qla4010(a))
706 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
707 QL4010_FLASH_SEM_BITS);
708 else
afaf5a2d
DS		 709 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
710 (QL4022_RESOURCE_BITS_BASE_CODE |
711 (a->mac_index)) << 13);
afaf5a2d
DS		 712}
713
714static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
715{
d915058f 716 if (is_qla4010(a))
afaf5a2d 717 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
d915058f
DS		 718 else
719 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
afaf5a2d
DS		 720}
721
722static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
723{
d915058f
DS		 724 if (is_qla4010(a))
725 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
726 QL4010_NVRAM_SEM_BITS);
727 else
afaf5a2d
DS		 728 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
729 (QL4022_RESOURCE_BITS_BASE_CODE |
730 (a->mac_index)) << 10);
afaf5a2d
DS		 731}
732
733static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
734{
d915058f 735 if (is_qla4010(a))
afaf5a2d 736 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
d915058f
DS		 737 else
738 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
afaf5a2d
DS		 739}
740
741static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
742{
d915058f
DS		 743 if (is_qla4010(a))
744 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
745 QL4010_DRVR_SEM_BITS);
746 else
afaf5a2d
DS		 747 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
748 (QL4022_RESOURCE_BITS_BASE_CODE |
749 (a->mac_index)) << 1);
afaf5a2d
DS		 750}
751
752static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
753{
d915058f 754 if (is_qla4010(a))
afaf5a2d 755 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
d915058f
DS		 756 else
757 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
afaf5a2d
DS		 758}
759
760/*---------------------------------------------------------------------------*/
761
762/* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
763#define PRESERVE_DDB_LIST 0
764#define REBUILD_DDB_LIST 1
765
766/* Defines for process_aen() */
767#define PROCESS_ALL_AENS 0
768#define FLUSH_DDB_CHANGED_AENS 1
769#define RELOGIN_DDB_CHANGED_AENS 2
770
afaf5a2d 771#endif /*_QLA4XXX_H */
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