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[SCSI] qla2xxx: Simplify redundant target/device reset logic.
[net-next-2.6.git] / drivers / scsi / qla2xxx / qla_def.h
CommitLineData
1da177e4
LT		 1/********************************************************************************
2* QLOGIC LINUX SOFTWARE
3*
4* QLogic ISP2x00 device driver for Linux 2.6.x
ae91193c 5* Copyright (C) 2003-2005 QLogic Corporation
1da177e4
LT		 6* (www.qlogic.com)
7*
8* This program is free software; you can redistribute it and/or modify it
9* under the terms of the GNU General Public License as published by the
10* Free Software Foundation; either version 2, or (at your option) any
11* later version.
12*
13* This program is distributed in the hope that it will be useful, but
14* WITHOUT ANY WARRANTY; without even the implied warranty of
15* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16* General Public License for more details.
17**
18******************************************************************************/
19
20#ifndef __QLA_DEF_H
21#define __QLA_DEF_H
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/module.h>
27#include <linux/list.h>
28#include <linux/pci.h>
29#include <linux/dma-mapping.h>
30#include <linux/sched.h>
31#include <linux/slab.h>
32#include <linux/dmapool.h>
33#include <linux/mempool.h>
34#include <linux/spinlock.h>
35#include <linux/completion.h>
abbd8870 36#include <linux/interrupt.h>
1da177e4
LT		 37#include <asm/semaphore.h>
38
39#include <scsi/scsi.h>
40#include <scsi/scsi_host.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_cmnd.h>
43
1da177e4
LT		 44#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
45#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
46#else
47#define IS_QLA2100(ha) 0
48#endif
49
50#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
51#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
52#else
53#define IS_QLA2200(ha) 0
54#endif
55
56#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
57#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
58#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
59#else
60#define IS_QLA2300(ha) 0
61#define IS_QLA2312(ha) 0
62#endif
63
64#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
65#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
66#else
67#define IS_QLA2322(ha) 0
68#endif
69
70#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
71#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
72#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
73#else
74#define IS_QLA6312(ha) 0
75#define IS_QLA6322(ha) 0
76#endif
77
3d71644c
AV		 78#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
79#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
80#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
81#else
82#define IS_QLA2422(ha) 0
83#define IS_QLA2432(ha) 0
84#endif
85
86#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
87#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
88#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
89#else
90#define IS_QLA2512(ha) 0
91#define IS_QLA2522(ha) 0
92#endif
93
1da177e4
LT		 94#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
95 IS_QLA6312(ha) || IS_QLA6322(ha))
96
3d71644c
AV		 97#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
98#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
99
1da177e4
LT		 100/*
101 * Only non-ISP2[12]00 have extended addressing support in the firmware.
102 */
103#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
104
105/*
106 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
107 * but that's fine as we don't look at the last 24 ones for
108 * ISP2100 HBAs.
109 */
110#define MAILBOX_REGISTER_COUNT_2100 8
111#define MAILBOX_REGISTER_COUNT 32
112
113#define QLA2200A_RISC_ROM_VER 4
114#define FPM_2300 6
115#define FPM_2310 7
116
117#include "qla_settings.h"
118
fa2a1ce5 119/*
1da177e4
LT		 120 * Data bit definitions
121 */
122#define BIT_0 0x1
123#define BIT_1 0x2
124#define BIT_2 0x4
125#define BIT_3 0x8
126#define BIT_4 0x10
127#define BIT_5 0x20
128#define BIT_6 0x40
129#define BIT_7 0x80
130#define BIT_8 0x100
131#define BIT_9 0x200
132#define BIT_10 0x400
133#define BIT_11 0x800
134#define BIT_12 0x1000
135#define BIT_13 0x2000
136#define BIT_14 0x4000
137#define BIT_15 0x8000
138#define BIT_16 0x10000
139#define BIT_17 0x20000
140#define BIT_18 0x40000
141#define BIT_19 0x80000
142#define BIT_20 0x100000
143#define BIT_21 0x200000
144#define BIT_22 0x400000
145#define BIT_23 0x800000
146#define BIT_24 0x1000000
147#define BIT_25 0x2000000
148#define BIT_26 0x4000000
149#define BIT_27 0x8000000
150#define BIT_28 0x10000000
151#define BIT_29 0x20000000
152#define BIT_30 0x40000000
153#define BIT_31 0x80000000
154
155#define LSB(x) ((uint8_t)(x))
156#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
157
158#define LSW(x) ((uint16_t)(x))
159#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
160
161#define LSD(x) ((uint32_t)((uint64_t)(x)))
162#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
163
164
165/*
166 * I/O register
167*/
168
169#define RD_REG_BYTE(addr) readb(addr)
170#define RD_REG_WORD(addr) readw(addr)
171#define RD_REG_DWORD(addr) readl(addr)
172#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
173#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
174#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
175#define WRT_REG_BYTE(addr, data) writeb(data,addr)
176#define WRT_REG_WORD(addr, data) writew(data,addr)
177#define WRT_REG_DWORD(addr, data) writel(data,addr)
178
179/*
180 * Fibre Channel device definitions.
181 */
182#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
183#define MAX_FIBRE_DEVICES 512
cc4731f5 184#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT		 185#define MAX_RSCN_COUNT 32
186#define MAX_HOST_COUNT 16
187
188/*
189 * Host adapter default definitions.
190 */
191#define MAX_BUSES 1 /* We only have one bus today */
192#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
193#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT		 194#define MIN_LUNS 8
195#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV		 196#define MAX_CMDS_PER_LUN 255
197
1da177e4
LT		 198/*
199 * Fibre Channel device definitions.
200 */
201#define SNS_LAST_LOOP_ID_2100 0xfe
202#define SNS_LAST_LOOP_ID_2300 0x7ff
203
204#define LAST_LOCAL_LOOP_ID 0x7d
205#define SNS_FL_PORT 0x7e
206#define FABRIC_CONTROLLER 0x7f
207#define SIMPLE_NAME_SERVER 0x80
208#define SNS_FIRST_LOOP_ID 0x81
209#define MANAGEMENT_SERVER 0xfe
210#define BROADCAST 0xff
211
3d71644c
AV		 212/*
213 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
214 * valid range of an N-PORT id is 0 through 0x7ef.
215 */
216#define NPH_LAST_HANDLE 0x7ef
cca5335c 217#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV		 218#define NPH_SNS 0x7fc /* FFFFFC */
219#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
220#define NPH_F_PORT 0x7fe /* FFFFFE */
221#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
222
223#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
224#include "qla_fw.h"
1da177e4
LT		 225
226/*
227 * Timeout timer counts in seconds
228 */
8482e118 229#define PORT_RETRY_TIME 1
1da177e4
LT		 230#define LOOP_DOWN_TIMEOUT 60
231#define LOOP_DOWN_TIME 255 /* 240 */
232#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
233
234/* Maximum outstanding commands in ISP queues (1-65535) */
235#define MAX_OUTSTANDING_COMMANDS 1024
236
237/* ISP request and response entry counts (37-65535) */
238#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
239#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
240#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
3d71644c 241#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
1da177e4
LT		 242#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
243#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
244
245/*
fa2a1ce5 246 * SCSI Request Block
1da177e4
LT		 247 */
248typedef struct srb {
249 struct list_head list;
250
251 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 252 struct fc_port *fcport;
1da177e4
LT		 253
254 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
255
256 struct timer_list timer; /* Command timer */
fa2a1ce5 257 atomic_t ref_count; /* Reference count for this structure */
1da177e4
LT		 258 uint16_t flags;
259
260 /* Request state */
261 uint16_t state;
262
1da177e4
LT		 263 /* Single transfer DMA context */
264 dma_addr_t dma_handle;
265
266 uint32_t request_sense_length;
267 uint8_t *request_sense_ptr;
268
1da177e4
LT		 269 /* SRB magic number */
270 uint16_t magic;
271#define SRB_MAGIC 0x10CB
272} srb_t;
273
274/*
275 * SRB flag definitions
276 */
277#define SRB_TIMEOUT BIT_0 /* Command timed out */
278#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
279#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
280#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
281
282#define SRB_ABORTED BIT_4 /* Command aborted command already */
283#define SRB_RETRY BIT_5 /* Command needs retrying */
284#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
285#define SRB_FAILOVER BIT_7 /* Command in failover state */
286
287#define SRB_BUSY BIT_8 /* Command is in busy retry state */
288#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
289#define SRB_IOCTL BIT_10 /* IOCTL command. */
290#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
291
292/*
293 * SRB state definitions
294 */
295#define SRB_FREE_STATE 0 /* returned back */
296#define SRB_PENDING_STATE 1 /* queued in LUN Q */
297#define SRB_ACTIVE_STATE 2 /* in Active Array */
298#define SRB_DONE_STATE 3 /* queued in Done Queue */
299#define SRB_RETRY_STATE 4 /* in Retry Queue */
300#define SRB_SUSPENDED_STATE 5 /* in suspended state */
301#define SRB_NO_QUEUE_STATE 6 /* is in between states */
302#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
303#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
304#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
305
306
307/*
308 * ISP I/O Register Set structure definitions.
309 */
3d71644c
AV		 310struct device_reg_2xxx {
311 uint16_t flash_address; /* Flash BIOS address */
312 uint16_t flash_data; /* Flash BIOS data */
1da177e4 313 uint16_t unused_1[1]; /* Gap */
3d71644c 314 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 315#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT		 316#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
317#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
318
3d71644c 319 uint16_t ictrl; /* Interrupt control */
1da177e4
LT		 320#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
321#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
322
3d71644c 323 uint16_t istatus; /* Interrupt status */
1da177e4
LT		 324#define ISR_RISC_INT BIT_3 /* RISC interrupt */
325
3d71644c
AV		 326 uint16_t semaphore; /* Semaphore */
327 uint16_t nvram; /* NVRAM register. */
1da177e4
LT		 328#define NVR_DESELECT 0
329#define NVR_BUSY BIT_15
330#define NVR_WRT_ENABLE BIT_14 /* Write enable */
331#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
332#define NVR_DATA_IN BIT_3
333#define NVR_DATA_OUT BIT_2
334#define NVR_SELECT BIT_1
335#define NVR_CLOCK BIT_0
336
337 union {
338 struct {
3d71644c
AV		 339 uint16_t mailbox0;
340 uint16_t mailbox1;
341 uint16_t mailbox2;
342 uint16_t mailbox3;
343 uint16_t mailbox4;
344 uint16_t mailbox5;
345 uint16_t mailbox6;
346 uint16_t mailbox7;
347 uint16_t unused_2[59]; /* Gap */
1da177e4
LT		 348 } __attribute__((packed)) isp2100;
349 struct {
3d71644c
AV		 350 /* Request Queue */
351 uint16_t req_q_in; /* In-Pointer */
352 uint16_t req_q_out; /* Out-Pointer */
353 /* Response Queue */
354 uint16_t rsp_q_in; /* In-Pointer */
355 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT		 356
357 /* RISC to Host Status */
fa2a1ce5 358 uint32_t host_status;
1da177e4
LT		 359#define HSR_RISC_INT BIT_15 /* RISC interrupt */
360#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
361
362 /* Host to Host Semaphore */
fa2a1ce5 363 uint16_t host_semaphore;
3d71644c
AV		 364 uint16_t unused_3[17]; /* Gap */
365 uint16_t mailbox0;
366 uint16_t mailbox1;
367 uint16_t mailbox2;
368 uint16_t mailbox3;
369 uint16_t mailbox4;
370 uint16_t mailbox5;
371 uint16_t mailbox6;
372 uint16_t mailbox7;
373 uint16_t mailbox8;
374 uint16_t mailbox9;
375 uint16_t mailbox10;
376 uint16_t mailbox11;
377 uint16_t mailbox12;
378 uint16_t mailbox13;
379 uint16_t mailbox14;
380 uint16_t mailbox15;
381 uint16_t mailbox16;
382 uint16_t mailbox17;
383 uint16_t mailbox18;
384 uint16_t mailbox19;
385 uint16_t mailbox20;
386 uint16_t mailbox21;
387 uint16_t mailbox22;
388 uint16_t mailbox23;
389 uint16_t mailbox24;
390 uint16_t mailbox25;
391 uint16_t mailbox26;
392 uint16_t mailbox27;
393 uint16_t mailbox28;
394 uint16_t mailbox29;
395 uint16_t mailbox30;
396 uint16_t mailbox31;
397 uint16_t fb_cmd;
398 uint16_t unused_4[10]; /* Gap */
1da177e4
LT		 399 } __attribute__((packed)) isp2300;
400 } u;
401
3d71644c 402 uint16_t fpm_diag_config;
1da177e4 403 uint16_t unused_5[0x6]; /* Gap */
3d71644c 404 uint16_t pcr; /* Processor Control Register. */
1da177e4 405 uint16_t unused_6[0x5]; /* Gap */
3d71644c 406 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 407 uint16_t unused_7[0x3]; /* Gap */
3d71644c 408 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 409 uint16_t unused_8[0x3]; /* Gap */
3d71644c 410 uint16_t hccr; /* Host command & control register. */
1da177e4
LT		 411#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
412#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
413 /* HCCR commands */
414#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
415#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
416#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
417#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
418#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
419#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
420#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
421#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
422
423 uint16_t unused_9[5]; /* Gap */
3d71644c
AV		 424 uint16_t gpiod; /* GPIO Data register. */
425 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT		 426#define GPIO_LED_MASK 0x00C0
427#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
428#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
429#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
430#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
431
432 union {
433 struct {
3d71644c
AV		 434 uint16_t unused_10[8]; /* Gap */
435 uint16_t mailbox8;
436 uint16_t mailbox9;
437 uint16_t mailbox10;
438 uint16_t mailbox11;
439 uint16_t mailbox12;
440 uint16_t mailbox13;
441 uint16_t mailbox14;
442 uint16_t mailbox15;
443 uint16_t mailbox16;
444 uint16_t mailbox17;
445 uint16_t mailbox18;
446 uint16_t mailbox19;
447 uint16_t mailbox20;
448 uint16_t mailbox21;
449 uint16_t mailbox22;
450 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT		 451 } __attribute__((packed)) isp2200;
452 } u_end;
3d71644c
AV		 453};
454
9a168bdd 455typedef union {
3d71644c
AV		 456 struct device_reg_2xxx isp;
457 struct device_reg_24xx isp24;
1da177e4
LT		 458} device_reg_t;
459
460#define ISP_REQ_Q_IN(ha, reg) \
461 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
462 &(reg)->u.isp2100.mailbox4 : \
463 &(reg)->u.isp2300.req_q_in)
464#define ISP_REQ_Q_OUT(ha, reg) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 &(reg)->u.isp2100.mailbox4 : \
467 &(reg)->u.isp2300.req_q_out)
468#define ISP_RSP_Q_IN(ha, reg) \
469 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
470 &(reg)->u.isp2100.mailbox5 : \
471 &(reg)->u.isp2300.rsp_q_in)
472#define ISP_RSP_Q_OUT(ha, reg) \
473 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
474 &(reg)->u.isp2100.mailbox5 : \
475 &(reg)->u.isp2300.rsp_q_out)
476
477#define MAILBOX_REG(ha, reg, num) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 (num < 8 ? \
480 &(reg)->u.isp2100.mailbox0 + (num) : \
481 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
482 &(reg)->u.isp2300.mailbox0 + (num))
483#define RD_MAILBOX_REG(ha, reg, num) \
484 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
485#define WRT_MAILBOX_REG(ha, reg, num, data) \
486 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
487
488#define FB_CMD_REG(ha, reg) \
489 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
490 &(reg)->fb_cmd_2100 : \
491 &(reg)->u.isp2300.fb_cmd)
492#define RD_FB_CMD_REG(ha, reg) \
493 RD_REG_WORD(FB_CMD_REG(ha, reg))
494#define WRT_FB_CMD_REG(ha, reg, data) \
495 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
496
497typedef struct {
498 uint32_t out_mb; /* outbound from driver */
499 uint32_t in_mb; /* Incoming from RISC */
500 uint16_t mb[MAILBOX_REGISTER_COUNT];
501 long buf_size;
502 void *bufp;
503 uint32_t tov;
504 uint8_t flags;
505#define MBX_DMA_IN BIT_0
506#define MBX_DMA_OUT BIT_1
507#define IOCTL_CMD BIT_2
508} mbx_cmd_t;
509
510#define MBX_TOV_SECONDS 30
511
512/*
513 * ISP product identification definitions in mailboxes after reset.
514 */
515#define PROD_ID_1 0x4953
516#define PROD_ID_2 0x0000
517#define PROD_ID_2a 0x5020
518#define PROD_ID_3 0x2020
519
520/*
521 * ISP mailbox Self-Test status codes
522 */
523#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
524#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
525#define MBS_BUSY 4 /* Busy. */
526
527/*
528 * ISP mailbox command complete status codes
529 */
530#define MBS_COMMAND_COMPLETE 0x4000
531#define MBS_INVALID_COMMAND 0x4001
532#define MBS_HOST_INTERFACE_ERROR 0x4002
533#define MBS_TEST_FAILED 0x4003
534#define MBS_COMMAND_ERROR 0x4005
535#define MBS_COMMAND_PARAMETER_ERROR 0x4006
536#define MBS_PORT_ID_USED 0x4007
537#define MBS_LOOP_ID_USED 0x4008
538#define MBS_ALL_IDS_IN_USE 0x4009
539#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV		 540#define MBS_LINK_DOWN_ERROR 0x400B
541#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT		 542
543/*
544 * ISP mailbox asynchronous event status codes
545 */
546#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
547#define MBA_RESET 0x8001 /* Reset Detected. */
548#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
549#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
550#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
551#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
552#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
553 /* occurred. */
554#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
555#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
556#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
557#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
558#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
559#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
560#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
561#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
562#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
563#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
564#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
565#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
566#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
567#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
568#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
569#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
570 /* used. */
571#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
572#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
573#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
574#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
575#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
576#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
577#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
578#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
579#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
580#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
581#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
582#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
583#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
584
585/*
586 * Firmware options 1, 2, 3.
587 */
588#define FO1_AE_ON_LIPF8 BIT_0
589#define FO1_AE_ALL_LIP_RESET BIT_1
590#define FO1_CTIO_RETRY BIT_3
591#define FO1_DISABLE_LIP_F7_SW BIT_4
592#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 593#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT		 594#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
595#define FO1_SET_EMPHASIS_SWING BIT_8
596#define FO1_AE_AUTO_BYPASS BIT_9
597#define FO1_ENABLE_PURE_IOCB BIT_10
598#define FO1_AE_PLOGI_RJT BIT_11
599#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
600#define FO1_AE_QUEUE_FULL BIT_13
601
602#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
603#define FO2_REV_LOOPBACK BIT_1
604
605#define FO3_ENABLE_EMERG_IOCB BIT_0
606#define FO3_AE_RND_ERROR BIT_1
607
3d71644c
AV		 608/* 24XX additional firmware options */
609#define ADD_FO_COUNT 3
610#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
611#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
612
613#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
614
615#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
616
1da177e4
LT		 617/*
618 * ISP mailbox commands
619 */
620#define MBC_LOAD_RAM 1 /* Load RAM. */
621#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
622#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
623#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
624#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
625#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
626#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
627#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
628#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
629#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
630#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
631#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
632#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
633#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
634#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
635#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
636#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
637#define MBC_RESET 0x18 /* Reset. */
638#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
639#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
640#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
641#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
642#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
643#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
644#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
645#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
646#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
647#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
648#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
649#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
650#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
651#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
652#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
653#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
654#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
655#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
656#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
657#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
658#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
659#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
660 /* Initialization Procedure */
661#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
662#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
663#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
664#define MBC_TARGET_RESET 0x66 /* Target Reset. */
665#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
666#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
667#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
668#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
669#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
670#define MBC_LIP_RESET 0x6c /* LIP reset. */
671#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
672 /* commandd. */
673#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
674#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
675#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
676#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
677#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
678#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
679#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
680#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
681#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
682#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
683#define MBC_LUN_RESET 0x7E /* Send LUN reset */
684
3d71644c
AV		 685/*
686 * ISP24xx mailbox commands
687 */
688#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
689#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
690#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
691#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
692#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
693#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
694#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
695#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
696#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
697#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
698#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
699#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
700
1da177e4
LT		 701/* Firmware return data sizes */
702#define FCAL_MAP_SIZE 128
703
704/* Mailbox bit definitions for out_mb and in_mb */
705#define MBX_31 BIT_31
706#define MBX_30 BIT_30
707#define MBX_29 BIT_29
708#define MBX_28 BIT_28
709#define MBX_27 BIT_27
710#define MBX_26 BIT_26
711#define MBX_25 BIT_25
712#define MBX_24 BIT_24
713#define MBX_23 BIT_23
714#define MBX_22 BIT_22
715#define MBX_21 BIT_21
716#define MBX_20 BIT_20
717#define MBX_19 BIT_19
718#define MBX_18 BIT_18
719#define MBX_17 BIT_17
720#define MBX_16 BIT_16
721#define MBX_15 BIT_15
722#define MBX_14 BIT_14
723#define MBX_13 BIT_13
724#define MBX_12 BIT_12
725#define MBX_11 BIT_11
726#define MBX_10 BIT_10
727#define MBX_9 BIT_9
728#define MBX_8 BIT_8
729#define MBX_7 BIT_7
730#define MBX_6 BIT_6
731#define MBX_5 BIT_5
732#define MBX_4 BIT_4
733#define MBX_3 BIT_3
734#define MBX_2 BIT_2
735#define MBX_1 BIT_1
736#define MBX_0 BIT_0
737
738/*
739 * Firmware state codes from get firmware state mailbox command
740 */
741#define FSTATE_CONFIG_WAIT 0
742#define FSTATE_WAIT_AL_PA 1
743#define FSTATE_WAIT_LOGIN 2
744#define FSTATE_READY 3
745#define FSTATE_LOSS_OF_SYNC 4
746#define FSTATE_ERROR 5
747#define FSTATE_REINIT 6
748#define FSTATE_NON_PART 7
749
750#define FSTATE_CONFIG_CORRECT 0
751#define FSTATE_P2P_RCV_LIP 1
752#define FSTATE_P2P_CHOOSE_LOOP 2
753#define FSTATE_P2P_RCV_UNIDEN_LIP 3
754#define FSTATE_FATAL_ERROR 4
755#define FSTATE_LOOP_BACK_CONN 5
756
757/*
758 * Port Database structure definition
759 * Little endian except where noted.
760 */
761#define PORT_DATABASE_SIZE 128 /* bytes */
762typedef struct {
763 uint8_t options;
764 uint8_t control;
765 uint8_t master_state;
766 uint8_t slave_state;
767 uint8_t reserved[2];
768 uint8_t hard_address;
769 uint8_t reserved_1;
770 uint8_t port_id[4];
771 uint8_t node_name[WWN_SIZE];
772 uint8_t port_name[WWN_SIZE];
773 uint16_t execution_throttle;
774 uint16_t execution_count;
775 uint8_t reset_count;
776 uint8_t reserved_2;
777 uint16_t resource_allocation;
778 uint16_t current_allocation;
779 uint16_t queue_head;
780 uint16_t queue_tail;
781 uint16_t transmit_execution_list_next;
782 uint16_t transmit_execution_list_previous;
783 uint16_t common_features;
784 uint16_t total_concurrent_sequences;
785 uint16_t RO_by_information_category;
786 uint8_t recipient;
787 uint8_t initiator;
788 uint16_t receive_data_size;
789 uint16_t concurrent_sequences;
790 uint16_t open_sequences_per_exchange;
791 uint16_t lun_abort_flags;
792 uint16_t lun_stop_flags;
793 uint16_t stop_queue_head;
794 uint16_t stop_queue_tail;
795 uint16_t port_retry_timer;
796 uint16_t next_sequence_id;
797 uint16_t frame_count;
798 uint16_t PRLI_payload_length;
799 uint8_t prli_svc_param_word_0[2]; /* Big endian */
800 /* Bits 15-0 of word 0 */
801 uint8_t prli_svc_param_word_3[2]; /* Big endian */
802 /* Bits 15-0 of word 3 */
803 uint16_t loop_id;
804 uint16_t extended_lun_info_list_pointer;
805 uint16_t extended_lun_stop_list_pointer;
806} port_database_t;
807
808/*
809 * Port database slave/master states
810 */
811#define PD_STATE_DISCOVERY 0
812#define PD_STATE_WAIT_DISCOVERY_ACK 1
813#define PD_STATE_PORT_LOGIN 2
814#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
815#define PD_STATE_PROCESS_LOGIN 4
816#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
817#define PD_STATE_PORT_LOGGED_IN 6
818#define PD_STATE_PORT_UNAVAILABLE 7
819#define PD_STATE_PROCESS_LOGOUT 8
820#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
821#define PD_STATE_PORT_LOGOUT 10
822#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
823
824
825/*
826 * ISP Initialization Control Block.
827 * Little endian except where noted.
828 */
829#define ICB_VERSION 1
830typedef struct {
831 uint8_t version;
832 uint8_t reserved_1;
833
834 /*
835 * LSB BIT 0 = Enable Hard Loop Id
836 * LSB BIT 1 = Enable Fairness
837 * LSB BIT 2 = Enable Full-Duplex
838 * LSB BIT 3 = Enable Fast Posting
839 * LSB BIT 4 = Enable Target Mode
840 * LSB BIT 5 = Disable Initiator Mode
841 * LSB BIT 6 = Enable ADISC
842 * LSB BIT 7 = Enable Target Inquiry Data
843 *
844 * MSB BIT 0 = Enable PDBC Notify
845 * MSB BIT 1 = Non Participating LIP
846 * MSB BIT 2 = Descending Loop ID Search
847 * MSB BIT 3 = Acquire Loop ID in LIPA
848 * MSB BIT 4 = Stop PortQ on Full Status
849 * MSB BIT 5 = Full Login after LIP
850 * MSB BIT 6 = Node Name Option
851 * MSB BIT 7 = Ext IFWCB enable bit
852 */
853 uint8_t firmware_options[2];
854
855 uint16_t frame_payload_size;
856 uint16_t max_iocb_allocation;
857 uint16_t execution_throttle;
858 uint8_t retry_count;
859 uint8_t retry_delay; /* unused */
860 uint8_t port_name[WWN_SIZE]; /* Big endian. */
861 uint16_t hard_address;
862 uint8_t inquiry_data;
863 uint8_t login_timeout;
864 uint8_t node_name[WWN_SIZE]; /* Big endian. */
865
866 uint16_t request_q_outpointer;
867 uint16_t response_q_inpointer;
868 uint16_t request_q_length;
869 uint16_t response_q_length;
870 uint32_t request_q_address[2];
871 uint32_t response_q_address[2];
872
873 uint16_t lun_enables;
874 uint8_t command_resource_count;
875 uint8_t immediate_notify_resource_count;
876 uint16_t timeout;
877 uint8_t reserved_2[2];
878
879 /*
880 * LSB BIT 0 = Timer Operation mode bit 0
881 * LSB BIT 1 = Timer Operation mode bit 1
882 * LSB BIT 2 = Timer Operation mode bit 2
883 * LSB BIT 3 = Timer Operation mode bit 3
884 * LSB BIT 4 = Init Config Mode bit 0
885 * LSB BIT 5 = Init Config Mode bit 1
886 * LSB BIT 6 = Init Config Mode bit 2
887 * LSB BIT 7 = Enable Non part on LIHA failure
888 *
889 * MSB BIT 0 = Enable class 2
890 * MSB BIT 1 = Enable ACK0
891 * MSB BIT 2 =
892 * MSB BIT 3 =
893 * MSB BIT 4 = FC Tape Enable
894 * MSB BIT 5 = Enable FC Confirm
895 * MSB BIT 6 = Enable command queuing in target mode
896 * MSB BIT 7 = No Logo On Link Down
897 */
898 uint8_t add_firmware_options[2];
899
900 uint8_t response_accumulation_timer;
901 uint8_t interrupt_delay_timer;
902
903 /*
904 * LSB BIT 0 = Enable Read xfr_rdy
905 * LSB BIT 1 = Soft ID only
906 * LSB BIT 2 =
907 * LSB BIT 3 =
908 * LSB BIT 4 = FCP RSP Payload [0]
909 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
910 * LSB BIT 6 = Enable Out-of-Order frame handling
911 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
912 *
913 * MSB BIT 0 = Sbus enable - 2300
914 * MSB BIT 1 =
915 * MSB BIT 2 =
916 * MSB BIT 3 =
917 * MSB BIT 4 =
918 * MSB BIT 5 = enable 50 ohm termination
919 * MSB BIT 6 = Data Rate (2300 only)
920 * MSB BIT 7 = Data Rate (2300 only)
921 */
922 uint8_t special_options[2];
923
924 uint8_t reserved_3[26];
925} init_cb_t;
926
927/*
928 * Get Link Status mailbox command return buffer.
929 */
3d71644c
AV		 930#define GLSO_SEND_RPS BIT_0
931#define GLSO_USE_DID BIT_3
932
1da177e4
LT		 933typedef struct {
934 uint32_t link_fail_cnt;
935 uint32_t loss_sync_cnt;
936 uint32_t loss_sig_cnt;
937 uint32_t prim_seq_err_cnt;
938 uint32_t inval_xmit_word_cnt;
939 uint32_t inval_crc_cnt;
940} link_stat_t;
941
942/*
943 * NVRAM Command values.
944 */
945#define NV_START_BIT BIT_2
946#define NV_WRITE_OP (BIT_26+BIT_24)
947#define NV_READ_OP (BIT_26+BIT_25)
948#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
949#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
950#define NV_DELAY_COUNT 10
951
952/*
953 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
954 */
955typedef struct {
956 /*
957 * NVRAM header
958 */
959 uint8_t id[4];
960 uint8_t nvram_version;
961 uint8_t reserved_0;
962
963 /*
964 * NVRAM RISC parameter block
965 */
966 uint8_t parameter_block_version;
967 uint8_t reserved_1;
968
969 /*
970 * LSB BIT 0 = Enable Hard Loop Id
971 * LSB BIT 1 = Enable Fairness
972 * LSB BIT 2 = Enable Full-Duplex
973 * LSB BIT 3 = Enable Fast Posting
974 * LSB BIT 4 = Enable Target Mode
975 * LSB BIT 5 = Disable Initiator Mode
976 * LSB BIT 6 = Enable ADISC
977 * LSB BIT 7 = Enable Target Inquiry Data
978 *
979 * MSB BIT 0 = Enable PDBC Notify
980 * MSB BIT 1 = Non Participating LIP
981 * MSB BIT 2 = Descending Loop ID Search
982 * MSB BIT 3 = Acquire Loop ID in LIPA
983 * MSB BIT 4 = Stop PortQ on Full Status
984 * MSB BIT 5 = Full Login after LIP
985 * MSB BIT 6 = Node Name Option
986 * MSB BIT 7 = Ext IFWCB enable bit
987 */
988 uint8_t firmware_options[2];
989
990 uint16_t frame_payload_size;
991 uint16_t max_iocb_allocation;
992 uint16_t execution_throttle;
993 uint8_t retry_count;
994 uint8_t retry_delay; /* unused */
995 uint8_t port_name[WWN_SIZE]; /* Big endian. */
996 uint16_t hard_address;
997 uint8_t inquiry_data;
998 uint8_t login_timeout;
999 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1000
1001 /*
1002 * LSB BIT 0 = Timer Operation mode bit 0
1003 * LSB BIT 1 = Timer Operation mode bit 1
1004 * LSB BIT 2 = Timer Operation mode bit 2
1005 * LSB BIT 3 = Timer Operation mode bit 3
1006 * LSB BIT 4 = Init Config Mode bit 0
1007 * LSB BIT 5 = Init Config Mode bit 1
1008 * LSB BIT 6 = Init Config Mode bit 2
1009 * LSB BIT 7 = Enable Non part on LIHA failure
1010 *
1011 * MSB BIT 0 = Enable class 2
1012 * MSB BIT 1 = Enable ACK0
1013 * MSB BIT 2 =
1014 * MSB BIT 3 =
1015 * MSB BIT 4 = FC Tape Enable
1016 * MSB BIT 5 = Enable FC Confirm
1017 * MSB BIT 6 = Enable command queuing in target mode
1018 * MSB BIT 7 = No Logo On Link Down
1019 */
1020 uint8_t add_firmware_options[2];
1021
1022 uint8_t response_accumulation_timer;
1023 uint8_t interrupt_delay_timer;
1024
1025 /*
1026 * LSB BIT 0 = Enable Read xfr_rdy
1027 * LSB BIT 1 = Soft ID only
1028 * LSB BIT 2 =
1029 * LSB BIT 3 =
1030 * LSB BIT 4 = FCP RSP Payload [0]
1031 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1032 * LSB BIT 6 = Enable Out-of-Order frame handling
1033 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1034 *
1035 * MSB BIT 0 = Sbus enable - 2300
1036 * MSB BIT 1 =
1037 * MSB BIT 2 =
1038 * MSB BIT 3 =
1039 * MSB BIT 4 =
1040 * MSB BIT 5 = enable 50 ohm termination
1041 * MSB BIT 6 = Data Rate (2300 only)
1042 * MSB BIT 7 = Data Rate (2300 only)
1043 */
1044 uint8_t special_options[2];
1045
1046 /* Reserved for expanded RISC parameter block */
1047 uint8_t reserved_2[22];
1048
1049 /*
1050 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1051 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1052 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1053 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1054 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1055 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1056 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1057 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 1058 *
1da177e4
LT		 1059 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1060 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1061 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1062 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1063 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1064 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1065 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1066 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1067 *
1068 * LSB BIT 0 = Output Swing 1G bit 0
1069 * LSB BIT 1 = Output Swing 1G bit 1
1070 * LSB BIT 2 = Output Swing 1G bit 2
1071 * LSB BIT 3 = Output Emphasis 1G bit 0
1072 * LSB BIT 4 = Output Emphasis 1G bit 1
1073 * LSB BIT 5 = Output Swing 2G bit 0
1074 * LSB BIT 6 = Output Swing 2G bit 1
1075 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1076 *
1da177e4
LT		 1077 * MSB BIT 0 = Output Emphasis 2G bit 0
1078 * MSB BIT 1 = Output Emphasis 2G bit 1
1079 * MSB BIT 2 = Output Enable
1080 * MSB BIT 3 =
1081 * MSB BIT 4 =
1082 * MSB BIT 5 =
1083 * MSB BIT 6 =
1084 * MSB BIT 7 =
1085 */
1086 uint8_t seriallink_options[4];
1087
1088 /*
1089 * NVRAM host parameter block
1090 *
1091 * LSB BIT 0 = Enable spinup delay
1092 * LSB BIT 1 = Disable BIOS
1093 * LSB BIT 2 = Enable Memory Map BIOS
1094 * LSB BIT 3 = Enable Selectable Boot
1095 * LSB BIT 4 = Disable RISC code load
1096 * LSB BIT 5 = Set cache line size 1
1097 * LSB BIT 6 = PCI Parity Disable
1098 * LSB BIT 7 = Enable extended logging
1099 *
1100 * MSB BIT 0 = Enable 64bit addressing
1101 * MSB BIT 1 = Enable lip reset
1102 * MSB BIT 2 = Enable lip full login
1103 * MSB BIT 3 = Enable target reset
1104 * MSB BIT 4 = Enable database storage
1105 * MSB BIT 5 = Enable cache flush read
1106 * MSB BIT 6 = Enable database load
1107 * MSB BIT 7 = Enable alternate WWN
1108 */
1109 uint8_t host_p[2];
1110
1111 uint8_t boot_node_name[WWN_SIZE];
1112 uint8_t boot_lun_number;
1113 uint8_t reset_delay;
1114 uint8_t port_down_retry_count;
1115 uint8_t boot_id_number;
1116 uint16_t max_luns_per_target;
1117 uint8_t fcode_boot_port_name[WWN_SIZE];
1118 uint8_t alternate_port_name[WWN_SIZE];
1119 uint8_t alternate_node_name[WWN_SIZE];
1120
1121 /*
1122 * BIT 0 = Selective Login
1123 * BIT 1 = Alt-Boot Enable
1124 * BIT 2 =
1125 * BIT 3 = Boot Order List
1126 * BIT 4 =
1127 * BIT 5 = Selective LUN
1128 * BIT 6 =
1129 * BIT 7 = unused
1130 */
1131 uint8_t efi_parameters;
1132
1133 uint8_t link_down_timeout;
1134
cca5335c 1135 uint8_t adapter_id[16];
1da177e4
LT		 1136
1137 uint8_t alt1_boot_node_name[WWN_SIZE];
1138 uint16_t alt1_boot_lun_number;
1139 uint8_t alt2_boot_node_name[WWN_SIZE];
1140 uint16_t alt2_boot_lun_number;
1141 uint8_t alt3_boot_node_name[WWN_SIZE];
1142 uint16_t alt3_boot_lun_number;
1143 uint8_t alt4_boot_node_name[WWN_SIZE];
1144 uint16_t alt4_boot_lun_number;
1145 uint8_t alt5_boot_node_name[WWN_SIZE];
1146 uint16_t alt5_boot_lun_number;
1147 uint8_t alt6_boot_node_name[WWN_SIZE];
1148 uint16_t alt6_boot_lun_number;
1149 uint8_t alt7_boot_node_name[WWN_SIZE];
1150 uint16_t alt7_boot_lun_number;
1151
1152 uint8_t reserved_3[2];
1153
1154 /* Offset 200-215 : Model Number */
1155 uint8_t model_number[16];
1156
1157 /* OEM related items */
1158 uint8_t oem_specific[16];
1159
1160 /*
1161 * NVRAM Adapter Features offset 232-239
1162 *
1163 * LSB BIT 0 = External GBIC
1164 * LSB BIT 1 = Risc RAM parity
1165 * LSB BIT 2 = Buffer Plus Module
1166 * LSB BIT 3 = Multi Chip Adapter
1167 * LSB BIT 4 = Internal connector
1168 * LSB BIT 5 =
1169 * LSB BIT 6 =
1170 * LSB BIT 7 =
1171 *
1172 * MSB BIT 0 =
1173 * MSB BIT 1 =
1174 * MSB BIT 2 =
1175 * MSB BIT 3 =
1176 * MSB BIT 4 =
1177 * MSB BIT 5 =
1178 * MSB BIT 6 =
1179 * MSB BIT 7 =
1180 */
1181 uint8_t adapter_features[2];
1182
1183 uint8_t reserved_4[16];
1184
1185 /* Subsystem vendor ID for ISP2200 */
1186 uint16_t subsystem_vendor_id_2200;
1187
1188 /* Subsystem device ID for ISP2200 */
1189 uint16_t subsystem_device_id_2200;
1190
1191 uint8_t reserved_5;
1192 uint8_t checksum;
1193} nvram_t;
1194
1195/*
1196 * ISP queue - response queue entry definition.
1197 */
1198typedef struct {
1199 uint8_t data[60];
1200 uint32_t signature;
1201#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1202} response_t;
1203
1204typedef union {
1205 uint16_t extended;
1206 struct {
1207 uint8_t reserved;
1208 uint8_t standard;
1209 } id;
1210} target_id_t;
1211
1212#define SET_TARGET_ID(ha, to, from) \
1213do { \
1214 if (HAS_EXTENDED_IDS(ha)) \
1215 to.extended = cpu_to_le16(from); \
1216 else \
1217 to.id.standard = (uint8_t)from; \
1218} while (0)
1219
1220/*
1221 * ISP queue - command entry structure definition.
1222 */
1223#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT		 1224typedef struct {
1225 uint8_t entry_type; /* Entry type. */
1226 uint8_t entry_count; /* Entry count. */
1227 uint8_t sys_define; /* System defined. */
1228 uint8_t entry_status; /* Entry Status. */
1229 uint32_t handle; /* System handle. */
1230 target_id_t target; /* SCSI ID */
1231 uint16_t lun; /* SCSI LUN */
1232 uint16_t control_flags; /* Control flags. */
1233#define CF_WRITE BIT_6
1234#define CF_READ BIT_5
1235#define CF_SIMPLE_TAG BIT_3
1236#define CF_ORDERED_TAG BIT_2
1237#define CF_HEAD_TAG BIT_1
1238 uint16_t reserved_1;
1239 uint16_t timeout; /* Command timeout. */
1240 uint16_t dseg_count; /* Data segment count. */
1241 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1242 uint32_t byte_count; /* Total byte count. */
1243 uint32_t dseg_0_address; /* Data segment 0 address. */
1244 uint32_t dseg_0_length; /* Data segment 0 length. */
1245 uint32_t dseg_1_address; /* Data segment 1 address. */
1246 uint32_t dseg_1_length; /* Data segment 1 length. */
1247 uint32_t dseg_2_address; /* Data segment 2 address. */
1248 uint32_t dseg_2_length; /* Data segment 2 length. */
1249} cmd_entry_t;
1250
1251/*
1252 * ISP queue - 64-Bit addressing, command entry structure definition.
1253 */
1254#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1255typedef struct {
1256 uint8_t entry_type; /* Entry type. */
1257 uint8_t entry_count; /* Entry count. */
1258 uint8_t sys_define; /* System defined. */
1259 uint8_t entry_status; /* Entry Status. */
1260 uint32_t handle; /* System handle. */
1261 target_id_t target; /* SCSI ID */
1262 uint16_t lun; /* SCSI LUN */
1263 uint16_t control_flags; /* Control flags. */
1264 uint16_t reserved_1;
1265 uint16_t timeout; /* Command timeout. */
1266 uint16_t dseg_count; /* Data segment count. */
1267 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1268 uint32_t byte_count; /* Total byte count. */
1269 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1270 uint32_t dseg_0_length; /* Data segment 0 length. */
1271 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1272 uint32_t dseg_1_length; /* Data segment 1 length. */
1273} cmd_a64_entry_t, request_t;
1274
1275/*
1276 * ISP queue - continuation entry structure definition.
1277 */
1278#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1279typedef struct {
1280 uint8_t entry_type; /* Entry type. */
1281 uint8_t entry_count; /* Entry count. */
1282 uint8_t sys_define; /* System defined. */
1283 uint8_t entry_status; /* Entry Status. */
1284 uint32_t reserved;
1285 uint32_t dseg_0_address; /* Data segment 0 address. */
1286 uint32_t dseg_0_length; /* Data segment 0 length. */
1287 uint32_t dseg_1_address; /* Data segment 1 address. */
1288 uint32_t dseg_1_length; /* Data segment 1 length. */
1289 uint32_t dseg_2_address; /* Data segment 2 address. */
1290 uint32_t dseg_2_length; /* Data segment 2 length. */
1291 uint32_t dseg_3_address; /* Data segment 3 address. */
1292 uint32_t dseg_3_length; /* Data segment 3 length. */
1293 uint32_t dseg_4_address; /* Data segment 4 address. */
1294 uint32_t dseg_4_length; /* Data segment 4 length. */
1295 uint32_t dseg_5_address; /* Data segment 5 address. */
1296 uint32_t dseg_5_length; /* Data segment 5 length. */
1297 uint32_t dseg_6_address; /* Data segment 6 address. */
1298 uint32_t dseg_6_length; /* Data segment 6 length. */
1299} cont_entry_t;
1300
1301/*
1302 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1303 */
1304#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1305typedef struct {
1306 uint8_t entry_type; /* Entry type. */
1307 uint8_t entry_count; /* Entry count. */
1308 uint8_t sys_define; /* System defined. */
1309 uint8_t entry_status; /* Entry Status. */
1310 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1311 uint32_t dseg_0_length; /* Data segment 0 length. */
1312 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1313 uint32_t dseg_1_length; /* Data segment 1 length. */
1314 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1315 uint32_t dseg_2_length; /* Data segment 2 length. */
1316 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1317 uint32_t dseg_3_length; /* Data segment 3 length. */
1318 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1319 uint32_t dseg_4_length; /* Data segment 4 length. */
1320} cont_a64_entry_t;
1321
1322/*
1323 * ISP queue - status entry structure definition.
1324 */
1325#define STATUS_TYPE 0x03 /* Status entry. */
1326typedef struct {
1327 uint8_t entry_type; /* Entry type. */
1328 uint8_t entry_count; /* Entry count. */
1329 uint8_t sys_define; /* System defined. */
1330 uint8_t entry_status; /* Entry Status. */
1331 uint32_t handle; /* System handle. */
1332 uint16_t scsi_status; /* SCSI status. */
1333 uint16_t comp_status; /* Completion status. */
1334 uint16_t state_flags; /* State flags. */
1335 uint16_t status_flags; /* Status flags. */
1336 uint16_t rsp_info_len; /* Response Info Length. */
1337 uint16_t req_sense_length; /* Request sense data length. */
1338 uint32_t residual_length; /* Residual transfer length. */
1339 uint8_t rsp_info[8]; /* FCP response information. */
1340 uint8_t req_sense_data[32]; /* Request sense data. */
1341} sts_entry_t;
1342
1343/*
1344 * Status entry entry status
1345 */
3d71644c 1346#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT		 1347#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1348#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1349#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1350#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1351#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV		 1352#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1353 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1354#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1355 RF_INV_E_TYPE)
1da177e4
LT		 1356
1357/*
1358 * Status entry SCSI status bit definitions.
1359 */
1360#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1361#define SS_RESIDUAL_UNDER BIT_11
1362#define SS_RESIDUAL_OVER BIT_10
1363#define SS_SENSE_LEN_VALID BIT_9
1364#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1365
1366#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1367#define SS_BUSY_CONDITION BIT_3
1368#define SS_CONDITION_MET BIT_2
1369#define SS_CHECK_CONDITION BIT_1
1370
1371/*
1372 * Status entry completion status
1373 */
1374#define CS_COMPLETE 0x0 /* No errors */
1375#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1376#define CS_DMA 0x2 /* A DMA direction error. */
1377#define CS_TRANSPORT 0x3 /* Transport error. */
1378#define CS_RESET 0x4 /* SCSI bus reset occurred */
1379#define CS_ABORTED 0x5 /* System aborted command. */
1380#define CS_TIMEOUT 0x6 /* Timeout error. */
1381#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1382
1383#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1384#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1385#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1386 /* (selection timeout) */
1387#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1388#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1389#define CS_PORT_BUSY 0x2B /* Port Busy */
1390#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1391#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1392#define CS_UNKNOWN 0x81 /* Driver defined */
1393#define CS_RETRY 0x82 /* Driver defined */
1394#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1395
1396/*
1397 * Status entry status flags
1398 */
1399#define SF_ABTS_TERMINATED BIT_10
1400#define SF_LOGOUT_SENT BIT_13
1401
1402/*
1403 * ISP queue - status continuation entry structure definition.
1404 */
1405#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1406typedef struct {
1407 uint8_t entry_type; /* Entry type. */
1408 uint8_t entry_count; /* Entry count. */
1409 uint8_t sys_define; /* System defined. */
1410 uint8_t entry_status; /* Entry Status. */
1411 uint8_t data[60]; /* data */
1412} sts_cont_entry_t;
1413
1414/*
1415 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1416 * structure definition.
1417 */
1418#define STATUS_TYPE_21 0x21 /* Status entry. */
1419typedef struct {
1420 uint8_t entry_type; /* Entry type. */
1421 uint8_t entry_count; /* Entry count. */
1422 uint8_t handle_count; /* Handle count. */
1423 uint8_t entry_status; /* Entry Status. */
1424 uint32_t handle[15]; /* System handles. */
1425} sts21_entry_t;
1426
1427/*
1428 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1429 * structure definition.
1430 */
1431#define STATUS_TYPE_22 0x22 /* Status entry. */
1432typedef struct {
1433 uint8_t entry_type; /* Entry type. */
1434 uint8_t entry_count; /* Entry count. */
1435 uint8_t handle_count; /* Handle count. */
1436 uint8_t entry_status; /* Entry Status. */
1437 uint16_t handle[30]; /* System handles. */
1438} sts22_entry_t;
1439
1440/*
1441 * ISP queue - marker entry structure definition.
1442 */
1443#define MARKER_TYPE 0x04 /* Marker entry. */
1444typedef struct {
1445 uint8_t entry_type; /* Entry type. */
1446 uint8_t entry_count; /* Entry count. */
1447 uint8_t handle_count; /* Handle count. */
1448 uint8_t entry_status; /* Entry Status. */
1449 uint32_t sys_define_2; /* System defined. */
1450 target_id_t target; /* SCSI ID */
1451 uint8_t modifier; /* Modifier (7-0). */
1452#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1453#define MK_SYNC_ID 1 /* Synchronize ID */
1454#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1455#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1456 /* clear port changed, */
1457 /* use sequence number. */
1458 uint8_t reserved_1;
1459 uint16_t sequence_number; /* Sequence number of event */
1460 uint16_t lun; /* SCSI LUN */
1461 uint8_t reserved_2[48];
1462} mrk_entry_t;
1463
1464/*
1465 * ISP queue - Management Server entry structure definition.
1466 */
1467#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1468typedef struct {
1469 uint8_t entry_type; /* Entry type. */
1470 uint8_t entry_count; /* Entry count. */
1471 uint8_t handle_count; /* Handle count. */
1472 uint8_t entry_status; /* Entry Status. */
1473 uint32_t handle1; /* System handle. */
1474 target_id_t loop_id;
1475 uint16_t status;
1476 uint16_t control_flags; /* Control flags. */
1477 uint16_t reserved2;
1478 uint16_t timeout;
1479 uint16_t cmd_dsd_count;
1480 uint16_t total_dsd_count;
1481 uint8_t type;
1482 uint8_t r_ctl;
1483 uint16_t rx_id;
1484 uint16_t reserved3;
1485 uint32_t handle2;
1486 uint32_t rsp_bytecount;
1487 uint32_t req_bytecount;
1488 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1489 uint32_t dseg_req_length; /* Data segment 0 length. */
1490 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1491 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1492} ms_iocb_entry_t;
1493
1494
1495/*
1496 * ISP queue - Mailbox Command entry structure definition.
1497 */
1498#define MBX_IOCB_TYPE 0x39
1499struct mbx_entry {
1500 uint8_t entry_type;
1501 uint8_t entry_count;
1502 uint8_t sys_define1;
1503 /* Use sys_define1 for source type */
1504#define SOURCE_SCSI 0x00
1505#define SOURCE_IP 0x01
1506#define SOURCE_VI 0x02
1507#define SOURCE_SCTP 0x03
1508#define SOURCE_MP 0x04
1509#define SOURCE_MPIOCTL 0x05
1510#define SOURCE_ASYNC_IOCB 0x07
1511
1512 uint8_t entry_status;
1513
1514 uint32_t handle;
1515 target_id_t loop_id;
1516
1517 uint16_t status;
1518 uint16_t state_flags;
1519 uint16_t status_flags;
1520
1521 uint32_t sys_define2[2];
1522
1523 uint16_t mb0;
1524 uint16_t mb1;
1525 uint16_t mb2;
1526 uint16_t mb3;
1527 uint16_t mb6;
1528 uint16_t mb7;
1529 uint16_t mb9;
1530 uint16_t mb10;
1531 uint32_t reserved_2[2];
1532 uint8_t node_name[WWN_SIZE];
1533 uint8_t port_name[WWN_SIZE];
1534};
1535
1536/*
1537 * ISP request and response queue entry sizes
1538 */
1539#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1540#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1541
1542
1543/*
1544 * 24 bit port ID type definition.
1545 */
1546typedef union {
1547 uint32_t b24 : 24;
1548
1549 struct {
1550 uint8_t d_id[3];
1551 uint8_t rsvd_1;
1552 } r;
1553
1554 struct {
1555 uint8_t al_pa;
1556 uint8_t area;
1557 uint8_t domain;
1558 uint8_t rsvd_1;
1559 } b;
1560} port_id_t;
1561#define INVALID_PORT_ID 0xFFFFFF
1562
1563/*
1564 * Switch info gathering structure.
1565 */
1566typedef struct {
1567 port_id_t d_id;
1568 uint8_t node_name[WWN_SIZE];
1569 uint8_t port_name[WWN_SIZE];
1da177e4
LT		 1570} sw_info_t;
1571
1572/*
1573 * Inquiry command structure.
1574 */
1575#define INQ_DATA_SIZE 36
1576
1577/*
1578 * Inquiry mailbox IOCB packet definition.
1579 */
1580typedef struct {
1581 union {
1582 cmd_a64_entry_t cmd;
1583 sts_entry_t rsp;
3d71644c
AV		 1584 struct cmd_type_7 cmd24;
1585 struct sts_entry_24xx rsp24;
1da177e4
LT		 1586 } p;
1587 uint8_t inq[INQ_DATA_SIZE];
1588} inq_cmd_rsp_t;
1589
1590/*
1591 * Report LUN command structure.
1592 */
1593#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1594
1595typedef struct {
1596 uint32_t len;
1597 uint32_t rsrv;
1598} rpt_hdr_t;
1599
1600typedef struct {
1601 struct {
1602 uint8_t b : 6;
1603 uint8_t address_method : 2;
1604 } msb;
1605 uint8_t lsb;
1606 uint8_t unused[6];
1607} rpt_lun_t;
1608
1609typedef struct {
1610 rpt_hdr_t hdr;
1611 rpt_lun_t lst[MAX_LUNS];
1612} rpt_lun_lst_t;
1613
1614/*
1615 * Report Lun mailbox IOCB packet definition.
1616 */
1617typedef struct {
1618 union {
1619 cmd_a64_entry_t cmd;
1620 sts_entry_t rsp;
3d71644c
AV		 1621 struct cmd_type_7 cmd24;
1622 struct sts_entry_24xx rsp24;
1da177e4
LT		 1623 } p;
1624 rpt_lun_lst_t list;
1625} rpt_lun_cmd_rsp_t;
1626
3d71644c 1627
1da177e4
LT		 1628/*
1629 * Fibre channel port type.
1630 */
1631 typedef enum {
1632 FCT_UNKNOWN,
1633 FCT_RSCN,
1634 FCT_SWITCH,
1635 FCT_BROADCAST,
1636 FCT_INITIATOR,
1637 FCT_TARGET
1638} fc_port_type_t;
1639
1640/*
1641 * Fibre channel port structure.
1642 */
1643typedef struct fc_port {
1644 struct list_head list;
1da177e4
LT		 1645 struct scsi_qla_host *ha;
1646 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1647
1648 uint8_t node_name[WWN_SIZE];
1649 uint8_t port_name[WWN_SIZE];
1650 port_id_t d_id;
1651 uint16_t loop_id;
1652 uint16_t old_loop_id;
1653
1654 fc_port_type_t port_type;
1655
1656 atomic_t state;
1657 uint32_t flags;
1658
bdf79621 1659 unsigned int os_target_id;
1da177e4
LT		 1660
1661 uint16_t iodesc_idx_sent;
1662
1663 int port_login_retry_count;
1664 int login_retry;
1665 atomic_t port_down_timer;
1666
1667 uint8_t device_type;
1668 uint8_t unused;
1669
1670 uint8_t mp_byte; /* multi-path byte (not used) */
1671 uint8_t cur_path; /* current path id */
1672
8482e118 1673 struct fc_rport *rport;
ad3e0eda 1674 u32 supported_classes;
1da177e4
LT		 1675} fc_port_t;
1676
1677/*
1678 * Fibre channel port/lun states.
1679 */
1680#define FCS_UNCONFIGURED 1
1681#define FCS_DEVICE_DEAD 2
1682#define FCS_DEVICE_LOST 3
1683#define FCS_ONLINE 4
1684#define FCS_NOT_SUPPORTED 5
1685#define FCS_FAILOVER 6
1686#define FCS_FAILOVER_FAILED 7
1687
1688/*
1689 * FC port flags.
1690 */
1691#define FCF_FABRIC_DEVICE BIT_0
1692#define FCF_LOGIN_NEEDED BIT_1
1693#define FCF_FO_MASKED BIT_2
1694#define FCF_FAILOVER_NEEDED BIT_3
1695#define FCF_RESET_NEEDED BIT_4
1696#define FCF_PERSISTENT_BOUND BIT_5
1697#define FCF_TAPE_PRESENT BIT_6
1698#define FCF_FARP_DONE BIT_7
1699#define FCF_FARP_FAILED BIT_8
1700#define FCF_FARP_REPLY_NEEDED BIT_9
1701#define FCF_AUTH_REQ BIT_10
1702#define FCF_SEND_AUTH_REQ BIT_11
1703#define FCF_RECEIVE_AUTH_REQ BIT_12
1704#define FCF_AUTH_SUCCESS BIT_13
1705#define FCF_RLC_SUPPORT BIT_14
1706#define FCF_CONFIG BIT_15 /* Needed? */
1707#define FCF_RESCAN_NEEDED BIT_16
1708#define FCF_XP_DEVICE BIT_17
1709#define FCF_MSA_DEVICE BIT_18
1710#define FCF_EVA_DEVICE BIT_19
1711#define FCF_MSA_PORT_ACTIVE BIT_20
1712#define FCF_FAILBACK_DISABLE BIT_21
1713#define FCF_FAILOVER_DISABLE BIT_22
1714#define FCF_DSXXX_DEVICE BIT_23
1715#define FCF_AA_EVA_DEVICE BIT_24
3d71644c 1716#define FCF_AA_MSA_DEVICE BIT_25
1da177e4
LT		 1717
1718/* No loop ID flag. */
1719#define FC_NO_LOOP_ID 0x1000
1720
1da177e4
LT		 1721/*
1722 * FC-CT interface
1723 *
1724 * NOTE: All structures are big-endian in form.
1725 */
1726
1727#define CT_REJECT_RESPONSE 0x8001
1728#define CT_ACCEPT_RESPONSE 0x8002
cca5335c
AV		 1729#define CT_REASON_CANNOT_PERFORM 0x09
1730#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT		 1731
1732#define NS_N_PORT_TYPE 0x01
1733#define NS_NL_PORT_TYPE 0x02
1734#define NS_NX_PORT_TYPE 0x7F
1735
1736#define GA_NXT_CMD 0x100
1737#define GA_NXT_REQ_SIZE (16 + 4)
1738#define GA_NXT_RSP_SIZE (16 + 620)
1739
1740#define GID_PT_CMD 0x1A1
1741#define GID_PT_REQ_SIZE (16 + 4)
1742#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1743
1744#define GPN_ID_CMD 0x112
1745#define GPN_ID_REQ_SIZE (16 + 4)
1746#define GPN_ID_RSP_SIZE (16 + 8)
1747
1748#define GNN_ID_CMD 0x113
1749#define GNN_ID_REQ_SIZE (16 + 4)
1750#define GNN_ID_RSP_SIZE (16 + 8)
1751
1752#define GFT_ID_CMD 0x117
1753#define GFT_ID_REQ_SIZE (16 + 4)
1754#define GFT_ID_RSP_SIZE (16 + 32)
1755
1756#define RFT_ID_CMD 0x217
1757#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1758#define RFT_ID_RSP_SIZE 16
1759
1760#define RFF_ID_CMD 0x21F
1761#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1762#define RFF_ID_RSP_SIZE 16
1763
1764#define RNN_ID_CMD 0x213
1765#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1766#define RNN_ID_RSP_SIZE 16
1767
1768#define RSNN_NN_CMD 0x239
1769#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1770#define RSNN_NN_RSP_SIZE 16
1771
cca5335c
AV		 1772/*
1773 * HBA attribute types.
1774 */
1775#define FDMI_HBA_ATTR_COUNT 9
1776#define FDMI_HBA_NODE_NAME 1
1777#define FDMI_HBA_MANUFACTURER 2
1778#define FDMI_HBA_SERIAL_NUMBER 3
1779#define FDMI_HBA_MODEL 4
1780#define FDMI_HBA_MODEL_DESCRIPTION 5
1781#define FDMI_HBA_HARDWARE_VERSION 6
1782#define FDMI_HBA_DRIVER_VERSION 7
1783#define FDMI_HBA_OPTION_ROM_VERSION 8
1784#define FDMI_HBA_FIRMWARE_VERSION 9
1785#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1786#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1787
1788struct ct_fdmi_hba_attr {
1789 uint16_t type;
1790 uint16_t len;
1791 union {
1792 uint8_t node_name[WWN_SIZE];
1793 uint8_t manufacturer[32];
1794 uint8_t serial_num[8];
1795 uint8_t model[16];
1796 uint8_t model_desc[80];
1797 uint8_t hw_version[16];
1798 uint8_t driver_version[32];
1799 uint8_t orom_version[16];
1800 uint8_t fw_version[16];
1801 uint8_t os_version[128];
1802 uint8_t max_ct_len[4];
1803 } a;
1804};
1805
1806struct ct_fdmi_hba_attributes {
1807 uint32_t count;
1808 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1809};
1810
1811/*
1812 * Port attribute types.
1813 */
1814#define FDMI_PORT_ATTR_COUNT 5
1815#define FDMI_PORT_FC4_TYPES 1
1816#define FDMI_PORT_SUPPORT_SPEED 2
1817#define FDMI_PORT_CURRENT_SPEED 3
1818#define FDMI_PORT_MAX_FRAME_SIZE 4
1819#define FDMI_PORT_OS_DEVICE_NAME 5
1820#define FDMI_PORT_HOST_NAME 6
1821
1822struct ct_fdmi_port_attr {
1823 uint16_t type;
1824 uint16_t len;
1825 union {
1826 uint8_t fc4_types[32];
1827 uint32_t sup_speed;
1828 uint32_t cur_speed;
1829 uint32_t max_frame_size;
1830 uint8_t os_dev_name[32];
1831 uint8_t host_name[32];
1832 } a;
1833};
1834
1835/*
1836 * Port Attribute Block.
1837 */
1838struct ct_fdmi_port_attributes {
1839 uint32_t count;
1840 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1841};
1842
1843/* FDMI definitions. */
1844#define GRHL_CMD 0x100
1845#define GHAT_CMD 0x101
1846#define GRPL_CMD 0x102
1847#define GPAT_CMD 0x110
1848
1849#define RHBA_CMD 0x200
1850#define RHBA_RSP_SIZE 16
1851
1852#define RHAT_CMD 0x201
1853#define RPRT_CMD 0x210
1854
1855#define RPA_CMD 0x211
1856#define RPA_RSP_SIZE 16
1857
1858#define DHBA_CMD 0x300
1859#define DHBA_REQ_SIZE (16 + 8)
1860#define DHBA_RSP_SIZE 16
1861
1862#define DHAT_CMD 0x301
1863#define DPRT_CMD 0x310
1864#define DPA_CMD 0x311
1865
1da177e4
LT		 1866/* CT command header -- request/response common fields */
1867struct ct_cmd_hdr {
1868 uint8_t revision;
1869 uint8_t in_id[3];
1870 uint8_t gs_type;
1871 uint8_t gs_subtype;
1872 uint8_t options;
1873 uint8_t reserved;
1874};
1875
1876/* CT command request */
1877struct ct_sns_req {
1878 struct ct_cmd_hdr header;
1879 uint16_t command;
1880 uint16_t max_rsp_size;
1881 uint8_t fragment_id;
1882 uint8_t reserved[3];
1883
1884 union {
1885 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1886 struct {
1887 uint8_t reserved;
1888 uint8_t port_id[3];
1889 } port_id;
1890
1891 struct {
1892 uint8_t port_type;
1893 uint8_t domain;
1894 uint8_t area;
1895 uint8_t reserved;
1896 } gid_pt;
1897
1898 struct {
1899 uint8_t reserved;
1900 uint8_t port_id[3];
1901 uint8_t fc4_types[32];
1902 } rft_id;
1903
1904 struct {
1905 uint8_t reserved;
1906 uint8_t port_id[3];
1907 uint16_t reserved2;
1908 uint8_t fc4_feature;
1909 uint8_t fc4_type;
1910 } rff_id;
1911
1912 struct {
1913 uint8_t reserved;
1914 uint8_t port_id[3];
1915 uint8_t node_name[8];
1916 } rnn_id;
1917
1918 struct {
1919 uint8_t node_name[8];
1920 uint8_t name_len;
1921 uint8_t sym_node_name[255];
1922 } rsnn_nn;
cca5335c
AV		 1923
1924 struct {
1925 uint8_t hba_indentifier[8];
1926 } ghat;
1927
1928 struct {
1929 uint8_t hba_identifier[8];
1930 uint32_t entry_count;
1931 uint8_t port_name[8];
1932 struct ct_fdmi_hba_attributes attrs;
1933 } rhba;
1934
1935 struct {
1936 uint8_t hba_identifier[8];
1937 struct ct_fdmi_hba_attributes attrs;
1938 } rhat;
1939
1940 struct {
1941 uint8_t port_name[8];
1942 struct ct_fdmi_port_attributes attrs;
1943 } rpa;
1944
1945 struct {
1946 uint8_t port_name[8];
1947 } dhba;
1948
1949 struct {
1950 uint8_t port_name[8];
1951 } dhat;
1952
1953 struct {
1954 uint8_t port_name[8];
1955 } dprt;
1956
1957 struct {
1958 uint8_t port_name[8];
1959 } dpa;
1da177e4
LT		 1960 } req;
1961};
1962
1963/* CT command response header */
1964struct ct_rsp_hdr {
1965 struct ct_cmd_hdr header;
1966 uint16_t response;
1967 uint16_t residual;
1968 uint8_t fragment_id;
1969 uint8_t reason_code;
1970 uint8_t explanation_code;
1971 uint8_t vendor_unique;
1972};
1973
1974struct ct_sns_gid_pt_data {
1975 uint8_t control_byte;
1976 uint8_t port_id[3];
1977};
1978
1979struct ct_sns_rsp {
1980 struct ct_rsp_hdr header;
1981
1982 union {
1983 struct {
1984 uint8_t port_type;
1985 uint8_t port_id[3];
1986 uint8_t port_name[8];
1987 uint8_t sym_port_name_len;
1988 uint8_t sym_port_name[255];
1989 uint8_t node_name[8];
1990 uint8_t sym_node_name_len;
1991 uint8_t sym_node_name[255];
1992 uint8_t init_proc_assoc[8];
1993 uint8_t node_ip_addr[16];
1994 uint8_t class_of_service[4];
1995 uint8_t fc4_types[32];
1996 uint8_t ip_address[16];
1997 uint8_t fabric_port_name[8];
1998 uint8_t reserved;
1999 uint8_t hard_address[3];
2000 } ga_nxt;
2001
2002 struct {
2003 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2004 } gid_pt;
2005
2006 struct {
2007 uint8_t port_name[8];
2008 } gpn_id;
2009
2010 struct {
2011 uint8_t node_name[8];
2012 } gnn_id;
2013
2014 struct {
2015 uint8_t fc4_types[32];
2016 } gft_id;
cca5335c
AV		 2017
2018 struct {
2019 uint32_t entry_count;
2020 uint8_t port_name[8];
2021 struct ct_fdmi_hba_attributes attrs;
2022 } ghat;
1da177e4
LT		 2023 } rsp;
2024};
2025
2026struct ct_sns_pkt {
2027 union {
2028 struct ct_sns_req req;
2029 struct ct_sns_rsp rsp;
2030 } p;
2031};
2032
2033/*
2034 * SNS command structures -- for 2200 compatability.
2035 */
2036#define RFT_ID_SNS_SCMD_LEN 22
2037#define RFT_ID_SNS_CMD_SIZE 60
2038#define RFT_ID_SNS_DATA_SIZE 16
2039
2040#define RNN_ID_SNS_SCMD_LEN 10
2041#define RNN_ID_SNS_CMD_SIZE 36
2042#define RNN_ID_SNS_DATA_SIZE 16
2043
2044#define GA_NXT_SNS_SCMD_LEN 6
2045#define GA_NXT_SNS_CMD_SIZE 28
2046#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2047
2048#define GID_PT_SNS_SCMD_LEN 6
2049#define GID_PT_SNS_CMD_SIZE 28
2050#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2051
2052#define GPN_ID_SNS_SCMD_LEN 6
2053#define GPN_ID_SNS_CMD_SIZE 28
2054#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2055
2056#define GNN_ID_SNS_SCMD_LEN 6
2057#define GNN_ID_SNS_CMD_SIZE 28
2058#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2059
2060struct sns_cmd_pkt {
2061 union {
2062 struct {
2063 uint16_t buffer_length;
2064 uint16_t reserved_1;
2065 uint32_t buffer_address[2];
2066 uint16_t subcommand_length;
2067 uint16_t reserved_2;
2068 uint16_t subcommand;
2069 uint16_t size;
2070 uint32_t reserved_3;
2071 uint8_t param[36];
2072 } cmd;
2073
2074 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2075 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2076 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2077 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2078 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2079 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2080 } p;
2081};
2082
2083/* IO descriptors */
2084#define MAX_IO_DESCRIPTORS 32
2085
2086#define ABORT_IOCB_CB 0
2087#define ADISC_PORT_IOCB_CB 1
2088#define LOGOUT_PORT_IOCB_CB 2
2089#define LOGIN_PORT_IOCB_CB 3
2090#define LAST_IOCB_CB 4
2091
2092#define IODESC_INVALID_INDEX 0xFFFF
2093#define IODESC_ADISC_NEEDED 0xFFFE
2094#define IODESC_LOGIN_NEEDED 0xFFFD
2095
2096struct io_descriptor {
2097 uint16_t used:1;
2098 uint16_t idx:11;
2099 uint16_t cb_idx:4;
2100
2101 struct timer_list timer;
2102
2103 struct scsi_qla_host *ha;
2104
2105 port_id_t d_id;
2106 fc_port_t *remote_fcport;
2107
2108 uint32_t signature;
2109};
2110
2111struct qla_fw_info {
2112 unsigned short addressing; /* addressing method used to load fw */
2113#define FW_INFO_ADDR_NORMAL 0
2114#define FW_INFO_ADDR_EXTENDED 1
2115#define FW_INFO_ADDR_NOMORE 0xffff
2116 unsigned short *fwcode; /* pointer to FW array */
2117 unsigned short *fwlen; /* number of words in array */
2118 unsigned short *fwstart; /* start address for F/W */
2119 unsigned long *lfwstart; /* start address (long) for F/W */
2120};
2121
2122struct qla_board_info {
2123 char *drv_name;
2124
2125 char isp_name[8];
2126 struct qla_fw_info *fw_info;
fca29703
AV		 2127 char *fw_fname;
2128 struct scsi_host_template *sht;
1da177e4
LT		 2129};
2130
2131/* Return data from MBC_GET_ID_LIST call. */
2132struct gid_list_info {
2133 uint8_t al_pa;
2134 uint8_t area;
fa2a1ce5 2135 uint8_t domain;
1da177e4
LT		 2136 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2137 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2138 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT		 2139};
2140#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2141
abbd8870
AV		 2142/*
2143 * ISP operations
2144 */
2145struct isp_operations {
2146
2147 int (*pci_config) (struct scsi_qla_host *);
2148 void (*reset_chip) (struct scsi_qla_host *);
2149 int (*chip_diag) (struct scsi_qla_host *);
2150 void (*config_rings) (struct scsi_qla_host *);
2151 void (*reset_adapter) (struct scsi_qla_host *);
2152 int (*nvram_config) (struct scsi_qla_host *);
2153 void (*update_fw_options) (struct scsi_qla_host *);
2154 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2155
2156 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2157 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2158
2159 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2160 void (*enable_intrs) (struct scsi_qla_host *);
2161 void (*disable_intrs) (struct scsi_qla_host *);
2162
2163 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2164 int (*abort_target) (struct fc_port *);
2165 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2166 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV		 2167 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2168 uint8_t, uint8_t);
abbd8870
AV		 2169
2170 uint16_t (*calc_req_entries) (uint16_t);
2171 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2172 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV		 2173 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2174 uint32_t);
abbd8870
AV		 2175
2176 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2177 uint32_t, uint32_t);
2178 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2179 uint32_t);
2180
2181 void (*fw_dump) (struct scsi_qla_host *, int);
2182 void (*ascii_fw_dump) (struct scsi_qla_host *);
2183};
2184
1da177e4
LT		 2185/*
2186 * Linux Host Adapter structure
2187 */
2188typedef struct scsi_qla_host {
2189 struct list_head list;
2190
2191 /* Commonly used flags and state information. */
2192 struct Scsi_Host *host;
2193 struct pci_dev *pdev;
2194
2195 unsigned long host_no;
2196 unsigned long instance;
2197
2198 volatile struct {
2199 uint32_t init_done :1;
2200 uint32_t online :1;
2201 uint32_t mbox_int :1;
2202 uint32_t mbox_busy :1;
2203 uint32_t rscn_queue_overflow :1;
2204 uint32_t reset_active :1;
2205
2206 uint32_t management_server_logged_in :1;
2207 uint32_t process_response_queue :1;
2208
2209 uint32_t disable_risc_code_load :1;
2210 uint32_t enable_64bit_addressing :1;
2211 uint32_t enable_lip_reset :1;
2212 uint32_t enable_lip_full_login :1;
2213 uint32_t enable_target_reset :1;
2214 uint32_t enable_led_scheme :1;
3d71644c
AV		 2215 uint32_t msi_enabled :1;
2216 uint32_t msix_enabled :1;
1da177e4
LT		 2217 } flags;
2218
2219 atomic_t loop_state;
2220#define LOOP_TIMEOUT 1
2221#define LOOP_DOWN 2
2222#define LOOP_UP 3
2223#define LOOP_UPDATE 4
2224#define LOOP_READY 5
2225#define LOOP_DEAD 6
2226
2227 unsigned long dpc_flags;
2228#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2229#define RESET_ACTIVE 1
2230#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2231#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2232#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2233#define LOOP_RESYNC_ACTIVE 5
2234#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2235#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2236#define MAILBOX_RETRY 8
2237#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2238#define FAILOVER_EVENT_NEEDED 10
2239#define FAILOVER_EVENT 11
2240#define FAILOVER_NEEDED 12
2241#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2242#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2243#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2244#define ABORT_QUEUES_NEEDED 16
2245#define RELOGIN_NEEDED 17
2246#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2247#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2248#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2249#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2250#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
fa2a1ce5 2251#define IOCTL_ERROR_RECOVERY 23
1da177e4 2252#define LOOP_RESET_NEEDED 24
3d71644c 2253#define BEACON_BLINK_NEEDED 25
cca5335c 2254#define REGISTER_FDMI_NEEDED 26
1da177e4
LT		 2255
2256 uint32_t device_flags;
2257#define DFLG_LOCAL_DEVICES BIT_0
2258#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2259#define DFLG_FABRIC_DEVICES BIT_2
2260#define SWITCH_FOUND BIT_3
2261#define DFLG_NO_CABLE BIT_4
2262
2263 /* SRB cache. */
2264#define SRB_MIN_REQ 128
2265 mempool_t *srb_mempool;
2266
fa2a1ce5 2267 /* This spinlock is used to protect "io transactions", you must
1da177e4
LT		 2268 * aquire it before doing any IO to the card, eg with RD_REG*() and
2269 * WRT_REG*() for the duration of your entire commandtransaction.
2270 *
2271 * This spinlock is of lower priority than the io request lock.
2272 */
2273
2274 spinlock_t hardware_lock ____cacheline_aligned;
2275
2276 device_reg_t __iomem *iobase; /* Base I/O address */
2277 unsigned long pio_address;
2278 unsigned long pio_length;
2279#define MIN_IOBASE_LEN 0x100
2280
2281 /* ISP ring lock, rings, and indexes */
2282 dma_addr_t request_dma; /* Physical address. */
2283 request_t *request_ring; /* Base virtual address */
2284 request_t *request_ring_ptr; /* Current address. */
2285 uint16_t req_ring_index; /* Current index. */
2286 uint16_t req_q_cnt; /* Number of available entries. */
2287 uint16_t request_q_length;
2288
2289 dma_addr_t response_dma; /* Physical address. */
2290 response_t *response_ring; /* Base virtual address */
2291 response_t *response_ring_ptr; /* Current address. */
2292 uint16_t rsp_ring_index; /* Current index. */
2293 uint16_t response_q_length;
fa2a1ce5 2294
abbd8870 2295 struct isp_operations isp_ops;
1da177e4
LT		 2296
2297 /* Outstandings ISP commands. */
2298 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
fa2a1ce5 2299 uint32_t current_outstanding_cmd;
1da177e4
LT		 2300 srb_t *status_srb; /* Status continuation entry. */
2301
1da177e4
LT		 2302 uint16_t revision;
2303 uint8_t ports;
1da177e4
LT		 2304
2305 /* ISP configuration data. */
2306 uint16_t loop_id; /* Host adapter loop id */
2307 uint16_t fb_rev;
2308
2309 port_id_t d_id; /* Host adapter port id */
2310 uint16_t max_public_loop_ids;
2311 uint16_t min_external_loopid; /* First external loop Id */
2312
2313 uint16_t link_data_rate; /* F/W operating speed */
2314
2315 uint8_t current_topology;
2316 uint8_t prev_topology;
2317#define ISP_CFG_NL 1
2318#define ISP_CFG_N 2
2319#define ISP_CFG_FL 4
2320#define ISP_CFG_F 8
2321
2322 uint8_t operating_mode; /* F/W operating mode */
2323#define LOOP 0
2324#define P2P 1
2325#define LOOP_P2P 2
2326#define P2P_LOOP 3
2327
fa2a1ce5 2328 uint8_t marker_needed;
1da177e4
LT		 2329
2330 uint8_t interrupts_on;
2331
2332 /* HBA serial number */
2333 uint8_t serial0;
2334 uint8_t serial1;
2335 uint8_t serial2;
2336
2337 /* NVRAM configuration data */
3d71644c 2338 uint16_t nvram_size;
1da177e4
LT		 2339 uint16_t nvram_base;
2340
2341 uint16_t loop_reset_delay;
1da177e4
LT		 2342 uint8_t retry_count;
2343 uint8_t login_timeout;
2344 uint16_t r_a_tov;
2345 int port_down_retry_count;
1da177e4 2346 uint8_t mbx_count;
1da177e4 2347 uint16_t last_loop_id;
cca5335c 2348 uint16_t mgmt_svr_loop_id;
1da177e4 2349
fa2a1ce5 2350 uint32_t login_retry_count;
1da177e4
LT		 2351
2352 /* Fibre Channel Device List. */
2353 struct list_head fcports;
2354 struct list_head rscn_fcports;
2355
2356 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2357 uint16_t iodesc_signature;
2358
1da177e4
LT		 2359 /* RSCN queue. */
2360 uint32_t rscn_queue[MAX_RSCN_COUNT];
2361 uint8_t rscn_in_ptr;
2362 uint8_t rscn_out_ptr;
2363
2364 /* SNS command interfaces. */
2365 ms_iocb_entry_t *ms_iocb;
2366 dma_addr_t ms_iocb_dma;
2367 struct ct_sns_pkt *ct_sns;
2368 dma_addr_t ct_sns_dma;
2369 /* SNS command interfaces for 2200. */
2370 struct sns_cmd_pkt *sns_cmd;
2371 dma_addr_t sns_cmd_dma;
2372
2373 pid_t dpc_pid;
2374 int dpc_should_die;
2375 struct completion dpc_inited;
2376 struct completion dpc_exited;
2377 struct semaphore *dpc_wait;
2378 uint8_t dpc_active; /* DPC routine is active */
2379
2380 /* Timeout timers. */
1da177e4
LT		 2381 uint8_t loop_down_abort_time; /* port down timer */
2382 atomic_t loop_down_timer; /* loop down timer */
2383 uint8_t link_down_timeout; /* link down timeout */
2384
2385 uint32_t timer_active;
2386 struct timer_list timer;
2387
2388 dma_addr_t gid_list_dma;
2389 struct gid_list_info *gid_list;
abbd8870 2390 int gid_list_info_size;
1da177e4
LT		 2391
2392 dma_addr_t rlc_rsp_dma;
2393 rpt_lun_cmd_rsp_t *rlc_rsp;
2394
fa2a1ce5 2395 /* Small DMA pool allocations -- maximum 256 bytes in length. */
1da177e4
LT		 2396#define DMA_POOL_SIZE 256
2397 struct dma_pool *s_dma_pool;
2398
2399 dma_addr_t init_cb_dma;
3d71644c
AV		 2400 init_cb_t *init_cb;
2401 int init_cb_size;
1da177e4
LT		 2402
2403 dma_addr_t iodesc_pd_dma;
2404 port_database_t *iodesc_pd;
2405
2406 /* These are used by mailbox operations. */
2407 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2408
2409 mbx_cmd_t *mcp;
2410 unsigned long mbx_cmd_flags;
2411#define MBX_INTERRUPT 1
2412#define MBX_INTR_WAIT 2
2413#define MBX_UPDATE_FLASH_ACTIVE 3
2414
2415 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2416
2417 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2418 struct semaphore mbx_intr_sem; /* Used for completion notification */
2419
2420 uint32_t mbx_flags;
2421#define MBX_IN_PROGRESS BIT_0
2422#define MBX_BUSY BIT_1 /* Got the Access */
fa2a1ce5 2423#define MBX_SLEEPING_ON_SEM BIT_2
1da177e4
LT		 2424#define MBX_POLLING_FOR_COMP BIT_3
2425#define MBX_COMPLETED BIT_4
fa2a1ce5 2426#define MBX_TIMEDOUT BIT_5
1da177e4
LT		 2427#define MBX_ACCESS_TIMEDOUT BIT_6
2428
2429 mbx_cmd_t mc;
2430
1da177e4
LT		 2431 /* Basic firmware related information. */
2432 struct qla_board_info *brd_info;
2433 uint16_t fw_major_version;
2434 uint16_t fw_minor_version;
2435 uint16_t fw_subminor_version;
2436 uint16_t fw_attributes;
2437 uint32_t fw_memory_size;
2438 uint32_t fw_transfer_size;
2439
2440 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2441 uint8_t fw_seriallink_options[4];
3d71644c 2442 uint16_t fw_seriallink_options24[4];
1da177e4
LT		 2443
2444 /* Firmware dump information. */
2445 void *fw_dump;
2446 int fw_dump_order;
2447 int fw_dump_reading;
2448 char *fw_dump_buffer;
2449 int fw_dump_buffer_len;
2450
3d71644c
AV		 2451 int fw_dumped;
2452 void *fw_dump24;
2453 int fw_dump24_len;
2454
1da177e4 2455 uint8_t host_str[16];
3d71644c 2456 uint32_t pci_attr;
1da177e4
LT		 2457
2458 uint16_t product_id[4];
2459
2460 uint8_t model_number[16+1];
2461#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2462 char *model_desc;
cca5335c 2463 uint8_t adapter_id[16+1];
1da177e4 2464
3d71644c
AV		 2465 uint8_t *node_name;
2466 uint8_t *port_name;
1da177e4
LT		 2467 uint32_t isp_abort_cnt;
2468
1da177e4
LT		 2469 /* Needed for BEACON */
2470 uint16_t beacon_blink_led;
2471 uint16_t beacon_green_on;
2472} scsi_qla_host_t;
2473
2474
2475/*
2476 * Macros to help code, maintain, etc.
2477 */
2478#define LOOP_TRANSITION(ha) \
2479 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2480 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2481
2482#define LOOP_NOT_READY(ha) \
2483 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2484 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2485 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2486 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2487 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2488
1da177e4
LT		 2489#define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2490
2491#define TGT_Q(ha, t) (ha->otgt[t])
1da177e4
LT		 2492
2493#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2494
2495#define qla_printk(level, ha, format, arg...) \
2496 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2497
2498/*
2499 * qla2x00 local function return status codes
2500 */
2501#define MBS_MASK 0x3fff
2502
2503#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2504#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2505#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2506#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2507#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2508#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2509#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2510#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2511#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2512#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2513
2514#define QLA_FUNCTION_TIMEOUT 0x100
2515#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2516#define QLA_FUNCTION_FAILED 0x102
2517#define QLA_MEMORY_ALLOC_FAILED 0x103
2518#define QLA_LOCK_TIMEOUT 0x104
2519#define QLA_ABORTED 0x105
2520#define QLA_SUSPENDED 0x106
2521#define QLA_BUSY 0x107
2522#define QLA_RSCNS_HANDLED 0x108
cca5335c 2523#define QLA_ALREADY_REGISTERED 0x109
1da177e4
LT		 2524
2525/*
2526* Stat info for all adpaters
2527*/
2528struct _qla2x00stats {
2529 unsigned long mboxtout; /* mailbox timeouts */
2530 unsigned long mboxerr; /* mailbox errors */
2531 unsigned long ispAbort; /* ISP aborts */
2532 unsigned long debugNo;
2533 unsigned long loop_resync;
2534 unsigned long outarray_full;
2535 unsigned long retry_q_cnt;
2536};
2537
2538#define NVRAM_DELAY() udelay(10)
2539
2540#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2541
2542/*
2543 * Flash support definitions
2544 */
2545#define FLASH_IMAGE_SIZE 131072
2546
2547#include "qla_gbl.h"
2548#include "qla_dbg.h"
2549#include "qla_inline.h"
1da177e4
LT		 2550
2551/*
2552* String arrays
2553*/
2554#define LINESIZE 256
2555#define MAXARGS 26
2556
2557#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2558#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2559#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2560#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2561#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2562#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2563
2564#endif
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