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[SCSI] qla2xxx: Add host port-type FC transport attribute.
[net-next-2.6.git] / drivers / scsi / qla2xxx / qla_def.h
CommitLineData
fa90c54f
AV		 1/*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
1da177e4
LT		 7#ifndef __QLA_DEF_H
8#define __QLA_DEF_H
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/completion.h>
abbd8870 23#include <linux/interrupt.h>
19a7b4ae 24#include <linux/workqueue.h>
5433383e 25#include <linux/firmware.h>
1da177e4
LT		 26#include <asm/semaphore.h>
27
28#include <scsi/scsi.h>
29#include <scsi/scsi_host.h>
30#include <scsi/scsi_device.h>
31#include <scsi/scsi_cmnd.h>
32
5433383e 33#if defined(CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE)
1da177e4
LT		 34#if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
35#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
36#else
37#define IS_QLA2100(ha) 0
38#endif
39
40#if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
41#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
42#else
43#define IS_QLA2200(ha) 0
44#endif
45
46#if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
47#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
48#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
49#else
50#define IS_QLA2300(ha) 0
51#define IS_QLA2312(ha) 0
52#endif
53
54#if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
55#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
56#else
57#define IS_QLA2322(ha) 0
58#endif
59
60#if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
61#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
62#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
63#else
64#define IS_QLA6312(ha) 0
65#define IS_QLA6322(ha) 0
66#endif
67
3d71644c
AV		 68#if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
69#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
70#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
71#else
72#define IS_QLA2422(ha) 0
73#define IS_QLA2432(ha) 0
74#endif
75
76#if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
77#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
78#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
79#else
80#define IS_QLA2512(ha) 0
81#define IS_QLA2522(ha) 0
82#endif
83
5433383e
AV		 84#else /* !defined(CONFIG_SCSI_QLA2XXX_EMBEDDED_FIRMWARE) */
85
86#define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
87#define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
88#define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
89#define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
90#define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
91#define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
92#define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
93#define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
94#define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
95#define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
96#define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
97#endif
98
1da177e4
LT		 99#define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
100 IS_QLA6312(ha) || IS_QLA6322(ha))
3d71644c
AV		 101#define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
102#define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
103
1da177e4
LT		 104/*
105 * Only non-ISP2[12]00 have extended addressing support in the firmware.
106 */
107#define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
108
109/*
110 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
111 * but that's fine as we don't look at the last 24 ones for
112 * ISP2100 HBAs.
113 */
114#define MAILBOX_REGISTER_COUNT_2100 8
115#define MAILBOX_REGISTER_COUNT 32
116
117#define QLA2200A_RISC_ROM_VER 4
118#define FPM_2300 6
119#define FPM_2310 7
120
121#include "qla_settings.h"
122
fa2a1ce5 123/*
1da177e4
LT		 124 * Data bit definitions
125 */
126#define BIT_0 0x1
127#define BIT_1 0x2
128#define BIT_2 0x4
129#define BIT_3 0x8
130#define BIT_4 0x10
131#define BIT_5 0x20
132#define BIT_6 0x40
133#define BIT_7 0x80
134#define BIT_8 0x100
135#define BIT_9 0x200
136#define BIT_10 0x400
137#define BIT_11 0x800
138#define BIT_12 0x1000
139#define BIT_13 0x2000
140#define BIT_14 0x4000
141#define BIT_15 0x8000
142#define BIT_16 0x10000
143#define BIT_17 0x20000
144#define BIT_18 0x40000
145#define BIT_19 0x80000
146#define BIT_20 0x100000
147#define BIT_21 0x200000
148#define BIT_22 0x400000
149#define BIT_23 0x800000
150#define BIT_24 0x1000000
151#define BIT_25 0x2000000
152#define BIT_26 0x4000000
153#define BIT_27 0x8000000
154#define BIT_28 0x10000000
155#define BIT_29 0x20000000
156#define BIT_30 0x40000000
157#define BIT_31 0x80000000
158
159#define LSB(x) ((uint8_t)(x))
160#define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
161
162#define LSW(x) ((uint16_t)(x))
163#define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
164
165#define LSD(x) ((uint32_t)((uint64_t)(x)))
166#define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
167
168
169/*
170 * I/O register
171*/
172
173#define RD_REG_BYTE(addr) readb(addr)
174#define RD_REG_WORD(addr) readw(addr)
175#define RD_REG_DWORD(addr) readl(addr)
176#define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
177#define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
178#define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
179#define WRT_REG_BYTE(addr, data) writeb(data,addr)
180#define WRT_REG_WORD(addr, data) writew(data,addr)
181#define WRT_REG_DWORD(addr, data) writel(data,addr)
182
183/*
184 * Fibre Channel device definitions.
185 */
186#define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
187#define MAX_FIBRE_DEVICES 512
cc4731f5 188#define MAX_FIBRE_LUNS 0xFFFF
1da177e4
LT		 189#define MAX_RSCN_COUNT 32
190#define MAX_HOST_COUNT 16
191
192/*
193 * Host adapter default definitions.
194 */
195#define MAX_BUSES 1 /* We only have one bus today */
196#define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
197#define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
1da177e4
LT		 198#define MIN_LUNS 8
199#define MAX_LUNS MAX_FIBRE_LUNS
fa2a1ce5
AV		 200#define MAX_CMDS_PER_LUN 255
201
1da177e4
LT		 202/*
203 * Fibre Channel device definitions.
204 */
205#define SNS_LAST_LOOP_ID_2100 0xfe
206#define SNS_LAST_LOOP_ID_2300 0x7ff
207
208#define LAST_LOCAL_LOOP_ID 0x7d
209#define SNS_FL_PORT 0x7e
210#define FABRIC_CONTROLLER 0x7f
211#define SIMPLE_NAME_SERVER 0x80
212#define SNS_FIRST_LOOP_ID 0x81
213#define MANAGEMENT_SERVER 0xfe
214#define BROADCAST 0xff
215
3d71644c
AV		 216/*
217 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
218 * valid range of an N-PORT id is 0 through 0x7ef.
219 */
220#define NPH_LAST_HANDLE 0x7ef
cca5335c 221#define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
3d71644c
AV		 222#define NPH_SNS 0x7fc /* FFFFFC */
223#define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
224#define NPH_F_PORT 0x7fe /* FFFFFE */
225#define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
226
227#define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
228#include "qla_fw.h"
1da177e4
LT		 229
230/*
231 * Timeout timer counts in seconds
232 */
8482e118 233#define PORT_RETRY_TIME 1
1da177e4
LT		 234#define LOOP_DOWN_TIMEOUT 60
235#define LOOP_DOWN_TIME 255 /* 240 */
236#define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
237
238/* Maximum outstanding commands in ISP queues (1-65535) */
239#define MAX_OUTSTANDING_COMMANDS 1024
240
241/* ISP request and response entry counts (37-65535) */
242#define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
243#define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
244#define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
3d71644c 245#define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
1da177e4
LT		 246#define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
247#define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
248
249/*
fa2a1ce5 250 * SCSI Request Block
1da177e4
LT		 251 */
252typedef struct srb {
253 struct list_head list;
254
255 struct scsi_qla_host *ha; /* HA the SP is queued on */
bdf79621 256 struct fc_port *fcport;
1da177e4
LT		 257
258 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
259
260 struct timer_list timer; /* Command timer */
fa2a1ce5 261 atomic_t ref_count; /* Reference count for this structure */
1da177e4
LT		 262 uint16_t flags;
263
264 /* Request state */
265 uint16_t state;
266
1da177e4
LT		 267 /* Single transfer DMA context */
268 dma_addr_t dma_handle;
269
270 uint32_t request_sense_length;
271 uint8_t *request_sense_ptr;
272
1da177e4
LT		 273 /* SRB magic number */
274 uint16_t magic;
275#define SRB_MAGIC 0x10CB
276} srb_t;
277
278/*
279 * SRB flag definitions
280 */
281#define SRB_TIMEOUT BIT_0 /* Command timed out */
282#define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
283#define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
284#define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
285
286#define SRB_ABORTED BIT_4 /* Command aborted command already */
287#define SRB_RETRY BIT_5 /* Command needs retrying */
288#define SRB_GOT_SENSE BIT_6 /* Command has sense data */
289#define SRB_FAILOVER BIT_7 /* Command in failover state */
290
291#define SRB_BUSY BIT_8 /* Command is in busy retry state */
292#define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
293#define SRB_IOCTL BIT_10 /* IOCTL command. */
294#define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
295
296/*
297 * SRB state definitions
298 */
299#define SRB_FREE_STATE 0 /* returned back */
300#define SRB_PENDING_STATE 1 /* queued in LUN Q */
301#define SRB_ACTIVE_STATE 2 /* in Active Array */
302#define SRB_DONE_STATE 3 /* queued in Done Queue */
303#define SRB_RETRY_STATE 4 /* in Retry Queue */
304#define SRB_SUSPENDED_STATE 5 /* in suspended state */
305#define SRB_NO_QUEUE_STATE 6 /* is in between states */
306#define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
307#define SRB_FAILOVER_STATE 8 /* in Failover Queue */
308#define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
309
310
311/*
312 * ISP I/O Register Set structure definitions.
313 */
3d71644c
AV		 314struct device_reg_2xxx {
315 uint16_t flash_address; /* Flash BIOS address */
316 uint16_t flash_data; /* Flash BIOS data */
1da177e4 317 uint16_t unused_1[1]; /* Gap */
3d71644c 318 uint16_t ctrl_status; /* Control/Status */
fa2a1ce5 319#define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
1da177e4
LT		 320#define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
321#define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
322
3d71644c 323 uint16_t ictrl; /* Interrupt control */
1da177e4
LT		 324#define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
325#define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
326
3d71644c 327 uint16_t istatus; /* Interrupt status */
1da177e4
LT		 328#define ISR_RISC_INT BIT_3 /* RISC interrupt */
329
3d71644c
AV		 330 uint16_t semaphore; /* Semaphore */
331 uint16_t nvram; /* NVRAM register. */
1da177e4
LT		 332#define NVR_DESELECT 0
333#define NVR_BUSY BIT_15
334#define NVR_WRT_ENABLE BIT_14 /* Write enable */
335#define NVR_PR_ENABLE BIT_13 /* Protection register enable */
336#define NVR_DATA_IN BIT_3
337#define NVR_DATA_OUT BIT_2
338#define NVR_SELECT BIT_1
339#define NVR_CLOCK BIT_0
340
341 union {
342 struct {
3d71644c
AV		 343 uint16_t mailbox0;
344 uint16_t mailbox1;
345 uint16_t mailbox2;
346 uint16_t mailbox3;
347 uint16_t mailbox4;
348 uint16_t mailbox5;
349 uint16_t mailbox6;
350 uint16_t mailbox7;
351 uint16_t unused_2[59]; /* Gap */
1da177e4
LT		 352 } __attribute__((packed)) isp2100;
353 struct {
3d71644c
AV		 354 /* Request Queue */
355 uint16_t req_q_in; /* In-Pointer */
356 uint16_t req_q_out; /* Out-Pointer */
357 /* Response Queue */
358 uint16_t rsp_q_in; /* In-Pointer */
359 uint16_t rsp_q_out; /* Out-Pointer */
1da177e4
LT		 360
361 /* RISC to Host Status */
fa2a1ce5 362 uint32_t host_status;
1da177e4
LT		 363#define HSR_RISC_INT BIT_15 /* RISC interrupt */
364#define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
365
366 /* Host to Host Semaphore */
fa2a1ce5 367 uint16_t host_semaphore;
3d71644c
AV		 368 uint16_t unused_3[17]; /* Gap */
369 uint16_t mailbox0;
370 uint16_t mailbox1;
371 uint16_t mailbox2;
372 uint16_t mailbox3;
373 uint16_t mailbox4;
374 uint16_t mailbox5;
375 uint16_t mailbox6;
376 uint16_t mailbox7;
377 uint16_t mailbox8;
378 uint16_t mailbox9;
379 uint16_t mailbox10;
380 uint16_t mailbox11;
381 uint16_t mailbox12;
382 uint16_t mailbox13;
383 uint16_t mailbox14;
384 uint16_t mailbox15;
385 uint16_t mailbox16;
386 uint16_t mailbox17;
387 uint16_t mailbox18;
388 uint16_t mailbox19;
389 uint16_t mailbox20;
390 uint16_t mailbox21;
391 uint16_t mailbox22;
392 uint16_t mailbox23;
393 uint16_t mailbox24;
394 uint16_t mailbox25;
395 uint16_t mailbox26;
396 uint16_t mailbox27;
397 uint16_t mailbox28;
398 uint16_t mailbox29;
399 uint16_t mailbox30;
400 uint16_t mailbox31;
401 uint16_t fb_cmd;
402 uint16_t unused_4[10]; /* Gap */
1da177e4
LT		 403 } __attribute__((packed)) isp2300;
404 } u;
405
3d71644c 406 uint16_t fpm_diag_config;
1da177e4 407 uint16_t unused_5[0x6]; /* Gap */
3d71644c 408 uint16_t pcr; /* Processor Control Register. */
1da177e4 409 uint16_t unused_6[0x5]; /* Gap */
3d71644c 410 uint16_t mctr; /* Memory Configuration and Timing. */
1da177e4 411 uint16_t unused_7[0x3]; /* Gap */
3d71644c 412 uint16_t fb_cmd_2100; /* Unused on 23XX */
1da177e4 413 uint16_t unused_8[0x3]; /* Gap */
3d71644c 414 uint16_t hccr; /* Host command & control register. */
1da177e4
LT		 415#define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
416#define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
417 /* HCCR commands */
418#define HCCR_RESET_RISC 0x1000 /* Reset RISC */
419#define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
420#define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
421#define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
422#define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
423#define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
424#define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
425#define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
426
427 uint16_t unused_9[5]; /* Gap */
3d71644c
AV		 428 uint16_t gpiod; /* GPIO Data register. */
429 uint16_t gpioe; /* GPIO Enable register. */
1da177e4
LT		 430#define GPIO_LED_MASK 0x00C0
431#define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
432#define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
433#define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
434#define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
435
436 union {
437 struct {
3d71644c
AV		 438 uint16_t unused_10[8]; /* Gap */
439 uint16_t mailbox8;
440 uint16_t mailbox9;
441 uint16_t mailbox10;
442 uint16_t mailbox11;
443 uint16_t mailbox12;
444 uint16_t mailbox13;
445 uint16_t mailbox14;
446 uint16_t mailbox15;
447 uint16_t mailbox16;
448 uint16_t mailbox17;
449 uint16_t mailbox18;
450 uint16_t mailbox19;
451 uint16_t mailbox20;
452 uint16_t mailbox21;
453 uint16_t mailbox22;
454 uint16_t mailbox23; /* Also probe reg. */
1da177e4
LT		 455 } __attribute__((packed)) isp2200;
456 } u_end;
3d71644c
AV		 457};
458
9a168bdd 459typedef union {
3d71644c
AV		 460 struct device_reg_2xxx isp;
461 struct device_reg_24xx isp24;
1da177e4
LT		 462} device_reg_t;
463
464#define ISP_REQ_Q_IN(ha, reg) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 &(reg)->u.isp2100.mailbox4 : \
467 &(reg)->u.isp2300.req_q_in)
468#define ISP_REQ_Q_OUT(ha, reg) \
469 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
470 &(reg)->u.isp2100.mailbox4 : \
471 &(reg)->u.isp2300.req_q_out)
472#define ISP_RSP_Q_IN(ha, reg) \
473 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
474 &(reg)->u.isp2100.mailbox5 : \
475 &(reg)->u.isp2300.rsp_q_in)
476#define ISP_RSP_Q_OUT(ha, reg) \
477 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
478 &(reg)->u.isp2100.mailbox5 : \
479 &(reg)->u.isp2300.rsp_q_out)
480
481#define MAILBOX_REG(ha, reg, num) \
482 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
483 (num < 8 ? \
484 &(reg)->u.isp2100.mailbox0 + (num) : \
485 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
486 &(reg)->u.isp2300.mailbox0 + (num))
487#define RD_MAILBOX_REG(ha, reg, num) \
488 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
489#define WRT_MAILBOX_REG(ha, reg, num, data) \
490 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
491
492#define FB_CMD_REG(ha, reg) \
493 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
494 &(reg)->fb_cmd_2100 : \
495 &(reg)->u.isp2300.fb_cmd)
496#define RD_FB_CMD_REG(ha, reg) \
497 RD_REG_WORD(FB_CMD_REG(ha, reg))
498#define WRT_FB_CMD_REG(ha, reg, data) \
499 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
500
501typedef struct {
502 uint32_t out_mb; /* outbound from driver */
503 uint32_t in_mb; /* Incoming from RISC */
504 uint16_t mb[MAILBOX_REGISTER_COUNT];
505 long buf_size;
506 void *bufp;
507 uint32_t tov;
508 uint8_t flags;
509#define MBX_DMA_IN BIT_0
510#define MBX_DMA_OUT BIT_1
511#define IOCTL_CMD BIT_2
512} mbx_cmd_t;
513
514#define MBX_TOV_SECONDS 30
515
516/*
517 * ISP product identification definitions in mailboxes after reset.
518 */
519#define PROD_ID_1 0x4953
520#define PROD_ID_2 0x0000
521#define PROD_ID_2a 0x5020
522#define PROD_ID_3 0x2020
523
524/*
525 * ISP mailbox Self-Test status codes
526 */
527#define MBS_FRM_ALIVE 0 /* Firmware Alive. */
528#define MBS_CHKSUM_ERR 1 /* Checksum Error. */
529#define MBS_BUSY 4 /* Busy. */
530
531/*
532 * ISP mailbox command complete status codes
533 */
534#define MBS_COMMAND_COMPLETE 0x4000
535#define MBS_INVALID_COMMAND 0x4001
536#define MBS_HOST_INTERFACE_ERROR 0x4002
537#define MBS_TEST_FAILED 0x4003
538#define MBS_COMMAND_ERROR 0x4005
539#define MBS_COMMAND_PARAMETER_ERROR 0x4006
540#define MBS_PORT_ID_USED 0x4007
541#define MBS_LOOP_ID_USED 0x4008
542#define MBS_ALL_IDS_IN_USE 0x4009
543#define MBS_NOT_LOGGED_IN 0x400A
3d71644c
AV		 544#define MBS_LINK_DOWN_ERROR 0x400B
545#define MBS_DIAG_ECHO_TEST_ERROR 0x400C
1da177e4
LT		 546
547/*
548 * ISP mailbox asynchronous event status codes
549 */
550#define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
551#define MBA_RESET 0x8001 /* Reset Detected. */
552#define MBA_SYSTEM_ERR 0x8002 /* System Error. */
553#define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
554#define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
555#define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
556#define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
557 /* occurred. */
558#define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
559#define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
560#define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
561#define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
562#define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
563#define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
564#define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
565#define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
566#define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
567#define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
568#define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
569#define MBA_IP_RECEIVE 0x8023 /* IP Received. */
570#define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
571#define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
572#define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
573#define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
574 /* used. */
575#define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
576#define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
577#define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
578#define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
579#define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
580#define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
581#define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
582#define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
583#define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
584#define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
585#define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
586#define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
587#define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
588
589/*
590 * Firmware options 1, 2, 3.
591 */
592#define FO1_AE_ON_LIPF8 BIT_0
593#define FO1_AE_ALL_LIP_RESET BIT_1
594#define FO1_CTIO_RETRY BIT_3
595#define FO1_DISABLE_LIP_F7_SW BIT_4
596#define FO1_DISABLE_100MS_LOS_WAIT BIT_5
3d71644c 597#define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
1da177e4
LT		 598#define FO1_AE_ON_LOOP_INIT_ERR BIT_7
599#define FO1_SET_EMPHASIS_SWING BIT_8
600#define FO1_AE_AUTO_BYPASS BIT_9
601#define FO1_ENABLE_PURE_IOCB BIT_10
602#define FO1_AE_PLOGI_RJT BIT_11
603#define FO1_ENABLE_ABORT_SEQUENCE BIT_12
604#define FO1_AE_QUEUE_FULL BIT_13
605
606#define FO2_ENABLE_ATIO_TYPE_3 BIT_0
607#define FO2_REV_LOOPBACK BIT_1
608
609#define FO3_ENABLE_EMERG_IOCB BIT_0
610#define FO3_AE_RND_ERROR BIT_1
611
3d71644c
AV		 612/* 24XX additional firmware options */
613#define ADD_FO_COUNT 3
614#define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
615#define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
616
617#define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
618
619#define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
620
1da177e4
LT		 621/*
622 * ISP mailbox commands
623 */
624#define MBC_LOAD_RAM 1 /* Load RAM. */
625#define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
626#define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
627#define MBC_READ_RAM_WORD 5 /* Read RAM word. */
628#define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
629#define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
630#define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
631#define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
632#define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
633#define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
634#define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
635#define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
636#define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
637#define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
f6ef3b18 638#define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
1da177e4
LT		 639#define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
640#define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
641#define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
642#define MBC_RESET 0x18 /* Reset. */
643#define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
644#define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
645#define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
646#define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
647#define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
648#define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
649#define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
650#define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
651#define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
652#define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
653#define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
654#define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
655#define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
656#define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
657#define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
658#define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
659#define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
660#define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
661#define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
662#define MBC_DATA_RATE 0x5d /* Get RNID parameters */
663#define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
664#define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
665 /* Initialization Procedure */
666#define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
667#define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
668#define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
669#define MBC_TARGET_RESET 0x66 /* Target Reset. */
670#define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
671#define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
672#define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
673#define MBC_GET_PORT_NAME 0x6a /* Get port name. */
674#define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
675#define MBC_LIP_RESET 0x6c /* LIP reset. */
676#define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
677 /* commandd. */
678#define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
679#define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
680#define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
681#define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
682#define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
683#define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
684#define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
685#define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
686#define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
687#define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
688#define MBC_LUN_RESET 0x7E /* Send LUN reset */
689
3d71644c
AV		 690/*
691 * ISP24xx mailbox commands
692 */
693#define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
694#define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
695#define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
696#define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
697#define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
698#define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
699#define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
700#define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
701#define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
702#define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
703#define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
704#define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
705
1da177e4
LT		 706/* Firmware return data sizes */
707#define FCAL_MAP_SIZE 128
708
709/* Mailbox bit definitions for out_mb and in_mb */
710#define MBX_31 BIT_31
711#define MBX_30 BIT_30
712#define MBX_29 BIT_29
713#define MBX_28 BIT_28
714#define MBX_27 BIT_27
715#define MBX_26 BIT_26
716#define MBX_25 BIT_25
717#define MBX_24 BIT_24
718#define MBX_23 BIT_23
719#define MBX_22 BIT_22
720#define MBX_21 BIT_21
721#define MBX_20 BIT_20
722#define MBX_19 BIT_19
723#define MBX_18 BIT_18
724#define MBX_17 BIT_17
725#define MBX_16 BIT_16
726#define MBX_15 BIT_15
727#define MBX_14 BIT_14
728#define MBX_13 BIT_13
729#define MBX_12 BIT_12
730#define MBX_11 BIT_11
731#define MBX_10 BIT_10
732#define MBX_9 BIT_9
733#define MBX_8 BIT_8
734#define MBX_7 BIT_7
735#define MBX_6 BIT_6
736#define MBX_5 BIT_5
737#define MBX_4 BIT_4
738#define MBX_3 BIT_3
739#define MBX_2 BIT_2
740#define MBX_1 BIT_1
741#define MBX_0 BIT_0
742
743/*
744 * Firmware state codes from get firmware state mailbox command
745 */
746#define FSTATE_CONFIG_WAIT 0
747#define FSTATE_WAIT_AL_PA 1
748#define FSTATE_WAIT_LOGIN 2
749#define FSTATE_READY 3
750#define FSTATE_LOSS_OF_SYNC 4
751#define FSTATE_ERROR 5
752#define FSTATE_REINIT 6
753#define FSTATE_NON_PART 7
754
755#define FSTATE_CONFIG_CORRECT 0
756#define FSTATE_P2P_RCV_LIP 1
757#define FSTATE_P2P_CHOOSE_LOOP 2
758#define FSTATE_P2P_RCV_UNIDEN_LIP 3
759#define FSTATE_FATAL_ERROR 4
760#define FSTATE_LOOP_BACK_CONN 5
761
762/*
763 * Port Database structure definition
764 * Little endian except where noted.
765 */
766#define PORT_DATABASE_SIZE 128 /* bytes */
767typedef struct {
768 uint8_t options;
769 uint8_t control;
770 uint8_t master_state;
771 uint8_t slave_state;
772 uint8_t reserved[2];
773 uint8_t hard_address;
774 uint8_t reserved_1;
775 uint8_t port_id[4];
776 uint8_t node_name[WWN_SIZE];
777 uint8_t port_name[WWN_SIZE];
778 uint16_t execution_throttle;
779 uint16_t execution_count;
780 uint8_t reset_count;
781 uint8_t reserved_2;
782 uint16_t resource_allocation;
783 uint16_t current_allocation;
784 uint16_t queue_head;
785 uint16_t queue_tail;
786 uint16_t transmit_execution_list_next;
787 uint16_t transmit_execution_list_previous;
788 uint16_t common_features;
789 uint16_t total_concurrent_sequences;
790 uint16_t RO_by_information_category;
791 uint8_t recipient;
792 uint8_t initiator;
793 uint16_t receive_data_size;
794 uint16_t concurrent_sequences;
795 uint16_t open_sequences_per_exchange;
796 uint16_t lun_abort_flags;
797 uint16_t lun_stop_flags;
798 uint16_t stop_queue_head;
799 uint16_t stop_queue_tail;
800 uint16_t port_retry_timer;
801 uint16_t next_sequence_id;
802 uint16_t frame_count;
803 uint16_t PRLI_payload_length;
804 uint8_t prli_svc_param_word_0[2]; /* Big endian */
805 /* Bits 15-0 of word 0 */
806 uint8_t prli_svc_param_word_3[2]; /* Big endian */
807 /* Bits 15-0 of word 3 */
808 uint16_t loop_id;
809 uint16_t extended_lun_info_list_pointer;
810 uint16_t extended_lun_stop_list_pointer;
811} port_database_t;
812
813/*
814 * Port database slave/master states
815 */
816#define PD_STATE_DISCOVERY 0
817#define PD_STATE_WAIT_DISCOVERY_ACK 1
818#define PD_STATE_PORT_LOGIN 2
819#define PD_STATE_WAIT_PORT_LOGIN_ACK 3
820#define PD_STATE_PROCESS_LOGIN 4
821#define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
822#define PD_STATE_PORT_LOGGED_IN 6
823#define PD_STATE_PORT_UNAVAILABLE 7
824#define PD_STATE_PROCESS_LOGOUT 8
825#define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
826#define PD_STATE_PORT_LOGOUT 10
827#define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
828
829
4fdfefe5
AV		 830#define QLA_ZIO_MODE_5 (BIT_2 | BIT_0)
831#define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
832#define QLA_ZIO_DISABLED 0
833#define QLA_ZIO_DEFAULT_TIMER 2
834
1da177e4
LT		 835/*
836 * ISP Initialization Control Block.
837 * Little endian except where noted.
838 */
839#define ICB_VERSION 1
840typedef struct {
841 uint8_t version;
842 uint8_t reserved_1;
843
844 /*
845 * LSB BIT 0 = Enable Hard Loop Id
846 * LSB BIT 1 = Enable Fairness
847 * LSB BIT 2 = Enable Full-Duplex
848 * LSB BIT 3 = Enable Fast Posting
849 * LSB BIT 4 = Enable Target Mode
850 * LSB BIT 5 = Disable Initiator Mode
851 * LSB BIT 6 = Enable ADISC
852 * LSB BIT 7 = Enable Target Inquiry Data
853 *
854 * MSB BIT 0 = Enable PDBC Notify
855 * MSB BIT 1 = Non Participating LIP
856 * MSB BIT 2 = Descending Loop ID Search
857 * MSB BIT 3 = Acquire Loop ID in LIPA
858 * MSB BIT 4 = Stop PortQ on Full Status
859 * MSB BIT 5 = Full Login after LIP
860 * MSB BIT 6 = Node Name Option
861 * MSB BIT 7 = Ext IFWCB enable bit
862 */
863 uint8_t firmware_options[2];
864
865 uint16_t frame_payload_size;
866 uint16_t max_iocb_allocation;
867 uint16_t execution_throttle;
868 uint8_t retry_count;
869 uint8_t retry_delay; /* unused */
870 uint8_t port_name[WWN_SIZE]; /* Big endian. */
871 uint16_t hard_address;
872 uint8_t inquiry_data;
873 uint8_t login_timeout;
874 uint8_t node_name[WWN_SIZE]; /* Big endian. */
875
876 uint16_t request_q_outpointer;
877 uint16_t response_q_inpointer;
878 uint16_t request_q_length;
879 uint16_t response_q_length;
880 uint32_t request_q_address[2];
881 uint32_t response_q_address[2];
882
883 uint16_t lun_enables;
884 uint8_t command_resource_count;
885 uint8_t immediate_notify_resource_count;
886 uint16_t timeout;
887 uint8_t reserved_2[2];
888
889 /*
890 * LSB BIT 0 = Timer Operation mode bit 0
891 * LSB BIT 1 = Timer Operation mode bit 1
892 * LSB BIT 2 = Timer Operation mode bit 2
893 * LSB BIT 3 = Timer Operation mode bit 3
894 * LSB BIT 4 = Init Config Mode bit 0
895 * LSB BIT 5 = Init Config Mode bit 1
896 * LSB BIT 6 = Init Config Mode bit 2
897 * LSB BIT 7 = Enable Non part on LIHA failure
898 *
899 * MSB BIT 0 = Enable class 2
900 * MSB BIT 1 = Enable ACK0
901 * MSB BIT 2 =
902 * MSB BIT 3 =
903 * MSB BIT 4 = FC Tape Enable
904 * MSB BIT 5 = Enable FC Confirm
905 * MSB BIT 6 = Enable command queuing in target mode
906 * MSB BIT 7 = No Logo On Link Down
907 */
908 uint8_t add_firmware_options[2];
909
910 uint8_t response_accumulation_timer;
911 uint8_t interrupt_delay_timer;
912
913 /*
914 * LSB BIT 0 = Enable Read xfr_rdy
915 * LSB BIT 1 = Soft ID only
916 * LSB BIT 2 =
917 * LSB BIT 3 =
918 * LSB BIT 4 = FCP RSP Payload [0]
919 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
920 * LSB BIT 6 = Enable Out-of-Order frame handling
921 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
922 *
923 * MSB BIT 0 = Sbus enable - 2300
924 * MSB BIT 1 =
925 * MSB BIT 2 =
926 * MSB BIT 3 =
06c22bd1 927 * MSB BIT 4 = LED mode
1da177e4
LT		 928 * MSB BIT 5 = enable 50 ohm termination
929 * MSB BIT 6 = Data Rate (2300 only)
930 * MSB BIT 7 = Data Rate (2300 only)
931 */
932 uint8_t special_options[2];
933
934 uint8_t reserved_3[26];
935} init_cb_t;
936
937/*
938 * Get Link Status mailbox command return buffer.
939 */
3d71644c
AV		 940#define GLSO_SEND_RPS BIT_0
941#define GLSO_USE_DID BIT_3
942
1da177e4
LT		 943typedef struct {
944 uint32_t link_fail_cnt;
945 uint32_t loss_sync_cnt;
946 uint32_t loss_sig_cnt;
947 uint32_t prim_seq_err_cnt;
948 uint32_t inval_xmit_word_cnt;
949 uint32_t inval_crc_cnt;
950} link_stat_t;
951
952/*
953 * NVRAM Command values.
954 */
955#define NV_START_BIT BIT_2
956#define NV_WRITE_OP (BIT_26+BIT_24)
957#define NV_READ_OP (BIT_26+BIT_25)
958#define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
959#define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
960#define NV_DELAY_COUNT 10
961
962/*
963 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
964 */
965typedef struct {
966 /*
967 * NVRAM header
968 */
969 uint8_t id[4];
970 uint8_t nvram_version;
971 uint8_t reserved_0;
972
973 /*
974 * NVRAM RISC parameter block
975 */
976 uint8_t parameter_block_version;
977 uint8_t reserved_1;
978
979 /*
980 * LSB BIT 0 = Enable Hard Loop Id
981 * LSB BIT 1 = Enable Fairness
982 * LSB BIT 2 = Enable Full-Duplex
983 * LSB BIT 3 = Enable Fast Posting
984 * LSB BIT 4 = Enable Target Mode
985 * LSB BIT 5 = Disable Initiator Mode
986 * LSB BIT 6 = Enable ADISC
987 * LSB BIT 7 = Enable Target Inquiry Data
988 *
989 * MSB BIT 0 = Enable PDBC Notify
990 * MSB BIT 1 = Non Participating LIP
991 * MSB BIT 2 = Descending Loop ID Search
992 * MSB BIT 3 = Acquire Loop ID in LIPA
993 * MSB BIT 4 = Stop PortQ on Full Status
994 * MSB BIT 5 = Full Login after LIP
995 * MSB BIT 6 = Node Name Option
996 * MSB BIT 7 = Ext IFWCB enable bit
997 */
998 uint8_t firmware_options[2];
999
1000 uint16_t frame_payload_size;
1001 uint16_t max_iocb_allocation;
1002 uint16_t execution_throttle;
1003 uint8_t retry_count;
1004 uint8_t retry_delay; /* unused */
1005 uint8_t port_name[WWN_SIZE]; /* Big endian. */
1006 uint16_t hard_address;
1007 uint8_t inquiry_data;
1008 uint8_t login_timeout;
1009 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1010
1011 /*
1012 * LSB BIT 0 = Timer Operation mode bit 0
1013 * LSB BIT 1 = Timer Operation mode bit 1
1014 * LSB BIT 2 = Timer Operation mode bit 2
1015 * LSB BIT 3 = Timer Operation mode bit 3
1016 * LSB BIT 4 = Init Config Mode bit 0
1017 * LSB BIT 5 = Init Config Mode bit 1
1018 * LSB BIT 6 = Init Config Mode bit 2
1019 * LSB BIT 7 = Enable Non part on LIHA failure
1020 *
1021 * MSB BIT 0 = Enable class 2
1022 * MSB BIT 1 = Enable ACK0
1023 * MSB BIT 2 =
1024 * MSB BIT 3 =
1025 * MSB BIT 4 = FC Tape Enable
1026 * MSB BIT 5 = Enable FC Confirm
1027 * MSB BIT 6 = Enable command queuing in target mode
1028 * MSB BIT 7 = No Logo On Link Down
1029 */
1030 uint8_t add_firmware_options[2];
1031
1032 uint8_t response_accumulation_timer;
1033 uint8_t interrupt_delay_timer;
1034
1035 /*
1036 * LSB BIT 0 = Enable Read xfr_rdy
1037 * LSB BIT 1 = Soft ID only
1038 * LSB BIT 2 =
1039 * LSB BIT 3 =
1040 * LSB BIT 4 = FCP RSP Payload [0]
1041 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1042 * LSB BIT 6 = Enable Out-of-Order frame handling
1043 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1044 *
1045 * MSB BIT 0 = Sbus enable - 2300
1046 * MSB BIT 1 =
1047 * MSB BIT 2 =
1048 * MSB BIT 3 =
06c22bd1 1049 * MSB BIT 4 = LED mode
1da177e4
LT		 1050 * MSB BIT 5 = enable 50 ohm termination
1051 * MSB BIT 6 = Data Rate (2300 only)
1052 * MSB BIT 7 = Data Rate (2300 only)
1053 */
1054 uint8_t special_options[2];
1055
1056 /* Reserved for expanded RISC parameter block */
1057 uint8_t reserved_2[22];
1058
1059 /*
1060 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1061 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1062 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1063 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1064 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1065 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1066 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1067 * LSB BIT 7 = Rx Sensitivity 1G bit 3
fa2a1ce5 1068 *
1da177e4
LT		 1069 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1070 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1071 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1072 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1073 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1074 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1075 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1076 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1077 *
1078 * LSB BIT 0 = Output Swing 1G bit 0
1079 * LSB BIT 1 = Output Swing 1G bit 1
1080 * LSB BIT 2 = Output Swing 1G bit 2
1081 * LSB BIT 3 = Output Emphasis 1G bit 0
1082 * LSB BIT 4 = Output Emphasis 1G bit 1
1083 * LSB BIT 5 = Output Swing 2G bit 0
1084 * LSB BIT 6 = Output Swing 2G bit 1
1085 * LSB BIT 7 = Output Swing 2G bit 2
fa2a1ce5 1086 *
1da177e4
LT		 1087 * MSB BIT 0 = Output Emphasis 2G bit 0
1088 * MSB BIT 1 = Output Emphasis 2G bit 1
1089 * MSB BIT 2 = Output Enable
1090 * MSB BIT 3 =
1091 * MSB BIT 4 =
1092 * MSB BIT 5 =
1093 * MSB BIT 6 =
1094 * MSB BIT 7 =
1095 */
1096 uint8_t seriallink_options[4];
1097
1098 /*
1099 * NVRAM host parameter block
1100 *
1101 * LSB BIT 0 = Enable spinup delay
1102 * LSB BIT 1 = Disable BIOS
1103 * LSB BIT 2 = Enable Memory Map BIOS
1104 * LSB BIT 3 = Enable Selectable Boot
1105 * LSB BIT 4 = Disable RISC code load
1106 * LSB BIT 5 = Set cache line size 1
1107 * LSB BIT 6 = PCI Parity Disable
1108 * LSB BIT 7 = Enable extended logging
1109 *
1110 * MSB BIT 0 = Enable 64bit addressing
1111 * MSB BIT 1 = Enable lip reset
1112 * MSB BIT 2 = Enable lip full login
1113 * MSB BIT 3 = Enable target reset
1114 * MSB BIT 4 = Enable database storage
1115 * MSB BIT 5 = Enable cache flush read
1116 * MSB BIT 6 = Enable database load
1117 * MSB BIT 7 = Enable alternate WWN
1118 */
1119 uint8_t host_p[2];
1120
1121 uint8_t boot_node_name[WWN_SIZE];
1122 uint8_t boot_lun_number;
1123 uint8_t reset_delay;
1124 uint8_t port_down_retry_count;
1125 uint8_t boot_id_number;
1126 uint16_t max_luns_per_target;
1127 uint8_t fcode_boot_port_name[WWN_SIZE];
1128 uint8_t alternate_port_name[WWN_SIZE];
1129 uint8_t alternate_node_name[WWN_SIZE];
1130
1131 /*
1132 * BIT 0 = Selective Login
1133 * BIT 1 = Alt-Boot Enable
1134 * BIT 2 =
1135 * BIT 3 = Boot Order List
1136 * BIT 4 =
1137 * BIT 5 = Selective LUN
1138 * BIT 6 =
1139 * BIT 7 = unused
1140 */
1141 uint8_t efi_parameters;
1142
1143 uint8_t link_down_timeout;
1144
cca5335c 1145 uint8_t adapter_id[16];
1da177e4
LT		 1146
1147 uint8_t alt1_boot_node_name[WWN_SIZE];
1148 uint16_t alt1_boot_lun_number;
1149 uint8_t alt2_boot_node_name[WWN_SIZE];
1150 uint16_t alt2_boot_lun_number;
1151 uint8_t alt3_boot_node_name[WWN_SIZE];
1152 uint16_t alt3_boot_lun_number;
1153 uint8_t alt4_boot_node_name[WWN_SIZE];
1154 uint16_t alt4_boot_lun_number;
1155 uint8_t alt5_boot_node_name[WWN_SIZE];
1156 uint16_t alt5_boot_lun_number;
1157 uint8_t alt6_boot_node_name[WWN_SIZE];
1158 uint16_t alt6_boot_lun_number;
1159 uint8_t alt7_boot_node_name[WWN_SIZE];
1160 uint16_t alt7_boot_lun_number;
1161
1162 uint8_t reserved_3[2];
1163
1164 /* Offset 200-215 : Model Number */
1165 uint8_t model_number[16];
1166
1167 /* OEM related items */
1168 uint8_t oem_specific[16];
1169
1170 /*
1171 * NVRAM Adapter Features offset 232-239
1172 *
1173 * LSB BIT 0 = External GBIC
1174 * LSB BIT 1 = Risc RAM parity
1175 * LSB BIT 2 = Buffer Plus Module
1176 * LSB BIT 3 = Multi Chip Adapter
1177 * LSB BIT 4 = Internal connector
1178 * LSB BIT 5 =
1179 * LSB BIT 6 =
1180 * LSB BIT 7 =
1181 *
1182 * MSB BIT 0 =
1183 * MSB BIT 1 =
1184 * MSB BIT 2 =
1185 * MSB BIT 3 =
1186 * MSB BIT 4 =
1187 * MSB BIT 5 =
1188 * MSB BIT 6 =
1189 * MSB BIT 7 =
1190 */
1191 uint8_t adapter_features[2];
1192
1193 uint8_t reserved_4[16];
1194
1195 /* Subsystem vendor ID for ISP2200 */
1196 uint16_t subsystem_vendor_id_2200;
1197
1198 /* Subsystem device ID for ISP2200 */
1199 uint16_t subsystem_device_id_2200;
1200
1201 uint8_t reserved_5;
1202 uint8_t checksum;
1203} nvram_t;
1204
1205/*
1206 * ISP queue - response queue entry definition.
1207 */
1208typedef struct {
1209 uint8_t data[60];
1210 uint32_t signature;
1211#define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1212} response_t;
1213
1214typedef union {
1215 uint16_t extended;
1216 struct {
1217 uint8_t reserved;
1218 uint8_t standard;
1219 } id;
1220} target_id_t;
1221
1222#define SET_TARGET_ID(ha, to, from) \
1223do { \
1224 if (HAS_EXTENDED_IDS(ha)) \
1225 to.extended = cpu_to_le16(from); \
1226 else \
1227 to.id.standard = (uint8_t)from; \
1228} while (0)
1229
1230/*
1231 * ISP queue - command entry structure definition.
1232 */
1233#define COMMAND_TYPE 0x11 /* Command entry */
1da177e4
LT		 1234typedef struct {
1235 uint8_t entry_type; /* Entry type. */
1236 uint8_t entry_count; /* Entry count. */
1237 uint8_t sys_define; /* System defined. */
1238 uint8_t entry_status; /* Entry Status. */
1239 uint32_t handle; /* System handle. */
1240 target_id_t target; /* SCSI ID */
1241 uint16_t lun; /* SCSI LUN */
1242 uint16_t control_flags; /* Control flags. */
1243#define CF_WRITE BIT_6
1244#define CF_READ BIT_5
1245#define CF_SIMPLE_TAG BIT_3
1246#define CF_ORDERED_TAG BIT_2
1247#define CF_HEAD_TAG BIT_1
1248 uint16_t reserved_1;
1249 uint16_t timeout; /* Command timeout. */
1250 uint16_t dseg_count; /* Data segment count. */
1251 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1252 uint32_t byte_count; /* Total byte count. */
1253 uint32_t dseg_0_address; /* Data segment 0 address. */
1254 uint32_t dseg_0_length; /* Data segment 0 length. */
1255 uint32_t dseg_1_address; /* Data segment 1 address. */
1256 uint32_t dseg_1_length; /* Data segment 1 length. */
1257 uint32_t dseg_2_address; /* Data segment 2 address. */
1258 uint32_t dseg_2_length; /* Data segment 2 length. */
1259} cmd_entry_t;
1260
1261/*
1262 * ISP queue - 64-Bit addressing, command entry structure definition.
1263 */
1264#define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1265typedef struct {
1266 uint8_t entry_type; /* Entry type. */
1267 uint8_t entry_count; /* Entry count. */
1268 uint8_t sys_define; /* System defined. */
1269 uint8_t entry_status; /* Entry Status. */
1270 uint32_t handle; /* System handle. */
1271 target_id_t target; /* SCSI ID */
1272 uint16_t lun; /* SCSI LUN */
1273 uint16_t control_flags; /* Control flags. */
1274 uint16_t reserved_1;
1275 uint16_t timeout; /* Command timeout. */
1276 uint16_t dseg_count; /* Data segment count. */
1277 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1278 uint32_t byte_count; /* Total byte count. */
1279 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1280 uint32_t dseg_0_length; /* Data segment 0 length. */
1281 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1282 uint32_t dseg_1_length; /* Data segment 1 length. */
1283} cmd_a64_entry_t, request_t;
1284
1285/*
1286 * ISP queue - continuation entry structure definition.
1287 */
1288#define CONTINUE_TYPE 0x02 /* Continuation entry. */
1289typedef struct {
1290 uint8_t entry_type; /* Entry type. */
1291 uint8_t entry_count; /* Entry count. */
1292 uint8_t sys_define; /* System defined. */
1293 uint8_t entry_status; /* Entry Status. */
1294 uint32_t reserved;
1295 uint32_t dseg_0_address; /* Data segment 0 address. */
1296 uint32_t dseg_0_length; /* Data segment 0 length. */
1297 uint32_t dseg_1_address; /* Data segment 1 address. */
1298 uint32_t dseg_1_length; /* Data segment 1 length. */
1299 uint32_t dseg_2_address; /* Data segment 2 address. */
1300 uint32_t dseg_2_length; /* Data segment 2 length. */
1301 uint32_t dseg_3_address; /* Data segment 3 address. */
1302 uint32_t dseg_3_length; /* Data segment 3 length. */
1303 uint32_t dseg_4_address; /* Data segment 4 address. */
1304 uint32_t dseg_4_length; /* Data segment 4 length. */
1305 uint32_t dseg_5_address; /* Data segment 5 address. */
1306 uint32_t dseg_5_length; /* Data segment 5 length. */
1307 uint32_t dseg_6_address; /* Data segment 6 address. */
1308 uint32_t dseg_6_length; /* Data segment 6 length. */
1309} cont_entry_t;
1310
1311/*
1312 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1313 */
1314#define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1315typedef struct {
1316 uint8_t entry_type; /* Entry type. */
1317 uint8_t entry_count; /* Entry count. */
1318 uint8_t sys_define; /* System defined. */
1319 uint8_t entry_status; /* Entry Status. */
1320 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1321 uint32_t dseg_0_length; /* Data segment 0 length. */
1322 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1323 uint32_t dseg_1_length; /* Data segment 1 length. */
1324 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1325 uint32_t dseg_2_length; /* Data segment 2 length. */
1326 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1327 uint32_t dseg_3_length; /* Data segment 3 length. */
1328 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1329 uint32_t dseg_4_length; /* Data segment 4 length. */
1330} cont_a64_entry_t;
1331
1332/*
1333 * ISP queue - status entry structure definition.
1334 */
1335#define STATUS_TYPE 0x03 /* Status entry. */
1336typedef struct {
1337 uint8_t entry_type; /* Entry type. */
1338 uint8_t entry_count; /* Entry count. */
1339 uint8_t sys_define; /* System defined. */
1340 uint8_t entry_status; /* Entry Status. */
1341 uint32_t handle; /* System handle. */
1342 uint16_t scsi_status; /* SCSI status. */
1343 uint16_t comp_status; /* Completion status. */
1344 uint16_t state_flags; /* State flags. */
1345 uint16_t status_flags; /* Status flags. */
1346 uint16_t rsp_info_len; /* Response Info Length. */
1347 uint16_t req_sense_length; /* Request sense data length. */
1348 uint32_t residual_length; /* Residual transfer length. */
1349 uint8_t rsp_info[8]; /* FCP response information. */
1350 uint8_t req_sense_data[32]; /* Request sense data. */
1351} sts_entry_t;
1352
1353/*
1354 * Status entry entry status
1355 */
3d71644c 1356#define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1da177e4
LT		 1357#define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1358#define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1359#define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1360#define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1361#define RF_BUSY BIT_1 /* Busy */
3d71644c
AV		 1362#define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1363 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1364#define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1365 RF_INV_E_TYPE)
1da177e4
LT		 1366
1367/*
1368 * Status entry SCSI status bit definitions.
1369 */
1370#define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1371#define SS_RESIDUAL_UNDER BIT_11
1372#define SS_RESIDUAL_OVER BIT_10
1373#define SS_SENSE_LEN_VALID BIT_9
1374#define SS_RESPONSE_INFO_LEN_VALID BIT_8
1375
1376#define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1377#define SS_BUSY_CONDITION BIT_3
1378#define SS_CONDITION_MET BIT_2
1379#define SS_CHECK_CONDITION BIT_1
1380
1381/*
1382 * Status entry completion status
1383 */
1384#define CS_COMPLETE 0x0 /* No errors */
1385#define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1386#define CS_DMA 0x2 /* A DMA direction error. */
1387#define CS_TRANSPORT 0x3 /* Transport error. */
1388#define CS_RESET 0x4 /* SCSI bus reset occurred */
1389#define CS_ABORTED 0x5 /* System aborted command. */
1390#define CS_TIMEOUT 0x6 /* Timeout error. */
1391#define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1392
1393#define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1394#define CS_QUEUE_FULL 0x1C /* Queue Full. */
1395#define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1396 /* (selection timeout) */
1397#define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1398#define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1399#define CS_PORT_BUSY 0x2B /* Port Busy */
1400#define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1401#define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1402#define CS_UNKNOWN 0x81 /* Driver defined */
1403#define CS_RETRY 0x82 /* Driver defined */
1404#define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1405
1406/*
1407 * Status entry status flags
1408 */
1409#define SF_ABTS_TERMINATED BIT_10
1410#define SF_LOGOUT_SENT BIT_13
1411
1412/*
1413 * ISP queue - status continuation entry structure definition.
1414 */
1415#define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1416typedef struct {
1417 uint8_t entry_type; /* Entry type. */
1418 uint8_t entry_count; /* Entry count. */
1419 uint8_t sys_define; /* System defined. */
1420 uint8_t entry_status; /* Entry Status. */
1421 uint8_t data[60]; /* data */
1422} sts_cont_entry_t;
1423
1424/*
1425 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1426 * structure definition.
1427 */
1428#define STATUS_TYPE_21 0x21 /* Status entry. */
1429typedef struct {
1430 uint8_t entry_type; /* Entry type. */
1431 uint8_t entry_count; /* Entry count. */
1432 uint8_t handle_count; /* Handle count. */
1433 uint8_t entry_status; /* Entry Status. */
1434 uint32_t handle[15]; /* System handles. */
1435} sts21_entry_t;
1436
1437/*
1438 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1439 * structure definition.
1440 */
1441#define STATUS_TYPE_22 0x22 /* Status entry. */
1442typedef struct {
1443 uint8_t entry_type; /* Entry type. */
1444 uint8_t entry_count; /* Entry count. */
1445 uint8_t handle_count; /* Handle count. */
1446 uint8_t entry_status; /* Entry Status. */
1447 uint16_t handle[30]; /* System handles. */
1448} sts22_entry_t;
1449
1450/*
1451 * ISP queue - marker entry structure definition.
1452 */
1453#define MARKER_TYPE 0x04 /* Marker entry. */
1454typedef struct {
1455 uint8_t entry_type; /* Entry type. */
1456 uint8_t entry_count; /* Entry count. */
1457 uint8_t handle_count; /* Handle count. */
1458 uint8_t entry_status; /* Entry Status. */
1459 uint32_t sys_define_2; /* System defined. */
1460 target_id_t target; /* SCSI ID */
1461 uint8_t modifier; /* Modifier (7-0). */
1462#define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1463#define MK_SYNC_ID 1 /* Synchronize ID */
1464#define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1465#define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1466 /* clear port changed, */
1467 /* use sequence number. */
1468 uint8_t reserved_1;
1469 uint16_t sequence_number; /* Sequence number of event */
1470 uint16_t lun; /* SCSI LUN */
1471 uint8_t reserved_2[48];
1472} mrk_entry_t;
1473
1474/*
1475 * ISP queue - Management Server entry structure definition.
1476 */
1477#define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1478typedef struct {
1479 uint8_t entry_type; /* Entry type. */
1480 uint8_t entry_count; /* Entry count. */
1481 uint8_t handle_count; /* Handle count. */
1482 uint8_t entry_status; /* Entry Status. */
1483 uint32_t handle1; /* System handle. */
1484 target_id_t loop_id;
1485 uint16_t status;
1486 uint16_t control_flags; /* Control flags. */
1487 uint16_t reserved2;
1488 uint16_t timeout;
1489 uint16_t cmd_dsd_count;
1490 uint16_t total_dsd_count;
1491 uint8_t type;
1492 uint8_t r_ctl;
1493 uint16_t rx_id;
1494 uint16_t reserved3;
1495 uint32_t handle2;
1496 uint32_t rsp_bytecount;
1497 uint32_t req_bytecount;
1498 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1499 uint32_t dseg_req_length; /* Data segment 0 length. */
1500 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1501 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1502} ms_iocb_entry_t;
1503
1504
1505/*
1506 * ISP queue - Mailbox Command entry structure definition.
1507 */
1508#define MBX_IOCB_TYPE 0x39
1509struct mbx_entry {
1510 uint8_t entry_type;
1511 uint8_t entry_count;
1512 uint8_t sys_define1;
1513 /* Use sys_define1 for source type */
1514#define SOURCE_SCSI 0x00
1515#define SOURCE_IP 0x01
1516#define SOURCE_VI 0x02
1517#define SOURCE_SCTP 0x03
1518#define SOURCE_MP 0x04
1519#define SOURCE_MPIOCTL 0x05
1520#define SOURCE_ASYNC_IOCB 0x07
1521
1522 uint8_t entry_status;
1523
1524 uint32_t handle;
1525 target_id_t loop_id;
1526
1527 uint16_t status;
1528 uint16_t state_flags;
1529 uint16_t status_flags;
1530
1531 uint32_t sys_define2[2];
1532
1533 uint16_t mb0;
1534 uint16_t mb1;
1535 uint16_t mb2;
1536 uint16_t mb3;
1537 uint16_t mb6;
1538 uint16_t mb7;
1539 uint16_t mb9;
1540 uint16_t mb10;
1541 uint32_t reserved_2[2];
1542 uint8_t node_name[WWN_SIZE];
1543 uint8_t port_name[WWN_SIZE];
1544};
1545
1546/*
1547 * ISP request and response queue entry sizes
1548 */
1549#define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1550#define REQUEST_ENTRY_SIZE (sizeof(request_t))
1551
1552
1553/*
1554 * 24 bit port ID type definition.
1555 */
1556typedef union {
1557 uint32_t b24 : 24;
1558
1559 struct {
1560 uint8_t d_id[3];
1561 uint8_t rsvd_1;
1562 } r;
1563
1564 struct {
1565 uint8_t al_pa;
1566 uint8_t area;
1567 uint8_t domain;
1568 uint8_t rsvd_1;
1569 } b;
1570} port_id_t;
1571#define INVALID_PORT_ID 0xFFFFFF
1572
1573/*
1574 * Switch info gathering structure.
1575 */
1576typedef struct {
1577 port_id_t d_id;
1578 uint8_t node_name[WWN_SIZE];
1579 uint8_t port_name[WWN_SIZE];
1da177e4
LT		 1580} sw_info_t;
1581
1582/*
1583 * Inquiry command structure.
1584 */
1585#define INQ_DATA_SIZE 36
1586
1587/*
1588 * Inquiry mailbox IOCB packet definition.
1589 */
1590typedef struct {
1591 union {
1592 cmd_a64_entry_t cmd;
1593 sts_entry_t rsp;
3d71644c
AV		 1594 struct cmd_type_7 cmd24;
1595 struct sts_entry_24xx rsp24;
1da177e4
LT		 1596 } p;
1597 uint8_t inq[INQ_DATA_SIZE];
1598} inq_cmd_rsp_t;
1599
1600/*
1601 * Report LUN command structure.
1602 */
1603#define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1604
1605typedef struct {
1606 uint32_t len;
1607 uint32_t rsrv;
1608} rpt_hdr_t;
1609
1610typedef struct {
1611 struct {
1612 uint8_t b : 6;
1613 uint8_t address_method : 2;
1614 } msb;
1615 uint8_t lsb;
1616 uint8_t unused[6];
1617} rpt_lun_t;
1618
1619typedef struct {
1620 rpt_hdr_t hdr;
1621 rpt_lun_t lst[MAX_LUNS];
1622} rpt_lun_lst_t;
1623
1624/*
1625 * Report Lun mailbox IOCB packet definition.
1626 */
1627typedef struct {
1628 union {
1629 cmd_a64_entry_t cmd;
1630 sts_entry_t rsp;
3d71644c
AV		 1631 struct cmd_type_7 cmd24;
1632 struct sts_entry_24xx rsp24;
1da177e4
LT		 1633 } p;
1634 rpt_lun_lst_t list;
1635} rpt_lun_cmd_rsp_t;
1636
3d71644c 1637
1da177e4
LT		 1638/*
1639 * Fibre channel port type.
1640 */
1641 typedef enum {
1642 FCT_UNKNOWN,
1643 FCT_RSCN,
1644 FCT_SWITCH,
1645 FCT_BROADCAST,
1646 FCT_INITIATOR,
1647 FCT_TARGET
1648} fc_port_type_t;
1649
1650/*
1651 * Fibre channel port structure.
1652 */
1653typedef struct fc_port {
1654 struct list_head list;
1da177e4
LT		 1655 struct scsi_qla_host *ha;
1656 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1657
1658 uint8_t node_name[WWN_SIZE];
1659 uint8_t port_name[WWN_SIZE];
1660 port_id_t d_id;
1661 uint16_t loop_id;
1662 uint16_t old_loop_id;
1663
1664 fc_port_type_t port_type;
1665
1666 atomic_t state;
1667 uint32_t flags;
1668
bdf79621 1669 unsigned int os_target_id;
1da177e4
LT		 1670
1671 uint16_t iodesc_idx_sent;
1672
1673 int port_login_retry_count;
1674 int login_retry;
1675 atomic_t port_down_timer;
1676
1677 uint8_t device_type;
1678 uint8_t unused;
1679
1680 uint8_t mp_byte; /* multi-path byte (not used) */
1681 uint8_t cur_path; /* current path id */
1682
d97994dc
AV		 1683 spinlock_t rport_lock;
1684 struct fc_rport *rport, *drport;
ad3e0eda 1685 u32 supported_classes;
19a7b4ae
JSEC		 1686 struct work_struct rport_add_work;
1687 struct work_struct rport_del_work;
1da177e4
LT		 1688} fc_port_t;
1689
1690/*
1691 * Fibre channel port/lun states.
1692 */
1693#define FCS_UNCONFIGURED 1
1694#define FCS_DEVICE_DEAD 2
1695#define FCS_DEVICE_LOST 3
1696#define FCS_ONLINE 4
1697#define FCS_NOT_SUPPORTED 5
1698#define FCS_FAILOVER 6
1699#define FCS_FAILOVER_FAILED 7
1700
1701/*
1702 * FC port flags.
1703 */
1704#define FCF_FABRIC_DEVICE BIT_0
1705#define FCF_LOGIN_NEEDED BIT_1
1706#define FCF_FO_MASKED BIT_2
1707#define FCF_FAILOVER_NEEDED BIT_3
1708#define FCF_RESET_NEEDED BIT_4
1709#define FCF_PERSISTENT_BOUND BIT_5
1710#define FCF_TAPE_PRESENT BIT_6
1711#define FCF_FARP_DONE BIT_7
1712#define FCF_FARP_FAILED BIT_8
1713#define FCF_FARP_REPLY_NEEDED BIT_9
1714#define FCF_AUTH_REQ BIT_10
1715#define FCF_SEND_AUTH_REQ BIT_11
1716#define FCF_RECEIVE_AUTH_REQ BIT_12
1717#define FCF_AUTH_SUCCESS BIT_13
1718#define FCF_RLC_SUPPORT BIT_14
1719#define FCF_CONFIG BIT_15 /* Needed? */
1720#define FCF_RESCAN_NEEDED BIT_16
1721#define FCF_XP_DEVICE BIT_17
1722#define FCF_MSA_DEVICE BIT_18
1723#define FCF_EVA_DEVICE BIT_19
1724#define FCF_MSA_PORT_ACTIVE BIT_20
1725#define FCF_FAILBACK_DISABLE BIT_21
1726#define FCF_FAILOVER_DISABLE BIT_22
1727#define FCF_DSXXX_DEVICE BIT_23
1728#define FCF_AA_EVA_DEVICE BIT_24
3d71644c 1729#define FCF_AA_MSA_DEVICE BIT_25
1da177e4
LT		 1730
1731/* No loop ID flag. */
1732#define FC_NO_LOOP_ID 0x1000
1733
1da177e4
LT		 1734/*
1735 * FC-CT interface
1736 *
1737 * NOTE: All structures are big-endian in form.
1738 */
1739
1740#define CT_REJECT_RESPONSE 0x8001
1741#define CT_ACCEPT_RESPONSE 0x8002
cca5335c
AV		 1742#define CT_REASON_CANNOT_PERFORM 0x09
1743#define CT_EXPL_ALREADY_REGISTERED 0x10
1da177e4
LT		 1744
1745#define NS_N_PORT_TYPE 0x01
1746#define NS_NL_PORT_TYPE 0x02
1747#define NS_NX_PORT_TYPE 0x7F
1748
1749#define GA_NXT_CMD 0x100
1750#define GA_NXT_REQ_SIZE (16 + 4)
1751#define GA_NXT_RSP_SIZE (16 + 620)
1752
1753#define GID_PT_CMD 0x1A1
1754#define GID_PT_REQ_SIZE (16 + 4)
1755#define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1756
1757#define GPN_ID_CMD 0x112
1758#define GPN_ID_REQ_SIZE (16 + 4)
1759#define GPN_ID_RSP_SIZE (16 + 8)
1760
1761#define GNN_ID_CMD 0x113
1762#define GNN_ID_REQ_SIZE (16 + 4)
1763#define GNN_ID_RSP_SIZE (16 + 8)
1764
1765#define GFT_ID_CMD 0x117
1766#define GFT_ID_REQ_SIZE (16 + 4)
1767#define GFT_ID_RSP_SIZE (16 + 32)
1768
1769#define RFT_ID_CMD 0x217
1770#define RFT_ID_REQ_SIZE (16 + 4 + 32)
1771#define RFT_ID_RSP_SIZE 16
1772
1773#define RFF_ID_CMD 0x21F
1774#define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1775#define RFF_ID_RSP_SIZE 16
1776
1777#define RNN_ID_CMD 0x213
1778#define RNN_ID_REQ_SIZE (16 + 4 + 8)
1779#define RNN_ID_RSP_SIZE 16
1780
1781#define RSNN_NN_CMD 0x239
1782#define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1783#define RSNN_NN_RSP_SIZE 16
1784
cca5335c
AV		 1785/*
1786 * HBA attribute types.
1787 */
1788#define FDMI_HBA_ATTR_COUNT 9
1789#define FDMI_HBA_NODE_NAME 1
1790#define FDMI_HBA_MANUFACTURER 2
1791#define FDMI_HBA_SERIAL_NUMBER 3
1792#define FDMI_HBA_MODEL 4
1793#define FDMI_HBA_MODEL_DESCRIPTION 5
1794#define FDMI_HBA_HARDWARE_VERSION 6
1795#define FDMI_HBA_DRIVER_VERSION 7
1796#define FDMI_HBA_OPTION_ROM_VERSION 8
1797#define FDMI_HBA_FIRMWARE_VERSION 9
1798#define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1799#define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1800
1801struct ct_fdmi_hba_attr {
1802 uint16_t type;
1803 uint16_t len;
1804 union {
1805 uint8_t node_name[WWN_SIZE];
1806 uint8_t manufacturer[32];
1807 uint8_t serial_num[8];
1808 uint8_t model[16];
1809 uint8_t model_desc[80];
1810 uint8_t hw_version[16];
1811 uint8_t driver_version[32];
1812 uint8_t orom_version[16];
1813 uint8_t fw_version[16];
1814 uint8_t os_version[128];
1815 uint8_t max_ct_len[4];
1816 } a;
1817};
1818
1819struct ct_fdmi_hba_attributes {
1820 uint32_t count;
1821 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1822};
1823
1824/*
1825 * Port attribute types.
1826 */
1827#define FDMI_PORT_ATTR_COUNT 5
1828#define FDMI_PORT_FC4_TYPES 1
1829#define FDMI_PORT_SUPPORT_SPEED 2
1830#define FDMI_PORT_CURRENT_SPEED 3
1831#define FDMI_PORT_MAX_FRAME_SIZE 4
1832#define FDMI_PORT_OS_DEVICE_NAME 5
1833#define FDMI_PORT_HOST_NAME 6
1834
1835struct ct_fdmi_port_attr {
1836 uint16_t type;
1837 uint16_t len;
1838 union {
1839 uint8_t fc4_types[32];
1840 uint32_t sup_speed;
1841 uint32_t cur_speed;
1842 uint32_t max_frame_size;
1843 uint8_t os_dev_name[32];
1844 uint8_t host_name[32];
1845 } a;
1846};
1847
1848/*
1849 * Port Attribute Block.
1850 */
1851struct ct_fdmi_port_attributes {
1852 uint32_t count;
1853 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1854};
1855
1856/* FDMI definitions. */
1857#define GRHL_CMD 0x100
1858#define GHAT_CMD 0x101
1859#define GRPL_CMD 0x102
1860#define GPAT_CMD 0x110
1861
1862#define RHBA_CMD 0x200
1863#define RHBA_RSP_SIZE 16
1864
1865#define RHAT_CMD 0x201
1866#define RPRT_CMD 0x210
1867
1868#define RPA_CMD 0x211
1869#define RPA_RSP_SIZE 16
1870
1871#define DHBA_CMD 0x300
1872#define DHBA_REQ_SIZE (16 + 8)
1873#define DHBA_RSP_SIZE 16
1874
1875#define DHAT_CMD 0x301
1876#define DPRT_CMD 0x310
1877#define DPA_CMD 0x311
1878
1da177e4
LT		 1879/* CT command header -- request/response common fields */
1880struct ct_cmd_hdr {
1881 uint8_t revision;
1882 uint8_t in_id[3];
1883 uint8_t gs_type;
1884 uint8_t gs_subtype;
1885 uint8_t options;
1886 uint8_t reserved;
1887};
1888
1889/* CT command request */
1890struct ct_sns_req {
1891 struct ct_cmd_hdr header;
1892 uint16_t command;
1893 uint16_t max_rsp_size;
1894 uint8_t fragment_id;
1895 uint8_t reserved[3];
1896
1897 union {
1898 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1899 struct {
1900 uint8_t reserved;
1901 uint8_t port_id[3];
1902 } port_id;
1903
1904 struct {
1905 uint8_t port_type;
1906 uint8_t domain;
1907 uint8_t area;
1908 uint8_t reserved;
1909 } gid_pt;
1910
1911 struct {
1912 uint8_t reserved;
1913 uint8_t port_id[3];
1914 uint8_t fc4_types[32];
1915 } rft_id;
1916
1917 struct {
1918 uint8_t reserved;
1919 uint8_t port_id[3];
1920 uint16_t reserved2;
1921 uint8_t fc4_feature;
1922 uint8_t fc4_type;
1923 } rff_id;
1924
1925 struct {
1926 uint8_t reserved;
1927 uint8_t port_id[3];
1928 uint8_t node_name[8];
1929 } rnn_id;
1930
1931 struct {
1932 uint8_t node_name[8];
1933 uint8_t name_len;
1934 uint8_t sym_node_name[255];
1935 } rsnn_nn;
cca5335c
AV		 1936
1937 struct {
1938 uint8_t hba_indentifier[8];
1939 } ghat;
1940
1941 struct {
1942 uint8_t hba_identifier[8];
1943 uint32_t entry_count;
1944 uint8_t port_name[8];
1945 struct ct_fdmi_hba_attributes attrs;
1946 } rhba;
1947
1948 struct {
1949 uint8_t hba_identifier[8];
1950 struct ct_fdmi_hba_attributes attrs;
1951 } rhat;
1952
1953 struct {
1954 uint8_t port_name[8];
1955 struct ct_fdmi_port_attributes attrs;
1956 } rpa;
1957
1958 struct {
1959 uint8_t port_name[8];
1960 } dhba;
1961
1962 struct {
1963 uint8_t port_name[8];
1964 } dhat;
1965
1966 struct {
1967 uint8_t port_name[8];
1968 } dprt;
1969
1970 struct {
1971 uint8_t port_name[8];
1972 } dpa;
1da177e4
LT		 1973 } req;
1974};
1975
1976/* CT command response header */
1977struct ct_rsp_hdr {
1978 struct ct_cmd_hdr header;
1979 uint16_t response;
1980 uint16_t residual;
1981 uint8_t fragment_id;
1982 uint8_t reason_code;
1983 uint8_t explanation_code;
1984 uint8_t vendor_unique;
1985};
1986
1987struct ct_sns_gid_pt_data {
1988 uint8_t control_byte;
1989 uint8_t port_id[3];
1990};
1991
1992struct ct_sns_rsp {
1993 struct ct_rsp_hdr header;
1994
1995 union {
1996 struct {
1997 uint8_t port_type;
1998 uint8_t port_id[3];
1999 uint8_t port_name[8];
2000 uint8_t sym_port_name_len;
2001 uint8_t sym_port_name[255];
2002 uint8_t node_name[8];
2003 uint8_t sym_node_name_len;
2004 uint8_t sym_node_name[255];
2005 uint8_t init_proc_assoc[8];
2006 uint8_t node_ip_addr[16];
2007 uint8_t class_of_service[4];
2008 uint8_t fc4_types[32];
2009 uint8_t ip_address[16];
2010 uint8_t fabric_port_name[8];
2011 uint8_t reserved;
2012 uint8_t hard_address[3];
2013 } ga_nxt;
2014
2015 struct {
2016 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2017 } gid_pt;
2018
2019 struct {
2020 uint8_t port_name[8];
2021 } gpn_id;
2022
2023 struct {
2024 uint8_t node_name[8];
2025 } gnn_id;
2026
2027 struct {
2028 uint8_t fc4_types[32];
2029 } gft_id;
cca5335c
AV		 2030
2031 struct {
2032 uint32_t entry_count;
2033 uint8_t port_name[8];
2034 struct ct_fdmi_hba_attributes attrs;
2035 } ghat;
1da177e4
LT		 2036 } rsp;
2037};
2038
2039struct ct_sns_pkt {
2040 union {
2041 struct ct_sns_req req;
2042 struct ct_sns_rsp rsp;
2043 } p;
2044};
2045
2046/*
2047 * SNS command structures -- for 2200 compatability.
2048 */
2049#define RFT_ID_SNS_SCMD_LEN 22
2050#define RFT_ID_SNS_CMD_SIZE 60
2051#define RFT_ID_SNS_DATA_SIZE 16
2052
2053#define RNN_ID_SNS_SCMD_LEN 10
2054#define RNN_ID_SNS_CMD_SIZE 36
2055#define RNN_ID_SNS_DATA_SIZE 16
2056
2057#define GA_NXT_SNS_SCMD_LEN 6
2058#define GA_NXT_SNS_CMD_SIZE 28
2059#define GA_NXT_SNS_DATA_SIZE (620 + 16)
2060
2061#define GID_PT_SNS_SCMD_LEN 6
2062#define GID_PT_SNS_CMD_SIZE 28
2063#define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2064
2065#define GPN_ID_SNS_SCMD_LEN 6
2066#define GPN_ID_SNS_CMD_SIZE 28
2067#define GPN_ID_SNS_DATA_SIZE (8 + 16)
2068
2069#define GNN_ID_SNS_SCMD_LEN 6
2070#define GNN_ID_SNS_CMD_SIZE 28
2071#define GNN_ID_SNS_DATA_SIZE (8 + 16)
2072
2073struct sns_cmd_pkt {
2074 union {
2075 struct {
2076 uint16_t buffer_length;
2077 uint16_t reserved_1;
2078 uint32_t buffer_address[2];
2079 uint16_t subcommand_length;
2080 uint16_t reserved_2;
2081 uint16_t subcommand;
2082 uint16_t size;
2083 uint32_t reserved_3;
2084 uint8_t param[36];
2085 } cmd;
2086
2087 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2088 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2089 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2090 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2091 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2092 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2093 } p;
2094};
2095
2096/* IO descriptors */
2097#define MAX_IO_DESCRIPTORS 32
2098
2099#define ABORT_IOCB_CB 0
2100#define ADISC_PORT_IOCB_CB 1
2101#define LOGOUT_PORT_IOCB_CB 2
2102#define LOGIN_PORT_IOCB_CB 3
2103#define LAST_IOCB_CB 4
2104
2105#define IODESC_INVALID_INDEX 0xFFFF
2106#define IODESC_ADISC_NEEDED 0xFFFE
2107#define IODESC_LOGIN_NEEDED 0xFFFD
2108
2109struct io_descriptor {
2110 uint16_t used:1;
2111 uint16_t idx:11;
2112 uint16_t cb_idx:4;
2113
2114 struct timer_list timer;
2115
2116 struct scsi_qla_host *ha;
2117
2118 port_id_t d_id;
2119 fc_port_t *remote_fcport;
2120
2121 uint32_t signature;
2122};
2123
2124struct qla_fw_info {
2125 unsigned short addressing; /* addressing method used to load fw */
2126#define FW_INFO_ADDR_NORMAL 0
2127#define FW_INFO_ADDR_EXTENDED 1
2128#define FW_INFO_ADDR_NOMORE 0xffff
2129 unsigned short *fwcode; /* pointer to FW array */
2130 unsigned short *fwlen; /* number of words in array */
2131 unsigned short *fwstart; /* start address for F/W */
2132 unsigned long *lfwstart; /* start address (long) for F/W */
2133};
2134
2135struct qla_board_info {
2136 char *drv_name;
2137
2138 char isp_name[8];
2139 struct qla_fw_info *fw_info;
fca29703
AV		 2140 char *fw_fname;
2141 struct scsi_host_template *sht;
1da177e4
LT		 2142};
2143
5433383e
AV		 2144struct fw_blob {
2145 char *name;
2146 uint32_t segs[4];
2147 const struct firmware *fw;
2148};
2149
1da177e4
LT		 2150/* Return data from MBC_GET_ID_LIST call. */
2151struct gid_list_info {
2152 uint8_t al_pa;
2153 uint8_t area;
fa2a1ce5 2154 uint8_t domain;
1da177e4
LT		 2155 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2156 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
3d71644c 2157 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
1da177e4
LT		 2158};
2159#define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2160
abbd8870
AV		 2161/*
2162 * ISP operations
2163 */
2164struct isp_operations {
2165
2166 int (*pci_config) (struct scsi_qla_host *);
2167 void (*reset_chip) (struct scsi_qla_host *);
2168 int (*chip_diag) (struct scsi_qla_host *);
2169 void (*config_rings) (struct scsi_qla_host *);
2170 void (*reset_adapter) (struct scsi_qla_host *);
2171 int (*nvram_config) (struct scsi_qla_host *);
2172 void (*update_fw_options) (struct scsi_qla_host *);
2173 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2174
2175 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2176 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2177
2178 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2179 void (*enable_intrs) (struct scsi_qla_host *);
2180 void (*disable_intrs) (struct scsi_qla_host *);
2181
2182 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2183 int (*abort_target) (struct fc_port *);
2184 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2185 uint8_t, uint8_t, uint16_t *, uint8_t);
1c7c6357
AV		 2186 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2187 uint8_t, uint8_t);
abbd8870
AV		 2188
2189 uint16_t (*calc_req_entries) (uint16_t);
2190 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
8c958a99 2191 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
cca5335c
AV		 2192 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2193 uint32_t);
abbd8870
AV		 2194
2195 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2196 uint32_t, uint32_t);
2197 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2198 uint32_t);
2199
2200 void (*fw_dump) (struct scsi_qla_host *, int);
2201 void (*ascii_fw_dump) (struct scsi_qla_host *);
2202};
2203
1da177e4
LT		 2204/*
2205 * Linux Host Adapter structure
2206 */
2207typedef struct scsi_qla_host {
2208 struct list_head list;
2209
2210 /* Commonly used flags and state information. */
2211 struct Scsi_Host *host;
2212 struct pci_dev *pdev;
2213
2214 unsigned long host_no;
2215 unsigned long instance;
2216
2217 volatile struct {
2218 uint32_t init_done :1;
2219 uint32_t online :1;
2220 uint32_t mbox_int :1;
2221 uint32_t mbox_busy :1;
2222 uint32_t rscn_queue_overflow :1;
2223 uint32_t reset_active :1;
2224
2225 uint32_t management_server_logged_in :1;
2226 uint32_t process_response_queue :1;
2227
2228 uint32_t disable_risc_code_load :1;
2229 uint32_t enable_64bit_addressing :1;
2230 uint32_t enable_lip_reset :1;
2231 uint32_t enable_lip_full_login :1;
2232 uint32_t enable_target_reset :1;
2233 uint32_t enable_led_scheme :1;
3d71644c
AV		 2234 uint32_t msi_enabled :1;
2235 uint32_t msix_enabled :1;
1da177e4
LT		 2236 } flags;
2237
2238 atomic_t loop_state;
2239#define LOOP_TIMEOUT 1
2240#define LOOP_DOWN 2
2241#define LOOP_UP 3
2242#define LOOP_UPDATE 4
2243#define LOOP_READY 5
2244#define LOOP_DEAD 6
2245
2246 unsigned long dpc_flags;
2247#define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2248#define RESET_ACTIVE 1
2249#define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2250#define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2251#define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2252#define LOOP_RESYNC_ACTIVE 5
2253#define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2254#define RSCN_UPDATE 7 /* Perform an RSCN update. */
2255#define MAILBOX_RETRY 8
2256#define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2257#define FAILOVER_EVENT_NEEDED 10
2258#define FAILOVER_EVENT 11
2259#define FAILOVER_NEEDED 12
2260#define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2261#define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2262#define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2263#define ABORT_QUEUES_NEEDED 16
2264#define RELOGIN_NEEDED 17
2265#define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2266#define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2267#define ISP_ABORT_RETRY 20 /* ISP aborted. */
2268#define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2269#define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
fa2a1ce5 2270#define IOCTL_ERROR_RECOVERY 23
1da177e4 2271#define LOOP_RESET_NEEDED 24
3d71644c 2272#define BEACON_BLINK_NEEDED 25
cca5335c 2273#define REGISTER_FDMI_NEEDED 26
d97994dc 2274#define FCPORT_UPDATE_NEEDED 27
1da177e4
LT		 2275
2276 uint32_t device_flags;
2277#define DFLG_LOCAL_DEVICES BIT_0
2278#define DFLG_RETRY_LOCAL_DEVICES BIT_1
2279#define DFLG_FABRIC_DEVICES BIT_2
2280#define SWITCH_FOUND BIT_3
2281#define DFLG_NO_CABLE BIT_4
2282
2283 /* SRB cache. */
2284#define SRB_MIN_REQ 128
2285 mempool_t *srb_mempool;
2286
fa2a1ce5 2287 /* This spinlock is used to protect "io transactions", you must
1da177e4
LT		 2288 * aquire it before doing any IO to the card, eg with RD_REG*() and
2289 * WRT_REG*() for the duration of your entire commandtransaction.
2290 *
2291 * This spinlock is of lower priority than the io request lock.
2292 */
2293
2294 spinlock_t hardware_lock ____cacheline_aligned;
2295
2296 device_reg_t __iomem *iobase; /* Base I/O address */
2297 unsigned long pio_address;
2298 unsigned long pio_length;
2299#define MIN_IOBASE_LEN 0x100
2300
2301 /* ISP ring lock, rings, and indexes */
2302 dma_addr_t request_dma; /* Physical address. */
2303 request_t *request_ring; /* Base virtual address */
2304 request_t *request_ring_ptr; /* Current address. */
2305 uint16_t req_ring_index; /* Current index. */
2306 uint16_t req_q_cnt; /* Number of available entries. */
2307 uint16_t request_q_length;
2308
2309 dma_addr_t response_dma; /* Physical address. */
2310 response_t *response_ring; /* Base virtual address */
2311 response_t *response_ring_ptr; /* Current address. */
2312 uint16_t rsp_ring_index; /* Current index. */
2313 uint16_t response_q_length;
fa2a1ce5 2314
abbd8870 2315 struct isp_operations isp_ops;
1da177e4
LT		 2316
2317 /* Outstandings ISP commands. */
2318 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
fa2a1ce5 2319 uint32_t current_outstanding_cmd;
1da177e4
LT		 2320 srb_t *status_srb; /* Status continuation entry. */
2321
1da177e4
LT		 2322 uint16_t revision;
2323 uint8_t ports;
1da177e4
LT		 2324
2325 /* ISP configuration data. */
2326 uint16_t loop_id; /* Host adapter loop id */
2327 uint16_t fb_rev;
2328
2329 port_id_t d_id; /* Host adapter port id */
2330 uint16_t max_public_loop_ids;
2331 uint16_t min_external_loopid; /* First external loop Id */
2332
2333 uint16_t link_data_rate; /* F/W operating speed */
04414013
AV		 2334#define LDR_1GB 0
2335#define LDR_2GB 1
2336#define LDR_4GB 3
2337#define LDR_UNKNOWN 0xFFFF
1da177e4
LT		 2338
2339 uint8_t current_topology;
2340 uint8_t prev_topology;
2341#define ISP_CFG_NL 1
2342#define ISP_CFG_N 2
2343#define ISP_CFG_FL 4
2344#define ISP_CFG_F 8
2345
2346 uint8_t operating_mode; /* F/W operating mode */
2347#define LOOP 0
2348#define P2P 1
2349#define LOOP_P2P 2
2350#define P2P_LOOP 3
2351
fa2a1ce5 2352 uint8_t marker_needed;
1da177e4
LT		 2353
2354 uint8_t interrupts_on;
2355
2356 /* HBA serial number */
2357 uint8_t serial0;
2358 uint8_t serial1;
2359 uint8_t serial2;
2360
2361 /* NVRAM configuration data */
3d71644c 2362 uint16_t nvram_size;
1da177e4
LT		 2363 uint16_t nvram_base;
2364
2365 uint16_t loop_reset_delay;
1da177e4
LT		 2366 uint8_t retry_count;
2367 uint8_t login_timeout;
2368 uint16_t r_a_tov;
2369 int port_down_retry_count;
1da177e4 2370 uint8_t mbx_count;
1da177e4 2371 uint16_t last_loop_id;
cca5335c 2372 uint16_t mgmt_svr_loop_id;
1da177e4 2373
fa2a1ce5 2374 uint32_t login_retry_count;
1da177e4
LT		 2375
2376 /* Fibre Channel Device List. */
2377 struct list_head fcports;
2378 struct list_head rscn_fcports;
2379
2380 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2381 uint16_t iodesc_signature;
2382
1da177e4
LT		 2383 /* RSCN queue. */
2384 uint32_t rscn_queue[MAX_RSCN_COUNT];
2385 uint8_t rscn_in_ptr;
2386 uint8_t rscn_out_ptr;
2387
2388 /* SNS command interfaces. */
2389 ms_iocb_entry_t *ms_iocb;
2390 dma_addr_t ms_iocb_dma;
2391 struct ct_sns_pkt *ct_sns;
2392 dma_addr_t ct_sns_dma;
2393 /* SNS command interfaces for 2200. */
2394 struct sns_cmd_pkt *sns_cmd;
2395 dma_addr_t sns_cmd_dma;
2396
2397 pid_t dpc_pid;
2398 int dpc_should_die;
2399 struct completion dpc_inited;
2400 struct completion dpc_exited;
2401 struct semaphore *dpc_wait;
2402 uint8_t dpc_active; /* DPC routine is active */
2403
2404 /* Timeout timers. */
1da177e4
LT		 2405 uint8_t loop_down_abort_time; /* port down timer */
2406 atomic_t loop_down_timer; /* loop down timer */
2407 uint8_t link_down_timeout; /* link down timeout */
2408
2409 uint32_t timer_active;
2410 struct timer_list timer;
2411
2412 dma_addr_t gid_list_dma;
2413 struct gid_list_info *gid_list;
abbd8870 2414 int gid_list_info_size;
1da177e4
LT		 2415
2416 dma_addr_t rlc_rsp_dma;
2417 rpt_lun_cmd_rsp_t *rlc_rsp;
2418
fa2a1ce5 2419 /* Small DMA pool allocations -- maximum 256 bytes in length. */
1da177e4
LT		 2420#define DMA_POOL_SIZE 256
2421 struct dma_pool *s_dma_pool;
2422
2423 dma_addr_t init_cb_dma;
3d71644c
AV		 2424 init_cb_t *init_cb;
2425 int init_cb_size;
1da177e4
LT		 2426
2427 dma_addr_t iodesc_pd_dma;
2428 port_database_t *iodesc_pd;
2429
2430 /* These are used by mailbox operations. */
2431 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2432
2433 mbx_cmd_t *mcp;
2434 unsigned long mbx_cmd_flags;
2435#define MBX_INTERRUPT 1
2436#define MBX_INTR_WAIT 2
2437#define MBX_UPDATE_FLASH_ACTIVE 3
2438
2439 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2440
2441 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2442 struct semaphore mbx_intr_sem; /* Used for completion notification */
2443
2444 uint32_t mbx_flags;
2445#define MBX_IN_PROGRESS BIT_0
2446#define MBX_BUSY BIT_1 /* Got the Access */
fa2a1ce5 2447#define MBX_SLEEPING_ON_SEM BIT_2
1da177e4
LT		 2448#define MBX_POLLING_FOR_COMP BIT_3
2449#define MBX_COMPLETED BIT_4
fa2a1ce5 2450#define MBX_TIMEDOUT BIT_5
1da177e4
LT		 2451#define MBX_ACCESS_TIMEDOUT BIT_6
2452
2453 mbx_cmd_t mc;
2454
1da177e4
LT		 2455 /* Basic firmware related information. */
2456 struct qla_board_info *brd_info;
2457 uint16_t fw_major_version;
2458 uint16_t fw_minor_version;
2459 uint16_t fw_subminor_version;
2460 uint16_t fw_attributes;
2461 uint32_t fw_memory_size;
2462 uint32_t fw_transfer_size;
2463
2464 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2465 uint8_t fw_seriallink_options[4];
3d71644c 2466 uint16_t fw_seriallink_options24[4];
1da177e4
LT		 2467
2468 /* Firmware dump information. */
2469 void *fw_dump;
2470 int fw_dump_order;
2471 int fw_dump_reading;
2472 char *fw_dump_buffer;
2473 int fw_dump_buffer_len;
2474
3d71644c
AV		 2475 int fw_dumped;
2476 void *fw_dump24;
2477 int fw_dump24_len;
2478
1da177e4 2479 uint8_t host_str[16];
3d71644c 2480 uint32_t pci_attr;
1da177e4
LT		 2481
2482 uint16_t product_id[4];
2483
2484 uint8_t model_number[16+1];
2485#define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2486 char *model_desc;
cca5335c 2487 uint8_t adapter_id[16+1];
1da177e4 2488
3d71644c
AV		 2489 uint8_t *node_name;
2490 uint8_t *port_name;
1da177e4
LT		 2491 uint32_t isp_abort_cnt;
2492
1da177e4
LT		 2493 /* Needed for BEACON */
2494 uint16_t beacon_blink_led;
2495 uint16_t beacon_green_on;
4fdfefe5
AV		 2496
2497 uint16_t zio_mode;
2498 uint16_t zio_timer;
1da177e4
LT		 2499} scsi_qla_host_t;
2500
2501
2502/*
2503 * Macros to help code, maintain, etc.
2504 */
2505#define LOOP_TRANSITION(ha) \
2506 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
23443b1d 2507 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
1da177e4 2508 atomic_read(&ha->loop_state) == LOOP_DOWN)
fa2a1ce5 2509
1da177e4 2510#define TGT_Q(ha, t) (ha->otgt[t])
1da177e4
LT		 2511
2512#define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2513
2514#define qla_printk(level, ha, format, arg...) \
2515 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2516
2517/*
2518 * qla2x00 local function return status codes
2519 */
2520#define MBS_MASK 0x3fff
2521
2522#define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2523#define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2524#define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2525#define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2526#define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2527#define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2528#define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2529#define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2530#define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2531#define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2532
2533#define QLA_FUNCTION_TIMEOUT 0x100
2534#define QLA_FUNCTION_PARAMETER_ERROR 0x101
2535#define QLA_FUNCTION_FAILED 0x102
2536#define QLA_MEMORY_ALLOC_FAILED 0x103
2537#define QLA_LOCK_TIMEOUT 0x104
2538#define QLA_ABORTED 0x105
2539#define QLA_SUSPENDED 0x106
2540#define QLA_BUSY 0x107
2541#define QLA_RSCNS_HANDLED 0x108
cca5335c 2542#define QLA_ALREADY_REGISTERED 0x109
1da177e4
LT		 2543
2544/*
2545* Stat info for all adpaters
2546*/
2547struct _qla2x00stats {
2548 unsigned long mboxtout; /* mailbox timeouts */
2549 unsigned long mboxerr; /* mailbox errors */
2550 unsigned long ispAbort; /* ISP aborts */
2551 unsigned long debugNo;
2552 unsigned long loop_resync;
2553 unsigned long outarray_full;
2554 unsigned long retry_q_cnt;
2555};
2556
2557#define NVRAM_DELAY() udelay(10)
2558
2559#define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2560
2561/*
2562 * Flash support definitions
2563 */
2564#define FLASH_IMAGE_SIZE 131072
2565
2566#include "qla_gbl.h"
2567#include "qla_dbg.h"
2568#include "qla_inline.h"
1da177e4
LT		 2569
2570/*
2571* String arrays
2572*/
2573#define LINESIZE 256
2574#define MAXARGS 26
2575
2576#define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2577#define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2578#define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2579#define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2580#define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2581#define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2582
2583#endif
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