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[SCSI] qla2xxx: Use midlayer's int_to_scsilun() function.
[net-next-2.6.git] / drivers / scsi / qla2xxx / qla_dbg.c
CommitLineData
1da177e4
LT		 1/*
2 * QLOGIC LINUX SOFTWARE
3 *
4 * QLogic ISP2x00 device driver for Linux 2.6.x
ae91193c 5 * Copyright (C) 2003-2005 QLogic Corporation
1da177e4
LT		 6 * (www.qlogic.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 */
19#include "qla_def.h"
20
21#include <linux/delay.h>
22
23static int qla_uprintf(char **, char *, ...);
24
25/**
26 * qla2300_fw_dump() - Dumps binary data from the 2300 firmware.
27 * @ha: HA context
28 * @hardware_locked: Called with the hardware_lock
29 */
30void
31qla2300_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
32{
33 int rval;
34 uint32_t cnt, timer;
35 uint32_t risc_address;
36 uint16_t mb0, mb2;
37
38 uint32_t stat;
3d71644c 39 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 40 uint16_t __iomem *dmp_reg;
41 unsigned long flags;
42 struct qla2300_fw_dump *fw;
43 uint32_t dump_size, data_ram_cnt;
44
45 risc_address = data_ram_cnt = 0;
46 mb0 = mb2 = 0;
47 flags = 0;
48
49 if (!hardware_locked)
50 spin_lock_irqsave(&ha->hardware_lock, flags);
51
52 if (ha->fw_dump != NULL) {
53 qla_printk(KERN_WARNING, ha,
54 "Firmware has been previously dumped (%p) -- ignoring "
55 "request...\n", ha->fw_dump);
56 goto qla2300_fw_dump_failed;
57 }
58
59 /* Allocate (large) dump buffer. */
60 dump_size = sizeof(struct qla2300_fw_dump);
61 dump_size += (ha->fw_memory_size - 0x11000) * sizeof(uint16_t);
62 ha->fw_dump_order = get_order(dump_size);
63 ha->fw_dump = (struct qla2300_fw_dump *) __get_free_pages(GFP_ATOMIC,
64 ha->fw_dump_order);
65 if (ha->fw_dump == NULL) {
66 qla_printk(KERN_WARNING, ha,
67 "Unable to allocated memory for firmware dump (%d/%d).\n",
68 ha->fw_dump_order, dump_size);
69 goto qla2300_fw_dump_failed;
70 }
71 fw = ha->fw_dump;
72
73 rval = QLA_SUCCESS;
74 fw->hccr = RD_REG_WORD(&reg->hccr);
75
76 /* Pause RISC. */
fa2a1ce5 77 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 78 if (IS_QLA2300(ha)) {
79 for (cnt = 30000;
80 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
81 rval == QLA_SUCCESS; cnt--) {
82 if (cnt)
83 udelay(100);
84 else
85 rval = QLA_FUNCTION_TIMEOUT;
86 }
87 } else {
88 RD_REG_WORD(&reg->hccr); /* PCI Posting. */
89 udelay(10);
90 }
91
92 if (rval == QLA_SUCCESS) {
93 dmp_reg = (uint16_t __iomem *)(reg + 0);
fa2a1ce5 94 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
1da177e4
LT		 95 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
96
97 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
fa2a1ce5 98 for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; cnt++)
1da177e4
LT		 99 fw->risc_host_reg[cnt] = RD_REG_WORD(dmp_reg++);
100
101 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x40);
fa2a1ce5 102 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1da177e4
LT		 103 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
104
105 WRT_REG_WORD(&reg->ctrl_status, 0x40);
106 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 107 for (cnt = 0; cnt < sizeof(fw->resp_dma_reg) / 2; cnt++)
1da177e4
LT		 108 fw->resp_dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
109
110 WRT_REG_WORD(&reg->ctrl_status, 0x50);
111 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 112 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
1da177e4
LT		 113 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
114
115 WRT_REG_WORD(&reg->ctrl_status, 0x00);
116 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
fa2a1ce5 117 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
1da177e4
LT		 118 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
119
fa2a1ce5 120 WRT_REG_WORD(&reg->pcr, 0x2000);
1da177e4 121 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 122 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
1da177e4
LT		 123 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
124
fa2a1ce5 125 WRT_REG_WORD(&reg->pcr, 0x2200);
1da177e4 126 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 127 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
1da177e4
LT		 128 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
129
fa2a1ce5 130 WRT_REG_WORD(&reg->pcr, 0x2400);
1da177e4 131 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 132 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
1da177e4
LT		 133 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
134
fa2a1ce5 135 WRT_REG_WORD(&reg->pcr, 0x2600);
1da177e4 136 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 137 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
1da177e4
LT		 138 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
139
fa2a1ce5 140 WRT_REG_WORD(&reg->pcr, 0x2800);
1da177e4 141 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 142 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
1da177e4
LT		 143 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
144
fa2a1ce5 145 WRT_REG_WORD(&reg->pcr, 0x2A00);
1da177e4 146 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 147 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
1da177e4
LT		 148 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
149
fa2a1ce5 150 WRT_REG_WORD(&reg->pcr, 0x2C00);
1da177e4 151 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 152 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
1da177e4
LT		 153 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
154
fa2a1ce5 155 WRT_REG_WORD(&reg->pcr, 0x2E00);
1da177e4 156 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 157 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
1da177e4
LT		 158 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
159
fa2a1ce5 160 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1da177e4 161 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 162 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
1da177e4
LT		 163 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
164
fa2a1ce5 165 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1da177e4 166 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 167 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
1da177e4
LT		 168 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
169
fa2a1ce5 170 WRT_REG_WORD(&reg->ctrl_status, 0x30);
1da177e4 171 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 172 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
1da177e4
LT		 173 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
174
175 /* Reset RISC. */
176 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
177 for (cnt = 0; cnt < 30000; cnt++) {
178 if ((RD_REG_WORD(&reg->ctrl_status) &
179 CSR_ISP_SOFT_RESET) == 0)
180 break;
181
182 udelay(10);
183 }
184 }
185
186 if (!IS_QLA2300(ha)) {
187 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
188 rval == QLA_SUCCESS; cnt--) {
189 if (cnt)
190 udelay(100);
191 else
192 rval = QLA_FUNCTION_TIMEOUT;
193 }
194 }
195
196 if (rval == QLA_SUCCESS) {
197 /* Get RISC SRAM. */
198 risc_address = 0x800;
199 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
200 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
201 }
202 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
203 cnt++, risc_address++) {
204 WRT_MAILBOX_REG(ha, reg, 1, (uint16_t)risc_address);
205 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
206
207 for (timer = 6000000; timer; timer--) {
208 /* Check for pending interrupts. */
209 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
210 if (stat & HSR_RISC_INT) {
211 stat &= 0xff;
212
213 if (stat == 0x1 || stat == 0x2) {
214 set_bit(MBX_INTERRUPT,
215 &ha->mbx_cmd_flags);
216
217 mb0 = RD_MAILBOX_REG(ha, reg, 0);
218 mb2 = RD_MAILBOX_REG(ha, reg, 2);
219
220 /* Release mailbox registers. */
221 WRT_REG_WORD(&reg->semaphore, 0);
222 WRT_REG_WORD(&reg->hccr,
223 HCCR_CLR_RISC_INT);
224 RD_REG_WORD(&reg->hccr);
225 break;
226 } else if (stat == 0x10 || stat == 0x11) {
227 set_bit(MBX_INTERRUPT,
228 &ha->mbx_cmd_flags);
229
230 mb0 = RD_MAILBOX_REG(ha, reg, 0);
231 mb2 = RD_MAILBOX_REG(ha, reg, 2);
232
233 WRT_REG_WORD(&reg->hccr,
234 HCCR_CLR_RISC_INT);
235 RD_REG_WORD(&reg->hccr);
236 break;
237 }
238
239 /* clear this intr; it wasn't a mailbox intr */
240 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
241 RD_REG_WORD(&reg->hccr);
242 }
243 udelay(5);
244 }
245
246 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
247 rval = mb0 & MBS_MASK;
248 fw->risc_ram[cnt] = mb2;
249 } else {
250 rval = QLA_FUNCTION_FAILED;
251 }
252 }
253
254 if (rval == QLA_SUCCESS) {
255 /* Get stack SRAM. */
256 risc_address = 0x10000;
257 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
258 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
259 }
260 for (cnt = 0; cnt < sizeof(fw->stack_ram) / 2 && rval == QLA_SUCCESS;
261 cnt++, risc_address++) {
262 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
263 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
264 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
265
266 for (timer = 6000000; timer; timer--) {
267 /* Check for pending interrupts. */
268 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
269 if (stat & HSR_RISC_INT) {
270 stat &= 0xff;
271
272 if (stat == 0x1 || stat == 0x2) {
273 set_bit(MBX_INTERRUPT,
274 &ha->mbx_cmd_flags);
275
276 mb0 = RD_MAILBOX_REG(ha, reg, 0);
277 mb2 = RD_MAILBOX_REG(ha, reg, 2);
278
279 /* Release mailbox registers. */
280 WRT_REG_WORD(&reg->semaphore, 0);
281 WRT_REG_WORD(&reg->hccr,
282 HCCR_CLR_RISC_INT);
283 RD_REG_WORD(&reg->hccr);
284 break;
285 } else if (stat == 0x10 || stat == 0x11) {
286 set_bit(MBX_INTERRUPT,
287 &ha->mbx_cmd_flags);
288
289 mb0 = RD_MAILBOX_REG(ha, reg, 0);
290 mb2 = RD_MAILBOX_REG(ha, reg, 2);
291
292 WRT_REG_WORD(&reg->hccr,
293 HCCR_CLR_RISC_INT);
294 RD_REG_WORD(&reg->hccr);
295 break;
296 }
297
298 /* clear this intr; it wasn't a mailbox intr */
299 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
300 RD_REG_WORD(&reg->hccr);
301 }
302 udelay(5);
303 }
304
305 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
306 rval = mb0 & MBS_MASK;
307 fw->stack_ram[cnt] = mb2;
308 } else {
309 rval = QLA_FUNCTION_FAILED;
310 }
311 }
312
313 if (rval == QLA_SUCCESS) {
314 /* Get data SRAM. */
315 risc_address = 0x11000;
316 data_ram_cnt = ha->fw_memory_size - risc_address + 1;
317 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_EXTENDED);
318 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
319 }
320 for (cnt = 0; cnt < data_ram_cnt && rval == QLA_SUCCESS;
321 cnt++, risc_address++) {
322 WRT_MAILBOX_REG(ha, reg, 1, LSW(risc_address));
323 WRT_MAILBOX_REG(ha, reg, 8, MSW(risc_address));
324 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
325
326 for (timer = 6000000; timer; timer--) {
327 /* Check for pending interrupts. */
328 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
329 if (stat & HSR_RISC_INT) {
330 stat &= 0xff;
331
332 if (stat == 0x1 || stat == 0x2) {
333 set_bit(MBX_INTERRUPT,
334 &ha->mbx_cmd_flags);
335
336 mb0 = RD_MAILBOX_REG(ha, reg, 0);
337 mb2 = RD_MAILBOX_REG(ha, reg, 2);
338
339 /* Release mailbox registers. */
340 WRT_REG_WORD(&reg->semaphore, 0);
341 WRT_REG_WORD(&reg->hccr,
342 HCCR_CLR_RISC_INT);
343 RD_REG_WORD(&reg->hccr);
344 break;
345 } else if (stat == 0x10 || stat == 0x11) {
346 set_bit(MBX_INTERRUPT,
347 &ha->mbx_cmd_flags);
348
349 mb0 = RD_MAILBOX_REG(ha, reg, 0);
350 mb2 = RD_MAILBOX_REG(ha, reg, 2);
351
352 WRT_REG_WORD(&reg->hccr,
353 HCCR_CLR_RISC_INT);
354 RD_REG_WORD(&reg->hccr);
355 break;
356 }
357
358 /* clear this intr; it wasn't a mailbox intr */
359 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
360 RD_REG_WORD(&reg->hccr);
361 }
362 udelay(5);
363 }
364
365 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
366 rval = mb0 & MBS_MASK;
367 fw->data_ram[cnt] = mb2;
368 } else {
369 rval = QLA_FUNCTION_FAILED;
370 }
371 }
372
373
374 if (rval != QLA_SUCCESS) {
375 qla_printk(KERN_WARNING, ha,
376 "Failed to dump firmware (%x)!!!\n", rval);
377
378 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
379 ha->fw_dump = NULL;
380 } else {
381 qla_printk(KERN_INFO, ha,
382 "Firmware dump saved to temp buffer (%ld/%p).\n",
383 ha->host_no, ha->fw_dump);
384 }
385
386qla2300_fw_dump_failed:
387 if (!hardware_locked)
388 spin_unlock_irqrestore(&ha->hardware_lock, flags);
389}
390
391/**
392 * qla2300_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
393 * @ha: HA context
394 */
395void
396qla2300_ascii_fw_dump(scsi_qla_host_t *ha)
397{
398 uint32_t cnt;
399 char *uiter;
400 char fw_info[30];
401 struct qla2300_fw_dump *fw;
402 uint32_t data_ram_cnt;
403
404 uiter = ha->fw_dump_buffer;
405 fw = ha->fw_dump;
406
407 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
abbd8870 408 ha->isp_ops.fw_version_str(ha, fw_info));
1da177e4
LT		 409
410 qla_uprintf(&uiter, "\n[==>BEG]\n");
411
412 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
413
414 qla_uprintf(&uiter, "PBIU Registers:");
415 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
416 if (cnt % 8 == 0) {
417 qla_uprintf(&uiter, "\n");
418 }
419 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
420 }
421
422 qla_uprintf(&uiter, "\n\nReqQ-RspQ-Risc2Host Status registers:");
423 for (cnt = 0; cnt < sizeof (fw->risc_host_reg) / 2; cnt++) {
424 if (cnt % 8 == 0) {
425 qla_uprintf(&uiter, "\n");
426 }
427 qla_uprintf(&uiter, "%04x ", fw->risc_host_reg[cnt]);
428 }
429
430 qla_uprintf(&uiter, "\n\nMailbox Registers:");
431 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
432 if (cnt % 8 == 0) {
433 qla_uprintf(&uiter, "\n");
434 }
435 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
436 }
437
438 qla_uprintf(&uiter, "\n\nAuto Request Response DMA Registers:");
439 for (cnt = 0; cnt < sizeof (fw->resp_dma_reg) / 2; cnt++) {
440 if (cnt % 8 == 0) {
441 qla_uprintf(&uiter, "\n");
442 }
443 qla_uprintf(&uiter, "%04x ", fw->resp_dma_reg[cnt]);
444 }
445
446 qla_uprintf(&uiter, "\n\nDMA Registers:");
447 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
448 if (cnt % 8 == 0) {
449 qla_uprintf(&uiter, "\n");
450 }
451 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
452 }
453
454 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
455 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
456 if (cnt % 8 == 0) {
457 qla_uprintf(&uiter, "\n");
458 }
459 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
460 }
461
462 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
463 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
464 if (cnt % 8 == 0) {
465 qla_uprintf(&uiter, "\n");
466 }
467 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
468 }
469
470 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
471 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
472 if (cnt % 8 == 0) {
473 qla_uprintf(&uiter, "\n");
474 }
475 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
476 }
477
478 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
479 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
480 if (cnt % 8 == 0) {
481 qla_uprintf(&uiter, "\n");
482 }
483 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
484 }
485
486 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
487 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
488 if (cnt % 8 == 0) {
489 qla_uprintf(&uiter, "\n");
490 }
491 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
492 }
493
494 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
495 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
496 if (cnt % 8 == 0) {
497 qla_uprintf(&uiter, "\n");
498 }
499 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
500 }
501
502 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
503 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
504 if (cnt % 8 == 0) {
505 qla_uprintf(&uiter, "\n");
506 }
507 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
508 }
509
510 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
511 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
512 if (cnt % 8 == 0) {
513 qla_uprintf(&uiter, "\n");
514 }
515 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
516 }
517
518 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
519 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
520 if (cnt % 8 == 0) {
521 qla_uprintf(&uiter, "\n");
522 }
523 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
524 }
525
526 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
527 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
528 if (cnt % 8 == 0) {
529 qla_uprintf(&uiter, "\n");
530 }
531 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
532 }
533
534 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
535 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
536 if (cnt % 8 == 0) {
537 qla_uprintf(&uiter, "\n");
538 }
539 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
540 }
541
542 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
543 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
544 if (cnt % 8 == 0) {
545 qla_uprintf(&uiter, "\n");
546 }
547 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
548 }
549
550 qla_uprintf(&uiter, "\n\nCode RAM Dump:");
551 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
552 if (cnt % 8 == 0) {
553 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x0800);
554 }
555 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
556 }
557
558 qla_uprintf(&uiter, "\n\nStack RAM Dump:");
559 for (cnt = 0; cnt < sizeof (fw->stack_ram) / 2; cnt++) {
560 if (cnt % 8 == 0) {
561 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x10000);
562 }
563 qla_uprintf(&uiter, "%04x ", fw->stack_ram[cnt]);
564 }
565
566 qla_uprintf(&uiter, "\n\nData RAM Dump:");
567 data_ram_cnt = ha->fw_memory_size - 0x11000 + 1;
568 for (cnt = 0; cnt < data_ram_cnt; cnt++) {
569 if (cnt % 8 == 0) {
570 qla_uprintf(&uiter, "\n%05x: ", cnt + 0x11000);
571 }
572 qla_uprintf(&uiter, "%04x ", fw->data_ram[cnt]);
573 }
574
575 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
576}
577
578/**
579 * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware.
580 * @ha: HA context
581 * @hardware_locked: Called with the hardware_lock
582 */
583void
584qla2100_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
585{
586 int rval;
587 uint32_t cnt, timer;
588 uint16_t risc_address;
589 uint16_t mb0, mb2;
3d71644c 590 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 591 uint16_t __iomem *dmp_reg;
592 unsigned long flags;
593 struct qla2100_fw_dump *fw;
594
595 risc_address = 0;
596 mb0 = mb2 = 0;
597 flags = 0;
598
599 if (!hardware_locked)
600 spin_lock_irqsave(&ha->hardware_lock, flags);
601
602 if (ha->fw_dump != NULL) {
603 qla_printk(KERN_WARNING, ha,
604 "Firmware has been previously dumped (%p) -- ignoring "
605 "request...\n", ha->fw_dump);
606 goto qla2100_fw_dump_failed;
607 }
608
609 /* Allocate (large) dump buffer. */
610 ha->fw_dump_order = get_order(sizeof(struct qla2100_fw_dump));
611 ha->fw_dump = (struct qla2100_fw_dump *) __get_free_pages(GFP_ATOMIC,
612 ha->fw_dump_order);
613 if (ha->fw_dump == NULL) {
614 qla_printk(KERN_WARNING, ha,
615 "Unable to allocated memory for firmware dump (%d/%Zd).\n",
616 ha->fw_dump_order, sizeof(struct qla2100_fw_dump));
617 goto qla2100_fw_dump_failed;
618 }
619 fw = ha->fw_dump;
620
621 rval = QLA_SUCCESS;
622 fw->hccr = RD_REG_WORD(&reg->hccr);
623
624 /* Pause RISC. */
fa2a1ce5 625 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 626 for (cnt = 30000; (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
627 rval == QLA_SUCCESS; cnt--) {
628 if (cnt)
629 udelay(100);
630 else
631 rval = QLA_FUNCTION_TIMEOUT;
632 }
633 if (rval == QLA_SUCCESS) {
634 dmp_reg = (uint16_t __iomem *)(reg + 0);
fa2a1ce5 635 for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++)
1da177e4
LT		 636 fw->pbiu_reg[cnt] = RD_REG_WORD(dmp_reg++);
637
638 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x10);
639 for (cnt = 0; cnt < ha->mbx_count; cnt++) {
640 if (cnt == 8) {
641 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xe0);
642 }
643 fw->mailbox_reg[cnt] = RD_REG_WORD(dmp_reg++);
644 }
645
646 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x20);
fa2a1ce5 647 for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++)
1da177e4
LT		 648 fw->dma_reg[cnt] = RD_REG_WORD(dmp_reg++);
649
650 WRT_REG_WORD(&reg->ctrl_status, 0x00);
651 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0xA0);
fa2a1ce5 652 for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++)
1da177e4
LT		 653 fw->risc_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
654
fa2a1ce5 655 WRT_REG_WORD(&reg->pcr, 0x2000);
1da177e4 656 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 657 for (cnt = 0; cnt < sizeof(fw->risc_gp0_reg) / 2; cnt++)
1da177e4
LT		 658 fw->risc_gp0_reg[cnt] = RD_REG_WORD(dmp_reg++);
659
fa2a1ce5 660 WRT_REG_WORD(&reg->pcr, 0x2100);
1da177e4 661 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 662 for (cnt = 0; cnt < sizeof(fw->risc_gp1_reg) / 2; cnt++)
1da177e4
LT		 663 fw->risc_gp1_reg[cnt] = RD_REG_WORD(dmp_reg++);
664
fa2a1ce5 665 WRT_REG_WORD(&reg->pcr, 0x2200);
1da177e4 666 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 667 for (cnt = 0; cnt < sizeof(fw->risc_gp2_reg) / 2; cnt++)
1da177e4
LT		 668 fw->risc_gp2_reg[cnt] = RD_REG_WORD(dmp_reg++);
669
fa2a1ce5 670 WRT_REG_WORD(&reg->pcr, 0x2300);
1da177e4 671 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 672 for (cnt = 0; cnt < sizeof(fw->risc_gp3_reg) / 2; cnt++)
1da177e4
LT		 673 fw->risc_gp3_reg[cnt] = RD_REG_WORD(dmp_reg++);
674
fa2a1ce5 675 WRT_REG_WORD(&reg->pcr, 0x2400);
1da177e4 676 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 677 for (cnt = 0; cnt < sizeof(fw->risc_gp4_reg) / 2; cnt++)
1da177e4
LT		 678 fw->risc_gp4_reg[cnt] = RD_REG_WORD(dmp_reg++);
679
fa2a1ce5 680 WRT_REG_WORD(&reg->pcr, 0x2500);
1da177e4 681 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 682 for (cnt = 0; cnt < sizeof(fw->risc_gp5_reg) / 2; cnt++)
1da177e4
LT		 683 fw->risc_gp5_reg[cnt] = RD_REG_WORD(dmp_reg++);
684
fa2a1ce5 685 WRT_REG_WORD(&reg->pcr, 0x2600);
1da177e4 686 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 687 for (cnt = 0; cnt < sizeof(fw->risc_gp6_reg) / 2; cnt++)
1da177e4
LT		 688 fw->risc_gp6_reg[cnt] = RD_REG_WORD(dmp_reg++);
689
fa2a1ce5 690 WRT_REG_WORD(&reg->pcr, 0x2700);
1da177e4 691 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 692 for (cnt = 0; cnt < sizeof(fw->risc_gp7_reg) / 2; cnt++)
1da177e4
LT		 693 fw->risc_gp7_reg[cnt] = RD_REG_WORD(dmp_reg++);
694
fa2a1ce5 695 WRT_REG_WORD(&reg->ctrl_status, 0x10);
1da177e4 696 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 697 for (cnt = 0; cnt < sizeof(fw->frame_buf_hdw_reg) / 2; cnt++)
1da177e4
LT		 698 fw->frame_buf_hdw_reg[cnt] = RD_REG_WORD(dmp_reg++);
699
fa2a1ce5 700 WRT_REG_WORD(&reg->ctrl_status, 0x20);
1da177e4 701 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 702 for (cnt = 0; cnt < sizeof(fw->fpm_b0_reg) / 2; cnt++)
1da177e4
LT		 703 fw->fpm_b0_reg[cnt] = RD_REG_WORD(dmp_reg++);
704
fa2a1ce5 705 WRT_REG_WORD(&reg->ctrl_status, 0x30);
1da177e4 706 dmp_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
fa2a1ce5 707 for (cnt = 0; cnt < sizeof(fw->fpm_b1_reg) / 2; cnt++)
1da177e4
LT		 708 fw->fpm_b1_reg[cnt] = RD_REG_WORD(dmp_reg++);
709
710 /* Reset the ISP. */
711 WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
712 }
713
714 for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 &&
715 rval == QLA_SUCCESS; cnt--) {
716 if (cnt)
717 udelay(100);
718 else
719 rval = QLA_FUNCTION_TIMEOUT;
720 }
721
722 /* Pause RISC. */
723 if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) &&
724 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
725
fa2a1ce5 726 WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1da177e4
LT		 727 for (cnt = 30000;
728 (RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) == 0 &&
729 rval == QLA_SUCCESS; cnt--) {
730 if (cnt)
731 udelay(100);
732 else
733 rval = QLA_FUNCTION_TIMEOUT;
734 }
735 if (rval == QLA_SUCCESS) {
736 /* Set memory configuration and timing. */
737 if (IS_QLA2100(ha))
738 WRT_REG_WORD(&reg->mctr, 0xf1);
739 else
740 WRT_REG_WORD(&reg->mctr, 0xf2);
741 RD_REG_WORD(&reg->mctr); /* PCI Posting. */
742
743 /* Release RISC. */
744 WRT_REG_WORD(&reg->hccr, HCCR_RELEASE_RISC);
745 }
746 }
747
748 if (rval == QLA_SUCCESS) {
749 /* Get RISC SRAM. */
750 risc_address = 0x1000;
751 WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD);
752 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
753 }
754 for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS;
755 cnt++, risc_address++) {
756 WRT_MAILBOX_REG(ha, reg, 1, risc_address);
757 WRT_REG_WORD(&reg->hccr, HCCR_SET_HOST_INT);
758
759 for (timer = 6000000; timer != 0; timer--) {
760 /* Check for pending interrupts. */
761 if (RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) {
762 if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
763 set_bit(MBX_INTERRUPT,
764 &ha->mbx_cmd_flags);
765
766 mb0 = RD_MAILBOX_REG(ha, reg, 0);
767 mb2 = RD_MAILBOX_REG(ha, reg, 2);
768
769 WRT_REG_WORD(&reg->semaphore, 0);
770 WRT_REG_WORD(&reg->hccr,
771 HCCR_CLR_RISC_INT);
772 RD_REG_WORD(&reg->hccr);
773 break;
774 }
775 WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
776 RD_REG_WORD(&reg->hccr);
777 }
778 udelay(5);
779 }
780
781 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
782 rval = mb0 & MBS_MASK;
783 fw->risc_ram[cnt] = mb2;
784 } else {
785 rval = QLA_FUNCTION_FAILED;
786 }
787 }
788
789 if (rval != QLA_SUCCESS) {
790 qla_printk(KERN_WARNING, ha,
791 "Failed to dump firmware (%x)!!!\n", rval);
792
793 free_pages((unsigned long)ha->fw_dump, ha->fw_dump_order);
794 ha->fw_dump = NULL;
795 } else {
796 qla_printk(KERN_INFO, ha,
797 "Firmware dump saved to temp buffer (%ld/%p).\n",
798 ha->host_no, ha->fw_dump);
799 }
800
801qla2100_fw_dump_failed:
802 if (!hardware_locked)
803 spin_unlock_irqrestore(&ha->hardware_lock, flags);
804}
805
806/**
807 * qla2100_ascii_fw_dump() - Converts a binary firmware dump to ASCII.
808 * @ha: HA context
809 */
810void
811qla2100_ascii_fw_dump(scsi_qla_host_t *ha)
812{
813 uint32_t cnt;
814 char *uiter;
815 char fw_info[30];
816 struct qla2100_fw_dump *fw;
817
818 uiter = ha->fw_dump_buffer;
819 fw = ha->fw_dump;
820
821 qla_uprintf(&uiter, "%s Firmware Version %s\n", ha->model_number,
abbd8870 822 ha->isp_ops.fw_version_str(ha, fw_info));
1da177e4
LT		 823
824 qla_uprintf(&uiter, "\n[==>BEG]\n");
825
826 qla_uprintf(&uiter, "HCCR Register:\n%04x\n\n", fw->hccr);
827
828 qla_uprintf(&uiter, "PBIU Registers:");
829 for (cnt = 0; cnt < sizeof (fw->pbiu_reg) / 2; cnt++) {
830 if (cnt % 8 == 0) {
831 qla_uprintf(&uiter, "\n");
832 }
833 qla_uprintf(&uiter, "%04x ", fw->pbiu_reg[cnt]);
834 }
835
836 qla_uprintf(&uiter, "\n\nMailbox Registers:");
837 for (cnt = 0; cnt < sizeof (fw->mailbox_reg) / 2; cnt++) {
838 if (cnt % 8 == 0) {
839 qla_uprintf(&uiter, "\n");
840 }
841 qla_uprintf(&uiter, "%04x ", fw->mailbox_reg[cnt]);
842 }
843
844 qla_uprintf(&uiter, "\n\nDMA Registers:");
845 for (cnt = 0; cnt < sizeof (fw->dma_reg) / 2; cnt++) {
846 if (cnt % 8 == 0) {
847 qla_uprintf(&uiter, "\n");
848 }
849 qla_uprintf(&uiter, "%04x ", fw->dma_reg[cnt]);
850 }
851
852 qla_uprintf(&uiter, "\n\nRISC Hardware Registers:");
853 for (cnt = 0; cnt < sizeof (fw->risc_hdw_reg) / 2; cnt++) {
854 if (cnt % 8 == 0) {
855 qla_uprintf(&uiter, "\n");
856 }
857 qla_uprintf(&uiter, "%04x ", fw->risc_hdw_reg[cnt]);
858 }
859
860 qla_uprintf(&uiter, "\n\nRISC GP0 Registers:");
861 for (cnt = 0; cnt < sizeof (fw->risc_gp0_reg) / 2; cnt++) {
862 if (cnt % 8 == 0) {
863 qla_uprintf(&uiter, "\n");
864 }
865 qla_uprintf(&uiter, "%04x ", fw->risc_gp0_reg[cnt]);
866 }
867
868 qla_uprintf(&uiter, "\n\nRISC GP1 Registers:");
869 for (cnt = 0; cnt < sizeof (fw->risc_gp1_reg) / 2; cnt++) {
870 if (cnt % 8 == 0) {
871 qla_uprintf(&uiter, "\n");
872 }
873 qla_uprintf(&uiter, "%04x ", fw->risc_gp1_reg[cnt]);
874 }
875
876 qla_uprintf(&uiter, "\n\nRISC GP2 Registers:");
877 for (cnt = 0; cnt < sizeof (fw->risc_gp2_reg) / 2; cnt++) {
878 if (cnt % 8 == 0) {
879 qla_uprintf(&uiter, "\n");
880 }
881 qla_uprintf(&uiter, "%04x ", fw->risc_gp2_reg[cnt]);
882 }
883
884 qla_uprintf(&uiter, "\n\nRISC GP3 Registers:");
885 for (cnt = 0; cnt < sizeof (fw->risc_gp3_reg) / 2; cnt++) {
886 if (cnt % 8 == 0) {
887 qla_uprintf(&uiter, "\n");
888 }
889 qla_uprintf(&uiter, "%04x ", fw->risc_gp3_reg[cnt]);
890 }
891
892 qla_uprintf(&uiter, "\n\nRISC GP4 Registers:");
893 for (cnt = 0; cnt < sizeof (fw->risc_gp4_reg) / 2; cnt++) {
894 if (cnt % 8 == 0) {
895 qla_uprintf(&uiter, "\n");
896 }
897 qla_uprintf(&uiter, "%04x ", fw->risc_gp4_reg[cnt]);
898 }
899
900 qla_uprintf(&uiter, "\n\nRISC GP5 Registers:");
901 for (cnt = 0; cnt < sizeof (fw->risc_gp5_reg) / 2; cnt++) {
902 if (cnt % 8 == 0) {
903 qla_uprintf(&uiter, "\n");
904 }
905 qla_uprintf(&uiter, "%04x ", fw->risc_gp5_reg[cnt]);
906 }
907
908 qla_uprintf(&uiter, "\n\nRISC GP6 Registers:");
909 for (cnt = 0; cnt < sizeof (fw->risc_gp6_reg) / 2; cnt++) {
910 if (cnt % 8 == 0) {
911 qla_uprintf(&uiter, "\n");
912 }
913 qla_uprintf(&uiter, "%04x ", fw->risc_gp6_reg[cnt]);
914 }
915
916 qla_uprintf(&uiter, "\n\nRISC GP7 Registers:");
917 for (cnt = 0; cnt < sizeof (fw->risc_gp7_reg) / 2; cnt++) {
918 if (cnt % 8 == 0) {
919 qla_uprintf(&uiter, "\n");
920 }
921 qla_uprintf(&uiter, "%04x ", fw->risc_gp7_reg[cnt]);
922 }
923
924 qla_uprintf(&uiter, "\n\nFrame Buffer Hardware Registers:");
925 for (cnt = 0; cnt < sizeof (fw->frame_buf_hdw_reg) / 2; cnt++) {
926 if (cnt % 8 == 0) {
927 qla_uprintf(&uiter, "\n");
928 }
929 qla_uprintf(&uiter, "%04x ", fw->frame_buf_hdw_reg[cnt]);
930 }
931
932 qla_uprintf(&uiter, "\n\nFPM B0 Registers:");
933 for (cnt = 0; cnt < sizeof (fw->fpm_b0_reg) / 2; cnt++) {
934 if (cnt % 8 == 0) {
935 qla_uprintf(&uiter, "\n");
936 }
937 qla_uprintf(&uiter, "%04x ", fw->fpm_b0_reg[cnt]);
938 }
939
940 qla_uprintf(&uiter, "\n\nFPM B1 Registers:");
941 for (cnt = 0; cnt < sizeof (fw->fpm_b1_reg) / 2; cnt++) {
942 if (cnt % 8 == 0) {
943 qla_uprintf(&uiter, "\n");
944 }
945 qla_uprintf(&uiter, "%04x ", fw->fpm_b1_reg[cnt]);
946 }
947
948 qla_uprintf(&uiter, "\n\nRISC SRAM:");
949 for (cnt = 0; cnt < sizeof (fw->risc_ram) / 2; cnt++) {
950 if (cnt % 8 == 0) {
951 qla_uprintf(&uiter, "\n%04x: ", cnt + 0x1000);
952 }
953 qla_uprintf(&uiter, "%04x ", fw->risc_ram[cnt]);
954 }
955
956 qla_uprintf(&uiter, "\n\n[<==END] ISP Debug Dump.");
957
958 return;
959}
960
961static int
962qla_uprintf(char **uiter, char *fmt, ...)
963{
964 int iter, len;
965 char buf[128];
966 va_list args;
fa2a1ce5 967
1da177e4
LT		 968 va_start(args, fmt);
969 len = vsprintf(buf, fmt, args);
970 va_end(args);
971
972 for (iter = 0; iter < len; iter++, *uiter += 1)
973 *uiter[0] = buf[iter];
974
975 return (len);
976}
977
6d9b61ed
AV		 978
979void
980qla24xx_fw_dump(scsi_qla_host_t *ha, int hardware_locked)
981{
982 int rval;
983 uint32_t cnt, timer;
984 uint32_t risc_address;
985 uint16_t mb[4];
986
987 uint32_t stat;
988 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
989 uint32_t __iomem *dmp_reg;
990 uint32_t *iter_reg;
991 uint16_t __iomem *mbx_reg;
992 unsigned long flags;
993 struct qla24xx_fw_dump *fw;
994 uint32_t ext_mem_cnt;
995
996 risc_address = ext_mem_cnt = 0;
997 memset(mb, 0, sizeof(mb));
998 flags = 0;
999
1000 if (!hardware_locked)
1001 spin_lock_irqsave(&ha->hardware_lock, flags);
1002
1003 if (!ha->fw_dump24) {
1004 qla_printk(KERN_WARNING, ha,
1005 "No buffer available for dump!!!\n");
1006 goto qla24xx_fw_dump_failed;
1007 }
1008
1009 if (ha->fw_dumped) {
1010 qla_printk(KERN_WARNING, ha,
1011 "Firmware has been previously dumped (%p) -- ignoring "
1012 "request...\n", ha->fw_dump24);
1013 goto qla24xx_fw_dump_failed;
1014 }
1015 fw = (struct qla24xx_fw_dump *) ha->fw_dump24;
1016
1017 rval = QLA_SUCCESS;
1018 fw->hccr = RD_REG_DWORD(&reg->hccr);
1019
1020 /* Pause RISC. */
1021 if ((fw->hccr & HCCRX_RISC_PAUSE) == 0) {
1022 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_RESET |
1023 HCCRX_CLR_HOST_INT);
1024 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1025 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_RISC_PAUSE);
1026 for (cnt = 30000;
1027 (RD_REG_DWORD(&reg->hccr) & HCCRX_RISC_PAUSE) == 0 &&
1028 rval == QLA_SUCCESS; cnt--) {
1029 if (cnt)
1030 udelay(100);
1031 else
1032 rval = QLA_FUNCTION_TIMEOUT;
1033 }
1034 }
1035
1036 /* Disable interrupts. */
1037 WRT_REG_DWORD(&reg->ictrl, 0);
1038 RD_REG_DWORD(&reg->ictrl);
1039
1040 if (rval == QLA_SUCCESS) {
1041 /* Host interface registers. */
1042 dmp_reg = (uint32_t __iomem *)(reg + 0);
1043 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++)
1044 fw->host_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1045
1046 /* Mailbox registers. */
1047 mbx_reg = (uint16_t __iomem *)((uint8_t __iomem *)reg + 0x80);
1048 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++)
1049 fw->mailbox_reg[cnt] = RD_REG_WORD(mbx_reg++);
1050
1051 /* Transfer sequence registers. */
1052 iter_reg = fw->xseq_gp_reg;
1053 WRT_REG_DWORD(&reg->iobase_addr, 0xBF00);
1054 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1055 for (cnt = 0; cnt < 16; cnt++)
1056 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1057
1058 WRT_REG_DWORD(&reg->iobase_addr, 0xBF10);
1059 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1060 for (cnt = 0; cnt < 16; cnt++)
1061 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1062
1063 WRT_REG_DWORD(&reg->iobase_addr, 0xBF20);
1064 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1065 for (cnt = 0; cnt < 16; cnt++)
1066 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1067
1068 WRT_REG_DWORD(&reg->iobase_addr, 0xBF30);
1069 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1070 for (cnt = 0; cnt < 16; cnt++)
1071 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1072
1073 WRT_REG_DWORD(&reg->iobase_addr, 0xBF40);
1074 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1075 for (cnt = 0; cnt < 16; cnt++)
1076 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1077
1078 WRT_REG_DWORD(&reg->iobase_addr, 0xBF50);
1079 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1080 for (cnt = 0; cnt < 16; cnt++)
1081 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1082
1083 WRT_REG_DWORD(&reg->iobase_addr, 0xBF60);
1084 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1085 for (cnt = 0; cnt < 16; cnt++)
1086 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1087
1088 WRT_REG_DWORD(&reg->iobase_addr, 0xBF70);
1089 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1090 for (cnt = 0; cnt < 16; cnt++)
1091 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1092
1093 WRT_REG_DWORD(&reg->iobase_addr, 0xBFE0);
1094 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1095 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++)
1096 fw->xseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1097
1098 WRT_REG_DWORD(&reg->iobase_addr, 0xBFF0);
1099 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1100 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++)
1101 fw->xseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1102
1103 /* Receive sequence registers. */
1104 iter_reg = fw->rseq_gp_reg;
1105 WRT_REG_DWORD(&reg->iobase_addr, 0xFF00);
1106 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1107 for (cnt = 0; cnt < 16; cnt++)
1108 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1109
1110 WRT_REG_DWORD(&reg->iobase_addr, 0xFF10);
1111 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1112 for (cnt = 0; cnt < 16; cnt++)
1113 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1114
1115 WRT_REG_DWORD(&reg->iobase_addr, 0xFF20);
1116 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1117 for (cnt = 0; cnt < 16; cnt++)
1118 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1119
1120 WRT_REG_DWORD(&reg->iobase_addr, 0xFF30);
1121 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1122 for (cnt = 0; cnt < 16; cnt++)
1123 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1124
1125 WRT_REG_DWORD(&reg->iobase_addr, 0xFF40);
1126 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1127 for (cnt = 0; cnt < 16; cnt++)
1128 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1129
1130 WRT_REG_DWORD(&reg->iobase_addr, 0xFF50);
1131 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1132 for (cnt = 0; cnt < 16; cnt++)
1133 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1134
1135 WRT_REG_DWORD(&reg->iobase_addr, 0xFF60);
1136 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1137 for (cnt = 0; cnt < 16; cnt++)
1138 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1139
1140 WRT_REG_DWORD(&reg->iobase_addr, 0xFF70);
1141 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1142 for (cnt = 0; cnt < 16; cnt++)
1143 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1144
1145 WRT_REG_DWORD(&reg->iobase_addr, 0xFFD0);
1146 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1147 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++)
1148 fw->rseq_0_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1149
1150 WRT_REG_DWORD(&reg->iobase_addr, 0xFFE0);
1151 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1152 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++)
1153 fw->rseq_1_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1154
1155 WRT_REG_DWORD(&reg->iobase_addr, 0xFFF0);
1156 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1157 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++)
1158 fw->rseq_2_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1159
1160 /* Command DMA registers. */
1161 WRT_REG_DWORD(&reg->iobase_addr, 0x7100);
1162 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1163 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++)
1164 fw->cmd_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1165
1166 /* Queues. */
1167 iter_reg = fw->req0_dma_reg;
1168 WRT_REG_DWORD(&reg->iobase_addr, 0x7200);
1169 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1170 for (cnt = 0; cnt < 8; cnt++)
1171 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1172
1173 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1174 for (cnt = 0; cnt < 7; cnt++)
1175 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1176
1177 iter_reg = fw->resp0_dma_reg;
1178 WRT_REG_DWORD(&reg->iobase_addr, 0x7300);
1179 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1180 for (cnt = 0; cnt < 8; cnt++)
1181 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1182
1183 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1184 for (cnt = 0; cnt < 7; cnt++)
1185 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1186
1187 iter_reg = fw->req1_dma_reg;
1188 WRT_REG_DWORD(&reg->iobase_addr, 0x7400);
1189 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1190 for (cnt = 0; cnt < 8; cnt++)
1191 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1192
1193 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xE4);
1194 for (cnt = 0; cnt < 7; cnt++)
1195 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1196
1197 /* Transmit DMA registers. */
1198 iter_reg = fw->xmt0_dma_reg;
1199 WRT_REG_DWORD(&reg->iobase_addr, 0x7600);
1200 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1201 for (cnt = 0; cnt < 16; cnt++)
1202 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1203
1204 WRT_REG_DWORD(&reg->iobase_addr, 0x7610);
1205 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1206 for (cnt = 0; cnt < 16; cnt++)
1207 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1208
1209 iter_reg = fw->xmt1_dma_reg;
1210 WRT_REG_DWORD(&reg->iobase_addr, 0x7620);
1211 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1212 for (cnt = 0; cnt < 16; cnt++)
1213 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1214
1215 WRT_REG_DWORD(&reg->iobase_addr, 0x7630);
1216 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1217 for (cnt = 0; cnt < 16; cnt++)
1218 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1219
1220 iter_reg = fw->xmt2_dma_reg;
1221 WRT_REG_DWORD(&reg->iobase_addr, 0x7640);
1222 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1223 for (cnt = 0; cnt < 16; cnt++)
1224 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1225
1226 WRT_REG_DWORD(&reg->iobase_addr, 0x7650);
1227 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1228 for (cnt = 0; cnt < 16; cnt++)
1229 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1230
1231 iter_reg = fw->xmt3_dma_reg;
1232 WRT_REG_DWORD(&reg->iobase_addr, 0x7660);
1233 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1234 for (cnt = 0; cnt < 16; cnt++)
1235 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1236
1237 WRT_REG_DWORD(&reg->iobase_addr, 0x7670);
1238 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1239 for (cnt = 0; cnt < 16; cnt++)
1240 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1241
1242 iter_reg = fw->xmt4_dma_reg;
1243 WRT_REG_DWORD(&reg->iobase_addr, 0x7680);
1244 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1245 for (cnt = 0; cnt < 16; cnt++)
1246 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1247
1248 WRT_REG_DWORD(&reg->iobase_addr, 0x7690);
1249 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1250 for (cnt = 0; cnt < 16; cnt++)
1251 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1252
1253 WRT_REG_DWORD(&reg->iobase_addr, 0x76A0);
1254 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1255 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++)
1256 fw->xmt_data_dma_reg[cnt] = RD_REG_DWORD(dmp_reg++);
1257
1258 /* Receive DMA registers. */
1259 iter_reg = fw->rcvt0_data_dma_reg;
1260 WRT_REG_DWORD(&reg->iobase_addr, 0x7700);
1261 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1262 for (cnt = 0; cnt < 16; cnt++)
1263 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1264
1265 WRT_REG_DWORD(&reg->iobase_addr, 0x7710);
1266 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1267 for (cnt = 0; cnt < 16; cnt++)
1268 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1269
1270 iter_reg = fw->rcvt1_data_dma_reg;
1271 WRT_REG_DWORD(&reg->iobase_addr, 0x7720);
1272 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1273 for (cnt = 0; cnt < 16; cnt++)
1274 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1275
1276 WRT_REG_DWORD(&reg->iobase_addr, 0x7730);
1277 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1278 for (cnt = 0; cnt < 16; cnt++)
1279 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1280
1281 /* RISC registers. */
1282 iter_reg = fw->risc_gp_reg;
1283 WRT_REG_DWORD(&reg->iobase_addr, 0x0F00);
1284 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1285 for (cnt = 0; cnt < 16; cnt++)
1286 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1287
1288 WRT_REG_DWORD(&reg->iobase_addr, 0x0F10);
1289 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1290 for (cnt = 0; cnt < 16; cnt++)
1291 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1292
1293 WRT_REG_DWORD(&reg->iobase_addr, 0x0F20);
1294 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1295 for (cnt = 0; cnt < 16; cnt++)
1296 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1297
1298 WRT_REG_DWORD(&reg->iobase_addr, 0x0F30);
1299 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1300 for (cnt = 0; cnt < 16; cnt++)
1301 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1302
1303 WRT_REG_DWORD(&reg->iobase_addr, 0x0F40);
1304 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1305 for (cnt = 0; cnt < 16; cnt++)
1306 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1307
1308 WRT_REG_DWORD(&reg->iobase_addr, 0x0F50);
1309 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1310 for (cnt = 0; cnt < 16; cnt++)
1311 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1312
1313 WRT_REG_DWORD(&reg->iobase_addr, 0x0F60);
1314 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1315 for (cnt = 0; cnt < 16; cnt++)
1316 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1317
1318 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1319 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1320 for (cnt = 0; cnt < 16; cnt++)
1321 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1322
1323 WRT_REG_DWORD(&reg->iobase_addr, 0x0F70);
1324 RD_REG_DWORD(&reg->iobase_addr);
1325 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1326 WRT_REG_DWORD(dmp_reg, 0xB0000000);
1327 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1328 fw->shadow_reg[0] = RD_REG_DWORD(dmp_reg);
1329
1330 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1331 WRT_REG_DWORD(dmp_reg, 0xB0100000);
1332 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1333 fw->shadow_reg[1] = RD_REG_DWORD(dmp_reg);
1334
1335 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1336 WRT_REG_DWORD(dmp_reg, 0xB0200000);
b95adac7 1337 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
6d9b61ed
AV		 1338 fw->shadow_reg[2] = RD_REG_DWORD(dmp_reg);
1339
1340 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1341 WRT_REG_DWORD(dmp_reg, 0xB0300000);
1342 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1343 fw->shadow_reg[3] = RD_REG_DWORD(dmp_reg);
1344
1345 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1346 WRT_REG_DWORD(dmp_reg, 0xB0400000);
1347 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1348 fw->shadow_reg[4] = RD_REG_DWORD(dmp_reg);
1349
1350 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1351 WRT_REG_DWORD(dmp_reg, 0xB0500000);
1352 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1353 fw->shadow_reg[5] = RD_REG_DWORD(dmp_reg);
1354
1355 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xF0);
1356 WRT_REG_DWORD(dmp_reg, 0xB0600000);
1357 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xFC);
1358 fw->shadow_reg[6] = RD_REG_DWORD(dmp_reg);
1359
1360 /* Local memory controller registers. */
1361 iter_reg = fw->lmc_reg;
1362 WRT_REG_DWORD(&reg->iobase_addr, 0x3000);
1363 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1364 for (cnt = 0; cnt < 16; cnt++)
1365 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1366
1367 WRT_REG_DWORD(&reg->iobase_addr, 0x3010);
1368 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1369 for (cnt = 0; cnt < 16; cnt++)
1370 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1371
1372 WRT_REG_DWORD(&reg->iobase_addr, 0x3020);
1373 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1374 for (cnt = 0; cnt < 16; cnt++)
1375 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1376
1377 WRT_REG_DWORD(&reg->iobase_addr, 0x3030);
1378 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1379 for (cnt = 0; cnt < 16; cnt++)
1380 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1381
1382 WRT_REG_DWORD(&reg->iobase_addr, 0x3040);
1383 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1384 for (cnt = 0; cnt < 16; cnt++)
1385 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1386
1387 WRT_REG_DWORD(&reg->iobase_addr, 0x3050);
1388 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1389 for (cnt = 0; cnt < 16; cnt++)
1390 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1391
1392 WRT_REG_DWORD(&reg->iobase_addr, 0x3060);
1393 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1394 for (cnt = 0; cnt < 16; cnt++)
1395 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1396
1397 /* Fibre Protocol Module registers. */
1398 iter_reg = fw->fpm_hdw_reg;
1399 WRT_REG_DWORD(&reg->iobase_addr, 0x4000);
1400 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1401 for (cnt = 0; cnt < 16; cnt++)
1402 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1403
1404 WRT_REG_DWORD(&reg->iobase_addr, 0x4010);
1405 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1406 for (cnt = 0; cnt < 16; cnt++)
1407 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1408
1409 WRT_REG_DWORD(&reg->iobase_addr, 0x4020);
1410 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1411 for (cnt = 0; cnt < 16; cnt++)
1412 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1413
1414 WRT_REG_DWORD(&reg->iobase_addr, 0x4030);
1415 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1416 for (cnt = 0; cnt < 16; cnt++)
1417 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1418
1419 WRT_REG_DWORD(&reg->iobase_addr, 0x4040);
1420 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1421 for (cnt = 0; cnt < 16; cnt++)
1422 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1423
1424 WRT_REG_DWORD(&reg->iobase_addr, 0x4050);
1425 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1426 for (cnt = 0; cnt < 16; cnt++)
1427 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1428
1429 WRT_REG_DWORD(&reg->iobase_addr, 0x4060);
1430 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1431 for (cnt = 0; cnt < 16; cnt++)
1432 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1433
1434 WRT_REG_DWORD(&reg->iobase_addr, 0x4070);
1435 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1436 for (cnt = 0; cnt < 16; cnt++)
1437 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1438
1439 WRT_REG_DWORD(&reg->iobase_addr, 0x4080);
1440 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1441 for (cnt = 0; cnt < 16; cnt++)
1442 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1443
1444 WRT_REG_DWORD(&reg->iobase_addr, 0x4090);
1445 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1446 for (cnt = 0; cnt < 16; cnt++)
1447 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1448
1449 WRT_REG_DWORD(&reg->iobase_addr, 0x40A0);
1450 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1451 for (cnt = 0; cnt < 16; cnt++)
1452 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1453
1454 WRT_REG_DWORD(&reg->iobase_addr, 0x40B0);
1455 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1456 for (cnt = 0; cnt < 16; cnt++)
1457 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1458
1459 /* Frame Buffer registers. */
1460 iter_reg = fw->fb_hdw_reg;
1461 WRT_REG_DWORD(&reg->iobase_addr, 0x6000);
1462 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1463 for (cnt = 0; cnt < 16; cnt++)
1464 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1465
1466 WRT_REG_DWORD(&reg->iobase_addr, 0x6010);
1467 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1468 for (cnt = 0; cnt < 16; cnt++)
1469 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1470
1471 WRT_REG_DWORD(&reg->iobase_addr, 0x6020);
1472 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1473 for (cnt = 0; cnt < 16; cnt++)
1474 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1475
1476 WRT_REG_DWORD(&reg->iobase_addr, 0x6030);
1477 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1478 for (cnt = 0; cnt < 16; cnt++)
1479 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1480
1481 WRT_REG_DWORD(&reg->iobase_addr, 0x6040);
1482 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1483 for (cnt = 0; cnt < 16; cnt++)
1484 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1485
1486 WRT_REG_DWORD(&reg->iobase_addr, 0x6100);
1487 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1488 for (cnt = 0; cnt < 16; cnt++)
1489 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1490
1491 WRT_REG_DWORD(&reg->iobase_addr, 0x6130);
1492 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1493 for (cnt = 0; cnt < 16; cnt++)
1494 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1495
1496 WRT_REG_DWORD(&reg->iobase_addr, 0x6150);
1497 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1498 for (cnt = 0; cnt < 16; cnt++)
1499 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1500
1501 WRT_REG_DWORD(&reg->iobase_addr, 0x6170);
1502 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1503 for (cnt = 0; cnt < 16; cnt++)
1504 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1505
1506 WRT_REG_DWORD(&reg->iobase_addr, 0x6190);
1507 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1508 for (cnt = 0; cnt < 16; cnt++)
1509 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1510
1511 WRT_REG_DWORD(&reg->iobase_addr, 0x61B0);
1512 dmp_reg = (uint32_t __iomem *)((uint8_t __iomem *)reg + 0xC0);
1513 for (cnt = 0; cnt < 16; cnt++)
1514 *iter_reg++ = RD_REG_DWORD(dmp_reg++);
1515
1516 /* Reset RISC. */
1517 WRT_REG_DWORD(&reg->ctrl_status,
1518 CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
1519 for (cnt = 0; cnt < 30000; cnt++) {
1520 if ((RD_REG_DWORD(&reg->ctrl_status) &
1521 CSRX_DMA_ACTIVE) == 0)
1522 break;
1523
1524 udelay(10);
1525 }
1526
1527 WRT_REG_DWORD(&reg->ctrl_status,
1528 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
88c26663
AV		 1529 RD_REG_DWORD(&reg->ctrl_status);
1530
1531 /* Wait for firmware to complete NVRAM accesses. */
1532 udelay(5);
1533 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1534 for (cnt = 10000 ; cnt && mb[0]; cnt--) {
1535 udelay(5);
1536 mb[0] = (uint32_t) RD_REG_WORD(&reg->mailbox0);
1537 barrier();
1538 }
1539
6d9b61ed
AV		 1540 udelay(20);
1541 for (cnt = 0; cnt < 30000; cnt++) {
1542 if ((RD_REG_DWORD(&reg->ctrl_status) &
1543 CSRX_ISP_SOFT_RESET) == 0)
1544 break;
1545
1546 udelay(10);
1547 }
1548 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_RESET);
1549 RD_REG_DWORD(&reg->hccr); /* PCI Posting. */
1550 }
1551
1552 for (cnt = 30000; RD_REG_WORD(&reg->mailbox0) != 0 &&
1553 rval == QLA_SUCCESS; cnt--) {
1554 if (cnt)
1555 udelay(100);
1556 else
1557 rval = QLA_FUNCTION_TIMEOUT;
1558 }
1559
1560 /* Memory. */
1561 if (rval == QLA_SUCCESS) {
1562 /* Code RAM. */
1563 risc_address = 0x20000;
1564 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1565 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1566 }
1567 for (cnt = 0; cnt < sizeof(fw->code_ram) / 4 && rval == QLA_SUCCESS;
1568 cnt++, risc_address++) {
1569 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1570 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1571 RD_REG_WORD(&reg->mailbox8);
1572 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1573
1574 for (timer = 6000000; timer; timer--) {
1575 /* Check for pending interrupts. */
1576 stat = RD_REG_DWORD(&reg->host_status);
1577 if (stat & HSRX_RISC_INT) {
1578 stat &= 0xff;
1579
1580 if (stat == 0x1 || stat == 0x2 ||
1581 stat == 0x10 || stat == 0x11) {
1582 set_bit(MBX_INTERRUPT,
1583 &ha->mbx_cmd_flags);
1584
1585 mb[0] = RD_REG_WORD(&reg->mailbox0);
1586 mb[2] = RD_REG_WORD(&reg->mailbox2);
1587 mb[3] = RD_REG_WORD(&reg->mailbox3);
1588
1589 WRT_REG_DWORD(&reg->hccr,
1590 HCCRX_CLR_RISC_INT);
1591 RD_REG_DWORD(&reg->hccr);
1592 break;
1593 }
1594
1595 /* Clear this intr; it wasn't a mailbox intr */
1596 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1597 RD_REG_DWORD(&reg->hccr);
1598 }
1599 udelay(5);
1600 }
1601
1602 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1603 rval = mb[0] & MBS_MASK;
1604 fw->code_ram[cnt] = (mb[3] << 16) | mb[2];
1605 } else {
1606 rval = QLA_FUNCTION_FAILED;
1607 }
1608 }
1609
1610 if (rval == QLA_SUCCESS) {
1611 /* External Memory. */
1612 risc_address = 0x100000;
1613 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1614 WRT_REG_WORD(&reg->mailbox0, MBC_READ_RAM_EXTENDED);
1615 clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
1616 }
1617 for (cnt = 0; cnt < ext_mem_cnt && rval == QLA_SUCCESS;
1618 cnt++, risc_address++) {
1619 WRT_REG_WORD(&reg->mailbox1, LSW(risc_address));
1620 WRT_REG_WORD(&reg->mailbox8, MSW(risc_address));
1621 RD_REG_WORD(&reg->mailbox8);
1622 WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
1623
1624 for (timer = 6000000; timer; timer--) {
1625 /* Check for pending interrupts. */
1626 stat = RD_REG_DWORD(&reg->host_status);
1627 if (stat & HSRX_RISC_INT) {
1628 stat &= 0xff;
1629
1630 if (stat == 0x1 || stat == 0x2 ||
1631 stat == 0x10 || stat == 0x11) {
1632 set_bit(MBX_INTERRUPT,
1633 &ha->mbx_cmd_flags);
1634
1635 mb[0] = RD_REG_WORD(&reg->mailbox0);
1636 mb[2] = RD_REG_WORD(&reg->mailbox2);
1637 mb[3] = RD_REG_WORD(&reg->mailbox3);
1638
1639 WRT_REG_DWORD(&reg->hccr,
1640 HCCRX_CLR_RISC_INT);
1641 RD_REG_DWORD(&reg->hccr);
1642 break;
1643 }
1644
1645 /* Clear this intr; it wasn't a mailbox intr */
1646 WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
1647 RD_REG_DWORD(&reg->hccr);
1648 }
1649 udelay(5);
1650 }
1651
1652 if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) {
1653 rval = mb[0] & MBS_MASK;
1654 fw->ext_mem[cnt] = (mb[3] << 16) | mb[2];
1655 } else {
1656 rval = QLA_FUNCTION_FAILED;
1657 }
1658 }
1659
1660 if (rval != QLA_SUCCESS) {
1661 qla_printk(KERN_WARNING, ha,
1662 "Failed to dump firmware (%x)!!!\n", rval);
1663 ha->fw_dumped = 0;
1664
1665 } else {
1666 qla_printk(KERN_INFO, ha,
1667 "Firmware dump saved to temp buffer (%ld/%p).\n",
1668 ha->host_no, ha->fw_dump24);
1669 ha->fw_dumped = 1;
1670 }
1671
1672qla24xx_fw_dump_failed:
1673 if (!hardware_locked)
1674 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1675}
1676
1677void
1678qla24xx_ascii_fw_dump(scsi_qla_host_t *ha)
1679{
1680 uint32_t cnt;
1681 char *uiter;
1682 struct qla24xx_fw_dump *fw;
1683 uint32_t ext_mem_cnt;
1684
1685 uiter = ha->fw_dump_buffer;
1686 fw = ha->fw_dump24;
1687
1688 qla_uprintf(&uiter, "ISP FW Version %d.%02d.%02d Attributes %04x\n",
1689 ha->fw_major_version, ha->fw_minor_version,
1690 ha->fw_subminor_version, ha->fw_attributes);
1691
1692 qla_uprintf(&uiter, "\nHCCR Register\n%04x\n", fw->hccr);
1693
1694 qla_uprintf(&uiter, "\nHost Interface Registers");
1695 for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++) {
1696 if (cnt % 8 == 0)
1697 qla_uprintf(&uiter, "\n");
1698
1699 qla_uprintf(&uiter, "%08x ", fw->host_reg[cnt]);
1700 }
1701
1702 qla_uprintf(&uiter, "\n\nMailbox Registers");
1703 for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++) {
1704 if (cnt % 8 == 0)
1705 qla_uprintf(&uiter, "\n");
1706
1707 qla_uprintf(&uiter, "%08x ", fw->mailbox_reg[cnt]);
1708 }
1709
1710 qla_uprintf(&uiter, "\n\nXSEQ GP Registers");
1711 for (cnt = 0; cnt < sizeof(fw->xseq_gp_reg) / 4; cnt++) {
1712 if (cnt % 8 == 0)
1713 qla_uprintf(&uiter, "\n");
1714
1715 qla_uprintf(&uiter, "%08x ", fw->xseq_gp_reg[cnt]);
1716 }
1717
1718 qla_uprintf(&uiter, "\n\nXSEQ-0 Registers");
1719 for (cnt = 0; cnt < sizeof(fw->xseq_0_reg) / 4; cnt++) {
1720 if (cnt % 8 == 0)
1721 qla_uprintf(&uiter, "\n");
1722
1723 qla_uprintf(&uiter, "%08x ", fw->xseq_0_reg[cnt]);
1724 }
1725
1726 qla_uprintf(&uiter, "\n\nXSEQ-1 Registers");
1727 for (cnt = 0; cnt < sizeof(fw->xseq_1_reg) / 4; cnt++) {
1728 if (cnt % 8 == 0)
1729 qla_uprintf(&uiter, "\n");
1730
1731 qla_uprintf(&uiter, "%08x ", fw->xseq_1_reg[cnt]);
1732 }
1733
1734 qla_uprintf(&uiter, "\n\nRSEQ GP Registers");
1735 for (cnt = 0; cnt < sizeof(fw->rseq_gp_reg) / 4; cnt++) {
1736 if (cnt % 8 == 0)
1737 qla_uprintf(&uiter, "\n");
1738
1739 qla_uprintf(&uiter, "%08x ", fw->rseq_gp_reg[cnt]);
1740 }
1741
1742 qla_uprintf(&uiter, "\n\nRSEQ-0 Registers");
1743 for (cnt = 0; cnt < sizeof(fw->rseq_0_reg) / 4; cnt++) {
1744 if (cnt % 8 == 0)
1745 qla_uprintf(&uiter, "\n");
1746
1747 qla_uprintf(&uiter, "%08x ", fw->rseq_0_reg[cnt]);
1748 }
1749
1750 qla_uprintf(&uiter, "\n\nRSEQ-1 Registers");
1751 for (cnt = 0; cnt < sizeof(fw->rseq_1_reg) / 4; cnt++) {
1752 if (cnt % 8 == 0)
1753 qla_uprintf(&uiter, "\n");
1754
1755 qla_uprintf(&uiter, "%08x ", fw->rseq_1_reg[cnt]);
1756 }
1757
1758 qla_uprintf(&uiter, "\n\nRSEQ-2 Registers");
1759 for (cnt = 0; cnt < sizeof(fw->rseq_2_reg) / 4; cnt++) {
1760 if (cnt % 8 == 0)
1761 qla_uprintf(&uiter, "\n");
1762
1763 qla_uprintf(&uiter, "%08x ", fw->rseq_2_reg[cnt]);
1764 }
1765
1766 qla_uprintf(&uiter, "\n\nCommand DMA Registers");
1767 for (cnt = 0; cnt < sizeof(fw->cmd_dma_reg) / 4; cnt++) {
1768 if (cnt % 8 == 0)
1769 qla_uprintf(&uiter, "\n");
1770
1771 qla_uprintf(&uiter, "%08x ", fw->cmd_dma_reg[cnt]);
1772 }
1773
1774 qla_uprintf(&uiter, "\n\nRequest0 Queue DMA Channel Registers");
1775 for (cnt = 0; cnt < sizeof(fw->req0_dma_reg) / 4; cnt++) {
1776 if (cnt % 8 == 0)
1777 qla_uprintf(&uiter, "\n");
1778
1779 qla_uprintf(&uiter, "%08x ", fw->req0_dma_reg[cnt]);
1780 }
1781
1782 qla_uprintf(&uiter, "\n\nResponse0 Queue DMA Channel Registers");
1783 for (cnt = 0; cnt < sizeof(fw->resp0_dma_reg) / 4; cnt++) {
1784 if (cnt % 8 == 0)
1785 qla_uprintf(&uiter, "\n");
1786
1787 qla_uprintf(&uiter, "%08x ", fw->resp0_dma_reg[cnt]);
1788 }
1789
1790 qla_uprintf(&uiter, "\n\nRequest1 Queue DMA Channel Registers");
1791 for (cnt = 0; cnt < sizeof(fw->req1_dma_reg) / 4; cnt++) {
1792 if (cnt % 8 == 0)
1793 qla_uprintf(&uiter, "\n");
1794
1795 qla_uprintf(&uiter, "%08x ", fw->req1_dma_reg[cnt]);
1796 }
1797
1798 qla_uprintf(&uiter, "\n\nXMT0 Data DMA Registers");
1799 for (cnt = 0; cnt < sizeof(fw->xmt0_dma_reg) / 4; cnt++) {
1800 if (cnt % 8 == 0)
1801 qla_uprintf(&uiter, "\n");
1802
1803 qla_uprintf(&uiter, "%08x ", fw->xmt0_dma_reg[cnt]);
1804 }
1805
1806 qla_uprintf(&uiter, "\n\nXMT1 Data DMA Registers");
1807 for (cnt = 0; cnt < sizeof(fw->xmt1_dma_reg) / 4; cnt++) {
1808 if (cnt % 8 == 0)
1809 qla_uprintf(&uiter, "\n");
1810
1811 qla_uprintf(&uiter, "%08x ", fw->xmt1_dma_reg[cnt]);
1812 }
1813
1814 qla_uprintf(&uiter, "\n\nXMT2 Data DMA Registers");
1815 for (cnt = 0; cnt < sizeof(fw->xmt2_dma_reg) / 4; cnt++) {
1816 if (cnt % 8 == 0)
1817 qla_uprintf(&uiter, "\n");
1818
1819 qla_uprintf(&uiter, "%08x ", fw->xmt2_dma_reg[cnt]);
1820 }
1821
1822 qla_uprintf(&uiter, "\n\nXMT3 Data DMA Registers");
1823 for (cnt = 0; cnt < sizeof(fw->xmt3_dma_reg) / 4; cnt++) {
1824 if (cnt % 8 == 0)
1825 qla_uprintf(&uiter, "\n");
1826
1827 qla_uprintf(&uiter, "%08x ", fw->xmt3_dma_reg[cnt]);
1828 }
1829
1830 qla_uprintf(&uiter, "\n\nXMT4 Data DMA Registers");
1831 for (cnt = 0; cnt < sizeof(fw->xmt4_dma_reg) / 4; cnt++) {
1832 if (cnt % 8 == 0)
1833 qla_uprintf(&uiter, "\n");
1834
1835 qla_uprintf(&uiter, "%08x ", fw->xmt4_dma_reg[cnt]);
1836 }
1837
1838 qla_uprintf(&uiter, "\n\nXMT Data DMA Common Registers");
1839 for (cnt = 0; cnt < sizeof(fw->xmt_data_dma_reg) / 4; cnt++) {
1840 if (cnt % 8 == 0)
1841 qla_uprintf(&uiter, "\n");
1842
1843 qla_uprintf(&uiter, "%08x ", fw->xmt_data_dma_reg[cnt]);
1844 }
1845
1846 qla_uprintf(&uiter, "\n\nRCV Thread 0 Data DMA Registers");
1847 for (cnt = 0; cnt < sizeof(fw->rcvt0_data_dma_reg) / 4; cnt++) {
1848 if (cnt % 8 == 0)
1849 qla_uprintf(&uiter, "\n");
1850
1851 qla_uprintf(&uiter, "%08x ", fw->rcvt0_data_dma_reg[cnt]);
1852 }
1853
1854 qla_uprintf(&uiter, "\n\nRCV Thread 1 Data DMA Registers");
1855 for (cnt = 0; cnt < sizeof(fw->rcvt1_data_dma_reg) / 4; cnt++) {
1856 if (cnt % 8 == 0)
1857 qla_uprintf(&uiter, "\n");
1858
1859 qla_uprintf(&uiter, "%08x ", fw->rcvt1_data_dma_reg[cnt]);
1860 }
1861
1862 qla_uprintf(&uiter, "\n\nRISC GP Registers");
1863 for (cnt = 0; cnt < sizeof(fw->risc_gp_reg) / 4; cnt++) {
1864 if (cnt % 8 == 0)
1865 qla_uprintf(&uiter, "\n");
1866
1867 qla_uprintf(&uiter, "%08x ", fw->risc_gp_reg[cnt]);
1868 }
1869
1870 qla_uprintf(&uiter, "\n\nShadow Registers");
1871 for (cnt = 0; cnt < sizeof(fw->shadow_reg) / 4; cnt++) {
1872 if (cnt % 8 == 0)
1873 qla_uprintf(&uiter, "\n");
1874
1875 qla_uprintf(&uiter, "%08x ", fw->shadow_reg[cnt]);
1876 }
1877
1878 qla_uprintf(&uiter, "\n\nLMC Registers");
1879 for (cnt = 0; cnt < sizeof(fw->lmc_reg) / 4; cnt++) {
1880 if (cnt % 8 == 0)
1881 qla_uprintf(&uiter, "\n");
1882
1883 qla_uprintf(&uiter, "%08x ", fw->lmc_reg[cnt]);
1884 }
1885
1886 qla_uprintf(&uiter, "\n\nFPM Hardware Registers");
1887 for (cnt = 0; cnt < sizeof(fw->fpm_hdw_reg) / 4; cnt++) {
1888 if (cnt % 8 == 0)
1889 qla_uprintf(&uiter, "\n");
1890
1891 qla_uprintf(&uiter, "%08x ", fw->fpm_hdw_reg[cnt]);
1892 }
1893
1894 qla_uprintf(&uiter, "\n\nFB Hardware Registers");
1895 for (cnt = 0; cnt < sizeof(fw->fb_hdw_reg) / 4; cnt++) {
1896 if (cnt % 8 == 0)
1897 qla_uprintf(&uiter, "\n");
1898
1899 qla_uprintf(&uiter, "%08x ", fw->fb_hdw_reg[cnt]);
1900 }
1901
1902 qla_uprintf(&uiter, "\n\nCode RAM");
1903 for (cnt = 0; cnt < sizeof (fw->code_ram) / 4; cnt++) {
1904 if (cnt % 8 == 0) {
1905 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x20000);
1906 }
1907 qla_uprintf(&uiter, "%08x ", fw->code_ram[cnt]);
1908 }
1909
1910 qla_uprintf(&uiter, "\n\nExternal Memory");
1911 ext_mem_cnt = ha->fw_memory_size - 0x100000 + 1;
1912 for (cnt = 0; cnt < ext_mem_cnt; cnt++) {
1913 if (cnt % 8 == 0) {
1914 qla_uprintf(&uiter, "\n%08x: ", cnt + 0x100000);
1915 }
1916 qla_uprintf(&uiter, "%08x ", fw->ext_mem[cnt]);
1917 }
1918
1919 qla_uprintf(&uiter, "\n[<==END] ISP Debug Dump");
1920}
1921
1da177e4
LT		 1922
1923/****************************************************************************/
1924/* Driver Debug Functions. */
1925/****************************************************************************/
1926
fa2a1ce5
AV		 1927void
1928qla2x00_dump_regs(scsi_qla_host_t *ha)
1da177e4 1929{
3d71644c 1930 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1da177e4
LT		 1931
1932 printk("Mailbox registers:\n");
1933 printk("scsi(%ld): mbox 0 0x%04x \n",
1934 ha->host_no, RD_MAILBOX_REG(ha, reg, 0));
1935 printk("scsi(%ld): mbox 1 0x%04x \n",
1936 ha->host_no, RD_MAILBOX_REG(ha, reg, 1));
1937 printk("scsi(%ld): mbox 2 0x%04x \n",
1938 ha->host_no, RD_MAILBOX_REG(ha, reg, 2));
1939 printk("scsi(%ld): mbox 3 0x%04x \n",
1940 ha->host_no, RD_MAILBOX_REG(ha, reg, 3));
1941 printk("scsi(%ld): mbox 4 0x%04x \n",
1942 ha->host_no, RD_MAILBOX_REG(ha, reg, 4));
1943 printk("scsi(%ld): mbox 5 0x%04x \n",
1944 ha->host_no, RD_MAILBOX_REG(ha, reg, 5));
1945}
1946
1947
1948void
fa2a1ce5 1949qla2x00_dump_buffer(uint8_t * b, uint32_t size)
1da177e4
LT		 1950{
1951 uint32_t cnt;
1952 uint8_t c;
1953
1954 printk(" 0 1 2 3 4 5 6 7 8 9 "
1955 "Ah Bh Ch Dh Eh Fh\n");
1956 printk("----------------------------------------"
1957 "----------------------\n");
1958
1959 for (cnt = 0; cnt < size;) {
1960 c = *b++;
1961 printk("%02x",(uint32_t) c);
1962 cnt++;
1963 if (!(cnt % 16))
1964 printk("\n");
1965 else
1966 printk(" ");
1967 }
1968 if (cnt % 16)
1969 printk("\n");
1970}
1971
1972/**************************************************************************
1973 * qla2x00_print_scsi_cmd
1974 * Dumps out info about the scsi cmd and srb.
fa2a1ce5 1975 * Input
1da177e4
LT		 1976 * cmd : struct scsi_cmnd
1977 **************************************************************************/
1978void
fa2a1ce5 1979qla2x00_print_scsi_cmd(struct scsi_cmnd * cmd)
1da177e4
LT		 1980{
1981 int i;
1982 struct scsi_qla_host *ha;
1983 srb_t *sp;
1984
1985 ha = (struct scsi_qla_host *)cmd->device->host->hostdata;
1986
1987 sp = (srb_t *) cmd->SCp.ptr;
1988 printk("SCSI Command @=0x%p, Handle=0x%p\n", cmd, cmd->host_scribble);
1989 printk(" chan=0x%02x, target=0x%02x, lun=0x%02x, cmd_len=0x%02x\n",
1990 cmd->device->channel, cmd->device->id, cmd->device->lun,
1991 cmd->cmd_len);
1992 printk(" CDB: ");
1993 for (i = 0; i < cmd->cmd_len; i++) {
1994 printk("0x%02x ", cmd->cmnd[i]);
1995 }
c6295cdf
TH		 1996 printk("\n seg_cnt=%d, allowed=%d, retries=%d\n",
1997 cmd->use_sg, cmd->allowed, cmd->retries);
1da177e4
LT		 1998 printk(" request buffer=0x%p, request buffer len=0x%x\n",
1999 cmd->request_buffer, cmd->request_bufflen);
2000 printk(" tag=%d, transfersize=0x%x\n",
2001 cmd->tag, cmd->transfersize);
fa2a1ce5 2002 printk(" serial_number=%lx, SP=%p\n", cmd->serial_number, sp);
1da177e4
LT		 2003 printk(" data direction=%d\n", cmd->sc_data_direction);
2004
2005 if (!sp)
2006 return;
2007
2008 printk(" sp flags=0x%x\n", sp->flags);
354d6b21 2009 printk(" state=%d\n", sp->state);
1da177e4
LT		 2010}
2011
6d9b61ed
AV		 2012void
2013qla2x00_dump_pkt(void *pkt)
2014{
2015 uint32_t i;
2016 uint8_t *data = (uint8_t *) pkt;
2017
2018 for (i = 0; i < 64; i++) {
2019 if (!(i % 4))
2020 printk("\n%02x: ", i);
2021
2022 printk("%02x ", data[i]);
2023 }
2024 printk("\n");
2025}
2026
1da177e4
LT		 2027#if defined(QL_DEBUG_ROUTINES)
2028/*
2029 * qla2x00_formatted_dump_buffer
2030 * Prints string plus buffer.
2031 *
2032 * Input:
2033 * string = Null terminated string (no newline at end).
2034 * buffer = buffer address.
2035 * wd_size = word size 8, 16, 32 or 64 bits
2036 * count = number of words.
2037 */
2038void
fa2a1ce5
AV		 2039qla2x00_formatted_dump_buffer(char *string, uint8_t * buffer,
2040 uint8_t wd_size, uint32_t count)
1da177e4
LT		 2041{
2042 uint32_t cnt;
2043 uint16_t *buf16;
2044 uint32_t *buf32;
2045
2046 if (strcmp(string, "") != 0)
2047 printk("%s\n",string);
2048
2049 switch (wd_size) {
2050 case 8:
2051 printk(" 0 1 2 3 4 5 6 7 "
2052 "8 9 Ah Bh Ch Dh Eh Fh\n");
2053 printk("-----------------------------------------"
2054 "-------------------------------------\n");
2055
2056 for (cnt = 1; cnt <= count; cnt++, buffer++) {
2057 printk("%02x",*buffer);
2058 if (cnt % 16 == 0)
2059 printk("\n");
2060 else
2061 printk(" ");
2062 }
2063 if (cnt % 16 != 0)
2064 printk("\n");
2065 break;
2066 case 16:
2067 printk(" 0 2 4 6 8 Ah "
2068 " Ch Eh\n");
2069 printk("-----------------------------------------"
2070 "-------------\n");
2071
2072 buf16 = (uint16_t *) buffer;
2073 for (cnt = 1; cnt <= count; cnt++, buf16++) {
2074 printk("%4x",*buf16);
2075
2076 if (cnt % 8 == 0)
2077 printk("\n");
2078 else if (*buf16 < 10)
2079 printk(" ");
2080 else
2081 printk(" ");
2082 }
2083 if (cnt % 8 != 0)
2084 printk("\n");
2085 break;
2086 case 32:
2087 printk(" 0 4 8 Ch\n");
2088 printk("------------------------------------------\n");
2089
2090 buf32 = (uint32_t *) buffer;
2091 for (cnt = 1; cnt <= count; cnt++, buf32++) {
2092 printk("%8x", *buf32);
2093
2094 if (cnt % 4 == 0)
2095 printk("\n");
2096 else if (*buf32 < 10)
2097 printk(" ");
2098 else
2099 printk(" ");
2100 }
2101 if (cnt % 4 != 0)
2102 printk("\n");
2103 break;
2104 default:
2105 break;
2106 }
2107}
2108#endif
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