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[net-next-2.6.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5
BS		 1/*
2 *
3 * Linux MegaRAID driver for SAS based RAID controllers
4 *
f28cd7cf 5 * Copyright (c) 2003-2005 LSI Corporation.
c4a3e0a5
BS		 6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 *
12 * FILE : megaraid_sas.h
13 */
14
15#ifndef LSI_MEGARAID_SAS_H
16#define LSI_MEGARAID_SAS_H
17
a69b74d3 18/*
c4a3e0a5
BS		 19 * MegaRAID SAS Driver meta data
20 */
e340c353
YB		 21#define MEGASAS_VERSION "00.00.04.31-rc1"
22#define MEGASAS_RELDATE "May 3, 2010"
23#define MEGASAS_EXT_VERSION "Mon. May 3, 11:41:51 PST 2010"
0e98936c
SP		 24
25/*
26 * Device IDs
27 */
28#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 29#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 30#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 31#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
32#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 33#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
34#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
0e98936c 35
c4a3e0a5
BS		 36/*
37 * =====================================
38 * MegaRAID SAS MFI firmware definitions
39 * =====================================
40 */
41
42/*
43 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
44 * protocol between the software and firmware. Commands are issued using
45 * "message frames"
46 */
47
a69b74d3 48/*
c4a3e0a5
BS		 49 * FW posts its state in upper 4 bits of outbound_msg_0 register
50 */
51#define MFI_STATE_MASK 0xF0000000
52#define MFI_STATE_UNDEFINED 0x00000000
53#define MFI_STATE_BB_INIT 0x10000000
54#define MFI_STATE_FW_INIT 0x40000000
55#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
56#define MFI_STATE_FW_INIT_2 0x70000000
57#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 58#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 59#define MFI_STATE_FLUSH_CACHE 0xA0000000
60#define MFI_STATE_READY 0xB0000000
61#define MFI_STATE_OPERATIONAL 0xC0000000
62#define MFI_STATE_FAULT 0xF0000000
39a98554 63#define MFI_RESET_REQUIRED 0x00000001
c4a3e0a5
BS		 64
65#define MEGAMFI_FRAME_SIZE 64
66
a69b74d3 67/*
c4a3e0a5
BS		 68 * During FW init, clear pending cmds & reset state using inbound_msg_0
69 *
70 * ABORT : Abort all pending cmds
71 * READY : Move from OPERATIONAL to READY state; discard queue info
72 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
73 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 74 * HOTPLUG : Resume from Hotplug
75 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 76 */
39a98554 77#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
78#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
79#define DIAG_WRITE_ENABLE (0x00000080)
80#define DIAG_RESET_ADAPTER (0x00000004)
81
82#define MFI_ADP_RESET 0x00000040
e3bbff9f 83#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 84#define MFI_INIT_READY 0x00000002
85#define MFI_INIT_MFIMODE 0x00000004
86#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 87#define MFI_INIT_HOTPLUG 0x00000010
88#define MFI_STOP_ADP 0x00000020
89#define MFI_RESET_FLAGS MFI_INIT_READY| \
90 MFI_INIT_MFIMODE| \
91 MFI_INIT_ABORT
c4a3e0a5 92
a69b74d3 93/*
c4a3e0a5
BS		 94 * MFI frame flags
95 */
96#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
97#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
98#define MFI_FRAME_SGL32 0x0000
99#define MFI_FRAME_SGL64 0x0002
100#define MFI_FRAME_SENSE32 0x0000
101#define MFI_FRAME_SENSE64 0x0004
102#define MFI_FRAME_DIR_NONE 0x0000
103#define MFI_FRAME_DIR_WRITE 0x0008
104#define MFI_FRAME_DIR_READ 0x0010
105#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 106#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 107
a69b74d3 108/*
c4a3e0a5
BS		 109 * Definition for cmd_status
110 */
111#define MFI_CMD_STATUS_POLL_MODE 0xFF
112
a69b74d3 113/*
c4a3e0a5
BS		 114 * MFI command opcodes
115 */
116#define MFI_CMD_INIT 0x00
117#define MFI_CMD_LD_READ 0x01
118#define MFI_CMD_LD_WRITE 0x02
119#define MFI_CMD_LD_SCSI_IO 0x03
120#define MFI_CMD_PD_SCSI_IO 0x04
121#define MFI_CMD_DCMD 0x05
122#define MFI_CMD_ABORT 0x06
123#define MFI_CMD_SMP 0x07
124#define MFI_CMD_STP 0x08
125
126#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 127#define MR_DCMD_LD_GET_LIST 0x03010000
c4a3e0a5
BS		 128
129#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
130#define MR_FLUSH_CTRL_CACHE 0x01
131#define MR_FLUSH_DISK_CACHE 0x02
132
133#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 134#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 135#define MR_ENABLE_DRIVE_SPINDOWN 0x01
136
137#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
138#define MR_DCMD_CTRL_EVENT_GET 0x01040300
139#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
140#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
141
142#define MR_DCMD_CLUSTER 0x08000000
143#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
144#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 145#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 146
a69b74d3 147/*
c4a3e0a5
BS		 148 * MFI command completion codes
149 */
150enum MFI_STAT {
151 MFI_STAT_OK = 0x00,
152 MFI_STAT_INVALID_CMD = 0x01,
153 MFI_STAT_INVALID_DCMD = 0x02,
154 MFI_STAT_INVALID_PARAMETER = 0x03,
155 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
156 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
157 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
158 MFI_STAT_APP_IN_USE = 0x07,
159 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
160 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
161 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
162 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
163 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
164 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
165 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
166 MFI_STAT_FLASH_BUSY = 0x0f,
167 MFI_STAT_FLASH_ERROR = 0x10,
168 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
169 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
170 MFI_STAT_FLASH_NOT_OPEN = 0x13,
171 MFI_STAT_FLASH_NOT_STARTED = 0x14,
172 MFI_STAT_FLUSH_FAILED = 0x15,
173 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
174 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
175 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
176 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
177 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
178 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
179 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
180 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
181 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
182 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
183 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
184 MFI_STAT_MFC_HW_ERROR = 0x21,
185 MFI_STAT_NO_HW_PRESENT = 0x22,
186 MFI_STAT_NOT_FOUND = 0x23,
187 MFI_STAT_NOT_IN_ENCL = 0x24,
188 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
189 MFI_STAT_PD_TYPE_WRONG = 0x26,
190 MFI_STAT_PR_DISABLED = 0x27,
191 MFI_STAT_ROW_INDEX_INVALID = 0x28,
192 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
193 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
194 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
195 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
196 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
197 MFI_STAT_SCSI_IO_FAILED = 0x2e,
198 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
199 MFI_STAT_SHUTDOWN_FAILED = 0x30,
200 MFI_STAT_TIME_NOT_SET = 0x31,
201 MFI_STAT_WRONG_STATE = 0x32,
202 MFI_STAT_LD_OFFLINE = 0x33,
203 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
204 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
205 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
206 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
207 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
208
209 MFI_STAT_INVALID_STATUS = 0xFF
210};
211
212/*
213 * Number of mailbox bytes in DCMD message frame
214 */
215#define MFI_MBOX_SIZE 12
216
217enum MR_EVT_CLASS {
218
219 MR_EVT_CLASS_DEBUG = -2,
220 MR_EVT_CLASS_PROGRESS = -1,
221 MR_EVT_CLASS_INFO = 0,
222 MR_EVT_CLASS_WARNING = 1,
223 MR_EVT_CLASS_CRITICAL = 2,
224 MR_EVT_CLASS_FATAL = 3,
225 MR_EVT_CLASS_DEAD = 4,
226
227};
228
229enum MR_EVT_LOCALE {
230
231 MR_EVT_LOCALE_LD = 0x0001,
232 MR_EVT_LOCALE_PD = 0x0002,
233 MR_EVT_LOCALE_ENCL = 0x0004,
234 MR_EVT_LOCALE_BBU = 0x0008,
235 MR_EVT_LOCALE_SAS = 0x0010,
236 MR_EVT_LOCALE_CTRL = 0x0020,
237 MR_EVT_LOCALE_CONFIG = 0x0040,
238 MR_EVT_LOCALE_CLUSTER = 0x0080,
239 MR_EVT_LOCALE_ALL = 0xffff,
240
241};
242
243enum MR_EVT_ARGS {
244
245 MR_EVT_ARGS_NONE,
246 MR_EVT_ARGS_CDB_SENSE,
247 MR_EVT_ARGS_LD,
248 MR_EVT_ARGS_LD_COUNT,
249 MR_EVT_ARGS_LD_LBA,
250 MR_EVT_ARGS_LD_OWNER,
251 MR_EVT_ARGS_LD_LBA_PD_LBA,
252 MR_EVT_ARGS_LD_PROG,
253 MR_EVT_ARGS_LD_STATE,
254 MR_EVT_ARGS_LD_STRIP,
255 MR_EVT_ARGS_PD,
256 MR_EVT_ARGS_PD_ERR,
257 MR_EVT_ARGS_PD_LBA,
258 MR_EVT_ARGS_PD_LBA_LD,
259 MR_EVT_ARGS_PD_PROG,
260 MR_EVT_ARGS_PD_STATE,
261 MR_EVT_ARGS_PCI,
262 MR_EVT_ARGS_RATE,
263 MR_EVT_ARGS_STR,
264 MR_EVT_ARGS_TIME,
265 MR_EVT_ARGS_ECC,
81e403ce
YB		 266 MR_EVT_ARGS_LD_PROP,
267 MR_EVT_ARGS_PD_SPARE,
268 MR_EVT_ARGS_PD_INDEX,
269 MR_EVT_ARGS_DIAG_PASS,
270 MR_EVT_ARGS_DIAG_FAIL,
271 MR_EVT_ARGS_PD_LBA_LBA,
272 MR_EVT_ARGS_PORT_PHY,
273 MR_EVT_ARGS_PD_MISSING,
274 MR_EVT_ARGS_PD_ADDRESS,
275 MR_EVT_ARGS_BITMAP,
276 MR_EVT_ARGS_CONNECTOR,
277 MR_EVT_ARGS_PD_PD,
278 MR_EVT_ARGS_PD_FRU,
279 MR_EVT_ARGS_PD_PATHINFO,
280 MR_EVT_ARGS_PD_POWER_STATE,
281 MR_EVT_ARGS_GENERIC,
282};
c4a3e0a5 283
81e403ce
YB		 284/*
285 * define constants for device list query options
286 */
287enum MR_PD_QUERY_TYPE {
288 MR_PD_QUERY_TYPE_ALL = 0,
289 MR_PD_QUERY_TYPE_STATE = 1,
290 MR_PD_QUERY_TYPE_POWER_STATE = 2,
291 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
292 MR_PD_QUERY_TYPE_SPEED = 4,
293 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 294};
295
7e8a75f4
YB		 296#define MR_EVT_CFG_CLEARED 0x0004
297#define MR_EVT_LD_STATE_CHANGE 0x0051
298#define MR_EVT_PD_INSERTED 0x005b
299#define MR_EVT_PD_REMOVED 0x0070
300#define MR_EVT_LD_CREATED 0x008a
301#define MR_EVT_LD_DELETED 0x008b
302#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
303#define MR_EVT_LD_OFFLINE 0x00fc
304#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
305#define MAX_LOGICAL_DRIVES 64
306
81e403ce
YB		 307enum MR_PD_STATE {
308 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
309 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
310 MR_PD_STATE_HOT_SPARE = 0x02,
311 MR_PD_STATE_OFFLINE = 0x10,
312 MR_PD_STATE_FAILED = 0x11,
313 MR_PD_STATE_REBUILD = 0x14,
314 MR_PD_STATE_ONLINE = 0x18,
315 MR_PD_STATE_COPYBACK = 0x20,
316 MR_PD_STATE_SYSTEM = 0x40,
317 };
318
319
320 /*
321 * defines the physical drive address structure
322 */
323struct MR_PD_ADDRESS {
324 u16 deviceId;
325 u16 enclDeviceId;
326
327 union {
328 struct {
329 u8 enclIndex;
330 u8 slotNumber;
331 } mrPdAddress;
332 struct {
333 u8 enclPosition;
334 u8 enclConnectorIndex;
335 } mrEnclAddress;
336 };
337 u8 scsiDevType;
338 union {
339 u8 connectedPortBitmap;
340 u8 connectedPortNumbers;
341 };
342 u64 sasAddr[2];
343} __packed;
344
345/*
346 * defines the physical drive list structure
347 */
348struct MR_PD_LIST {
349 u32 size;
350 u32 count;
351 struct MR_PD_ADDRESS addr[1];
352} __packed;
353
354struct megasas_pd_list {
355 u16 tid;
356 u8 driveType;
357 u8 driveState;
358} __packed;
359
bdc6fb8d
YB		 360 /*
361 * defines the logical drive reference structure
362 */
363union MR_LD_REF {
364 struct {
365 u8 targetId;
366 u8 reserved;
367 u16 seqNum;
368 };
369 u32 ref;
370} __packed;
371
372/*
373 * defines the logical drive list structure
374 */
375struct MR_LD_LIST {
376 u32 ldCount;
377 u32 reserved;
378 struct {
379 union MR_LD_REF ref;
380 u8 state;
381 u8 reserved[3];
382 u64 size;
383 } ldList[MAX_LOGICAL_DRIVES];
384} __packed;
385
c4a3e0a5
BS		 386/*
387 * SAS controller properties
388 */
389struct megasas_ctrl_prop {
390
391 u16 seq_num;
392 u16 pred_fail_poll_interval;
393 u16 intr_throttle_count;
394 u16 intr_throttle_timeouts;
395 u8 rebuild_rate;
396 u8 patrol_read_rate;
397 u8 bgi_rate;
398 u8 cc_rate;
399 u8 recon_rate;
400 u8 cache_flush_interval;
401 u8 spinup_drv_count;
402 u8 spinup_delay;
403 u8 cluster_enable;
404 u8 coercion_mode;
405 u8 alarm_enable;
406 u8 disable_auto_rebuild;
407 u8 disable_battery_warn;
408 u8 ecc_bucket_size;
409 u16 ecc_bucket_leak_rate;
410 u8 restore_hotspare_on_insertion;
411 u8 expose_encl_devices;
39a98554 412 u8 maintainPdFailHistory;
413 u8 disallowHostRequestReordering;
414 u8 abortCCOnError;
415 u8 loadBalanceMode;
416 u8 disableAutoDetectBackplane;
417
418 u8 snapVDSpace;
419
420 /*
421 * Add properties that can be controlled by
422 * a bit in the following structure.
423 */
c4a3e0a5 424
39a98554 425 struct {
426 u32 copyBackDisabled : 1;
427 u32 SMARTerEnabled : 1;
428 u32 prCorrectUnconfiguredAreas : 1;
429 u32 useFdeOnly : 1;
430 u32 disableNCQ : 1;
431 u32 SSDSMARTerEnabled : 1;
432 u32 SSDPatrolReadEnabled : 1;
433 u32 enableSpinDownUnconfigured : 1;
434 u32 autoEnhancedImport : 1;
435 u32 enableSecretKeyControl : 1;
436 u32 disableOnlineCtrlReset : 1;
437 u32 allowBootWithPinnedCache : 1;
438 u32 disableSpinDownHS : 1;
439 u32 enableJBOD : 1;
440 u32 reserved :18;
441 } OnOffProperties;
442 u8 autoSnapVDSpace;
443 u8 viewSpace;
444 u16 spinDownTime;
445 u8 reserved[24];
81e403ce 446} __packed;
c4a3e0a5
BS		 447
448/*
449 * SAS controller information
450 */
451struct megasas_ctrl_info {
452
453 /*
454 * PCI device information
455 */
456 struct {
457
458 u16 vendor_id;
459 u16 device_id;
460 u16 sub_vendor_id;
461 u16 sub_device_id;
462 u8 reserved[24];
463
464 } __attribute__ ((packed)) pci;
465
466 /*
467 * Host interface information
468 */
469 struct {
470
471 u8 PCIX:1;
472 u8 PCIE:1;
473 u8 iSCSI:1;
474 u8 SAS_3G:1;
475 u8 reserved_0:4;
476 u8 reserved_1[6];
477 u8 port_count;
478 u64 port_addr[8];
479
480 } __attribute__ ((packed)) host_interface;
481
482 /*
483 * Device (backend) interface information
484 */
485 struct {
486
487 u8 SPI:1;
488 u8 SAS_3G:1;
489 u8 SATA_1_5G:1;
490 u8 SATA_3G:1;
491 u8 reserved_0:4;
492 u8 reserved_1[6];
493 u8 port_count;
494 u64 port_addr[8];
495
496 } __attribute__ ((packed)) device_interface;
497
498 /*
499 * List of components residing in flash. All str are null terminated
500 */
501 u32 image_check_word;
502 u32 image_component_count;
503
504 struct {
505
506 char name[8];
507 char version[32];
508 char build_date[16];
509 char built_time[16];
510
511 } __attribute__ ((packed)) image_component[8];
512
513 /*
514 * List of flash components that have been flashed on the card, but
515 * are not in use, pending reset of the adapter. This list will be
516 * empty if a flash operation has not occurred. All stings are null
517 * terminated
518 */
519 u32 pending_image_component_count;
520
521 struct {
522
523 char name[8];
524 char version[32];
525 char build_date[16];
526 char build_time[16];
527
528 } __attribute__ ((packed)) pending_image_component[8];
529
530 u8 max_arms;
531 u8 max_spans;
532 u8 max_arrays;
533 u8 max_lds;
534
535 char product_name[80];
536 char serial_no[32];
537
538 /*
539 * Other physical/controller/operation information. Indicates the
540 * presence of the hardware
541 */
542 struct {
543
544 u32 bbu:1;
545 u32 alarm:1;
546 u32 nvram:1;
547 u32 uart:1;
548 u32 reserved:28;
549
550 } __attribute__ ((packed)) hw_present;
551
552 u32 current_fw_time;
553
554 /*
555 * Maximum data transfer sizes
556 */
557 u16 max_concurrent_cmds;
558 u16 max_sge_count;
559 u32 max_request_size;
560
561 /*
562 * Logical and physical device counts
563 */
564 u16 ld_present_count;
565 u16 ld_degraded_count;
566 u16 ld_offline_count;
567
568 u16 pd_present_count;
569 u16 pd_disk_present_count;
570 u16 pd_disk_pred_failure_count;
571 u16 pd_disk_failed_count;
572
573 /*
574 * Memory size information
575 */
576 u16 nvram_size;
577 u16 memory_size;
578 u16 flash_size;
579
580 /*
581 * Error counters
582 */
583 u16 mem_correctable_error_count;
584 u16 mem_uncorrectable_error_count;
585
586 /*
587 * Cluster information
588 */
589 u8 cluster_permitted;
590 u8 cluster_active;
591
592 /*
593 * Additional max data transfer sizes
594 */
595 u16 max_strips_per_io;
596
597 /*
598 * Controller capabilities structures
599 */
600 struct {
601
602 u32 raid_level_0:1;
603 u32 raid_level_1:1;
604 u32 raid_level_5:1;
605 u32 raid_level_1E:1;
606 u32 raid_level_6:1;
607 u32 reserved:27;
608
609 } __attribute__ ((packed)) raid_levels;
610
611 struct {
612
613 u32 rbld_rate:1;
614 u32 cc_rate:1;
615 u32 bgi_rate:1;
616 u32 recon_rate:1;
617 u32 patrol_rate:1;
618 u32 alarm_control:1;
619 u32 cluster_supported:1;
620 u32 bbu:1;
621 u32 spanning_allowed:1;
622 u32 dedicated_hotspares:1;
623 u32 revertible_hotspares:1;
624 u32 foreign_config_import:1;
625 u32 self_diagnostic:1;
626 u32 mixed_redundancy_arr:1;
627 u32 global_hot_spares:1;
628 u32 reserved:17;
629
630 } __attribute__ ((packed)) adapter_operations;
631
632 struct {
633
634 u32 read_policy:1;
635 u32 write_policy:1;
636 u32 io_policy:1;
637 u32 access_policy:1;
638 u32 disk_cache_policy:1;
639 u32 reserved:27;
640
641 } __attribute__ ((packed)) ld_operations;
642
643 struct {
644
645 u8 min;
646 u8 max;
647 u8 reserved[2];
648
649 } __attribute__ ((packed)) stripe_sz_ops;
650
651 struct {
652
653 u32 force_online:1;
654 u32 force_offline:1;
655 u32 force_rebuild:1;
656 u32 reserved:29;
657
658 } __attribute__ ((packed)) pd_operations;
659
660 struct {
661
662 u32 ctrl_supports_sas:1;
663 u32 ctrl_supports_sata:1;
664 u32 allow_mix_in_encl:1;
665 u32 allow_mix_in_ld:1;
666 u32 allow_sata_in_cluster:1;
667 u32 reserved:27;
668
669 } __attribute__ ((packed)) pd_mix_support;
670
671 /*
672 * Define ECC single-bit-error bucket information
673 */
674 u8 ecc_bucket_count;
675 u8 reserved_2[11];
676
677 /*
678 * Include the controller properties (changeable items)
679 */
680 struct megasas_ctrl_prop properties;
681
682 /*
683 * Define FW pkg version (set in envt v'bles on OEM basis)
684 */
685 char package_version[0x60];
686
687 u8 pad[0x800 - 0x6a0];
688
81e403ce 689} __packed;
c4a3e0a5
BS		 690
691/*
692 * ===============================
693 * MegaRAID SAS driver definitions
694 * ===============================
695 */
696#define MEGASAS_MAX_PD_CHANNELS 2
697#define MEGASAS_MAX_LD_CHANNELS 2
698#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
699 MEGASAS_MAX_LD_CHANNELS)
700#define MEGASAS_MAX_DEV_PER_CHANNEL 128
701#define MEGASAS_DEFAULT_INIT_ID -1
702#define MEGASAS_MAX_LUN 8
703#define MEGASAS_MAX_LD 64
81e403ce
YB		 704#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
705 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 706#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
707 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 708
1fd10685 709#define MEGASAS_MAX_SECTORS (2*1024)
658dcedb
SP		 710#define MEGASAS_DBG_LVL 1
711
05e9ebbe
SP		 712#define MEGASAS_FW_BUSY 1
713
d532dbe2 714/* Frame Type */
715#define IO_FRAME 0
716#define PTHRU_FRAME 1
717
c4a3e0a5
BS		 718/*
719 * When SCSI mid-layer calls driver's reset routine, driver waits for
720 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
721 * that the driver cannot _actually_ abort or reset pending commands. While
722 * it is waiting for the commands to complete, it prints a diagnostic message
723 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
724 */
725#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 726#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 727#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 728#define MEGASAS_IOCTL_CMD 0
05e9ebbe 729#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c4a3e0a5
BS		 730
731/*
732 * FW reports the maximum of number of commands that it can accept (maximum
733 * commands that can be outstanding) at any time. The driver must report a
734 * lower number to the mid layer because it can issue a few internal commands
735 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
736 * is shown below
737 */
738#define MEGASAS_INT_CMDS 32
7bebf5c7 739#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5
BS		 740
741/*
742 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
743 * SGLs based on the size of dma_addr_t
744 */
745#define IS_DMA64 (sizeof(dma_addr_t) == 8)
746
39a98554 747#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
748
749#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
750#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
751#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
752
c4a3e0a5 753#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 754#define MFI_POLL_TIMEOUT_SECS 60
ad84db2e 755#define MEGASAS_COMPLETION_TIMER_INTERVAL (HZ/10)
c4a3e0a5 756
f9876f0b 757#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 758#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
759#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 760#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
761#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 762
39a98554 763#define MFI_1068_PCSR_OFFSET 0x84
764#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
765#define MFI_1068_FW_READY 0xDDDD0000
0e98936c
SP		 766/*
767* register set for both 1068 and 1078 controllers
768* structure extended for 1078 registers
769*/
f9876f0b 770
c4a3e0a5 771struct megasas_register_set {
f9876f0b 772 u32 reserved_0[4]; /*0000h*/
c4a3e0a5 773
f9876f0b
SP		 774 u32 inbound_msg_0; /*0010h*/
775 u32 inbound_msg_1; /*0014h*/
776 u32 outbound_msg_0; /*0018h*/
777 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 778
f9876f0b
SP		 779 u32 inbound_doorbell; /*0020h*/
780 u32 inbound_intr_status; /*0024h*/
781 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 782
f9876f0b
SP		 783 u32 outbound_doorbell; /*002Ch*/
784 u32 outbound_intr_status; /*0030h*/
785 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 786
f9876f0b 787 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 788
f9876f0b
SP		 789 u32 inbound_queue_port; /*0040h*/
790 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 791
f9876f0b 792 u32 reserved_2[22]; /*0048h*/
c4a3e0a5 793
f9876f0b 794 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 795
f9876f0b
SP		 796 u32 reserved_3[3]; /*00A4h*/
797
798 u32 outbound_scratch_pad ; /*00B0h*/
799
800 u32 reserved_4[3]; /*00B4h*/
801
802 u32 inbound_low_queue_port ; /*00C0h*/
803
804 u32 inbound_high_queue_port ; /*00C4h*/
805
806 u32 reserved_5; /*00C8h*/
39a98554 807 u32 res_6[11]; /*CCh*/
808 u32 host_diag;
809 u32 seq_offset;
810 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 811} __attribute__ ((packed));
812
813struct megasas_sge32 {
814
815 u32 phys_addr;
816 u32 length;
817
818} __attribute__ ((packed));
819
820struct megasas_sge64 {
821
822 u64 phys_addr;
823 u32 length;
824
825} __attribute__ ((packed));
826
f4c9a131
YB		 827struct megasas_sge_skinny {
828 u64 phys_addr;
829 u32 length;
830 u32 flag;
831} __packed;
832
c4a3e0a5
BS		 833union megasas_sgl {
834
835 struct megasas_sge32 sge32[1];
836 struct megasas_sge64 sge64[1];
f4c9a131 837 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 838
839} __attribute__ ((packed));
840
841struct megasas_header {
842
843 u8 cmd; /*00h */
844 u8 sense_len; /*01h */
845 u8 cmd_status; /*02h */
846 u8 scsi_status; /*03h */
847
848 u8 target_id; /*04h */
849 u8 lun; /*05h */
850 u8 cdb_len; /*06h */
851 u8 sge_count; /*07h */
852
853 u32 context; /*08h */
854 u32 pad_0; /*0Ch */
855
856 u16 flags; /*10h */
857 u16 timeout; /*12h */
858 u32 data_xferlen; /*14h */
859
860} __attribute__ ((packed));
861
862union megasas_sgl_frame {
863
864 struct megasas_sge32 sge32[8];
865 struct megasas_sge64 sge64[5];
866
867} __attribute__ ((packed));
868
869struct megasas_init_frame {
870
871 u8 cmd; /*00h */
872 u8 reserved_0; /*01h */
873 u8 cmd_status; /*02h */
874
875 u8 reserved_1; /*03h */
876 u32 reserved_2; /*04h */
877
878 u32 context; /*08h */
879 u32 pad_0; /*0Ch */
880
881 u16 flags; /*10h */
882 u16 reserved_3; /*12h */
883 u32 data_xfer_len; /*14h */
884
885 u32 queue_info_new_phys_addr_lo; /*18h */
886 u32 queue_info_new_phys_addr_hi; /*1Ch */
887 u32 queue_info_old_phys_addr_lo; /*20h */
888 u32 queue_info_old_phys_addr_hi; /*24h */
889
890 u32 reserved_4[6]; /*28h */
891
892} __attribute__ ((packed));
893
894struct megasas_init_queue_info {
895
896 u32 init_flags; /*00h */
897 u32 reply_queue_entries; /*04h */
898
899 u32 reply_queue_start_phys_addr_lo; /*08h */
900 u32 reply_queue_start_phys_addr_hi; /*0Ch */
901 u32 producer_index_phys_addr_lo; /*10h */
902 u32 producer_index_phys_addr_hi; /*14h */
903 u32 consumer_index_phys_addr_lo; /*18h */
904 u32 consumer_index_phys_addr_hi; /*1Ch */
905
906} __attribute__ ((packed));
907
908struct megasas_io_frame {
909
910 u8 cmd; /*00h */
911 u8 sense_len; /*01h */
912 u8 cmd_status; /*02h */
913 u8 scsi_status; /*03h */
914
915 u8 target_id; /*04h */
916 u8 access_byte; /*05h */
917 u8 reserved_0; /*06h */
918 u8 sge_count; /*07h */
919
920 u32 context; /*08h */
921 u32 pad_0; /*0Ch */
922
923 u16 flags; /*10h */
924 u16 timeout; /*12h */
925 u32 lba_count; /*14h */
926
927 u32 sense_buf_phys_addr_lo; /*18h */
928 u32 sense_buf_phys_addr_hi; /*1Ch */
929
930 u32 start_lba_lo; /*20h */
931 u32 start_lba_hi; /*24h */
932
933 union megasas_sgl sgl; /*28h */
934
935} __attribute__ ((packed));
936
937struct megasas_pthru_frame {
938
939 u8 cmd; /*00h */
940 u8 sense_len; /*01h */
941 u8 cmd_status; /*02h */
942 u8 scsi_status; /*03h */
943
944 u8 target_id; /*04h */
945 u8 lun; /*05h */
946 u8 cdb_len; /*06h */
947 u8 sge_count; /*07h */
948
949 u32 context; /*08h */
950 u32 pad_0; /*0Ch */
951
952 u16 flags; /*10h */
953 u16 timeout; /*12h */
954 u32 data_xfer_len; /*14h */
955
956 u32 sense_buf_phys_addr_lo; /*18h */
957 u32 sense_buf_phys_addr_hi; /*1Ch */
958
959 u8 cdb[16]; /*20h */
960 union megasas_sgl sgl; /*30h */
961
962} __attribute__ ((packed));
963
964struct megasas_dcmd_frame {
965
966 u8 cmd; /*00h */
967 u8 reserved_0; /*01h */
968 u8 cmd_status; /*02h */
969 u8 reserved_1[4]; /*03h */
970 u8 sge_count; /*07h */
971
972 u32 context; /*08h */
973 u32 pad_0; /*0Ch */
974
975 u16 flags; /*10h */
976 u16 timeout; /*12h */
977
978 u32 data_xfer_len; /*14h */
979 u32 opcode; /*18h */
980
981 union { /*1Ch */
982 u8 b[12];
983 u16 s[6];
984 u32 w[3];
985 } mbox;
986
987 union megasas_sgl sgl; /*28h */
988
989} __attribute__ ((packed));
990
991struct megasas_abort_frame {
992
993 u8 cmd; /*00h */
994 u8 reserved_0; /*01h */
995 u8 cmd_status; /*02h */
996
997 u8 reserved_1; /*03h */
998 u32 reserved_2; /*04h */
999
1000 u32 context; /*08h */
1001 u32 pad_0; /*0Ch */
1002
1003 u16 flags; /*10h */
1004 u16 reserved_3; /*12h */
1005 u32 reserved_4; /*14h */
1006
1007 u32 abort_context; /*18h */
1008 u32 pad_1; /*1Ch */
1009
1010 u32 abort_mfi_phys_addr_lo; /*20h */
1011 u32 abort_mfi_phys_addr_hi; /*24h */
1012
1013 u32 reserved_5[6]; /*28h */
1014
1015} __attribute__ ((packed));
1016
1017struct megasas_smp_frame {
1018
1019 u8 cmd; /*00h */
1020 u8 reserved_1; /*01h */
1021 u8 cmd_status; /*02h */
1022 u8 connection_status; /*03h */
1023
1024 u8 reserved_2[3]; /*04h */
1025 u8 sge_count; /*07h */
1026
1027 u32 context; /*08h */
1028 u32 pad_0; /*0Ch */
1029
1030 u16 flags; /*10h */
1031 u16 timeout; /*12h */
1032
1033 u32 data_xfer_len; /*14h */
1034 u64 sas_addr; /*18h */
1035
1036 union {
1037 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1038 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1039 } sgl;
1040
1041} __attribute__ ((packed));
1042
1043struct megasas_stp_frame {
1044
1045 u8 cmd; /*00h */
1046 u8 reserved_1; /*01h */
1047 u8 cmd_status; /*02h */
1048 u8 reserved_2; /*03h */
1049
1050 u8 target_id; /*04h */
1051 u8 reserved_3[2]; /*05h */
1052 u8 sge_count; /*07h */
1053
1054 u32 context; /*08h */
1055 u32 pad_0; /*0Ch */
1056
1057 u16 flags; /*10h */
1058 u16 timeout; /*12h */
1059
1060 u32 data_xfer_len; /*14h */
1061
1062 u16 fis[10]; /*18h */
1063 u32 stp_flags;
1064
1065 union {
1066 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1067 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1068 } sgl;
1069
1070} __attribute__ ((packed));
1071
1072union megasas_frame {
1073
1074 struct megasas_header hdr;
1075 struct megasas_init_frame init;
1076 struct megasas_io_frame io;
1077 struct megasas_pthru_frame pthru;
1078 struct megasas_dcmd_frame dcmd;
1079 struct megasas_abort_frame abort;
1080 struct megasas_smp_frame smp;
1081 struct megasas_stp_frame stp;
1082
1083 u8 raw_bytes[64];
1084};
1085
1086struct megasas_cmd;
1087
1088union megasas_evt_class_locale {
1089
1090 struct {
1091 u16 locale;
1092 u8 reserved;
1093 s8 class;
1094 } __attribute__ ((packed)) members;
1095
1096 u32 word;
1097
1098} __attribute__ ((packed));
1099
1100struct megasas_evt_log_info {
1101 u32 newest_seq_num;
1102 u32 oldest_seq_num;
1103 u32 clear_seq_num;
1104 u32 shutdown_seq_num;
1105 u32 boot_seq_num;
1106
1107} __attribute__ ((packed));
1108
1109struct megasas_progress {
1110
1111 u16 progress;
1112 u16 elapsed_seconds;
1113
1114} __attribute__ ((packed));
1115
1116struct megasas_evtarg_ld {
1117
1118 u16 target_id;
1119 u8 ld_index;
1120 u8 reserved;
1121
1122} __attribute__ ((packed));
1123
1124struct megasas_evtarg_pd {
1125 u16 device_id;
1126 u8 encl_index;
1127 u8 slot_number;
1128
1129} __attribute__ ((packed));
1130
1131struct megasas_evt_detail {
1132
1133 u32 seq_num;
1134 u32 time_stamp;
1135 u32 code;
1136 union megasas_evt_class_locale cl;
1137 u8 arg_type;
1138 u8 reserved1[15];
1139
1140 union {
1141 struct {
1142 struct megasas_evtarg_pd pd;
1143 u8 cdb_length;
1144 u8 sense_length;
1145 u8 reserved[2];
1146 u8 cdb[16];
1147 u8 sense[64];
1148 } __attribute__ ((packed)) cdbSense;
1149
1150 struct megasas_evtarg_ld ld;
1151
1152 struct {
1153 struct megasas_evtarg_ld ld;
1154 u64 count;
1155 } __attribute__ ((packed)) ld_count;
1156
1157 struct {
1158 u64 lba;
1159 struct megasas_evtarg_ld ld;
1160 } __attribute__ ((packed)) ld_lba;
1161
1162 struct {
1163 struct megasas_evtarg_ld ld;
1164 u32 prevOwner;
1165 u32 newOwner;
1166 } __attribute__ ((packed)) ld_owner;
1167
1168 struct {
1169 u64 ld_lba;
1170 u64 pd_lba;
1171 struct megasas_evtarg_ld ld;
1172 struct megasas_evtarg_pd pd;
1173 } __attribute__ ((packed)) ld_lba_pd_lba;
1174
1175 struct {
1176 struct megasas_evtarg_ld ld;
1177 struct megasas_progress prog;
1178 } __attribute__ ((packed)) ld_prog;
1179
1180 struct {
1181 struct megasas_evtarg_ld ld;
1182 u32 prev_state;
1183 u32 new_state;
1184 } __attribute__ ((packed)) ld_state;
1185
1186 struct {
1187 u64 strip;
1188 struct megasas_evtarg_ld ld;
1189 } __attribute__ ((packed)) ld_strip;
1190
1191 struct megasas_evtarg_pd pd;
1192
1193 struct {
1194 struct megasas_evtarg_pd pd;
1195 u32 err;
1196 } __attribute__ ((packed)) pd_err;
1197
1198 struct {
1199 u64 lba;
1200 struct megasas_evtarg_pd pd;
1201 } __attribute__ ((packed)) pd_lba;
1202
1203 struct {
1204 u64 lba;
1205 struct megasas_evtarg_pd pd;
1206 struct megasas_evtarg_ld ld;
1207 } __attribute__ ((packed)) pd_lba_ld;
1208
1209 struct {
1210 struct megasas_evtarg_pd pd;
1211 struct megasas_progress prog;
1212 } __attribute__ ((packed)) pd_prog;
1213
1214 struct {
1215 struct megasas_evtarg_pd pd;
1216 u32 prevState;
1217 u32 newState;
1218 } __attribute__ ((packed)) pd_state;
1219
1220 struct {
1221 u16 vendorId;
1222 u16 deviceId;
1223 u16 subVendorId;
1224 u16 subDeviceId;
1225 } __attribute__ ((packed)) pci;
1226
1227 u32 rate;
1228 char str[96];
1229
1230 struct {
1231 u32 rtc;
1232 u32 elapsedSeconds;
1233 } __attribute__ ((packed)) time;
1234
1235 struct {
1236 u32 ecar;
1237 u32 elog;
1238 char str[64];
1239 } __attribute__ ((packed)) ecc;
1240
1241 u8 b[96];
1242 u16 s[48];
1243 u32 w[24];
1244 u64 d[12];
1245 } args;
1246
1247 char description[128];
1248
1249} __attribute__ ((packed));
1250
7e8a75f4
YB		 1251struct megasas_aen_event {
1252 struct work_struct hotplug_work;
1253 struct megasas_instance *instance;
1254};
1255
c4a3e0a5
BS		 1256struct megasas_instance {
1257
1258 u32 *producer;
1259 dma_addr_t producer_h;
1260 u32 *consumer;
1261 dma_addr_t consumer_h;
1262
1263 u32 *reply_queue;
1264 dma_addr_t reply_queue_h;
1265
1266 unsigned long base_addr;
1267 struct megasas_register_set __iomem *reg_set;
1268
81e403ce 1269 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1270 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1271 s8 init_id;
c4a3e0a5
BS		 1272
1273 u16 max_num_sge;
1274 u16 max_fw_cmds;
1275 u32 max_sectors_per_req;
7e8a75f4 1276 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1277
1278 struct megasas_cmd **cmd_list;
1279 struct list_head cmd_pool;
39a98554 1280 /* used to sync fire the cmd to fw */
c4a3e0a5 1281 spinlock_t cmd_pool_lock;
39a98554 1282 /* used to sync fire the cmd to fw */
1283 spinlock_t hba_lock;
7343eb65 1284 /* used to synch producer, consumer ptrs in dpc */
1285 spinlock_t completion_lock;
c4a3e0a5
BS		 1286 struct dma_pool *frame_dma_pool;
1287 struct dma_pool *sense_dma_pool;
1288
1289 struct megasas_evt_detail *evt_detail;
1290 dma_addr_t evt_detail_h;
1291 struct megasas_cmd *aen_cmd;
e5a69e27 1292 struct mutex aen_mutex;
c4a3e0a5
BS		 1293 struct semaphore ioctl_sem;
1294
1295 struct Scsi_Host *host;
1296
1297 wait_queue_head_t int_cmd_wait_q;
1298 wait_queue_head_t abort_cmd_wait_q;
1299
1300 struct pci_dev *pdev;
1301 u32 unique_id;
39a98554 1302 u32 fw_support_ieee;
c4a3e0a5 1303
e4a082c7 1304 atomic_t fw_outstanding;
39a98554 1305 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1306
1307 struct megasas_instance_template *instancet;
5d018ad0 1308 struct tasklet_struct isr_tasklet;
39a98554 1309 struct work_struct work_init;
05e9ebbe
SP		 1310
1311 u8 flag;
c3518837 1312 u8 unload;
f4c9a131 1313 u8 flag_ieee;
39a98554 1314 u8 issuepend_done;
1315 u8 disableOnlineCtrlReset;
1316 u8 adprecovery;
05e9ebbe 1317 unsigned long last_time;
39a98554 1318 u32 mfiStatus;
1319 u32 last_seq_num;
ad84db2e 1320
1321 struct timer_list io_completion_timer;
39a98554 1322 struct list_head internal_reset_pending_q;
1323};
1324
1325enum {
1326 MEGASAS_HBA_OPERATIONAL = 0,
1327 MEGASAS_ADPRESET_SM_INFAULT = 1,
1328 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1329 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1330 MEGASAS_HW_CRITICAL_ERROR = 4,
1331 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1332};
1333
0c79e681
YB		 1334struct megasas_instance_template {
1335 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1336 u32, struct megasas_register_set __iomem *);
1337
1338 void (*enable_intr)(struct megasas_register_set __iomem *) ;
1339 void (*disable_intr)(struct megasas_register_set __iomem *);
1340
1341 int (*clear_intr)(struct megasas_register_set __iomem *);
1342
1343 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1344 int (*adp_reset)(struct megasas_instance *, \
1345 struct megasas_register_set __iomem *);
1346 int (*check_reset)(struct megasas_instance *, \
1347 struct megasas_register_set __iomem *);
0c79e681
YB		 1348};
1349
c4a3e0a5
BS		 1350#define MEGASAS_IS_LOGICAL(scp) \
1351 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1352
1353#define MEGASAS_DEV_INDEX(inst, scp) \
1354 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1355 scp->device->id
1356
1357struct megasas_cmd {
1358
1359 union megasas_frame *frame;
1360 dma_addr_t frame_phys_addr;
1361 u8 *sense;
1362 dma_addr_t sense_phys_addr;
1363
1364 u32 index;
1365 u8 sync_cmd;
1366 u8 cmd_status;
39a98554 1367 u8 abort_aen;
1368 u8 retry_for_fw_reset;
1369
c4a3e0a5
BS		 1370
1371 struct list_head list;
1372 struct scsi_cmnd *scmd;
1373 struct megasas_instance *instance;
1374 u32 frame_count;
1375};
1376
1377#define MAX_MGMT_ADAPTERS 1024
1378#define MAX_IOCTL_SGE 16
1379
1380struct megasas_iocpacket {
1381
1382 u16 host_no;
1383 u16 __pad1;
1384 u32 sgl_off;
1385 u32 sge_count;
1386 u32 sense_off;
1387 u32 sense_len;
1388 union {
1389 u8 raw[128];
1390 struct megasas_header hdr;
1391 } frame;
1392
1393 struct iovec sgl[MAX_IOCTL_SGE];
1394
1395} __attribute__ ((packed));
1396
1397struct megasas_aen {
1398 u16 host_no;
1399 u16 __pad1;
1400 u32 seq_num;
1401 u32 class_locale_word;
1402} __attribute__ ((packed));
1403
1404#ifdef CONFIG_COMPAT
1405struct compat_megasas_iocpacket {
1406 u16 host_no;
1407 u16 __pad1;
1408 u32 sgl_off;
1409 u32 sge_count;
1410 u32 sense_off;
1411 u32 sense_len;
1412 union {
1413 u8 raw[128];
1414 struct megasas_header hdr;
1415 } frame;
1416 struct compat_iovec sgl[MAX_IOCTL_SGE];
1417} __attribute__ ((packed));
1418
0e98936c 1419#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1420#endif
1421
cb59aa6a 1422#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1423#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1424
1425struct megasas_mgmt_info {
1426
1427 u16 count;
1428 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1429 int max_index;
1430};
1431
1432#endif /*LSI_MEGARAID_SAS_H */
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