]> bbs.cooldavid.org Git - net-next-2.6.git/blame - drivers/scsi/lpfc/lpfc_sli.c
git://bbs.cooldavid.org / net-next-2.6.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
[SCSI] lpfc 8.1.12 : Rework offline path to solve HBA reset issues
[net-next-2.6.git] / drivers / scsi / lpfc / lpfc_sli.c
CommitLineData
dea3101e
JB		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
41415862 4 * Copyright (C) 2004-2006 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
c44ce173 7 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e
JB		 8 * *
9 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 10 * modify it under the terms of version 2 of the GNU General *
11 * Public License as published by the Free Software Foundation. *
12 * This program is distributed in the hope that it will be useful. *
13 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
14 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
15 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
16 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
17 * TO BE LEGALLY INVALID. See the GNU General Public License for *
18 * more details, a copy of which can be found in the file COPYING *
19 * included with this package. *
dea3101e
JB		 20 *******************************************************************/
21
dea3101e
JB		 22#include <linux/blkdev.h>
23#include <linux/pci.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26
91886523 27#include <scsi/scsi.h>
dea3101e
JB		 28#include <scsi/scsi_cmnd.h>
29#include <scsi/scsi_device.h>
30#include <scsi/scsi_host.h>
f888ba3c 31#include <scsi/scsi_transport_fc.h>
dea3101e
JB		 32
33#include "lpfc_hw.h"
34#include "lpfc_sli.h"
35#include "lpfc_disc.h"
36#include "lpfc_scsi.h"
37#include "lpfc.h"
38#include "lpfc_crtn.h"
39#include "lpfc_logmsg.h"
40#include "lpfc_compat.h"
41
42/*
43 * Define macro to log: Mailbox command x%x cannot issue Data
44 * This allows multiple uses of lpfc_msgBlk0311
45 * w/o perturbing log msg utility.
46 */
47#define LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag) \
48 lpfc_printf_log(phba, \
49 KERN_INFO, \
50 LOG_MBOX | LOG_SLI, \
51 "%d:0311 Mailbox command x%x cannot issue " \
52 "Data: x%x x%x x%x\n", \
53 phba->brd_no, \
54 mb->mbxCommand, \
55 phba->hba_state, \
56 psli->sli_flag, \
57 flag);
58
59
60/* There are only four IOCB completion types. */
61typedef enum _lpfc_iocb_type {
62 LPFC_UNKNOWN_IOCB,
63 LPFC_UNSOL_IOCB,
64 LPFC_SOL_IOCB,
65 LPFC_ABORT_IOCB
66} lpfc_iocb_type;
67
0bd4ca25
JSEC		 68struct lpfc_iocbq *
69lpfc_sli_get_iocbq(struct lpfc_hba * phba)
70{
71 struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
72 struct lpfc_iocbq * iocbq = NULL;
73
74 list_remove_head(lpfc_iocb_list, iocbq, struct lpfc_iocbq, list);
75 return iocbq;
76}
77
604a3e30
JB		 78void
79lpfc_sli_release_iocbq(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
80{
81 size_t start_clean = (size_t)(&((struct lpfc_iocbq *)NULL)->iocb);
82
83 /*
84 * Clean all volatile data fields, preserve iotag and node struct.
85 */
86 memset((char*)iocbq + start_clean, 0, sizeof(*iocbq) - start_clean);
87 list_add_tail(&iocbq->list, &phba->lpfc_iocb_list);
88}
89
dea3101e
JB		 90/*
91 * Translate the iocb command to an iocb command type used to decide the final
92 * disposition of each completed IOCB.
93 */
94static lpfc_iocb_type
95lpfc_sli_iocb_cmd_type(uint8_t iocb_cmnd)
96{
97 lpfc_iocb_type type = LPFC_UNKNOWN_IOCB;
98
99 if (iocb_cmnd > CMD_MAX_IOCB_CMD)
100 return 0;
101
102 switch (iocb_cmnd) {
103 case CMD_XMIT_SEQUENCE_CR:
104 case CMD_XMIT_SEQUENCE_CX:
105 case CMD_XMIT_BCAST_CN:
106 case CMD_XMIT_BCAST_CX:
107 case CMD_ELS_REQUEST_CR:
108 case CMD_ELS_REQUEST_CX:
109 case CMD_CREATE_XRI_CR:
110 case CMD_CREATE_XRI_CX:
111 case CMD_GET_RPI_CN:
112 case CMD_XMIT_ELS_RSP_CX:
113 case CMD_GET_RPI_CR:
114 case CMD_FCP_IWRITE_CR:
115 case CMD_FCP_IWRITE_CX:
116 case CMD_FCP_IREAD_CR:
117 case CMD_FCP_IREAD_CX:
118 case CMD_FCP_ICMND_CR:
119 case CMD_FCP_ICMND_CX:
f5603511
JS		 120 case CMD_FCP_TSEND_CX:
121 case CMD_FCP_TRSP_CX:
122 case CMD_FCP_TRECEIVE_CX:
123 case CMD_FCP_AUTO_TRSP_CX:
dea3101e
JB		 124 case CMD_ADAPTER_MSG:
125 case CMD_ADAPTER_DUMP:
126 case CMD_XMIT_SEQUENCE64_CR:
127 case CMD_XMIT_SEQUENCE64_CX:
128 case CMD_XMIT_BCAST64_CN:
129 case CMD_XMIT_BCAST64_CX:
130 case CMD_ELS_REQUEST64_CR:
131 case CMD_ELS_REQUEST64_CX:
132 case CMD_FCP_IWRITE64_CR:
133 case CMD_FCP_IWRITE64_CX:
134 case CMD_FCP_IREAD64_CR:
135 case CMD_FCP_IREAD64_CX:
136 case CMD_FCP_ICMND64_CR:
137 case CMD_FCP_ICMND64_CX:
f5603511
JS		 138 case CMD_FCP_TSEND64_CX:
139 case CMD_FCP_TRSP64_CX:
140 case CMD_FCP_TRECEIVE64_CX:
dea3101e
JB		 141 case CMD_GEN_REQUEST64_CR:
142 case CMD_GEN_REQUEST64_CX:
143 case CMD_XMIT_ELS_RSP64_CX:
144 type = LPFC_SOL_IOCB;
145 break;
146 case CMD_ABORT_XRI_CN:
147 case CMD_ABORT_XRI_CX:
148 case CMD_CLOSE_XRI_CN:
149 case CMD_CLOSE_XRI_CX:
150 case CMD_XRI_ABORTED_CX:
151 case CMD_ABORT_MXRI64_CN:
152 type = LPFC_ABORT_IOCB;
153 break;
154 case CMD_RCV_SEQUENCE_CX:
155 case CMD_RCV_ELS_REQ_CX:
156 case CMD_RCV_SEQUENCE64_CX:
157 case CMD_RCV_ELS_REQ64_CX:
158 type = LPFC_UNSOL_IOCB;
159 break;
160 default:
161 type = LPFC_UNKNOWN_IOCB;
162 break;
163 }
164
165 return type;
166}
167
168static int
169lpfc_sli_ring_map(struct lpfc_hba * phba, LPFC_MBOXQ_t *pmb)
170{
171 struct lpfc_sli *psli = &phba->sli;
172 MAILBOX_t *pmbox = &pmb->mb;
173 int i, rc;
174
175 for (i = 0; i < psli->num_rings; i++) {
176 phba->hba_state = LPFC_INIT_MBX_CMDS;
177 lpfc_config_ring(phba, i, pmb);
178 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
179 if (rc != MBX_SUCCESS) {
180 lpfc_printf_log(phba,
181 KERN_ERR,
182 LOG_INIT,
183 "%d:0446 Adapter failed to init, "
184 "mbxCmd x%x CFG_RING, mbxStatus x%x, "
185 "ring %d\n",
186 phba->brd_no,
187 pmbox->mbxCommand,
188 pmbox->mbxStatus,
189 i);
190 phba->hba_state = LPFC_HBA_ERROR;
191 return -ENXIO;
192 }
193 }
194 return 0;
195}
196
197static int
198lpfc_sli_ringtxcmpl_put(struct lpfc_hba * phba,
199 struct lpfc_sli_ring * pring, struct lpfc_iocbq * piocb)
200{
dea3101e
JB		 201 list_add_tail(&piocb->list, &pring->txcmplq);
202 pring->txcmplq_cnt++;
203 if (unlikely(pring->ringno == LPFC_ELS_RING))
204 mod_timer(&phba->els_tmofunc,
205 jiffies + HZ * (phba->fc_ratov << 1));
206
dea3101e
JB		 207 return (0);
208}
209
210static struct lpfc_iocbq *
211lpfc_sli_ringtx_get(struct lpfc_hba * phba, struct lpfc_sli_ring * pring)
212{
213 struct list_head *dlp;
214 struct lpfc_iocbq *cmd_iocb;
215
216 dlp = &pring->txq;
217 cmd_iocb = NULL;
218 list_remove_head((&pring->txq), cmd_iocb,
219 struct lpfc_iocbq,
220 list);
221 if (cmd_iocb) {
222 /* If the first ptr is not equal to the list header,
223 * deque the IOCBQ_t and return it.
224 */
225 pring->txq_cnt--;
226 }
227 return (cmd_iocb);
228}
229
230static IOCB_t *
231lpfc_sli_next_iocb_slot (struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
232{
4cc2da1d 233 struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
dea3101e
JB		 234 uint32_t max_cmd_idx = pring->numCiocb;
235 IOCB_t *iocb = NULL;
236
237 if ((pring->next_cmdidx == pring->cmdidx) &&
238 (++pring->next_cmdidx >= max_cmd_idx))
239 pring->next_cmdidx = 0;
240
241 if (unlikely(pring->local_getidx == pring->next_cmdidx)) {
242
243 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
244
245 if (unlikely(pring->local_getidx >= max_cmd_idx)) {
246 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
247 "%d:0315 Ring %d issue: portCmdGet %d "
248 "is bigger then cmd ring %d\n",
249 phba->brd_no, pring->ringno,
250 pring->local_getidx, max_cmd_idx);
251
252 phba->hba_state = LPFC_HBA_ERROR;
253 /*
254 * All error attention handlers are posted to
255 * worker thread
256 */
257 phba->work_ha |= HA_ERATT;
258 phba->work_hs = HS_FFER3;
259 if (phba->work_wait)
260 wake_up(phba->work_wait);
261
262 return NULL;
263 }
264
265 if (pring->local_getidx == pring->next_cmdidx)
266 return NULL;
267 }
268
269 iocb = IOCB_ENTRY(pring->cmdringaddr, pring->cmdidx);
270
271 return iocb;
272}
273
604a3e30
JB		 274uint16_t
275lpfc_sli_next_iotag(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
dea3101e 276{
604a3e30
JB		 277 struct lpfc_iocbq ** new_arr;
278 struct lpfc_iocbq ** old_arr;
279 size_t new_len;
280 struct lpfc_sli *psli = &phba->sli;
281 uint16_t iotag;
dea3101e 282
604a3e30
JB		 283 spin_lock_irq(phba->host->host_lock);
284 iotag = psli->last_iotag;
285 if(++iotag < psli->iocbq_lookup_len) {
286 psli->last_iotag = iotag;
287 psli->iocbq_lookup[iotag] = iocbq;
288 spin_unlock_irq(phba->host->host_lock);
289 iocbq->iotag = iotag;
290 return iotag;
291 }
292 else if (psli->iocbq_lookup_len < (0xffff
293 - LPFC_IOCBQ_LOOKUP_INCREMENT)) {
294 new_len = psli->iocbq_lookup_len + LPFC_IOCBQ_LOOKUP_INCREMENT;
295 spin_unlock_irq(phba->host->host_lock);
296 new_arr = kmalloc(new_len * sizeof (struct lpfc_iocbq *),
297 GFP_KERNEL);
298 if (new_arr) {
299 memset((char *)new_arr, 0,
300 new_len * sizeof (struct lpfc_iocbq *));
301 spin_lock_irq(phba->host->host_lock);
302 old_arr = psli->iocbq_lookup;
303 if (new_len <= psli->iocbq_lookup_len) {
304 /* highly unprobable case */
305 kfree(new_arr);
306 iotag = psli->last_iotag;
307 if(++iotag < psli->iocbq_lookup_len) {
308 psli->last_iotag = iotag;
309 psli->iocbq_lookup[iotag] = iocbq;
310 spin_unlock_irq(phba->host->host_lock);
311 iocbq->iotag = iotag;
312 return iotag;
313 }
314 spin_unlock_irq(phba->host->host_lock);
315 return 0;
316 }
317 if (psli->iocbq_lookup)
318 memcpy(new_arr, old_arr,
319 ((psli->last_iotag + 1) *
320 sizeof (struct lpfc_iocbq *)));
321 psli->iocbq_lookup = new_arr;
322 psli->iocbq_lookup_len = new_len;
323 psli->last_iotag = iotag;
324 psli->iocbq_lookup[iotag] = iocbq;
325 spin_unlock_irq(phba->host->host_lock);
326 iocbq->iotag = iotag;
327 kfree(old_arr);
328 return iotag;
329 }
8f6d98d2
JS		 330 } else
331 spin_unlock_irq(phba->host->host_lock);
dea3101e 332
604a3e30
JB		 333 lpfc_printf_log(phba, KERN_ERR,LOG_SLI,
334 "%d:0318 Failed to allocate IOTAG.last IOTAG is %d\n",
335 phba->brd_no, psli->last_iotag);
dea3101e 336
604a3e30 337 return 0;
dea3101e
JB		 338}
339
340static void
341lpfc_sli_submit_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
342 IOCB_t *iocb, struct lpfc_iocbq *nextiocb)
343{
344 /*
604a3e30 345 * Set up an iotag
dea3101e 346 */
604a3e30 347 nextiocb->iocb.ulpIoTag = (nextiocb->iocb_cmpl) ? nextiocb->iotag : 0;
dea3101e
JB		 348
349 /*
350 * Issue iocb command to adapter
351 */
352 lpfc_sli_pcimem_bcopy(&nextiocb->iocb, iocb, sizeof (IOCB_t));
353 wmb();
354 pring->stats.iocb_cmd++;
355
356 /*
357 * If there is no completion routine to call, we can release the
358 * IOCB buffer back right now. For IOCBs, like QUE_RING_BUF,
359 * that have no rsp ring completion, iocb_cmpl MUST be NULL.
360 */
361 if (nextiocb->iocb_cmpl)
362 lpfc_sli_ringtxcmpl_put(phba, pring, nextiocb);
604a3e30
JB		 363 else
364 lpfc_sli_release_iocbq(phba, nextiocb);
dea3101e
JB		 365
366 /*
367 * Let the HBA know what IOCB slot will be the next one the
368 * driver will put a command into.
369 */
370 pring->cmdidx = pring->next_cmdidx;
f91b392c 371 writel(pring->cmdidx, phba->MBslimaddr
dea3101e
JB		 372 + (SLIMOFF + (pring->ringno * 2)) * 4);
373}
374
375static void
376lpfc_sli_update_full_ring(struct lpfc_hba * phba,
377 struct lpfc_sli_ring *pring)
378{
379 int ringno = pring->ringno;
380
381 pring->flag |= LPFC_CALL_RING_AVAILABLE;
382
383 wmb();
384
385 /*
386 * Set ring 'ringno' to SET R0CE_REQ in Chip Att register.
387 * The HBA will tell us when an IOCB entry is available.
388 */
389 writel((CA_R0ATT|CA_R0CE_REQ) << (ringno*4), phba->CAregaddr);
390 readl(phba->CAregaddr); /* flush */
391
392 pring->stats.iocb_cmd_full++;
393}
394
395static void
396lpfc_sli_update_ring(struct lpfc_hba * phba,
397 struct lpfc_sli_ring *pring)
398{
399 int ringno = pring->ringno;
400
401 /*
402 * Tell the HBA that there is work to do in this ring.
403 */
404 wmb();
405 writel(CA_R0ATT << (ringno * 4), phba->CAregaddr);
406 readl(phba->CAregaddr); /* flush */
407}
408
409static void
410lpfc_sli_resume_iocb(struct lpfc_hba * phba, struct lpfc_sli_ring * pring)
411{
412 IOCB_t *iocb;
413 struct lpfc_iocbq *nextiocb;
414
415 /*
416 * Check to see if:
417 * (a) there is anything on the txq to send
418 * (b) link is up
419 * (c) link attention events can be processed (fcp ring only)
420 * (d) IOCB processing is not blocked by the outstanding mbox command.
421 */
422 if (pring->txq_cnt &&
423 (phba->hba_state > LPFC_LINK_DOWN) &&
424 (pring->ringno != phba->sli.fcp_ring ||
425 phba->sli.sli_flag & LPFC_PROCESS_LA) &&
426 !(pring->flag & LPFC_STOP_IOCB_MBX)) {
427
428 while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
429 (nextiocb = lpfc_sli_ringtx_get(phba, pring)))
430 lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
431
432 if (iocb)
433 lpfc_sli_update_ring(phba, pring);
434 else
435 lpfc_sli_update_full_ring(phba, pring);
436 }
437
438 return;
439}
440
441/* lpfc_sli_turn_on_ring is only called by lpfc_sli_handle_mb_event below */
442static void
443lpfc_sli_turn_on_ring(struct lpfc_hba * phba, int ringno)
444{
4cc2da1d 445 struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[ringno];
dea3101e
JB		 446
447 /* If the ring is active, flag it */
448 if (phba->sli.ring[ringno].cmdringaddr) {
449 if (phba->sli.ring[ringno].flag & LPFC_STOP_IOCB_MBX) {
450 phba->sli.ring[ringno].flag &= ~LPFC_STOP_IOCB_MBX;
451 /*
452 * Force update of the local copy of cmdGetInx
453 */
454 phba->sli.ring[ringno].local_getidx
455 = le32_to_cpu(pgp->cmdGetInx);
456 spin_lock_irq(phba->host->host_lock);
457 lpfc_sli_resume_iocb(phba, &phba->sli.ring[ringno]);
458 spin_unlock_irq(phba->host->host_lock);
459 }
460 }
461}
462
463static int
464lpfc_sli_chk_mbx_command(uint8_t mbxCommand)
465{
466 uint8_t ret;
467
468 switch (mbxCommand) {
469 case MBX_LOAD_SM:
470 case MBX_READ_NV:
471 case MBX_WRITE_NV:
472 case MBX_RUN_BIU_DIAG:
473 case MBX_INIT_LINK:
474 case MBX_DOWN_LINK:
475 case MBX_CONFIG_LINK:
476 case MBX_CONFIG_RING:
477 case MBX_RESET_RING:
478 case MBX_READ_CONFIG:
479 case MBX_READ_RCONFIG:
480 case MBX_READ_SPARM:
481 case MBX_READ_STATUS:
482 case MBX_READ_RPI:
483 case MBX_READ_XRI:
484 case MBX_READ_REV:
485 case MBX_READ_LNK_STAT:
486 case MBX_REG_LOGIN:
487 case MBX_UNREG_LOGIN:
488 case MBX_READ_LA:
489 case MBX_CLEAR_LA:
490 case MBX_DUMP_MEMORY:
491 case MBX_DUMP_CONTEXT:
492 case MBX_RUN_DIAGS:
493 case MBX_RESTART:
494 case MBX_UPDATE_CFG:
495 case MBX_DOWN_LOAD:
496 case MBX_DEL_LD_ENTRY:
497 case MBX_RUN_PROGRAM:
498 case MBX_SET_MASK:
499 case MBX_SET_SLIM:
500 case MBX_UNREG_D_ID:
41415862 501 case MBX_KILL_BOARD:
dea3101e 502 case MBX_CONFIG_FARP:
41415862 503 case MBX_BEACON:
dea3101e
JB		 504 case MBX_LOAD_AREA:
505 case MBX_RUN_BIU_DIAG64:
506 case MBX_CONFIG_PORT:
507 case MBX_READ_SPARM64:
508 case MBX_READ_RPI64:
509 case MBX_REG_LOGIN64:
510 case MBX_READ_LA64:
511 case MBX_FLASH_WR_ULA:
512 case MBX_SET_DEBUG:
513 case MBX_LOAD_EXP_ROM:
514 ret = mbxCommand;
515 break;
516 default:
517 ret = MBX_SHUTDOWN;
518 break;
519 }
520 return (ret);
521}
522static void
523lpfc_sli_wake_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
524{
525 wait_queue_head_t *pdone_q;
526
527 /*
528 * If pdone_q is empty, the driver thread gave up waiting and
529 * continued running.
530 */
531 pdone_q = (wait_queue_head_t *) pmboxq->context1;
532 if (pdone_q)
533 wake_up_interruptible(pdone_q);
534 return;
535}
536
537void
538lpfc_sli_def_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
539{
540 struct lpfc_dmabuf *mp;
541 mp = (struct lpfc_dmabuf *) (pmb->context1);
542 if (mp) {
543 lpfc_mbuf_free(phba, mp->virt, mp->phys);
544 kfree(mp);
545 }
546 mempool_free( pmb, phba->mbox_mem_pool);
547 return;
548}
549
550int
551lpfc_sli_handle_mb_event(struct lpfc_hba * phba)
552{
553 MAILBOX_t *mbox;
554 MAILBOX_t *pmbox;
555 LPFC_MBOXQ_t *pmb;
556 struct lpfc_sli *psli;
557 int i, rc;
558 uint32_t process_next;
559
560 psli = &phba->sli;
561 /* We should only get here if we are in SLI2 mode */
562 if (!(phba->sli.sli_flag & LPFC_SLI2_ACTIVE)) {
563 return (1);
564 }
565
566 phba->sli.slistat.mbox_event++;
567
568 /* Get a Mailbox buffer to setup mailbox commands for callback */
569 if ((pmb = phba->sli.mbox_active)) {
570 pmbox = &pmb->mb;
4cc2da1d 571 mbox = &phba->slim2p->mbx;
dea3101e
JB		 572
573 /* First check out the status word */
574 lpfc_sli_pcimem_bcopy(mbox, pmbox, sizeof (uint32_t));
575
576 /* Sanity check to ensure the host owns the mailbox */
577 if (pmbox->mbxOwner != OWN_HOST) {
578 /* Lets try for a while */
579 for (i = 0; i < 10240; i++) {
580 /* First copy command data */
581 lpfc_sli_pcimem_bcopy(mbox, pmbox,
582 sizeof (uint32_t));
583 if (pmbox->mbxOwner == OWN_HOST)
584 goto mbout;
585 }
586 /* Stray Mailbox Interrupt, mbxCommand <cmd> mbxStatus
587 <status> */
588 lpfc_printf_log(phba,
b4c02652 589 KERN_WARNING,
dea3101e
JB		 590 LOG_MBOX | LOG_SLI,
591 "%d:0304 Stray Mailbox Interrupt "
592 "mbxCommand x%x mbxStatus x%x\n",
593 phba->brd_no,
594 pmbox->mbxCommand,
595 pmbox->mbxStatus);
596
597 spin_lock_irq(phba->host->host_lock);
598 phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
599 spin_unlock_irq(phba->host->host_lock);
600 return (1);
601 }
602
603 mbout:
604 del_timer_sync(&phba->sli.mbox_tmo);
605 phba->work_hba_events &= ~WORKER_MBOX_TMO;
606
607 /*
608 * It is a fatal error if unknown mbox command completion.
609 */
610 if (lpfc_sli_chk_mbx_command(pmbox->mbxCommand) ==
611 MBX_SHUTDOWN) {
612
613 /* Unknow mailbox command compl */
614 lpfc_printf_log(phba,
615 KERN_ERR,
616 LOG_MBOX | LOG_SLI,
617 "%d:0323 Unknown Mailbox command %x Cmpl\n",
618 phba->brd_no,
619 pmbox->mbxCommand);
620 phba->hba_state = LPFC_HBA_ERROR;
621 phba->work_hs = HS_FFER3;
622 lpfc_handle_eratt(phba);
623 return (0);
624 }
625
626 phba->sli.mbox_active = NULL;
627 if (pmbox->mbxStatus) {
628 phba->sli.slistat.mbox_stat_err++;
629 if (pmbox->mbxStatus == MBXERR_NO_RESOURCES) {
630 /* Mbox cmd cmpl error - RETRYing */
631 lpfc_printf_log(phba,
632 KERN_INFO,
633 LOG_MBOX | LOG_SLI,
634 "%d:0305 Mbox cmd cmpl error - "
635 "RETRYing Data: x%x x%x x%x x%x\n",
636 phba->brd_no,
637 pmbox->mbxCommand,
638 pmbox->mbxStatus,
639 pmbox->un.varWords[0],
640 phba->hba_state);
641 pmbox->mbxStatus = 0;
642 pmbox->mbxOwner = OWN_HOST;
643 spin_lock_irq(phba->host->host_lock);
644 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
645 spin_unlock_irq(phba->host->host_lock);
646 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
647 if (rc == MBX_SUCCESS)
648 return (0);
649 }
650 }
651
652 /* Mailbox cmd <cmd> Cmpl <cmpl> */
653 lpfc_printf_log(phba,
654 KERN_INFO,
655 LOG_MBOX | LOG_SLI,
656 "%d:0307 Mailbox cmd x%x Cmpl x%p "
657 "Data: x%x x%x x%x x%x x%x x%x x%x x%x x%x\n",
658 phba->brd_no,
659 pmbox->mbxCommand,
660 pmb->mbox_cmpl,
661 *((uint32_t *) pmbox),
662 pmbox->un.varWords[0],
663 pmbox->un.varWords[1],
664 pmbox->un.varWords[2],
665 pmbox->un.varWords[3],
666 pmbox->un.varWords[4],
667 pmbox->un.varWords[5],
668 pmbox->un.varWords[6],
669 pmbox->un.varWords[7]);
670
671 if (pmb->mbox_cmpl) {
672 lpfc_sli_pcimem_bcopy(mbox, pmbox, MAILBOX_CMD_SIZE);
673 pmb->mbox_cmpl(phba,pmb);
674 }
675 }
676
677
678 do {
679 process_next = 0; /* by default don't loop */
680 spin_lock_irq(phba->host->host_lock);
681 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
682
683 /* Process next mailbox command if there is one */
684 if ((pmb = lpfc_mbox_get(phba))) {
685 spin_unlock_irq(phba->host->host_lock);
686 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
687 if (rc == MBX_NOT_FINISHED) {
688 pmb->mb.mbxStatus = MBX_NOT_FINISHED;
689 pmb->mbox_cmpl(phba,pmb);
690 process_next = 1;
691 continue; /* loop back */
692 }
693 } else {
694 spin_unlock_irq(phba->host->host_lock);
695 /* Turn on IOCB processing */
1dcb58e5 696 for (i = 0; i < phba->sli.num_rings; i++)
dea3101e 697 lpfc_sli_turn_on_ring(phba, i);
dea3101e
JB		 698 }
699
700 } while (process_next);
701
702 return (0);
703}
704static int
705lpfc_sli_process_unsol_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
706 struct lpfc_iocbq *saveq)
707{
708 IOCB_t * irsp;
709 WORD5 * w5p;
710 uint32_t Rctl, Type;
711 uint32_t match, i;
712
713 match = 0;
714 irsp = &(saveq->iocb);
715 if ((irsp->ulpCommand == CMD_RCV_ELS_REQ64_CX)
716 || (irsp->ulpCommand == CMD_RCV_ELS_REQ_CX)) {
717 Rctl = FC_ELS_REQ;
718 Type = FC_ELS_DATA;
719 } else {
720 w5p =
721 (WORD5 *) & (saveq->iocb.un.
722 ulpWord[5]);
723 Rctl = w5p->hcsw.Rctl;
724 Type = w5p->hcsw.Type;
725
726 /* Firmware Workaround */
727 if ((Rctl == 0) && (pring->ringno == LPFC_ELS_RING) &&
728 (irsp->ulpCommand == CMD_RCV_SEQUENCE64_CX)) {
729 Rctl = FC_ELS_REQ;
730 Type = FC_ELS_DATA;
731 w5p->hcsw.Rctl = Rctl;
732 w5p->hcsw.Type = Type;
733 }
734 }
735 /* unSolicited Responses */
736 if (pring->prt[0].profile) {
cf5bf97e
JW		 737 if (pring->prt[0].lpfc_sli_rcv_unsol_event)
738 (pring->prt[0].lpfc_sli_rcv_unsol_event) (phba, pring,
739 saveq);
dea3101e
JB		 740 match = 1;
741 } else {
742 /* We must search, based on rctl / type
743 for the right routine */
744 for (i = 0; i < pring->num_mask;
745 i++) {
746 if ((pring->prt[i].rctl ==
747 Rctl)
748 && (pring->prt[i].
749 type == Type)) {
cf5bf97e
JW		 750 if (pring->prt[i].lpfc_sli_rcv_unsol_event)
751 (pring->prt[i].lpfc_sli_rcv_unsol_event)
752 (phba, pring, saveq);
dea3101e
JB		 753 match = 1;
754 break;
755 }
756 }
757 }
758 if (match == 0) {
759 /* Unexpected Rctl / Type received */
760 /* Ring <ringno> handler: unexpected
761 Rctl <Rctl> Type <Type> received */
762 lpfc_printf_log(phba,
763 KERN_WARNING,
764 LOG_SLI,
765 "%d:0313 Ring %d handler: unexpected Rctl x%x "
766 "Type x%x received \n",
767 phba->brd_no,
768 pring->ringno,
769 Rctl,
770 Type);
771 }
772 return(1);
773}
774
775static struct lpfc_iocbq *
604a3e30
JB		 776lpfc_sli_iocbq_lookup(struct lpfc_hba * phba,
777 struct lpfc_sli_ring * pring,
778 struct lpfc_iocbq * prspiocb)
dea3101e 779{
dea3101e
JB		 780 struct lpfc_iocbq *cmd_iocb = NULL;
781 uint16_t iotag;
782
604a3e30
JB		 783 iotag = prspiocb->iocb.ulpIoTag;
784
785 if (iotag != 0 && iotag <= phba->sli.last_iotag) {
786 cmd_iocb = phba->sli.iocbq_lookup[iotag];
787 list_del(&cmd_iocb->list);
788 pring->txcmplq_cnt--;
789 return cmd_iocb;
dea3101e
JB		 790 }
791
dea3101e 792 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
604a3e30
JB		 793 "%d:0317 iotag x%x is out off "
794 "range: max iotag x%x wd0 x%x\n",
795 phba->brd_no, iotag,
796 phba->sli.last_iotag,
797 *(((uint32_t *) &prspiocb->iocb) + 7));
dea3101e
JB		 798 return NULL;
799}
800
801static int
802lpfc_sli_process_sol_iocb(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
803 struct lpfc_iocbq *saveq)
804{
805 struct lpfc_iocbq * cmdiocbp;
806 int rc = 1;
807 unsigned long iflag;
808
809 /* Based on the iotag field, get the cmd IOCB from the txcmplq */
810 spin_lock_irqsave(phba->host->host_lock, iflag);
604a3e30 811 cmdiocbp = lpfc_sli_iocbq_lookup(phba, pring, saveq);
dea3101e
JB		 812 if (cmdiocbp) {
813 if (cmdiocbp->iocb_cmpl) {
814 /*
815 * Post all ELS completions to the worker thread.
816 * All other are passed to the completion callback.
817 */
818 if (pring->ringno == LPFC_ELS_RING) {
07951076
JS		 819 if (cmdiocbp->iocb_flag & LPFC_DRIVER_ABORTED) {
820 cmdiocbp->iocb_flag &=
821 ~LPFC_DRIVER_ABORTED;
822 saveq->iocb.ulpStatus =
823 IOSTAT_LOCAL_REJECT;
824 saveq->iocb.un.ulpWord[4] =
825 IOERR_SLI_ABORTED;
826 }
dea3101e
JB		 827 spin_unlock_irqrestore(phba->host->host_lock,
828 iflag);
829 (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
830 spin_lock_irqsave(phba->host->host_lock, iflag);
831 }
832 else {
dea3101e
JB		 833 spin_unlock_irqrestore(phba->host->host_lock,
834 iflag);
835 (cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
836 spin_lock_irqsave(phba->host->host_lock, iflag);
837 }
604a3e30
JB		 838 } else
839 lpfc_sli_release_iocbq(phba, cmdiocbp);
dea3101e
JB		 840 } else {
841 /*
842 * Unknown initiating command based on the response iotag.
843 * This could be the case on the ELS ring because of
844 * lpfc_els_abort().
845 */
846 if (pring->ringno != LPFC_ELS_RING) {
847 /*
848 * Ring <ringno> handler: unexpected completion IoTag
849 * <IoTag>
850 */
851 lpfc_printf_log(phba,
852 KERN_WARNING,
853 LOG_SLI,
854 "%d:0322 Ring %d handler: unexpected "
855 "completion IoTag x%x Data: x%x x%x x%x x%x\n",
856 phba->brd_no,
857 pring->ringno,
858 saveq->iocb.ulpIoTag,
859 saveq->iocb.ulpStatus,
860 saveq->iocb.un.ulpWord[4],
861 saveq->iocb.ulpCommand,
862 saveq->iocb.ulpContext);
863 }
864 }
68876920 865
dea3101e
JB		 866 spin_unlock_irqrestore(phba->host->host_lock, iflag);
867 return rc;
868}
869
875fbdfe
JSEC		 870static void lpfc_sli_rsp_pointers_error(struct lpfc_hba * phba,
871 struct lpfc_sli_ring * pring)
872{
873 struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
874 /*
875 * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
876 * rsp ring <portRspMax>
877 */
878 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
879 "%d:0312 Ring %d handler: portRspPut %d "
880 "is bigger then rsp ring %d\n",
881 phba->brd_no, pring->ringno,
882 le32_to_cpu(pgp->rspPutInx),
883 pring->numRiocb);
884
885 phba->hba_state = LPFC_HBA_ERROR;
886
887 /*
888 * All error attention handlers are posted to
889 * worker thread
890 */
891 phba->work_ha |= HA_ERATT;
892 phba->work_hs = HS_FFER3;
893 if (phba->work_wait)
894 wake_up(phba->work_wait);
895
896 return;
897}
898
899void lpfc_sli_poll_fcp_ring(struct lpfc_hba * phba)
900{
901 struct lpfc_sli * psli = &phba->sli;
902 struct lpfc_sli_ring * pring = &psli->ring[LPFC_FCP_RING];
903 IOCB_t *irsp = NULL;
904 IOCB_t *entry = NULL;
905 struct lpfc_iocbq *cmdiocbq = NULL;
906 struct lpfc_iocbq rspiocbq;
907 struct lpfc_pgp *pgp;
908 uint32_t status;
909 uint32_t portRspPut, portRspMax;
910 int type;
911 uint32_t rsp_cmpl = 0;
912 void __iomem *to_slim;
913 uint32_t ha_copy;
914
915 pring->stats.iocb_event++;
916
917 /* The driver assumes SLI-2 mode */
918 pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
919
920 /*
921 * The next available response entry should never exceed the maximum
922 * entries. If it does, treat it as an adapter hardware error.
923 */
924 portRspMax = pring->numRiocb;
925 portRspPut = le32_to_cpu(pgp->rspPutInx);
926 if (unlikely(portRspPut >= portRspMax)) {
927 lpfc_sli_rsp_pointers_error(phba, pring);
928 return;
929 }
930
931 rmb();
932 while (pring->rspidx != portRspPut) {
933
934 entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
935
936 if (++pring->rspidx >= portRspMax)
937 pring->rspidx = 0;
938
939 lpfc_sli_pcimem_bcopy((uint32_t *) entry,
940 (uint32_t *) &rspiocbq.iocb,
941 sizeof (IOCB_t));
942 irsp = &rspiocbq.iocb;
943 type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
944 pring->stats.iocb_rsp++;
945 rsp_cmpl++;
946
947 if (unlikely(irsp->ulpStatus)) {
948 /* Rsp ring <ringno> error: IOCB */
949 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
950 "%d:0326 Rsp Ring %d error: IOCB Data: "
951 "x%x x%x x%x x%x x%x x%x x%x x%x\n",
952 phba->brd_no, pring->ringno,
953 irsp->un.ulpWord[0],
954 irsp->un.ulpWord[1],
955 irsp->un.ulpWord[2],
956 irsp->un.ulpWord[3],
957 irsp->un.ulpWord[4],
958 irsp->un.ulpWord[5],
959 *(((uint32_t *) irsp) + 6),
960 *(((uint32_t *) irsp) + 7));
961 }
962
963 switch (type) {
964 case LPFC_ABORT_IOCB:
965 case LPFC_SOL_IOCB:
966 /*
967 * Idle exchange closed via ABTS from port. No iocb
968 * resources need to be recovered.
969 */
970 if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
dca9479b
JS		 971 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
972 "%d:0314 IOCB cmd 0x%x"
973 " processed. Skipping"
974 " completion", phba->brd_no,
975 irsp->ulpCommand);
875fbdfe
JSEC		 976 break;
977 }
978
979 cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
980 &rspiocbq);
981 if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
982 (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
983 &rspiocbq);
984 }
985 break;
986 default:
987 if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
988 char adaptermsg[LPFC_MAX_ADPTMSG];
989 memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
990 memcpy(&adaptermsg[0], (uint8_t *) irsp,
991 MAX_MSG_DATA);
992 dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
993 phba->brd_no, adaptermsg);
994 } else {
995 /* Unknown IOCB command */
996 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
997 "%d:0321 Unknown IOCB command "
998 "Data: x%x, x%x x%x x%x x%x\n",
999 phba->brd_no, type,
1000 irsp->ulpCommand,
1001 irsp->ulpStatus,
1002 irsp->ulpIoTag,
1003 irsp->ulpContext);
1004 }
1005 break;
1006 }
1007
1008 /*
1009 * The response IOCB has been processed. Update the ring
1010 * pointer in SLIM. If the port response put pointer has not
1011 * been updated, sync the pgp->rspPutInx and fetch the new port
1012 * response put pointer.
1013 */
1014 to_slim = phba->MBslimaddr +
1015 (SLIMOFF + (pring->ringno * 2) + 1) * 4;
1016 writeb(pring->rspidx, to_slim);
1017
1018 if (pring->rspidx == portRspPut)
1019 portRspPut = le32_to_cpu(pgp->rspPutInx);
1020 }
1021
1022 ha_copy = readl(phba->HAregaddr);
1023 ha_copy >>= (LPFC_FCP_RING * 4);
1024
1025 if ((rsp_cmpl > 0) && (ha_copy & HA_R0RE_REQ)) {
1026 pring->stats.iocb_rsp_full++;
1027 status = ((CA_R0ATT | CA_R0RE_RSP) << (LPFC_FCP_RING * 4));
1028 writel(status, phba->CAregaddr);
1029 readl(phba->CAregaddr);
1030 }
1031 if ((ha_copy & HA_R0CE_RSP) &&
1032 (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
1033 pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
1034 pring->stats.iocb_cmd_empty++;
1035
1036 /* Force update of the local copy of cmdGetInx */
1037 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
1038 lpfc_sli_resume_iocb(phba, pring);
1039
1040 if ((pring->lpfc_sli_cmd_available))
1041 (pring->lpfc_sli_cmd_available) (phba, pring);
1042
1043 }
1044
1045 return;
1046}
1047
dea3101e
JB		 1048/*
1049 * This routine presumes LPFC_FCP_RING handling and doesn't bother
1050 * to check it explicitly.
1051 */
1052static int
1053lpfc_sli_handle_fast_ring_event(struct lpfc_hba * phba,
1054 struct lpfc_sli_ring * pring, uint32_t mask)
1055{
4cc2da1d 1056 struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
dea3101e 1057 IOCB_t *irsp = NULL;
87f6eaff 1058 IOCB_t *entry = NULL;
dea3101e
JB		 1059 struct lpfc_iocbq *cmdiocbq = NULL;
1060 struct lpfc_iocbq rspiocbq;
dea3101e
JB		 1061 uint32_t status;
1062 uint32_t portRspPut, portRspMax;
1063 int rc = 1;
1064 lpfc_iocb_type type;
1065 unsigned long iflag;
1066 uint32_t rsp_cmpl = 0;
1067 void __iomem *to_slim;
1068
1069 spin_lock_irqsave(phba->host->host_lock, iflag);
1070 pring->stats.iocb_event++;
1071
dea3101e
JB		 1072 /*
1073 * The next available response entry should never exceed the maximum
1074 * entries. If it does, treat it as an adapter hardware error.
1075 */
1076 portRspMax = pring->numRiocb;
1077 portRspPut = le32_to_cpu(pgp->rspPutInx);
1078 if (unlikely(portRspPut >= portRspMax)) {
875fbdfe 1079 lpfc_sli_rsp_pointers_error(phba, pring);
dea3101e
JB		 1080 spin_unlock_irqrestore(phba->host->host_lock, iflag);
1081 return 1;
1082 }
1083
1084 rmb();
1085 while (pring->rspidx != portRspPut) {
87f6eaff
JSEC		 1086 /*
1087 * Fetch an entry off the ring and copy it into a local data
1088 * structure. The copy involves a byte-swap since the
1089 * network byte order and pci byte orders are different.
1090 */
4a0dfcde 1091 entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
875fbdfe
JSEC		 1092
1093 if (++pring->rspidx >= portRspMax)
1094 pring->rspidx = 0;
1095
87f6eaff
JSEC		 1096 lpfc_sli_pcimem_bcopy((uint32_t *) entry,
1097 (uint32_t *) &rspiocbq.iocb,
1098 sizeof (IOCB_t));
a4bc3379 1099 INIT_LIST_HEAD(&(rspiocbq.list));
87f6eaff
JSEC		 1100 irsp = &rspiocbq.iocb;
1101
dea3101e
JB		 1102 type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
1103 pring->stats.iocb_rsp++;
1104 rsp_cmpl++;
1105
1106 if (unlikely(irsp->ulpStatus)) {
1107 /* Rsp ring <ringno> error: IOCB */
1108 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
dca9479b 1109 "%d:0336 Rsp Ring %d error: IOCB Data: "
dea3101e
JB		 1110 "x%x x%x x%x x%x x%x x%x x%x x%x\n",
1111 phba->brd_no, pring->ringno,
1112 irsp->un.ulpWord[0], irsp->un.ulpWord[1],
1113 irsp->un.ulpWord[2], irsp->un.ulpWord[3],
1114 irsp->un.ulpWord[4], irsp->un.ulpWord[5],
1115 *(((uint32_t *) irsp) + 6),
1116 *(((uint32_t *) irsp) + 7));
1117 }
1118
1119 switch (type) {
1120 case LPFC_ABORT_IOCB:
1121 case LPFC_SOL_IOCB:
1122 /*
1123 * Idle exchange closed via ABTS from port. No iocb
1124 * resources need to be recovered.
1125 */
1126 if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
dca9479b
JS		 1127 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
1128 "%d:0333 IOCB cmd 0x%x"
1129 " processed. Skipping"
1130 " completion\n", phba->brd_no,
1131 irsp->ulpCommand);
dea3101e
JB		 1132 break;
1133 }
1134
604a3e30
JB		 1135 cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
1136 &rspiocbq);
dea3101e 1137 if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
b808608b
JW		 1138 if (phba->cfg_poll & ENABLE_FCP_RING_POLLING) {
1139 (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
1140 &rspiocbq);
1141 } else {
1142 spin_unlock_irqrestore(
1143 phba->host->host_lock, iflag);
1144 (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
1145 &rspiocbq);
1146 spin_lock_irqsave(phba->host->host_lock,
1147 iflag);
1148 }
dea3101e
JB		 1149 }
1150 break;
a4bc3379
JS		 1151 case LPFC_UNSOL_IOCB:
1152 spin_unlock_irqrestore(phba->host->host_lock, iflag);
1153 lpfc_sli_process_unsol_iocb(phba, pring, &rspiocbq);
1154 spin_lock_irqsave(phba->host->host_lock, iflag);
1155 break;
dea3101e
JB		 1156 default:
1157 if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
1158 char adaptermsg[LPFC_MAX_ADPTMSG];
1159 memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
1160 memcpy(&adaptermsg[0], (uint8_t *) irsp,
1161 MAX_MSG_DATA);
1162 dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
1163 phba->brd_no, adaptermsg);
1164 } else {
1165 /* Unknown IOCB command */
1166 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
dca9479b 1167 "%d:0334 Unknown IOCB command "
dea3101e
JB		 1168 "Data: x%x, x%x x%x x%x x%x\n",
1169 phba->brd_no, type, irsp->ulpCommand,
1170 irsp->ulpStatus, irsp->ulpIoTag,
1171 irsp->ulpContext);
1172 }
1173 break;
1174 }
1175
1176 /*
1177 * The response IOCB has been processed. Update the ring
1178 * pointer in SLIM. If the port response put pointer has not
1179 * been updated, sync the pgp->rspPutInx and fetch the new port
1180 * response put pointer.
1181 */
dea3101e
JB		 1182 to_slim = phba->MBslimaddr +
1183 (SLIMOFF + (pring->ringno * 2) + 1) * 4;
f91b392c 1184 writel(pring->rspidx, to_slim);
dea3101e
JB		 1185
1186 if (pring->rspidx == portRspPut)
1187 portRspPut = le32_to_cpu(pgp->rspPutInx);
1188 }
1189
1190 if ((rsp_cmpl > 0) && (mask & HA_R0RE_REQ)) {
1191 pring->stats.iocb_rsp_full++;
1192 status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
1193 writel(status, phba->CAregaddr);
1194 readl(phba->CAregaddr);
1195 }
1196 if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
1197 pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
1198 pring->stats.iocb_cmd_empty++;
1199
1200 /* Force update of the local copy of cmdGetInx */
1201 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
1202 lpfc_sli_resume_iocb(phba, pring);
1203
1204 if ((pring->lpfc_sli_cmd_available))
1205 (pring->lpfc_sli_cmd_available) (phba, pring);
1206
1207 }
1208
1209 spin_unlock_irqrestore(phba->host->host_lock, iflag);
1210 return rc;
1211}
1212
1213
1214int
1215lpfc_sli_handle_slow_ring_event(struct lpfc_hba * phba,
1216 struct lpfc_sli_ring * pring, uint32_t mask)
1217{
1218 IOCB_t *entry;
1219 IOCB_t *irsp = NULL;
1220 struct lpfc_iocbq *rspiocbp = NULL;
1221 struct lpfc_iocbq *next_iocb;
1222 struct lpfc_iocbq *cmdiocbp;
1223 struct lpfc_iocbq *saveq;
4cc2da1d 1224 struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
dea3101e
JB		 1225 uint8_t iocb_cmd_type;
1226 lpfc_iocb_type type;
1227 uint32_t status, free_saveq;
1228 uint32_t portRspPut, portRspMax;
1229 int rc = 1;
1230 unsigned long iflag;
1231 void __iomem *to_slim;
1232
1233 spin_lock_irqsave(phba->host->host_lock, iflag);
1234 pring->stats.iocb_event++;
1235
dea3101e
JB		 1236 /*
1237 * The next available response entry should never exceed the maximum
1238 * entries. If it does, treat it as an adapter hardware error.
1239 */
1240 portRspMax = pring->numRiocb;
1241 portRspPut = le32_to_cpu(pgp->rspPutInx);
1242 if (portRspPut >= portRspMax) {
1243 /*
1244 * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
1245 * rsp ring <portRspMax>
1246 */
1247 lpfc_printf_log(phba,
1248 KERN_ERR,
1249 LOG_SLI,
dca9479b 1250 "%d:0303 Ring %d handler: portRspPut %d "
dea3101e
JB		 1251 "is bigger then rsp ring %d\n",
1252 phba->brd_no,
1253 pring->ringno, portRspPut, portRspMax);
1254
1255 phba->hba_state = LPFC_HBA_ERROR;
1256 spin_unlock_irqrestore(phba->host->host_lock, iflag);
1257
1258 phba->work_hs = HS_FFER3;
1259 lpfc_handle_eratt(phba);
1260
1261 return 1;
1262 }
1263
1264 rmb();
dea3101e
JB		 1265 while (pring->rspidx != portRspPut) {
1266 /*
1267 * Build a completion list and call the appropriate handler.
1268 * The process is to get the next available response iocb, get
1269 * a free iocb from the list, copy the response data into the
1270 * free iocb, insert to the continuation list, and update the
1271 * next response index to slim. This process makes response
1272 * iocb's in the ring available to DMA as fast as possible but
1273 * pays a penalty for a copy operation. Since the iocb is
1274 * only 32 bytes, this penalty is considered small relative to
1275 * the PCI reads for register values and a slim write. When
1276 * the ulpLe field is set, the entire Command has been
1277 * received.
1278 */
1279 entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
0bd4ca25 1280 rspiocbp = lpfc_sli_get_iocbq(phba);
dea3101e
JB		 1281 if (rspiocbp == NULL) {
1282 printk(KERN_ERR "%s: out of buffers! Failing "
1283 "completion.\n", __FUNCTION__);
1284 break;
1285 }
1286
1287 lpfc_sli_pcimem_bcopy(entry, &rspiocbp->iocb, sizeof (IOCB_t));
1288 irsp = &rspiocbp->iocb;
1289
1290 if (++pring->rspidx >= portRspMax)
1291 pring->rspidx = 0;
1292
1293 to_slim = phba->MBslimaddr + (SLIMOFF + (pring->ringno * 2)
1294 + 1) * 4;
f91b392c 1295 writel(pring->rspidx, to_slim);
dea3101e
JB		 1296
1297 if (list_empty(&(pring->iocb_continueq))) {
1298 list_add(&rspiocbp->list, &(pring->iocb_continueq));
1299 } else {
1300 list_add_tail(&rspiocbp->list,
1301 &(pring->iocb_continueq));
1302 }
1303
1304 pring->iocb_continueq_cnt++;
1305 if (irsp->ulpLe) {
1306 /*
1307 * By default, the driver expects to free all resources
1308 * associated with this iocb completion.
1309 */
1310 free_saveq = 1;
1311 saveq = list_get_first(&pring->iocb_continueq,
1312 struct lpfc_iocbq, list);
1313 irsp = &(saveq->iocb);
1314 list_del_init(&pring->iocb_continueq);
1315 pring->iocb_continueq_cnt = 0;
1316
1317 pring->stats.iocb_rsp++;
1318
1319 if (irsp->ulpStatus) {
1320 /* Rsp ring <ringno> error: IOCB */
1321 lpfc_printf_log(phba,
1322 KERN_WARNING,
1323 LOG_SLI,
1324 "%d:0328 Rsp Ring %d error: IOCB Data: "
1325 "x%x x%x x%x x%x x%x x%x x%x x%x\n",
1326 phba->brd_no,
1327 pring->ringno,
1328 irsp->un.ulpWord[0],
1329 irsp->un.ulpWord[1],
1330 irsp->un.ulpWord[2],
1331 irsp->un.ulpWord[3],
1332 irsp->un.ulpWord[4],
1333 irsp->un.ulpWord[5],
1334 *(((uint32_t *) irsp) + 6),
1335 *(((uint32_t *) irsp) + 7));
1336 }
1337
1338 /*
1339 * Fetch the IOCB command type and call the correct
1340 * completion routine. Solicited and Unsolicited
1341 * IOCBs on the ELS ring get freed back to the
1342 * lpfc_iocb_list by the discovery kernel thread.
1343 */
1344 iocb_cmd_type = irsp->ulpCommand & CMD_IOCB_MASK;
1345 type = lpfc_sli_iocb_cmd_type(iocb_cmd_type);
1346 if (type == LPFC_SOL_IOCB) {
1347 spin_unlock_irqrestore(phba->host->host_lock,
1348 iflag);
1349 rc = lpfc_sli_process_sol_iocb(phba, pring,
1350 saveq);
1351 spin_lock_irqsave(phba->host->host_lock, iflag);
1352 } else if (type == LPFC_UNSOL_IOCB) {
1353 spin_unlock_irqrestore(phba->host->host_lock,
1354 iflag);
1355 rc = lpfc_sli_process_unsol_iocb(phba, pring,
1356 saveq);
1357 spin_lock_irqsave(phba->host->host_lock, iflag);
1358 } else if (type == LPFC_ABORT_IOCB) {
1359 if ((irsp->ulpCommand != CMD_XRI_ABORTED_CX) &&
1360 ((cmdiocbp =
604a3e30
JB		 1361 lpfc_sli_iocbq_lookup(phba, pring,
1362 saveq)))) {
dea3101e
JB		 1363 /* Call the specified completion
1364 routine */
1365 if (cmdiocbp->iocb_cmpl) {
1366 spin_unlock_irqrestore(
1367 phba->host->host_lock,
1368 iflag);
1369 (cmdiocbp->iocb_cmpl) (phba,
1370 cmdiocbp, saveq);
1371 spin_lock_irqsave(
1372 phba->host->host_lock,
1373 iflag);
604a3e30
JB		 1374 } else
1375 lpfc_sli_release_iocbq(phba,
1376 cmdiocbp);
dea3101e
JB		 1377 }
1378 } else if (type == LPFC_UNKNOWN_IOCB) {
1379 if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
1380
1381 char adaptermsg[LPFC_MAX_ADPTMSG];
1382
1383 memset(adaptermsg, 0,
1384 LPFC_MAX_ADPTMSG);
1385 memcpy(&adaptermsg[0], (uint8_t *) irsp,
1386 MAX_MSG_DATA);
1387 dev_warn(&((phba->pcidev)->dev),
1388 "lpfc%d: %s",
1389 phba->brd_no, adaptermsg);
1390 } else {
1391 /* Unknown IOCB command */
1392 lpfc_printf_log(phba,
1393 KERN_ERR,
1394 LOG_SLI,
dca9479b 1395 "%d:0335 Unknown IOCB command "
dea3101e
JB		 1396 "Data: x%x x%x x%x x%x\n",
1397 phba->brd_no,
1398 irsp->ulpCommand,
1399 irsp->ulpStatus,
1400 irsp->ulpIoTag,
1401 irsp->ulpContext);
1402 }
1403 }
1404
1405 if (free_saveq) {
1406 if (!list_empty(&saveq->list)) {
1407 list_for_each_entry_safe(rspiocbp,
1408 next_iocb,
1409 &saveq->list,
1410 list) {
8f6d98d2 1411 list_del(&rspiocbp->list);
604a3e30
JB		 1412 lpfc_sli_release_iocbq(phba,
1413 rspiocbp);
dea3101e
JB		 1414 }
1415 }
604a3e30 1416 lpfc_sli_release_iocbq(phba, saveq);
dea3101e
JB		 1417 }
1418 }
1419
1420 /*
1421 * If the port response put pointer has not been updated, sync
1422 * the pgp->rspPutInx in the MAILBOX_tand fetch the new port
1423 * response put pointer.
1424 */
1425 if (pring->rspidx == portRspPut) {
1426 portRspPut = le32_to_cpu(pgp->rspPutInx);
1427 }
1428 } /* while (pring->rspidx != portRspPut) */
1429
1430 if ((rspiocbp != 0) && (mask & HA_R0RE_REQ)) {
1431 /* At least one response entry has been freed */
1432 pring->stats.iocb_rsp_full++;
1433 /* SET RxRE_RSP in Chip Att register */
1434 status = ((CA_R0ATT | CA_R0RE_RSP) << (pring->ringno * 4));
1435 writel(status, phba->CAregaddr);
1436 readl(phba->CAregaddr); /* flush */
1437 }
1438 if ((mask & HA_R0CE_RSP) && (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
1439 pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
1440 pring->stats.iocb_cmd_empty++;
1441
1442 /* Force update of the local copy of cmdGetInx */
1443 pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
1444 lpfc_sli_resume_iocb(phba, pring);
1445
1446 if ((pring->lpfc_sli_cmd_available))
1447 (pring->lpfc_sli_cmd_available) (phba, pring);
1448
1449 }
1450
1451 spin_unlock_irqrestore(phba->host->host_lock, iflag);
1452 return rc;
1453}
1454
1455int
1456lpfc_sli_abort_iocb_ring(struct lpfc_hba *phba, struct lpfc_sli_ring *pring)
1457{
1458 struct lpfc_iocbq *iocb, *next_iocb;
1459 IOCB_t *icmd = NULL, *cmd = NULL;
1460 int errcnt;
dea3101e
JB		 1461
1462 errcnt = 0;
1463
1464 /* Error everything on txq and txcmplq
1465 * First do the txq.
1466 */
1467 spin_lock_irq(phba->host->host_lock);
1468 list_for_each_entry_safe(iocb, next_iocb, &pring->txq, list) {
1469 list_del_init(&iocb->list);
1470 if (iocb->iocb_cmpl) {
1471 icmd = &iocb->iocb;
1472 icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
1473 icmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
1474 spin_unlock_irq(phba->host->host_lock);
1475 (iocb->iocb_cmpl) (phba, iocb, iocb);
1476 spin_lock_irq(phba->host->host_lock);
604a3e30
JB		 1477 } else
1478 lpfc_sli_release_iocbq(phba, iocb);
dea3101e
JB		 1479 }
1480 pring->txq_cnt = 0;
1481 INIT_LIST_HEAD(&(pring->txq));
1482
1483 /* Next issue ABTS for everything on the txcmplq */
1484 list_for_each_entry_safe(iocb, next_iocb, &pring->txcmplq, list) {
1485 cmd = &iocb->iocb;
1486
1487 /*
604a3e30 1488 * Imediate abort of IOCB, deque and call compl
dea3101e 1489 */
dea3101e
JB		 1490
1491 list_del_init(&iocb->list);
1492 pring->txcmplq_cnt--;
1493
1494 if (iocb->iocb_cmpl) {
1495 cmd->ulpStatus = IOSTAT_LOCAL_REJECT;
1496 cmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
1497 spin_unlock_irq(phba->host->host_lock);
1498 (iocb->iocb_cmpl) (phba, iocb, iocb);
1499 spin_lock_irq(phba->host->host_lock);
604a3e30
JB		 1500 } else
1501 lpfc_sli_release_iocbq(phba, iocb);
dea3101e
JB		 1502 }
1503
1504 INIT_LIST_HEAD(&pring->txcmplq);
1505 pring->txcmplq_cnt = 0;
1506 spin_unlock_irq(phba->host->host_lock);
1507
1508 return errcnt;
1509}
1510
41415862
JW		 1511int
1512lpfc_sli_brdready(struct lpfc_hba * phba, uint32_t mask)
dea3101e 1513{
41415862
JW		 1514 uint32_t status;
1515 int i = 0;
1516 int retval = 0;
dea3101e 1517
41415862
JW		 1518 /* Read the HBA Host Status Register */
1519 status = readl(phba->HSregaddr);
dea3101e 1520
41415862
JW		 1521 /*
1522 * Check status register every 100ms for 5 retries, then every
1523 * 500ms for 5, then every 2.5 sec for 5, then reset board and
1524 * every 2.5 sec for 4.
1525 * Break our of the loop if errors occurred during init.
1526 */
1527 while (((status & mask) != mask) &&
1528 !(status & HS_FFERM) &&
1529 i++ < 20) {
dea3101e 1530
41415862
JW		 1531 if (i <= 5)
1532 msleep(10);
1533 else if (i <= 10)
1534 msleep(500);
1535 else
1536 msleep(2500);
dea3101e 1537
41415862
JW		 1538 if (i == 15) {
1539 phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
1540 lpfc_sli_brdrestart(phba);
1541 }
1542 /* Read the HBA Host Status Register */
1543 status = readl(phba->HSregaddr);
1544 }
dea3101e 1545
41415862
JW		 1546 /* Check to see if any errors occurred during init */
1547 if ((status & HS_FFERM) || (i >= 20)) {
1548 phba->hba_state = LPFC_HBA_ERROR;
1549 retval = 1;
dea3101e 1550 }
dea3101e 1551
41415862
JW		 1552 return retval;
1553}
dea3101e 1554
9290831f
JS		 1555#define BARRIER_TEST_PATTERN (0xdeadbeef)
1556
1557void lpfc_reset_barrier(struct lpfc_hba * phba)
1558{
65a29c16
JS		 1559 uint32_t __iomem *resp_buf;
1560 uint32_t __iomem *mbox_buf;
9290831f
JS		 1561 volatile uint32_t mbox;
1562 uint32_t hc_copy;
1563 int i;
1564 uint8_t hdrtype;
1565
1566 pci_read_config_byte(phba->pcidev, PCI_HEADER_TYPE, &hdrtype);
1567 if (hdrtype != 0x80 ||
1568 (FC_JEDEC_ID(phba->vpd.rev.biuRev) != HELIOS_JEDEC_ID &&
1569 FC_JEDEC_ID(phba->vpd.rev.biuRev) != THOR_JEDEC_ID))
1570 return;
1571
1572 /*
1573 * Tell the other part of the chip to suspend temporarily all
1574 * its DMA activity.
1575 */
65a29c16 1576 resp_buf = phba->MBslimaddr;
9290831f
JS		 1577
1578 /* Disable the error attention */
1579 hc_copy = readl(phba->HCregaddr);
1580 writel((hc_copy & ~HC_ERINT_ENA), phba->HCregaddr);
1581 readl(phba->HCregaddr); /* flush */
1582
1583 if (readl(phba->HAregaddr) & HA_ERATT) {
1584 /* Clear Chip error bit */
1585 writel(HA_ERATT, phba->HAregaddr);
1586 phba->stopped = 1;
1587 }
1588
1589 mbox = 0;
1590 ((MAILBOX_t *)&mbox)->mbxCommand = MBX_KILL_BOARD;
1591 ((MAILBOX_t *)&mbox)->mbxOwner = OWN_CHIP;
1592
1593 writel(BARRIER_TEST_PATTERN, (resp_buf + 1));
65a29c16 1594 mbox_buf = phba->MBslimaddr;
9290831f
JS		 1595 writel(mbox, mbox_buf);
1596
1597 for (i = 0;
1598 readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN) && i < 50; i++)
1599 mdelay(1);
1600
1601 if (readl(resp_buf + 1) != ~(BARRIER_TEST_PATTERN)) {
1602 if (phba->sli.sli_flag & LPFC_SLI2_ACTIVE ||
1603 phba->stopped)
1604 goto restore_hc;
1605 else
1606 goto clear_errat;
1607 }
1608
1609 ((MAILBOX_t *)&mbox)->mbxOwner = OWN_HOST;
1610 for (i = 0; readl(resp_buf) != mbox && i < 500; i++)
1611 mdelay(1);
1612
1613clear_errat:
1614
1615 while (!(readl(phba->HAregaddr) & HA_ERATT) && ++i < 500)
1616 mdelay(1);
1617
1618 if (readl(phba->HAregaddr) & HA_ERATT) {
1619 writel(HA_ERATT, phba->HAregaddr);
1620 phba->stopped = 1;
1621 }
1622
1623restore_hc:
1624 writel(hc_copy, phba->HCregaddr);
1625 readl(phba->HCregaddr); /* flush */
1626}
1627
41415862
JW		 1628int
1629lpfc_sli_brdkill(struct lpfc_hba * phba)
1630{
1631 struct lpfc_sli *psli;
1632 LPFC_MBOXQ_t *pmb;
1633 uint32_t status;
1634 uint32_t ha_copy;
1635 int retval;
1636 int i = 0;
dea3101e 1637
41415862 1638 psli = &phba->sli;
dea3101e 1639
41415862
JW		 1640 /* Kill HBA */
1641 lpfc_printf_log(phba,
1642 KERN_INFO,
1643 LOG_SLI,
1644 "%d:0329 Kill HBA Data: x%x x%x\n",
1645 phba->brd_no,
1646 phba->hba_state,
1647 psli->sli_flag);
1648
1649 if ((pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9290831f 1650 GFP_KERNEL)) == 0)
41415862 1651 return 1;
41415862
JW		 1652
1653 /* Disable the error attention */
1654 spin_lock_irq(phba->host->host_lock);
1655 status = readl(phba->HCregaddr);
1656 status &= ~HC_ERINT_ENA;
1657 writel(status, phba->HCregaddr);
1658 readl(phba->HCregaddr); /* flush */
1659 spin_unlock_irq(phba->host->host_lock);
1660
1661 lpfc_kill_board(phba, pmb);
1662 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1663 retval = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
1664
1665 if (retval != MBX_SUCCESS) {
1666 if (retval != MBX_BUSY)
1667 mempool_free(pmb, phba->mbox_mem_pool);
1668 return 1;
1669 }
1670
9290831f
JS		 1671 psli->sli_flag &= ~LPFC_SLI2_ACTIVE;
1672
41415862
JW		 1673 mempool_free(pmb, phba->mbox_mem_pool);
1674
1675 /* There is no completion for a KILL_BOARD mbox cmd. Check for an error
1676 * attention every 100ms for 3 seconds. If we don't get ERATT after
1677 * 3 seconds we still set HBA_ERROR state because the status of the
1678 * board is now undefined.
1679 */
1680 ha_copy = readl(phba->HAregaddr);
1681
1682 while ((i++ < 30) && !(ha_copy & HA_ERATT)) {
1683 mdelay(100);
1684 ha_copy = readl(phba->HAregaddr);
1685 }
1686
1687 del_timer_sync(&psli->mbox_tmo);
9290831f
JS		 1688 if (ha_copy & HA_ERATT) {
1689 writel(HA_ERATT, phba->HAregaddr);
1690 phba->stopped = 1;
1691 }
41415862
JW		 1692 spin_lock_irq(phba->host->host_lock);
1693 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
1694 spin_unlock_irq(phba->host->host_lock);
1695
1696 psli->mbox_active = NULL;
1697 lpfc_hba_down_post(phba);
1698 phba->hba_state = LPFC_HBA_ERROR;
1699
1700 return (ha_copy & HA_ERATT ? 0 : 1);
dea3101e
JB		 1701}
1702
41415862
JW		 1703int
1704lpfc_sli_brdreset(struct lpfc_hba * phba)
dea3101e 1705{
41415862 1706 struct lpfc_sli *psli;
dea3101e 1707 struct lpfc_sli_ring *pring;
41415862 1708 uint16_t cfg_value;
dea3101e 1709 int i;
dea3101e 1710
41415862 1711 psli = &phba->sli;
dea3101e 1712
41415862
JW		 1713 /* Reset HBA */
1714 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
1715 "%d:0325 Reset HBA Data: x%x x%x\n", phba->brd_no,
1716 phba->hba_state, psli->sli_flag);
dea3101e
JB		 1717
1718 /* perform board reset */
1719 phba->fc_eventTag = 0;
1720 phba->fc_myDID = 0;
41415862 1721 phba->fc_prevDID = 0;
dea3101e 1722
41415862
JW		 1723 /* Turn off parity checking and serr during the physical reset */
1724 pci_read_config_word(phba->pcidev, PCI_COMMAND, &cfg_value);
1725 pci_write_config_word(phba->pcidev, PCI_COMMAND,
1726 (cfg_value &
1727 ~(PCI_COMMAND_PARITY | PCI_COMMAND_SERR)));
1728
1c067a42 1729 psli->sli_flag &= ~(LPFC_SLI2_ACTIVE | LPFC_PROCESS_LA);
41415862
JW		 1730 /* Now toggle INITFF bit in the Host Control Register */
1731 writel(HC_INITFF, phba->HCregaddr);
1732 mdelay(1);
1733 readl(phba->HCregaddr); /* flush */
1734 writel(0, phba->HCregaddr);
1735 readl(phba->HCregaddr); /* flush */
1736
1737 /* Restore PCI cmd register */
1738 pci_write_config_word(phba->pcidev, PCI_COMMAND, cfg_value);
dea3101e
JB		 1739
1740 /* Initialize relevant SLI info */
41415862
JW		 1741 for (i = 0; i < psli->num_rings; i++) {
1742 pring = &psli->ring[i];
dea3101e
JB		 1743 pring->flag = 0;
1744 pring->rspidx = 0;
1745 pring->next_cmdidx = 0;
1746 pring->local_getidx = 0;
1747 pring->cmdidx = 0;
1748 pring->missbufcnt = 0;
1749 }
dea3101e 1750
41415862
JW		 1751 phba->hba_state = LPFC_WARM_START;
1752 return 0;
1753}
1754
1755int
1756lpfc_sli_brdrestart(struct lpfc_hba * phba)
1757{
1758 MAILBOX_t *mb;
1759 struct lpfc_sli *psli;
1760 uint16_t skip_post;
1761 volatile uint32_t word0;
1762 void __iomem *to_slim;
1763
1764 spin_lock_irq(phba->host->host_lock);
1765
1766 psli = &phba->sli;
1767
1768 /* Restart HBA */
1769 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
dca9479b 1770 "%d:0337 Restart HBA Data: x%x x%x\n", phba->brd_no,
41415862
JW		 1771 phba->hba_state, psli->sli_flag);
1772
1773 word0 = 0;
1774 mb = (MAILBOX_t *) &word0;
1775 mb->mbxCommand = MBX_RESTART;
1776 mb->mbxHc = 1;
1777
9290831f
JS		 1778 lpfc_reset_barrier(phba);
1779
41415862
JW		 1780 to_slim = phba->MBslimaddr;
1781 writel(*(uint32_t *) mb, to_slim);
1782 readl(to_slim); /* flush */
1783
1784 /* Only skip post after fc_ffinit is completed */
1785 if (phba->hba_state) {
1786 skip_post = 1;
1787 word0 = 1; /* This is really setting up word1 */
dea3101e 1788 } else {
41415862
JW		 1789 skip_post = 0;
1790 word0 = 0; /* This is really setting up word1 */
dea3101e 1791 }
65a29c16 1792 to_slim = phba->MBslimaddr + sizeof (uint32_t);
41415862
JW		 1793 writel(*(uint32_t *) mb, to_slim);
1794 readl(to_slim); /* flush */
dea3101e 1795
41415862 1796 lpfc_sli_brdreset(phba);
9290831f 1797 phba->stopped = 0;
41415862
JW		 1798 phba->hba_state = LPFC_INIT_START;
1799
1800 spin_unlock_irq(phba->host->host_lock);
1801
64ba8818
JS		 1802 memset(&psli->lnk_stat_offsets, 0, sizeof(psli->lnk_stat_offsets));
1803 psli->stats_start = get_seconds();
1804
41415862
JW		 1805 if (skip_post)
1806 mdelay(100);
1807 else
1808 mdelay(2000);
1809
1810 lpfc_hba_down_post(phba);
dea3101e
JB		 1811
1812 return 0;
1813}
1814
1815static int
1816lpfc_sli_chipset_init(struct lpfc_hba *phba)
1817{
1818 uint32_t status, i = 0;
1819
1820 /* Read the HBA Host Status Register */
1821 status = readl(phba->HSregaddr);
1822
1823 /* Check status register to see what current state is */
1824 i = 0;
1825 while ((status & (HS_FFRDY | HS_MBRDY)) != (HS_FFRDY | HS_MBRDY)) {
1826
1827 /* Check every 100ms for 5 retries, then every 500ms for 5, then
1828 * every 2.5 sec for 5, then reset board and every 2.5 sec for
1829 * 4.
1830 */
1831 if (i++ >= 20) {
1832 /* Adapter failed to init, timeout, status reg
1833 <status> */
1834 lpfc_printf_log(phba,
1835 KERN_ERR,
1836 LOG_INIT,
1837 "%d:0436 Adapter failed to init, "
1838 "timeout, status reg x%x\n",
1839 phba->brd_no,
1840 status);
1841 phba->hba_state = LPFC_HBA_ERROR;
1842 return -ETIMEDOUT;
1843 }
1844
1845 /* Check to see if any errors occurred during init */
1846 if (status & HS_FFERM) {
1847 /* ERROR: During chipset initialization */
1848 /* Adapter failed to init, chipset, status reg
1849 <status> */
1850 lpfc_printf_log(phba,
1851 KERN_ERR,
1852 LOG_INIT,
1853 "%d:0437 Adapter failed to init, "
1854 "chipset, status reg x%x\n",
1855 phba->brd_no,
1856 status);
1857 phba->hba_state = LPFC_HBA_ERROR;
1858 return -EIO;
1859 }
1860
1861 if (i <= 5) {
1862 msleep(10);
1863 } else if (i <= 10) {
1864 msleep(500);
1865 } else {
1866 msleep(2500);
1867 }
1868
1869 if (i == 15) {
41415862
JW		 1870 phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
1871 lpfc_sli_brdrestart(phba);
dea3101e
JB		 1872 }
1873 /* Read the HBA Host Status Register */
1874 status = readl(phba->HSregaddr);
1875 }
1876
1877 /* Check to see if any errors occurred during init */
1878 if (status & HS_FFERM) {
1879 /* ERROR: During chipset initialization */
1880 /* Adapter failed to init, chipset, status reg <status> */
1881 lpfc_printf_log(phba,
1882 KERN_ERR,
1883 LOG_INIT,
1884 "%d:0438 Adapter failed to init, chipset, "
1885 "status reg x%x\n",
1886 phba->brd_no,
1887 status);
1888 phba->hba_state = LPFC_HBA_ERROR;
1889 return -EIO;
1890 }
1891
1892 /* Clear all interrupt enable conditions */
1893 writel(0, phba->HCregaddr);
1894 readl(phba->HCregaddr); /* flush */
1895
1896 /* setup host attn register */
1897 writel(0xffffffff, phba->HAregaddr);
1898 readl(phba->HAregaddr); /* flush */
1899 return 0;
1900}
1901
1902int
1903lpfc_sli_hba_setup(struct lpfc_hba * phba)
1904{
1905 LPFC_MBOXQ_t *pmb;
1906 uint32_t resetcount = 0, rc = 0, done = 0;
1907
1908 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
1909 if (!pmb) {
1910 phba->hba_state = LPFC_HBA_ERROR;
1911 return -ENOMEM;
1912 }
1913
1914 while (resetcount < 2 && !done) {
1c067a42
JS		 1915 spin_lock_irq(phba->host->host_lock);
1916 phba->sli.sli_flag |= LPFC_SLI_MBOX_ACTIVE;
1917 spin_unlock_irq(phba->host->host_lock);
41415862
JW		 1918 phba->hba_state = LPFC_STATE_UNKNOWN;
1919 lpfc_sli_brdrestart(phba);
dea3101e
JB		 1920 msleep(2500);
1921 rc = lpfc_sli_chipset_init(phba);
1922 if (rc)
1923 break;
1924
1c067a42
JS		 1925 spin_lock_irq(phba->host->host_lock);
1926 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
1927 spin_unlock_irq(phba->host->host_lock);
dea3101e
JB		 1928 resetcount++;
1929
1930 /* Call pre CONFIG_PORT mailbox command initialization. A value of 0
1931 * means the call was successful. Any other nonzero value is a failure,
1932 * but if ERESTART is returned, the driver may reset the HBA and try
1933 * again.
1934 */
1935 rc = lpfc_config_port_prep(phba);
1936 if (rc == -ERESTART) {
1937 phba->hba_state = 0;
1938 continue;
1939 } else if (rc) {
1940 break;
1941 }
1942
1943 phba->hba_state = LPFC_INIT_MBX_CMDS;
1944 lpfc_config_port(phba, pmb);
1945 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
1946 if (rc == MBX_SUCCESS)
1947 done = 1;
1948 else {
1949 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1950 "%d:0442 Adapter failed to init, mbxCmd x%x "
1951 "CONFIG_PORT, mbxStatus x%x Data: x%x\n",
1952 phba->brd_no, pmb->mb.mbxCommand,
1953 pmb->mb.mbxStatus, 0);
1954 phba->sli.sli_flag &= ~LPFC_SLI2_ACTIVE;
1955 }
1956 }
1957 if (!done)
1958 goto lpfc_sli_hba_setup_error;
1959
1960 rc = lpfc_sli_ring_map(phba, pmb);
1961
1962 if (rc)
1963 goto lpfc_sli_hba_setup_error;
1964
1965 phba->sli.sli_flag |= LPFC_PROCESS_LA;
1966
1967 rc = lpfc_config_port_post(phba);
1968 if (rc)
1969 goto lpfc_sli_hba_setup_error;
1970
1971 goto lpfc_sli_hba_setup_exit;
1972lpfc_sli_hba_setup_error:
1973 phba->hba_state = LPFC_HBA_ERROR;
1974lpfc_sli_hba_setup_exit:
1975 mempool_free(pmb, phba->mbox_mem_pool);
1976 return rc;
1977}
1978
dea3101e
JB		 1979/*! lpfc_mbox_timeout
1980 *
1981 * \pre
1982 * \post
1983 * \param hba Pointer to per struct lpfc_hba structure
1984 * \param l1 Pointer to the driver's mailbox queue.
1985 * \return
1986 * void
1987 *
1988 * \b Description:
1989 *
1990 * This routine handles mailbox timeout events at timer interrupt context.
1991 */
1992void
1993lpfc_mbox_timeout(unsigned long ptr)
1994{
1995 struct lpfc_hba *phba;
1996 unsigned long iflag;
1997
1998 phba = (struct lpfc_hba *)ptr;
1999 spin_lock_irqsave(phba->host->host_lock, iflag);
2000 if (!(phba->work_hba_events & WORKER_MBOX_TMO)) {
2001 phba->work_hba_events |= WORKER_MBOX_TMO;
2002 if (phba->work_wait)
2003 wake_up(phba->work_wait);
2004 }
2005 spin_unlock_irqrestore(phba->host->host_lock, iflag);
2006}
2007
2008void
2009lpfc_mbox_timeout_handler(struct lpfc_hba *phba)
2010{
2011 LPFC_MBOXQ_t *pmbox;
2012 MAILBOX_t *mb;
1dcb58e5
JS		 2013 struct lpfc_sli *psli = &phba->sli;
2014 struct lpfc_sli_ring *pring;
dea3101e
JB		 2015
2016 spin_lock_irq(phba->host->host_lock);
2017 if (!(phba->work_hba_events & WORKER_MBOX_TMO)) {
2018 spin_unlock_irq(phba->host->host_lock);
2019 return;
2020 }
2021
2022 pmbox = phba->sli.mbox_active;
2023 mb = &pmbox->mb;
2024
2025 /* Mbox cmd <mbxCommand> timeout */
2026 lpfc_printf_log(phba,
2027 KERN_ERR,
2028 LOG_MBOX | LOG_SLI,
2029 "%d:0310 Mailbox command x%x timeout Data: x%x x%x x%p\n",
2030 phba->brd_no,
2031 mb->mbxCommand,
2032 phba->hba_state,
2033 phba->sli.sli_flag,
2034 phba->sli.mbox_active);
2035
1dcb58e5
JS		 2036 /* Setting state unknown so lpfc_sli_abort_iocb_ring
2037 * would get IOCB_ERROR from lpfc_sli_issue_iocb, allowing
2038 * it to fail all oustanding SCSI IO.
2039 */
2040 phba->hba_state = LPFC_STATE_UNKNOWN;
2041 phba->work_hba_events &= ~WORKER_MBOX_TMO;
2042 phba->fc_flag |= FC_ESTABLISH_LINK;
2043 psli->sli_flag &= ~LPFC_SLI2_ACTIVE;
dea3101e 2044 spin_unlock_irq(phba->host->host_lock);
1dcb58e5
JS		 2045
2046 pring = &psli->ring[psli->fcp_ring];
2047 lpfc_sli_abort_iocb_ring(phba, pring);
2048
2049 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
2050 "%d:0316 Resetting board due to mailbox timeout\n",
2051 phba->brd_no);
2052 /*
2053 * lpfc_offline calls lpfc_sli_hba_down which will clean up
2054 * on oustanding mailbox commands.
2055 */
2056 lpfc_offline_prep(phba);
2057 lpfc_offline(phba);
2058 lpfc_sli_brdrestart(phba);
2059 if (lpfc_online(phba) == 0) /* Initialize the HBA */
2060 mod_timer(&phba->fc_estabtmo, jiffies + HZ * 60);
2061 lpfc_unblock_mgmt_io(phba);
dea3101e
JB		 2062 return;
2063}
2064
2065int
2066lpfc_sli_issue_mbox(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmbox, uint32_t flag)
2067{
dea3101e
JB		 2068 MAILBOX_t *mb;
2069 struct lpfc_sli *psli;
2070 uint32_t status, evtctr;
2071 uint32_t ha_copy;
2072 int i;
2073 unsigned long drvr_flag = 0;
2074 volatile uint32_t word0, ldata;
2075 void __iomem *to_slim;
2076
8d63f375
LV		 2077 /* If the PCI channel is in offline state, do not post mbox. */
2078 if (unlikely(pci_channel_offline(phba->pcidev)))
2079 return MBX_NOT_FINISHED;
2080
dea3101e
JB		 2081 psli = &phba->sli;
2082
2083 spin_lock_irqsave(phba->host->host_lock, drvr_flag);
2084
2085
2086 mb = &pmbox->mb;
2087 status = MBX_SUCCESS;
2088
41415862
JW		 2089 if (phba->hba_state == LPFC_HBA_ERROR) {
2090 spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
2091
2092 /* Mbox command <mbxCommand> cannot issue */
2093 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
2094 return (MBX_NOT_FINISHED);
2095 }
2096
9290831f
JS		 2097 if (mb->mbxCommand != MBX_KILL_BOARD && flag & MBX_NOWAIT &&
2098 !(readl(phba->HCregaddr) & HC_MBINT_ENA)) {
2099 spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
2100 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
2101 return (MBX_NOT_FINISHED);
2102 }
2103
dea3101e
JB		 2104 if (psli->sli_flag & LPFC_SLI_MBOX_ACTIVE) {
2105 /* Polling for a mbox command when another one is already active
2106 * is not allowed in SLI. Also, the driver must have established
2107 * SLI2 mode to queue and process multiple mbox commands.
2108 */
2109
2110 if (flag & MBX_POLL) {
2111 spin_unlock_irqrestore(phba->host->host_lock,
2112 drvr_flag);
2113
2114 /* Mbox command <mbxCommand> cannot issue */
2115 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
2116 return (MBX_NOT_FINISHED);
2117 }
2118
2119 if (!(psli->sli_flag & LPFC_SLI2_ACTIVE)) {
2120 spin_unlock_irqrestore(phba->host->host_lock,
2121 drvr_flag);
2122 /* Mbox command <mbxCommand> cannot issue */
2123 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
2124 return (MBX_NOT_FINISHED);
2125 }
2126
2127 /* Handle STOP IOCB processing flag. This is only meaningful
2128 * if we are not polling for mbox completion.
2129 */
2130 if (flag & MBX_STOP_IOCB) {
2131 flag &= ~MBX_STOP_IOCB;
2132 /* Now flag each ring */
2133 for (i = 0; i < psli->num_rings; i++) {
2134 /* If the ring is active, flag it */
2135 if (psli->ring[i].cmdringaddr) {
2136 psli->ring[i].flag |=
2137 LPFC_STOP_IOCB_MBX;
2138 }
2139 }
2140 }
2141
2142 /* Another mailbox command is still being processed, queue this
2143 * command to be processed later.
2144 */
2145 lpfc_mbox_put(phba, pmbox);
2146
2147 /* Mbox cmd issue - BUSY */
2148 lpfc_printf_log(phba,
2149 KERN_INFO,
2150 LOG_MBOX | LOG_SLI,
2151 "%d:0308 Mbox cmd issue - BUSY Data: x%x x%x x%x x%x\n",
2152 phba->brd_no,
2153 mb->mbxCommand,
2154 phba->hba_state,
2155 psli->sli_flag,
2156 flag);
2157
2158 psli->slistat.mbox_busy++;
2159 spin_unlock_irqrestore(phba->host->host_lock,
2160 drvr_flag);
2161
2162 return (MBX_BUSY);
2163 }
2164
2165 /* Handle STOP IOCB processing flag. This is only meaningful
2166 * if we are not polling for mbox completion.
2167 */
2168 if (flag & MBX_STOP_IOCB) {
2169 flag &= ~MBX_STOP_IOCB;
2170 if (flag == MBX_NOWAIT) {
2171 /* Now flag each ring */
2172 for (i = 0; i < psli->num_rings; i++) {
2173 /* If the ring is active, flag it */
2174 if (psli->ring[i].cmdringaddr) {
2175 psli->ring[i].flag |=
2176 LPFC_STOP_IOCB_MBX;
2177 }
2178 }
2179 }
2180 }
2181
2182 psli->sli_flag |= LPFC_SLI_MBOX_ACTIVE;
2183
2184 /* If we are not polling, we MUST be in SLI2 mode */
2185 if (flag != MBX_POLL) {
41415862
JW		 2186 if (!(psli->sli_flag & LPFC_SLI2_ACTIVE) &&
2187 (mb->mbxCommand != MBX_KILL_BOARD)) {
dea3101e
JB		 2188 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2189 spin_unlock_irqrestore(phba->host->host_lock,
2190 drvr_flag);
2191 /* Mbox command <mbxCommand> cannot issue */
2192 LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag);
2193 return (MBX_NOT_FINISHED);
2194 }
2195 /* timeout active mbox command */
a309a6b6
JS		 2196 mod_timer(&psli->mbox_tmo, (jiffies +
2197 (HZ * lpfc_mbox_tmo_val(phba, mb->mbxCommand))));
dea3101e
JB		 2198 }
2199
2200 /* Mailbox cmd <cmd> issue */
2201 lpfc_printf_log(phba,
2202 KERN_INFO,
2203 LOG_MBOX | LOG_SLI,
2204 "%d:0309 Mailbox cmd x%x issue Data: x%x x%x x%x\n",
2205 phba->brd_no,
2206 mb->mbxCommand,
2207 phba->hba_state,
2208 psli->sli_flag,
2209 flag);
2210
2211 psli->slistat.mbox_cmd++;
2212 evtctr = psli->slistat.mbox_event;
2213
2214 /* next set own bit for the adapter and copy over command word */
2215 mb->mbxOwner = OWN_CHIP;
2216
2217 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
dea3101e 2218 /* First copy command data to host SLIM area */
4cc2da1d 2219 lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx, MAILBOX_CMD_SIZE);
dea3101e 2220 } else {
9290831f 2221 if (mb->mbxCommand == MBX_CONFIG_PORT) {
dea3101e 2222 /* copy command data into host mbox for cmpl */
4cc2da1d
JSEC		 2223 lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx,
2224 MAILBOX_CMD_SIZE);
dea3101e
JB		 2225 }
2226
2227 /* First copy mbox command data to HBA SLIM, skip past first
2228 word */
2229 to_slim = phba->MBslimaddr + sizeof (uint32_t);
2230 lpfc_memcpy_to_slim(to_slim, &mb->un.varWords[0],
2231 MAILBOX_CMD_SIZE - sizeof (uint32_t));
2232
2233 /* Next copy over first word, with mbxOwner set */
2234 ldata = *((volatile uint32_t *)mb);
2235 to_slim = phba->MBslimaddr;
2236 writel(ldata, to_slim);
2237 readl(to_slim); /* flush */
2238
2239 if (mb->mbxCommand == MBX_CONFIG_PORT) {
2240 /* switch over to host mailbox */
2241 psli->sli_flag |= LPFC_SLI2_ACTIVE;
2242 }
2243 }
2244
2245 wmb();
2246 /* interrupt board to doit right away */
2247 writel(CA_MBATT, phba->CAregaddr);
2248 readl(phba->CAregaddr); /* flush */
2249
2250 switch (flag) {
2251 case MBX_NOWAIT:
2252 /* Don't wait for it to finish, just return */
2253 psli->mbox_active = pmbox;
2254 break;
2255
2256 case MBX_POLL:
dea3101e
JB		 2257 psli->mbox_active = NULL;
2258 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
2259 /* First read mbox status word */
4cc2da1d 2260 word0 = *((volatile uint32_t *)&phba->slim2p->mbx);
dea3101e
JB		 2261 word0 = le32_to_cpu(word0);
2262 } else {
2263 /* First read mbox status word */
2264 word0 = readl(phba->MBslimaddr);
2265 }
2266
2267 /* Read the HBA Host Attention Register */
2268 ha_copy = readl(phba->HAregaddr);
2269
a309a6b6
JS		 2270 i = lpfc_mbox_tmo_val(phba, mb->mbxCommand);
2271 i *= 1000; /* Convert to ms */
2272
dea3101e 2273 /* Wait for command to complete */
41415862
JW		 2274 while (((word0 & OWN_CHIP) == OWN_CHIP) ||
2275 (!(ha_copy & HA_MBATT) &&
2276 (phba->hba_state > LPFC_WARM_START))) {
a309a6b6 2277 if (i-- <= 0) {
dea3101e
JB		 2278 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2279 spin_unlock_irqrestore(phba->host->host_lock,
2280 drvr_flag);
2281 return (MBX_NOT_FINISHED);
2282 }
2283
2284 /* Check if we took a mbox interrupt while we were
2285 polling */
2286 if (((word0 & OWN_CHIP) != OWN_CHIP)
2287 && (evtctr != psli->slistat.mbox_event))
2288 break;
2289
2290 spin_unlock_irqrestore(phba->host->host_lock,
2291 drvr_flag);
2292
1dcb58e5 2293 msleep(1);
dea3101e
JB		 2294
2295 spin_lock_irqsave(phba->host->host_lock, drvr_flag);
2296
2297 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
2298 /* First copy command data */
4cc2da1d
JSEC		 2299 word0 = *((volatile uint32_t *)
2300 &phba->slim2p->mbx);
dea3101e
JB		 2301 word0 = le32_to_cpu(word0);
2302 if (mb->mbxCommand == MBX_CONFIG_PORT) {
2303 MAILBOX_t *slimmb;
2304 volatile uint32_t slimword0;
2305 /* Check real SLIM for any errors */
2306 slimword0 = readl(phba->MBslimaddr);
2307 slimmb = (MAILBOX_t *) & slimword0;
2308 if (((slimword0 & OWN_CHIP) != OWN_CHIP)
2309 && slimmb->mbxStatus) {
2310 psli->sli_flag &=
2311 ~LPFC_SLI2_ACTIVE;
2312 word0 = slimword0;
2313 }
2314 }
2315 } else {
2316 /* First copy command data */
2317 word0 = readl(phba->MBslimaddr);
2318 }
2319 /* Read the HBA Host Attention Register */
2320 ha_copy = readl(phba->HAregaddr);
2321 }
2322
2323 if (psli->sli_flag & LPFC_SLI2_ACTIVE) {
dea3101e 2324 /* copy results back to user */
4cc2da1d
JSEC		 2325 lpfc_sli_pcimem_bcopy(&phba->slim2p->mbx, mb,
2326 MAILBOX_CMD_SIZE);
dea3101e
JB		 2327 } else {
2328 /* First copy command data */
2329 lpfc_memcpy_from_slim(mb, phba->MBslimaddr,
2330 MAILBOX_CMD_SIZE);
2331 if ((mb->mbxCommand == MBX_DUMP_MEMORY) &&
2332 pmbox->context2) {
2333 lpfc_memcpy_from_slim((void *)pmbox->context2,
2334 phba->MBslimaddr + DMP_RSP_OFFSET,
2335 mb->un.varDmp.word_cnt);
2336 }
2337 }
2338
2339 writel(HA_MBATT, phba->HAregaddr);
2340 readl(phba->HAregaddr); /* flush */
2341
2342 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2343 status = mb->mbxStatus;
2344 }
2345
2346 spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
2347 return (status);
2348}
2349
2350static int
2351lpfc_sli_ringtx_put(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
2352 struct lpfc_iocbq * piocb)
2353{
2354 /* Insert the caller's iocb in the txq tail for later processing. */
2355 list_add_tail(&piocb->list, &pring->txq);
2356 pring->txq_cnt++;
2357 return (0);
2358}
2359
2360static struct lpfc_iocbq *
2361lpfc_sli_next_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2362 struct lpfc_iocbq ** piocb)
2363{
2364 struct lpfc_iocbq * nextiocb;
2365
2366 nextiocb = lpfc_sli_ringtx_get(phba, pring);
2367 if (!nextiocb) {
2368 nextiocb = *piocb;
2369 *piocb = NULL;
2370 }
2371
2372 return nextiocb;
2373}
2374
2375int
2376lpfc_sli_issue_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2377 struct lpfc_iocbq *piocb, uint32_t flag)
2378{
2379 struct lpfc_iocbq *nextiocb;
2380 IOCB_t *iocb;
2381
8d63f375
LV		 2382 /* If the PCI channel is in offline state, do not post iocbs. */
2383 if (unlikely(pci_channel_offline(phba->pcidev)))
2384 return IOCB_ERROR;
2385
dea3101e
JB		 2386 /*
2387 * We should never get an IOCB if we are in a < LINK_DOWN state
2388 */
2389 if (unlikely(phba->hba_state < LPFC_LINK_DOWN))
2390 return IOCB_ERROR;
2391
2392 /*
2393 * Check to see if we are blocking IOCB processing because of a
2394 * outstanding mbox command.
2395 */
2396 if (unlikely(pring->flag & LPFC_STOP_IOCB_MBX))
2397 goto iocb_busy;
2398
2399 if (unlikely(phba->hba_state == LPFC_LINK_DOWN)) {
2400 /*
2401 * Only CREATE_XRI, CLOSE_XRI, ABORT_XRI, and QUE_RING_BUF
2402 * can be issued if the link is not up.
2403 */
2404 switch (piocb->iocb.ulpCommand) {
2405 case CMD_QUE_RING_BUF_CN:
2406 case CMD_QUE_RING_BUF64_CN:
dea3101e
JB		 2407 /*
2408 * For IOCBs, like QUE_RING_BUF, that have no rsp ring
2409 * completion, iocb_cmpl MUST be 0.
2410 */
2411 if (piocb->iocb_cmpl)
2412 piocb->iocb_cmpl = NULL;
2413 /*FALLTHROUGH*/
2414 case CMD_CREATE_XRI_CR:
2415 break;
2416 default:
2417 goto iocb_busy;
2418 }
2419
2420 /*
2421 * For FCP commands, we must be in a state where we can process link
2422 * attention events.
2423 */
2424 } else if (unlikely(pring->ringno == phba->sli.fcp_ring &&
2425 !(phba->sli.sli_flag & LPFC_PROCESS_LA)))
2426 goto iocb_busy;
2427
dea3101e
JB		 2428 while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
2429 (nextiocb = lpfc_sli_next_iocb(phba, pring, &piocb)))
2430 lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
2431
2432 if (iocb)
2433 lpfc_sli_update_ring(phba, pring);
2434 else
2435 lpfc_sli_update_full_ring(phba, pring);
2436
2437 if (!piocb)
2438 return IOCB_SUCCESS;
2439
2440 goto out_busy;
2441
2442 iocb_busy:
2443 pring->stats.iocb_cmd_delay++;
2444
2445 out_busy:
2446
2447 if (!(flag & SLI_IOCB_RET_IOCB)) {
2448 lpfc_sli_ringtx_put(phba, pring, piocb);
2449 return IOCB_SUCCESS;
2450 }
2451
2452 return IOCB_BUSY;
2453}
2454
cf5bf97e
JW		 2455static int
2456lpfc_extra_ring_setup( struct lpfc_hba *phba)
2457{
2458 struct lpfc_sli *psli;
2459 struct lpfc_sli_ring *pring;
2460
2461 psli = &phba->sli;
2462
2463 /* Adjust cmd/rsp ring iocb entries more evenly */
a4bc3379
JS		 2464
2465 /* Take some away from the FCP ring */
cf5bf97e
JW		 2466 pring = &psli->ring[psli->fcp_ring];
2467 pring->numCiocb -= SLI2_IOCB_CMD_R1XTRA_ENTRIES;
2468 pring->numRiocb -= SLI2_IOCB_RSP_R1XTRA_ENTRIES;
2469 pring->numCiocb -= SLI2_IOCB_CMD_R3XTRA_ENTRIES;
2470 pring->numRiocb -= SLI2_IOCB_RSP_R3XTRA_ENTRIES;
2471
a4bc3379
JS		 2472 /* and give them to the extra ring */
2473 pring = &psli->ring[psli->extra_ring];
2474
cf5bf97e
JW		 2475 pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
2476 pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
2477 pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
2478 pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
2479
2480 /* Setup default profile for this ring */
2481 pring->iotag_max = 4096;
2482 pring->num_mask = 1;
2483 pring->prt[0].profile = 0; /* Mask 0 */
a4bc3379
JS		 2484 pring->prt[0].rctl = phba->cfg_multi_ring_rctl;
2485 pring->prt[0].type = phba->cfg_multi_ring_type;
cf5bf97e
JW		 2486 pring->prt[0].lpfc_sli_rcv_unsol_event = NULL;
2487 return 0;
2488}
2489
dea3101e
JB		 2490int
2491lpfc_sli_setup(struct lpfc_hba *phba)
2492{
2493 int i, totiocb = 0;
2494 struct lpfc_sli *psli = &phba->sli;
2495 struct lpfc_sli_ring *pring;
2496
2497 psli->num_rings = MAX_CONFIGURED_RINGS;
2498 psli->sli_flag = 0;
2499 psli->fcp_ring = LPFC_FCP_RING;
2500 psli->next_ring = LPFC_FCP_NEXT_RING;
a4bc3379 2501 psli->extra_ring = LPFC_EXTRA_RING;
dea3101e 2502
604a3e30
JB		 2503 psli->iocbq_lookup = NULL;
2504 psli->iocbq_lookup_len = 0;
2505 psli->last_iotag = 0;
2506
dea3101e
JB		 2507 for (i = 0; i < psli->num_rings; i++) {
2508 pring = &psli->ring[i];
2509 switch (i) {
2510 case LPFC_FCP_RING: /* ring 0 - FCP */
2511 /* numCiocb and numRiocb are used in config_port */
2512 pring->numCiocb = SLI2_IOCB_CMD_R0_ENTRIES;
2513 pring->numRiocb = SLI2_IOCB_RSP_R0_ENTRIES;
2514 pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
2515 pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
2516 pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
2517 pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
2518 pring->iotag_ctr = 0;
2519 pring->iotag_max =
2520 (phba->cfg_hba_queue_depth * 2);
2521 pring->fast_iotag = pring->iotag_max;
2522 pring->num_mask = 0;
2523 break;
a4bc3379 2524 case LPFC_EXTRA_RING: /* ring 1 - EXTRA */
dea3101e
JB		 2525 /* numCiocb and numRiocb are used in config_port */
2526 pring->numCiocb = SLI2_IOCB_CMD_R1_ENTRIES;
2527 pring->numRiocb = SLI2_IOCB_RSP_R1_ENTRIES;
2528 pring->num_mask = 0;
2529 break;
2530 case LPFC_ELS_RING: /* ring 2 - ELS / CT */
2531 /* numCiocb and numRiocb are used in config_port */
2532 pring->numCiocb = SLI2_IOCB_CMD_R2_ENTRIES;
2533 pring->numRiocb = SLI2_IOCB_RSP_R2_ENTRIES;
2534 pring->fast_iotag = 0;
2535 pring->iotag_ctr = 0;
2536 pring->iotag_max = 4096;
2537 pring->num_mask = 4;
2538 pring->prt[0].profile = 0; /* Mask 0 */
2539 pring->prt[0].rctl = FC_ELS_REQ;
2540 pring->prt[0].type = FC_ELS_DATA;
2541 pring->prt[0].lpfc_sli_rcv_unsol_event =
2542 lpfc_els_unsol_event;
2543 pring->prt[1].profile = 0; /* Mask 1 */
2544 pring->prt[1].rctl = FC_ELS_RSP;
2545 pring->prt[1].type = FC_ELS_DATA;
2546 pring->prt[1].lpfc_sli_rcv_unsol_event =
2547 lpfc_els_unsol_event;
2548 pring->prt[2].profile = 0; /* Mask 2 */
2549 /* NameServer Inquiry */
2550 pring->prt[2].rctl = FC_UNSOL_CTL;
2551 /* NameServer */
2552 pring->prt[2].type = FC_COMMON_TRANSPORT_ULP;
2553 pring->prt[2].lpfc_sli_rcv_unsol_event =
2554 lpfc_ct_unsol_event;
2555 pring->prt[3].profile = 0; /* Mask 3 */
2556 /* NameServer response */
2557 pring->prt[3].rctl = FC_SOL_CTL;
2558 /* NameServer */
2559 pring->prt[3].type = FC_COMMON_TRANSPORT_ULP;
2560 pring->prt[3].lpfc_sli_rcv_unsol_event =
2561 lpfc_ct_unsol_event;
2562 break;
2563 }
2564 totiocb += (pring->numCiocb + pring->numRiocb);
2565 }
2566 if (totiocb > MAX_SLI2_IOCB) {
2567 /* Too many cmd / rsp ring entries in SLI2 SLIM */
2568 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2569 "%d:0462 Too many cmd / rsp ring entries in "
2570 "SLI2 SLIM Data: x%x x%x\n",
2571 phba->brd_no, totiocb, MAX_SLI2_IOCB);
2572 }
cf5bf97e
JW		 2573 if (phba->cfg_multi_ring_support == 2)
2574 lpfc_extra_ring_setup(phba);
dea3101e
JB		 2575
2576 return 0;
2577}
2578
2579int
2580lpfc_sli_queue_setup(struct lpfc_hba * phba)
2581{
2582 struct lpfc_sli *psli;
2583 struct lpfc_sli_ring *pring;
604a3e30 2584 int i;
dea3101e
JB		 2585
2586 psli = &phba->sli;
2587 spin_lock_irq(phba->host->host_lock);
2588 INIT_LIST_HEAD(&psli->mboxq);
2589 /* Initialize list headers for txq and txcmplq as double linked lists */
2590 for (i = 0; i < psli->num_rings; i++) {
2591 pring = &psli->ring[i];
2592 pring->ringno = i;
2593 pring->next_cmdidx = 0;
2594 pring->local_getidx = 0;
2595 pring->cmdidx = 0;
2596 INIT_LIST_HEAD(&pring->txq);
2597 INIT_LIST_HEAD(&pring->txcmplq);
2598 INIT_LIST_HEAD(&pring->iocb_continueq);
2599 INIT_LIST_HEAD(&pring->postbufq);
dea3101e
JB		 2600 }
2601 spin_unlock_irq(phba->host->host_lock);
2602 return (1);
2603}
2604
2605int
2606lpfc_sli_hba_down(struct lpfc_hba * phba)
2607{
2608 struct lpfc_sli *psli;
2609 struct lpfc_sli_ring *pring;
2610 LPFC_MBOXQ_t *pmb;
2611 struct lpfc_iocbq *iocb, *next_iocb;
2612 IOCB_t *icmd = NULL;
2613 int i;
2614 unsigned long flags = 0;
2615
2616 psli = &phba->sli;
2617 lpfc_hba_down_prep(phba);
2618
2619 spin_lock_irqsave(phba->host->host_lock, flags);
2620
2621 for (i = 0; i < psli->num_rings; i++) {
2622 pring = &psli->ring[i];
2623 pring->flag |= LPFC_DEFERRED_RING_EVENT;
2624
2625 /*
2626 * Error everything on the txq since these iocbs have not been
2627 * given to the FW yet.
2628 */
2629 pring->txq_cnt = 0;
2630
2631 list_for_each_entry_safe(iocb, next_iocb, &pring->txq, list) {
2632 list_del_init(&iocb->list);
2633 if (iocb->iocb_cmpl) {
2634 icmd = &iocb->iocb;
2635 icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
2636 icmd->un.ulpWord[4] = IOERR_SLI_DOWN;
2637 spin_unlock_irqrestore(phba->host->host_lock,
2638 flags);
2639 (iocb->iocb_cmpl) (phba, iocb, iocb);
2640 spin_lock_irqsave(phba->host->host_lock, flags);
604a3e30
JB		 2641 } else
2642 lpfc_sli_release_iocbq(phba, iocb);
dea3101e
JB		 2643 }
2644
2645 INIT_LIST_HEAD(&(pring->txq));
2646
dea3101e
JB		 2647 }
2648
2649 spin_unlock_irqrestore(phba->host->host_lock, flags);
2650
2651 /* Return any active mbox cmds */
2652 del_timer_sync(&psli->mbox_tmo);
2653 spin_lock_irqsave(phba->host->host_lock, flags);
2654 phba->work_hba_events &= ~WORKER_MBOX_TMO;
2655 if (psli->mbox_active) {
2656 pmb = psli->mbox_active;
2657 pmb->mb.mbxStatus = MBX_NOT_FINISHED;
2658 if (pmb->mbox_cmpl) {
2659 spin_unlock_irqrestore(phba->host->host_lock, flags);
2660 pmb->mbox_cmpl(phba,pmb);
2661 spin_lock_irqsave(phba->host->host_lock, flags);
2662 }
2663 }
2664 psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
2665 psli->mbox_active = NULL;
2666
2667 /* Return any pending mbox cmds */
2668 while ((pmb = lpfc_mbox_get(phba)) != NULL) {
2669 pmb->mb.mbxStatus = MBX_NOT_FINISHED;
2670 if (pmb->mbox_cmpl) {
2671 spin_unlock_irqrestore(phba->host->host_lock, flags);
2672 pmb->mbox_cmpl(phba,pmb);
2673 spin_lock_irqsave(phba->host->host_lock, flags);
2674 }
2675 }
2676
2677 INIT_LIST_HEAD(&psli->mboxq);
2678
2679 spin_unlock_irqrestore(phba->host->host_lock, flags);
2680
dea3101e
JB		 2681 return 1;
2682}
2683
2684void
2685lpfc_sli_pcimem_bcopy(void *srcp, void *destp, uint32_t cnt)
2686{
2687 uint32_t *src = srcp;
2688 uint32_t *dest = destp;
2689 uint32_t ldata;
2690 int i;
2691
2692 for (i = 0; i < (int)cnt; i += sizeof (uint32_t)) {
2693 ldata = *src;
2694 ldata = le32_to_cpu(ldata);
2695 *dest = ldata;
2696 src++;
2697 dest++;
2698 }
2699}
2700
2701int
2702lpfc_sli_ringpostbuf_put(struct lpfc_hba * phba, struct lpfc_sli_ring * pring,
2703 struct lpfc_dmabuf * mp)
2704{
2705 /* Stick struct lpfc_dmabuf at end of postbufq so driver can look it up
2706 later */
2707 list_add_tail(&mp->list, &pring->postbufq);
2708
2709 pring->postbufq_cnt++;
2710 return 0;
2711}
2712
2713
2714struct lpfc_dmabuf *
2715lpfc_sli_ringpostbuf_get(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2716 dma_addr_t phys)
2717{
2718 struct lpfc_dmabuf *mp, *next_mp;
2719 struct list_head *slp = &pring->postbufq;
2720
2721 /* Search postbufq, from the begining, looking for a match on phys */
2722 list_for_each_entry_safe(mp, next_mp, &pring->postbufq, list) {
2723 if (mp->phys == phys) {
2724 list_del_init(&mp->list);
2725 pring->postbufq_cnt--;
2726 return mp;
2727 }
2728 }
2729
2730 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2731 "%d:0410 Cannot find virtual addr for mapped buf on "
2732 "ring %d Data x%llx x%p x%p x%x\n",
2733 phba->brd_no, pring->ringno, (unsigned long long)phys,
2734 slp->next, slp->prev, pring->postbufq_cnt);
2735 return NULL;
2736}
2737
2738static void
07951076
JS		 2739lpfc_sli_abort_els_cmpl(struct lpfc_hba * phba, struct lpfc_iocbq * cmdiocb,
2740 struct lpfc_iocbq * rspiocb)
dea3101e 2741{
07951076 2742 spin_lock_irq(phba->host->host_lock);
604a3e30 2743 lpfc_sli_release_iocbq(phba, cmdiocb);
07951076 2744 spin_unlock_irq(phba->host->host_lock);
dea3101e
JB		 2745 return;
2746}
2747
2748int
07951076
JS		 2749lpfc_sli_issue_abort_iotag(struct lpfc_hba * phba,
2750 struct lpfc_sli_ring * pring,
2751 struct lpfc_iocbq * cmdiocb)
dea3101e 2752{
0bd4ca25 2753 struct lpfc_iocbq *abtsiocbp;
dea3101e
JB		 2754 IOCB_t *icmd = NULL;
2755 IOCB_t *iabt = NULL;
07951076
JS		 2756 int retval = IOCB_ERROR;
2757
2758 /* There are certain command types we don't want
2759 * to abort.
2760 */
2761 icmd = &cmdiocb->iocb;
2762 if ((icmd->ulpCommand == CMD_ABORT_XRI_CN) ||
2763 (icmd->ulpCommand == CMD_CLOSE_XRI_CN))
2764 return 0;
2765
2766 /* If we're unloading, interrupts are disabled so we
2767 * need to cleanup the iocb here.
2768 */
2769 if (phba->fc_flag & FC_UNLOADING)
2770 goto abort_iotag_exit;
dea3101e
JB		 2771
2772 /* issue ABTS for this IOCB based on iotag */
0bd4ca25 2773 abtsiocbp = lpfc_sli_get_iocbq(phba);
dea3101e
JB		 2774 if (abtsiocbp == NULL)
2775 return 0;
dea3101e 2776
07951076
JS		 2777 /* This signals the response to set the correct status
2778 * before calling the completion handler.
2779 */
2780 cmdiocb->iocb_flag |= LPFC_DRIVER_ABORTED;
2781
dea3101e 2782 iabt = &abtsiocbp->iocb;
07951076
JS		 2783 iabt->un.acxri.abortType = ABORT_TYPE_ABTS;
2784 iabt->un.acxri.abortContextTag = icmd->ulpContext;
2785 iabt->un.acxri.abortIoTag = icmd->ulpIoTag;
2786 iabt->ulpLe = 1;
2787 iabt->ulpClass = icmd->ulpClass;
dea3101e 2788
07951076
JS		 2789 if (phba->hba_state >= LPFC_LINK_UP)
2790 iabt->ulpCommand = CMD_ABORT_XRI_CN;
2791 else
2792 iabt->ulpCommand = CMD_CLOSE_XRI_CN;
dea3101e 2793
07951076
JS		 2794 abtsiocbp->iocb_cmpl = lpfc_sli_abort_els_cmpl;
2795 retval = lpfc_sli_issue_iocb(phba, pring, abtsiocbp, 0);
dea3101e 2796
07951076
JS		 2797abort_iotag_exit:
2798
2799 /* If we could not issue an abort dequeue the iocb and handle
2800 * the completion here.
2801 */
2802 if (retval == IOCB_ERROR) {
2803 list_del(&cmdiocb->list);
2804 pring->txcmplq_cnt--;
2805
2806 if (cmdiocb->iocb_cmpl) {
2807 icmd->ulpStatus = IOSTAT_LOCAL_REJECT;
2808 icmd->un.ulpWord[4] = IOERR_SLI_ABORTED;
2809 spin_unlock_irq(phba->host->host_lock);
2810 (cmdiocb->iocb_cmpl) (phba, cmdiocb, cmdiocb);
2811 spin_lock_irq(phba->host->host_lock);
2812 } else
2813 lpfc_sli_release_iocbq(phba, cmdiocb);
dea3101e
JB		 2814 }
2815
2816 return 1;
2817}
2818
2819static int
0bd4ca25
JSEC		 2820lpfc_sli_validate_fcp_iocb(struct lpfc_iocbq *iocbq, uint16_t tgt_id,
2821 uint64_t lun_id, uint32_t ctx,
2822 lpfc_ctx_cmd ctx_cmd)
dea3101e 2823{
0bd4ca25
JSEC		 2824 struct lpfc_scsi_buf *lpfc_cmd;
2825 struct scsi_cmnd *cmnd;
dea3101e
JB		 2826 int rc = 1;
2827
0bd4ca25
JSEC		 2828 if (!(iocbq->iocb_flag & LPFC_IO_FCP))
2829 return rc;
2830
2831 lpfc_cmd = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq);
2832 cmnd = lpfc_cmd->pCmd;
2833
2834 if (cmnd == NULL)
dea3101e
JB		 2835 return rc;
2836
2837 switch (ctx_cmd) {
2838 case LPFC_CTX_LUN:
0bd4ca25
JSEC		 2839 if ((cmnd->device->id == tgt_id) &&
2840 (cmnd->device->lun == lun_id))
dea3101e
JB		 2841 rc = 0;
2842 break;
2843 case LPFC_CTX_TGT:
0bd4ca25 2844 if (cmnd->device->id == tgt_id)
dea3101e
JB		 2845 rc = 0;
2846 break;
2847 case LPFC_CTX_CTX:
0bd4ca25 2848 if (iocbq->iocb.ulpContext == ctx)
dea3101e 2849 rc = 0;
0bd4ca25 2850 break;
dea3101e
JB		 2851 case LPFC_CTX_HOST:
2852 rc = 0;
2853 break;
2854 default:
2855 printk(KERN_ERR "%s: Unknown context cmd type, value %d\n",
2856 __FUNCTION__, ctx_cmd);
2857 break;
2858 }
2859
2860 return rc;
2861}
2862
2863int
2864lpfc_sli_sum_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2865 uint16_t tgt_id, uint64_t lun_id, lpfc_ctx_cmd ctx_cmd)
2866{
0bd4ca25
JSEC		 2867 struct lpfc_iocbq *iocbq;
2868 int sum, i;
dea3101e 2869
0bd4ca25
JSEC		 2870 for (i = 1, sum = 0; i <= phba->sli.last_iotag; i++) {
2871 iocbq = phba->sli.iocbq_lookup[i];
dea3101e 2872
0bd4ca25
JSEC		 2873 if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
2874 0, ctx_cmd) == 0)
2875 sum++;
dea3101e 2876 }
0bd4ca25 2877
dea3101e
JB		 2878 return sum;
2879}
2880
5eb95af0
JSEC		 2881void
2882lpfc_sli_abort_fcp_cmpl(struct lpfc_hba * phba, struct lpfc_iocbq * cmdiocb,
2883 struct lpfc_iocbq * rspiocb)
2884{
2885 spin_lock_irq(phba->host->host_lock);
604a3e30 2886 lpfc_sli_release_iocbq(phba, cmdiocb);
5eb95af0
JSEC		 2887 spin_unlock_irq(phba->host->host_lock);
2888 return;
2889}
2890
dea3101e
JB		 2891int
2892lpfc_sli_abort_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
2893 uint16_t tgt_id, uint64_t lun_id, uint32_t ctx,
2894 lpfc_ctx_cmd abort_cmd)
2895{
0bd4ca25
JSEC		 2896 struct lpfc_iocbq *iocbq;
2897 struct lpfc_iocbq *abtsiocb;
dea3101e 2898 IOCB_t *cmd = NULL;
dea3101e 2899 int errcnt = 0, ret_val = 0;
0bd4ca25 2900 int i;
dea3101e 2901
0bd4ca25
JSEC		 2902 for (i = 1; i <= phba->sli.last_iotag; i++) {
2903 iocbq = phba->sli.iocbq_lookup[i];
dea3101e 2904
0bd4ca25
JSEC		 2905 if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
2906 0, abort_cmd) != 0)
dea3101e
JB		 2907 continue;
2908
2909 /* issue ABTS for this IOCB based on iotag */
0bd4ca25 2910 abtsiocb = lpfc_sli_get_iocbq(phba);
dea3101e
JB		 2911 if (abtsiocb == NULL) {
2912 errcnt++;
2913 continue;
2914 }
dea3101e 2915
0bd4ca25 2916 cmd = &iocbq->iocb;
dea3101e
JB		 2917 abtsiocb->iocb.un.acxri.abortType = ABORT_TYPE_ABTS;
2918 abtsiocb->iocb.un.acxri.abortContextTag = cmd->ulpContext;
2919 abtsiocb->iocb.un.acxri.abortIoTag = cmd->ulpIoTag;
2920 abtsiocb->iocb.ulpLe = 1;
2921 abtsiocb->iocb.ulpClass = cmd->ulpClass;
2922
2923 if (phba->hba_state >= LPFC_LINK_UP)
2924 abtsiocb->iocb.ulpCommand = CMD_ABORT_XRI_CN;
2925 else
2926 abtsiocb->iocb.ulpCommand = CMD_CLOSE_XRI_CN;
2927
5eb95af0
JSEC		 2928 /* Setup callback routine and issue the command. */
2929 abtsiocb->iocb_cmpl = lpfc_sli_abort_fcp_cmpl;
dea3101e
JB		 2930 ret_val = lpfc_sli_issue_iocb(phba, pring, abtsiocb, 0);
2931 if (ret_val == IOCB_ERROR) {
604a3e30 2932 lpfc_sli_release_iocbq(phba, abtsiocb);
dea3101e
JB		 2933 errcnt++;
2934 continue;
2935 }
2936 }
2937
2938 return errcnt;
2939}
2940
68876920
JSEC		 2941static void
2942lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba,
2943 struct lpfc_iocbq *cmdiocbq,
2944 struct lpfc_iocbq *rspiocbq)
dea3101e 2945{
68876920
JSEC		 2946 wait_queue_head_t *pdone_q;
2947 unsigned long iflags;
dea3101e 2948
68876920
JSEC		 2949 spin_lock_irqsave(phba->host->host_lock, iflags);
2950 cmdiocbq->iocb_flag |= LPFC_IO_WAKE;
2951 if (cmdiocbq->context2 && rspiocbq)
2952 memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb,
2953 &rspiocbq->iocb, sizeof(IOCB_t));
2954
2955 pdone_q = cmdiocbq->context_un.wait_queue;
2956 spin_unlock_irqrestore(phba->host->host_lock, iflags);
2957 if (pdone_q)
2958 wake_up(pdone_q);
dea3101e
JB		 2959 return;
2960}
2961
68876920
JSEC		 2962/*
2963 * Issue the caller's iocb and wait for its completion, but no longer than the
2964 * caller's timeout. Note that iocb_flags is cleared before the
2965 * lpfc_sli_issue_call since the wake routine sets a unique value and by
2966 * definition this is a wait function.
2967 */
dea3101e 2968int
68876920
JSEC		 2969lpfc_sli_issue_iocb_wait(struct lpfc_hba * phba,
2970 struct lpfc_sli_ring * pring,
2971 struct lpfc_iocbq * piocb,
2972 struct lpfc_iocbq * prspiocbq,
2973 uint32_t timeout)
dea3101e 2974{
7259f0d0 2975 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_q);
68876920
JSEC		 2976 long timeleft, timeout_req = 0;
2977 int retval = IOCB_SUCCESS;
875fbdfe 2978 uint32_t creg_val;
dea3101e
JB		 2979
2980 /*
68876920
JSEC		 2981 * If the caller has provided a response iocbq buffer, then context2
2982 * is NULL or its an error.
dea3101e 2983 */
68876920
JSEC		 2984 if (prspiocbq) {
2985 if (piocb->context2)
2986 return IOCB_ERROR;
2987 piocb->context2 = prspiocbq;
dea3101e
JB		 2988 }
2989
68876920
JSEC		 2990 piocb->iocb_cmpl = lpfc_sli_wake_iocb_wait;
2991 piocb->context_un.wait_queue = &done_q;
2992 piocb->iocb_flag &= ~LPFC_IO_WAKE;
dea3101e 2993
875fbdfe
JSEC		 2994 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
2995 creg_val = readl(phba->HCregaddr);
2996 creg_val |= (HC_R0INT_ENA << LPFC_FCP_RING);
2997 writel(creg_val, phba->HCregaddr);
2998 readl(phba->HCregaddr); /* flush */
2999 }
3000
68876920
JSEC		 3001 retval = lpfc_sli_issue_iocb(phba, pring, piocb, 0);
3002 if (retval == IOCB_SUCCESS) {
3003 timeout_req = timeout * HZ;
3004 spin_unlock_irq(phba->host->host_lock);
3005 timeleft = wait_event_timeout(done_q,
3006 piocb->iocb_flag & LPFC_IO_WAKE,
3007 timeout_req);
3008 spin_lock_irq(phba->host->host_lock);
dea3101e 3009
68876920
JSEC		 3010 if (timeleft == 0) {
3011 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
dca9479b 3012 "%d:0338 IOCB wait timeout error - no "
68876920
JSEC		 3013 "wake response Data x%x\n",
3014 phba->brd_no, timeout);
3015 retval = IOCB_TIMEDOUT;
3016 } else if (!(piocb->iocb_flag & LPFC_IO_WAKE)) {
3017 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3018 "%d:0330 IOCB wake NOT set, "
3019 "Data x%x x%lx\n", phba->brd_no,
3020 timeout, (timeleft / jiffies));
3021 retval = IOCB_TIMEDOUT;
3022 } else {
3023 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3024 "%d:0331 IOCB wake signaled\n",
3025 phba->brd_no);
dea3101e 3026 }
68876920
JSEC		 3027 } else {
3028 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3029 "%d:0332 IOCB wait issue failed, Data x%x\n",
3030 phba->brd_no, retval);
3031 retval = IOCB_ERROR;
dea3101e
JB		 3032 }
3033
875fbdfe
JSEC		 3034 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
3035 creg_val = readl(phba->HCregaddr);
3036 creg_val &= ~(HC_R0INT_ENA << LPFC_FCP_RING);
3037 writel(creg_val, phba->HCregaddr);
3038 readl(phba->HCregaddr); /* flush */
3039 }
3040
68876920
JSEC		 3041 if (prspiocbq)
3042 piocb->context2 = NULL;
3043
3044 piocb->context_un.wait_queue = NULL;
3045 piocb->iocb_cmpl = NULL;
dea3101e
JB		 3046 return retval;
3047}
68876920 3048
dea3101e
JB		 3049int
3050lpfc_sli_issue_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq,
3051 uint32_t timeout)
3052{
7259f0d0 3053 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_q);
dea3101e
JB		 3054 DECLARE_WAITQUEUE(wq_entry, current);
3055 uint32_t timeleft = 0;
3056 int retval;
3057
3058 /* The caller must leave context1 empty. */
3059 if (pmboxq->context1 != 0) {
3060 return (MBX_NOT_FINISHED);
3061 }
3062
3063 /* setup wake call as IOCB callback */
3064 pmboxq->mbox_cmpl = lpfc_sli_wake_mbox_wait;
3065 /* setup context field to pass wait_queue pointer to wake function */
3066 pmboxq->context1 = &done_q;
3067
3068 /* start to sleep before we wait, to avoid races */
3069 set_current_state(TASK_INTERRUPTIBLE);
3070 add_wait_queue(&done_q, &wq_entry);
3071
3072 /* now issue the command */
3073 retval = lpfc_sli_issue_mbox(phba, pmboxq, MBX_NOWAIT);
3074
3075 if (retval == MBX_BUSY || retval == MBX_SUCCESS) {
3076 timeleft = schedule_timeout(timeout * HZ);
3077 pmboxq->context1 = NULL;
3078 /* if schedule_timeout returns 0, we timed out and were not
3079 woken up */
406d6041 3080 if ((timeleft == 0) || signal_pending(current))
dea3101e 3081 retval = MBX_TIMEOUT;
406d6041 3082 else
dea3101e 3083 retval = MBX_SUCCESS;
dea3101e
JB		 3084 }
3085
3086
3087 set_current_state(TASK_RUNNING);
3088 remove_wait_queue(&done_q, &wq_entry);
3089 return retval;
3090}
3091
b4c02652
JS		 3092int
3093lpfc_sli_flush_mbox_queue(struct lpfc_hba * phba)
3094{
3095 int i = 0;
3096
3097 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE && !phba->stopped) {
3098 if (i++ > LPFC_MBOX_TMO * 1000)
3099 return 1;
3100
3101 if (lpfc_sli_handle_mb_event(phba) == 0)
3102 i = 0;
3103
3104 msleep(1);
3105 }
3106
3107 return (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) ? 1 : 0;
3108}
3109
dea3101e 3110irqreturn_t
7d12e780 3111lpfc_intr_handler(int irq, void *dev_id)
dea3101e
JB		 3112{
3113 struct lpfc_hba *phba;
3114 uint32_t ha_copy;
3115 uint32_t work_ha_copy;
3116 unsigned long status;
3117 int i;
3118 uint32_t control;
3119
3120 /*
3121 * Get the driver's phba structure from the dev_id and
3122 * assume the HBA is not interrupting.
3123 */
3124 phba = (struct lpfc_hba *) dev_id;
3125
3126 if (unlikely(!phba))
3127 return IRQ_NONE;
3128
8d63f375
LV		 3129 /* If the pci channel is offline, ignore all the interrupts. */
3130 if (unlikely(pci_channel_offline(phba->pcidev)))
3131 return IRQ_NONE;
3132
dea3101e
JB		 3133 phba->sli.slistat.sli_intr++;
3134
3135 /*
3136 * Call the HBA to see if it is interrupting. If not, don't claim
3137 * the interrupt
3138 */
3139
3140 /* Ignore all interrupts during initialization. */
3141 if (unlikely(phba->hba_state < LPFC_LINK_DOWN))
3142 return IRQ_NONE;
3143
3144 /*
3145 * Read host attention register to determine interrupt source
3146 * Clear Attention Sources, except Error Attention (to
3147 * preserve status) and Link Attention
3148 */
3149 spin_lock(phba->host->host_lock);
3150 ha_copy = readl(phba->HAregaddr);
3151 writel((ha_copy & ~(HA_LATT | HA_ERATT)), phba->HAregaddr);
3152 readl(phba->HAregaddr); /* flush */
3153 spin_unlock(phba->host->host_lock);
3154
3155 if (unlikely(!ha_copy))
3156 return IRQ_NONE;
3157
3158 work_ha_copy = ha_copy & phba->work_ha_mask;
3159
3160 if (unlikely(work_ha_copy)) {
3161 if (work_ha_copy & HA_LATT) {
3162 if (phba->sli.sli_flag & LPFC_PROCESS_LA) {
3163 /*
3164 * Turn off Link Attention interrupts
3165 * until CLEAR_LA done
3166 */
3167 spin_lock(phba->host->host_lock);
3168 phba->sli.sli_flag &= ~LPFC_PROCESS_LA;
3169 control = readl(phba->HCregaddr);
3170 control &= ~HC_LAINT_ENA;
3171 writel(control, phba->HCregaddr);
3172 readl(phba->HCregaddr); /* flush */
3173 spin_unlock(phba->host->host_lock);
3174 }
3175 else
3176 work_ha_copy &= ~HA_LATT;
3177 }
3178
3179 if (work_ha_copy & ~(HA_ERATT|HA_MBATT|HA_LATT)) {
3180 for (i = 0; i < phba->sli.num_rings; i++) {
3181 if (work_ha_copy & (HA_RXATT << (4*i))) {
3182 /*
3183 * Turn off Slow Rings interrupts
3184 */
3185 spin_lock(phba->host->host_lock);
3186 control = readl(phba->HCregaddr);
3187 control &= ~(HC_R0INT_ENA << i);
3188 writel(control, phba->HCregaddr);
3189 readl(phba->HCregaddr); /* flush */
3190 spin_unlock(phba->host->host_lock);
3191 }
3192 }
3193 }
3194
3195 if (work_ha_copy & HA_ERATT) {
3196 phba->hba_state = LPFC_HBA_ERROR;
3197 /*
3198 * There was a link/board error. Read the
3199 * status register to retrieve the error event
3200 * and process it.
3201 */
3202 phba->sli.slistat.err_attn_event++;
3203 /* Save status info */
3204 phba->work_hs = readl(phba->HSregaddr);
3205 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
3206 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
3207
3208 /* Clear Chip error bit */
3209 writel(HA_ERATT, phba->HAregaddr);
3210 readl(phba->HAregaddr); /* flush */
9290831f 3211 phba->stopped = 1;
dea3101e
JB		 3212 }
3213
3214 spin_lock(phba->host->host_lock);
3215 phba->work_ha |= work_ha_copy;
3216 if (phba->work_wait)
3217 wake_up(phba->work_wait);
3218 spin_unlock(phba->host->host_lock);
3219 }
3220
3221 ha_copy &= ~(phba->work_ha_mask);
3222
3223 /*
3224 * Process all events on FCP ring. Take the optimized path for
3225 * FCP IO. Any other IO is slow path and is handled by
3226 * the worker thread.
3227 */
3228 status = (ha_copy & (HA_RXMASK << (4*LPFC_FCP_RING)));
3229 status >>= (4*LPFC_FCP_RING);
3230 if (status & HA_RXATT)
3231 lpfc_sli_handle_fast_ring_event(phba,
3232 &phba->sli.ring[LPFC_FCP_RING],
3233 status);
a4bc3379
JS		 3234
3235 if (phba->cfg_multi_ring_support == 2) {
3236 /*
3237 * Process all events on extra ring. Take the optimized path
3238 * for extra ring IO. Any other IO is slow path and is handled
3239 * by the worker thread.
3240 */
3241 status = (ha_copy & (HA_RXMASK << (4*LPFC_EXTRA_RING)));
3242 status >>= (4*LPFC_EXTRA_RING);
3243 if (status & HA_RXATT) {
3244 lpfc_sli_handle_fast_ring_event(phba,
3245 &phba->sli.ring[LPFC_EXTRA_RING],
3246 status);
3247 }
3248 }
dea3101e
JB		 3249 return IRQ_HANDLED;
3250
3251} /* lpfc_intr_handler */
Clone of davem's net-next-2.6 tree