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1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
64static unsigned int ata_busy_sleep (struct ata_port *ap,
65 unsigned long tmout_pat,
66 unsigned long tmout);
59a10b17 67static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev);
8bf62ece 68static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev);
1da177e4
LT		 69static void ata_set_mode(struct ata_port *ap);
70static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
057ace5e 71static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift);
1da177e4 72static int fgb(u32 bitmap);
057ace5e 73static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 74 u8 *xfer_mode_out,
75 unsigned int *xfer_shift_out);
1da177e4
LT		 76static void __ata_qc_complete(struct ata_queued_cmd *qc);
77
78static unsigned int ata_unique_id = 1;
79static struct workqueue_struct *ata_wq;
80
1623c81e
JG		 81int atapi_enabled = 0;
82module_param(atapi_enabled, int, 0444);
83MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
84
1da177e4
LT		 85MODULE_AUTHOR("Jeff Garzik");
86MODULE_DESCRIPTION("Library module for ATA devices");
87MODULE_LICENSE("GPL");
88MODULE_VERSION(DRV_VERSION);
89
90/**
6f0ef4fa 91 * ata_tf_load_pio - send taskfile registers to host controller
1da177e4
LT		 92 * @ap: Port to which output is sent
93 * @tf: ATA taskfile register set
94 *
95 * Outputs ATA taskfile to standard ATA host controller.
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101static void ata_tf_load_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 102{
103 struct ata_ioports *ioaddr = &ap->ioaddr;
104 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
105
106 if (tf->ctl != ap->last_ctl) {
107 outb(tf->ctl, ioaddr->ctl_addr);
108 ap->last_ctl = tf->ctl;
109 ata_wait_idle(ap);
110 }
111
112 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
113 outb(tf->hob_feature, ioaddr->feature_addr);
114 outb(tf->hob_nsect, ioaddr->nsect_addr);
115 outb(tf->hob_lbal, ioaddr->lbal_addr);
116 outb(tf->hob_lbam, ioaddr->lbam_addr);
117 outb(tf->hob_lbah, ioaddr->lbah_addr);
118 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
119 tf->hob_feature,
120 tf->hob_nsect,
121 tf->hob_lbal,
122 tf->hob_lbam,
123 tf->hob_lbah);
124 }
125
126 if (is_addr) {
127 outb(tf->feature, ioaddr->feature_addr);
128 outb(tf->nsect, ioaddr->nsect_addr);
129 outb(tf->lbal, ioaddr->lbal_addr);
130 outb(tf->lbam, ioaddr->lbam_addr);
131 outb(tf->lbah, ioaddr->lbah_addr);
132 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
133 tf->feature,
134 tf->nsect,
135 tf->lbal,
136 tf->lbam,
137 tf->lbah);
138 }
139
140 if (tf->flags & ATA_TFLAG_DEVICE) {
141 outb(tf->device, ioaddr->device_addr);
142 VPRINTK("device 0x%X\n", tf->device);
143 }
144
145 ata_wait_idle(ap);
146}
147
148/**
149 * ata_tf_load_mmio - send taskfile registers to host controller
150 * @ap: Port to which output is sent
151 * @tf: ATA taskfile register set
152 *
153 * Outputs ATA taskfile to standard ATA host controller using MMIO.
154 *
155 * LOCKING:
156 * Inherited from caller.
157 */
158
057ace5e 159static void ata_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 160{
161 struct ata_ioports *ioaddr = &ap->ioaddr;
162 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
163
164 if (tf->ctl != ap->last_ctl) {
165 writeb(tf->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
166 ap->last_ctl = tf->ctl;
167 ata_wait_idle(ap);
168 }
169
170 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
171 writeb(tf->hob_feature, (void __iomem *) ioaddr->feature_addr);
172 writeb(tf->hob_nsect, (void __iomem *) ioaddr->nsect_addr);
173 writeb(tf->hob_lbal, (void __iomem *) ioaddr->lbal_addr);
174 writeb(tf->hob_lbam, (void __iomem *) ioaddr->lbam_addr);
175 writeb(tf->hob_lbah, (void __iomem *) ioaddr->lbah_addr);
176 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
177 tf->hob_feature,
178 tf->hob_nsect,
179 tf->hob_lbal,
180 tf->hob_lbam,
181 tf->hob_lbah);
182 }
183
184 if (is_addr) {
185 writeb(tf->feature, (void __iomem *) ioaddr->feature_addr);
186 writeb(tf->nsect, (void __iomem *) ioaddr->nsect_addr);
187 writeb(tf->lbal, (void __iomem *) ioaddr->lbal_addr);
188 writeb(tf->lbam, (void __iomem *) ioaddr->lbam_addr);
189 writeb(tf->lbah, (void __iomem *) ioaddr->lbah_addr);
190 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
191 tf->feature,
192 tf->nsect,
193 tf->lbal,
194 tf->lbam,
195 tf->lbah);
196 }
197
198 if (tf->flags & ATA_TFLAG_DEVICE) {
199 writeb(tf->device, (void __iomem *) ioaddr->device_addr);
200 VPRINTK("device 0x%X\n", tf->device);
201 }
202
203 ata_wait_idle(ap);
204}
205
0baab86b
EF		 206
207/**
208 * ata_tf_load - send taskfile registers to host controller
209 * @ap: Port to which output is sent
210 * @tf: ATA taskfile register set
211 *
212 * Outputs ATA taskfile to standard ATA host controller using MMIO
213 * or PIO as indicated by the ATA_FLAG_MMIO flag.
214 * Writes the control, feature, nsect, lbal, lbam, and lbah registers.
215 * Optionally (ATA_TFLAG_LBA48) writes hob_feature, hob_nsect,
216 * hob_lbal, hob_lbam, and hob_lbah.
217 *
218 * This function waits for idle (!BUSY and !DRQ) after writing
219 * registers. If the control register has a new value, this
220 * function also waits for idle after writing control and before
221 * writing the remaining registers.
222 *
223 * May be used as the tf_load() entry in ata_port_operations.
224 *
225 * LOCKING:
226 * Inherited from caller.
227 */
057ace5e 228void ata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 229{
230 if (ap->flags & ATA_FLAG_MMIO)
231 ata_tf_load_mmio(ap, tf);
232 else
233 ata_tf_load_pio(ap, tf);
234}
235
236/**
0baab86b 237 * ata_exec_command_pio - issue ATA command to host controller
1da177e4
LT		 238 * @ap: port to which command is being issued
239 * @tf: ATA taskfile register set
240 *
0baab86b 241 * Issues PIO write to ATA command register, with proper
1da177e4
LT		 242 * synchronization with interrupt handler / other threads.
243 *
244 * LOCKING:
245 * spin_lock_irqsave(host_set lock)
246 */
247
057ace5e 248static void ata_exec_command_pio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 249{
250 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
251
252 outb(tf->command, ap->ioaddr.command_addr);
253 ata_pause(ap);
254}
255
256
257/**
258 * ata_exec_command_mmio - issue ATA command to host controller
259 * @ap: port to which command is being issued
260 * @tf: ATA taskfile register set
261 *
262 * Issues MMIO write to ATA command register, with proper
263 * synchronization with interrupt handler / other threads.
264 *
265 * LOCKING:
266 * spin_lock_irqsave(host_set lock)
267 */
268
057ace5e 269static void ata_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 270{
271 DPRINTK("ata%u: cmd 0x%X\n", ap->id, tf->command);
272
273 writeb(tf->command, (void __iomem *) ap->ioaddr.command_addr);
274 ata_pause(ap);
275}
276
0baab86b
EF		 277
278/**
279 * ata_exec_command - issue ATA command to host controller
280 * @ap: port to which command is being issued
281 * @tf: ATA taskfile register set
282 *
283 * Issues PIO/MMIO write to ATA command register, with proper
284 * synchronization with interrupt handler / other threads.
285 *
286 * LOCKING:
287 * spin_lock_irqsave(host_set lock)
288 */
057ace5e 289void ata_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4
LT		 290{
291 if (ap->flags & ATA_FLAG_MMIO)
292 ata_exec_command_mmio(ap, tf);
293 else
294 ata_exec_command_pio(ap, tf);
295}
296
1da177e4
LT		 297/**
298 * ata_tf_to_host - issue ATA taskfile to host controller
299 * @ap: port to which command is being issued
300 * @tf: ATA taskfile register set
301 *
302 * Issues ATA taskfile register set to ATA host controller,
303 * with proper synchronization with interrupt handler and
304 * other threads.
305 *
306 * LOCKING:
1da177e4
LT		 307 * spin_lock_irqsave(host_set lock)
308 */
309
e5338254
JG		 310static inline void ata_tf_to_host(struct ata_port *ap,
311 const struct ata_taskfile *tf)
1da177e4
LT		 312{
313 ap->ops->tf_load(ap, tf);
314 ap->ops->exec_command(ap, tf);
315}
316
317/**
0baab86b 318 * ata_tf_read_pio - input device's ATA taskfile shadow registers
1da177e4
LT		 319 * @ap: Port from which input is read
320 * @tf: ATA taskfile register set for storing input
321 *
322 * Reads ATA taskfile registers for currently-selected device
323 * into @tf.
324 *
325 * LOCKING:
326 * Inherited from caller.
327 */
328
329static void ata_tf_read_pio(struct ata_port *ap, struct ata_taskfile *tf)
330{
331 struct ata_ioports *ioaddr = &ap->ioaddr;
332
ac19bff2 333 tf->command = ata_check_status(ap);
0169e284 334 tf->feature = inb(ioaddr->error_addr);
1da177e4
LT		 335 tf->nsect = inb(ioaddr->nsect_addr);
336 tf->lbal = inb(ioaddr->lbal_addr);
337 tf->lbam = inb(ioaddr->lbam_addr);
338 tf->lbah = inb(ioaddr->lbah_addr);
339 tf->device = inb(ioaddr->device_addr);
340
341 if (tf->flags & ATA_TFLAG_LBA48) {
342 outb(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
343 tf->hob_feature = inb(ioaddr->error_addr);
344 tf->hob_nsect = inb(ioaddr->nsect_addr);
345 tf->hob_lbal = inb(ioaddr->lbal_addr);
346 tf->hob_lbam = inb(ioaddr->lbam_addr);
347 tf->hob_lbah = inb(ioaddr->lbah_addr);
348 }
349}
350
351/**
352 * ata_tf_read_mmio - input device's ATA taskfile shadow registers
353 * @ap: Port from which input is read
354 * @tf: ATA taskfile register set for storing input
355 *
356 * Reads ATA taskfile registers for currently-selected device
357 * into @tf via MMIO.
358 *
359 * LOCKING:
360 * Inherited from caller.
361 */
362
363static void ata_tf_read_mmio(struct ata_port *ap, struct ata_taskfile *tf)
364{
365 struct ata_ioports *ioaddr = &ap->ioaddr;
366
ac19bff2 367 tf->command = ata_check_status(ap);
0169e284 368 tf->feature = readb((void __iomem *)ioaddr->error_addr);
1da177e4
LT		 369 tf->nsect = readb((void __iomem *)ioaddr->nsect_addr);
370 tf->lbal = readb((void __iomem *)ioaddr->lbal_addr);
371 tf->lbam = readb((void __iomem *)ioaddr->lbam_addr);
372 tf->lbah = readb((void __iomem *)ioaddr->lbah_addr);
373 tf->device = readb((void __iomem *)ioaddr->device_addr);
374
375 if (tf->flags & ATA_TFLAG_LBA48) {
376 writeb(tf->ctl | ATA_HOB, (void __iomem *) ap->ioaddr.ctl_addr);
377 tf->hob_feature = readb((void __iomem *)ioaddr->error_addr);
378 tf->hob_nsect = readb((void __iomem *)ioaddr->nsect_addr);
379 tf->hob_lbal = readb((void __iomem *)ioaddr->lbal_addr);
380 tf->hob_lbam = readb((void __iomem *)ioaddr->lbam_addr);
381 tf->hob_lbah = readb((void __iomem *)ioaddr->lbah_addr);
382 }
383}
384
0baab86b
EF		 385
386/**
387 * ata_tf_read - input device's ATA taskfile shadow registers
388 * @ap: Port from which input is read
389 * @tf: ATA taskfile register set for storing input
390 *
391 * Reads ATA taskfile registers for currently-selected device
392 * into @tf.
393 *
394 * Reads nsect, lbal, lbam, lbah, and device. If ATA_TFLAG_LBA48
395 * is set, also reads the hob registers.
396 *
397 * May be used as the tf_read() entry in ata_port_operations.
398 *
399 * LOCKING:
400 * Inherited from caller.
401 */
1da177e4
LT		 402void ata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
403{
404 if (ap->flags & ATA_FLAG_MMIO)
405 ata_tf_read_mmio(ap, tf);
406 else
407 ata_tf_read_pio(ap, tf);
408}
409
410/**
411 * ata_check_status_pio - Read device status reg & clear interrupt
412 * @ap: port where the device is
413 *
414 * Reads ATA taskfile status register for currently-selected device
0baab86b 415 * and return its value. This also clears pending interrupts
1da177e4
LT		 416 * from this device
417 *
418 * LOCKING:
419 * Inherited from caller.
420 */
421static u8 ata_check_status_pio(struct ata_port *ap)
422{
423 return inb(ap->ioaddr.status_addr);
424}
425
426/**
427 * ata_check_status_mmio - Read device status reg & clear interrupt
428 * @ap: port where the device is
429 *
430 * Reads ATA taskfile status register for currently-selected device
0baab86b 431 * via MMIO and return its value. This also clears pending interrupts
1da177e4
LT		 432 * from this device
433 *
434 * LOCKING:
435 * Inherited from caller.
436 */
437static u8 ata_check_status_mmio(struct ata_port *ap)
438{
439 return readb((void __iomem *) ap->ioaddr.status_addr);
440}
441
0baab86b
EF		 442
443/**
444 * ata_check_status - Read device status reg & clear interrupt
445 * @ap: port where the device is
446 *
447 * Reads ATA taskfile status register for currently-selected device
448 * and return its value. This also clears pending interrupts
449 * from this device
450 *
451 * May be used as the check_status() entry in ata_port_operations.
452 *
453 * LOCKING:
454 * Inherited from caller.
455 */
1da177e4
LT		 456u8 ata_check_status(struct ata_port *ap)
457{
458 if (ap->flags & ATA_FLAG_MMIO)
459 return ata_check_status_mmio(ap);
460 return ata_check_status_pio(ap);
461}
462
0baab86b
EF		 463
464/**
465 * ata_altstatus - Read device alternate status reg
466 * @ap: port where the device is
467 *
468 * Reads ATA taskfile alternate status register for
469 * currently-selected device and return its value.
470 *
471 * Note: may NOT be used as the check_altstatus() entry in
472 * ata_port_operations.
473 *
474 * LOCKING:
475 * Inherited from caller.
476 */
1da177e4
LT		 477u8 ata_altstatus(struct ata_port *ap)
478{
479 if (ap->ops->check_altstatus)
480 return ap->ops->check_altstatus(ap);
481
482 if (ap->flags & ATA_FLAG_MMIO)
483 return readb((void __iomem *)ap->ioaddr.altstatus_addr);
484 return inb(ap->ioaddr.altstatus_addr);
485}
486
0baab86b 487
1da177e4
LT		 488/**
489 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
490 * @tf: Taskfile to convert
491 * @fis: Buffer into which data will output
492 * @pmp: Port multiplier port
493 *
494 * Converts a standard ATA taskfile to a Serial ATA
495 * FIS structure (Register - Host to Device).
496 *
497 * LOCKING:
498 * Inherited from caller.
499 */
500
057ace5e 501void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 502{
503 fis[0] = 0x27; /* Register - Host to Device FIS */
504 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
505 bit 7 indicates Command FIS */
506 fis[2] = tf->command;
507 fis[3] = tf->feature;
508
509 fis[4] = tf->lbal;
510 fis[5] = tf->lbam;
511 fis[6] = tf->lbah;
512 fis[7] = tf->device;
513
514 fis[8] = tf->hob_lbal;
515 fis[9] = tf->hob_lbam;
516 fis[10] = tf->hob_lbah;
517 fis[11] = tf->hob_feature;
518
519 fis[12] = tf->nsect;
520 fis[13] = tf->hob_nsect;
521 fis[14] = 0;
522 fis[15] = tf->ctl;
523
524 fis[16] = 0;
525 fis[17] = 0;
526 fis[18] = 0;
527 fis[19] = 0;
528}
529
530/**
531 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
532 * @fis: Buffer from which data will be input
533 * @tf: Taskfile to output
534 *
e12a1be6 535 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 536 *
537 * LOCKING:
538 * Inherited from caller.
539 */
540
057ace5e 541void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 542{
543 tf->command = fis[2]; /* status */
544 tf->feature = fis[3]; /* error */
545
546 tf->lbal = fis[4];
547 tf->lbam = fis[5];
548 tf->lbah = fis[6];
549 tf->device = fis[7];
550
551 tf->hob_lbal = fis[8];
552 tf->hob_lbam = fis[9];
553 tf->hob_lbah = fis[10];
554
555 tf->nsect = fis[12];
556 tf->hob_nsect = fis[13];
557}
558
8cbd6df1
AL		 559static const u8 ata_rw_cmds[] = {
560 /* pio multi */
561 ATA_CMD_READ_MULTI,
562 ATA_CMD_WRITE_MULTI,
563 ATA_CMD_READ_MULTI_EXT,
564 ATA_CMD_WRITE_MULTI_EXT,
565 /* pio */
566 ATA_CMD_PIO_READ,
567 ATA_CMD_PIO_WRITE,
568 ATA_CMD_PIO_READ_EXT,
569 ATA_CMD_PIO_WRITE_EXT,
570 /* dma */
571 ATA_CMD_READ,
572 ATA_CMD_WRITE,
573 ATA_CMD_READ_EXT,
574 ATA_CMD_WRITE_EXT
575};
1da177e4
LT		 576
577/**
8cbd6df1
AL		 578 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
579 * @qc: command to examine and configure
1da177e4 580 *
8cbd6df1
AL		 581 * Examine the device configuration and tf->flags to calculate
582 * the proper read/write commands and protocol to use.
1da177e4
LT		 583 *
584 * LOCKING:
585 * caller.
586 */
8cbd6df1 587void ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 588{
8cbd6df1
AL		 589 struct ata_taskfile *tf = &qc->tf;
590 struct ata_device *dev = qc->dev;
1da177e4 591
8cbd6df1
AL		 592 int index, lba48, write;
593
594 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
595 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 596
8cbd6df1
AL		 597 if (dev->flags & ATA_DFLAG_PIO) {
598 tf->protocol = ATA_PROT_PIO;
599 index = dev->multi_count ? 0 : 4;
600 } else {
601 tf->protocol = ATA_PROT_DMA;
602 index = 8;
603 }
1da177e4 604
8cbd6df1 605 tf->command = ata_rw_cmds[index + lba48 + write];
1da177e4
LT		 606}
607
98ac62de 608static const char * const xfer_mode_str[] = {
1da177e4
LT		 609 "UDMA/16",
610 "UDMA/25",
611 "UDMA/33",
612 "UDMA/44",
613 "UDMA/66",
614 "UDMA/100",
615 "UDMA/133",
616 "UDMA7",
617 "MWDMA0",
618 "MWDMA1",
619 "MWDMA2",
620 "PIO0",
621 "PIO1",
622 "PIO2",
623 "PIO3",
624 "PIO4",
625};
626
627/**
628 * ata_udma_string - convert UDMA bit offset to string
629 * @mask: mask of bits supported; only highest bit counts.
630 *
631 * Determine string which represents the highest speed
632 * (highest bit in @udma_mask).
633 *
634 * LOCKING:
635 * None.
636 *
637 * RETURNS:
638 * Constant C string representing highest speed listed in
639 * @udma_mask, or the constant C string "<n/a>".
640 */
641
642static const char *ata_mode_string(unsigned int mask)
643{
644 int i;
645
646 for (i = 7; i >= 0; i--)
647 if (mask & (1 << i))
648 goto out;
649 for (i = ATA_SHIFT_MWDMA + 2; i >= ATA_SHIFT_MWDMA; i--)
650 if (mask & (1 << i))
651 goto out;
652 for (i = ATA_SHIFT_PIO + 4; i >= ATA_SHIFT_PIO; i--)
653 if (mask & (1 << i))
654 goto out;
655
656 return "<n/a>";
657
658out:
659 return xfer_mode_str[i];
660}
661
662/**
663 * ata_pio_devchk - PATA device presence detection
664 * @ap: ATA channel to examine
665 * @device: Device to examine (starting at zero)
666 *
667 * This technique was originally described in
668 * Hale Landis's ATADRVR (www.ata-atapi.com), and
669 * later found its way into the ATA/ATAPI spec.
670 *
671 * Write a pattern to the ATA shadow registers,
672 * and if a device is present, it will respond by
673 * correctly storing and echoing back the
674 * ATA shadow register contents.
675 *
676 * LOCKING:
677 * caller.
678 */
679
680static unsigned int ata_pio_devchk(struct ata_port *ap,
681 unsigned int device)
682{
683 struct ata_ioports *ioaddr = &ap->ioaddr;
684 u8 nsect, lbal;
685
686 ap->ops->dev_select(ap, device);
687
688 outb(0x55, ioaddr->nsect_addr);
689 outb(0xaa, ioaddr->lbal_addr);
690
691 outb(0xaa, ioaddr->nsect_addr);
692 outb(0x55, ioaddr->lbal_addr);
693
694 outb(0x55, ioaddr->nsect_addr);
695 outb(0xaa, ioaddr->lbal_addr);
696
697 nsect = inb(ioaddr->nsect_addr);
698 lbal = inb(ioaddr->lbal_addr);
699
700 if ((nsect == 0x55) && (lbal == 0xaa))
701 return 1; /* we found a device */
702
703 return 0; /* nothing found */
704}
705
706/**
707 * ata_mmio_devchk - PATA device presence detection
708 * @ap: ATA channel to examine
709 * @device: Device to examine (starting at zero)
710 *
711 * This technique was originally described in
712 * Hale Landis's ATADRVR (www.ata-atapi.com), and
713 * later found its way into the ATA/ATAPI spec.
714 *
715 * Write a pattern to the ATA shadow registers,
716 * and if a device is present, it will respond by
717 * correctly storing and echoing back the
718 * ATA shadow register contents.
719 *
720 * LOCKING:
721 * caller.
722 */
723
724static unsigned int ata_mmio_devchk(struct ata_port *ap,
725 unsigned int device)
726{
727 struct ata_ioports *ioaddr = &ap->ioaddr;
728 u8 nsect, lbal;
729
730 ap->ops->dev_select(ap, device);
731
732 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
733 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
734
735 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
736 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
737
738 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
739 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
740
741 nsect = readb((void __iomem *) ioaddr->nsect_addr);
742 lbal = readb((void __iomem *) ioaddr->lbal_addr);
743
744 if ((nsect == 0x55) && (lbal == 0xaa))
745 return 1; /* we found a device */
746
747 return 0; /* nothing found */
748}
749
750/**
751 * ata_devchk - PATA device presence detection
752 * @ap: ATA channel to examine
753 * @device: Device to examine (starting at zero)
754 *
755 * Dispatch ATA device presence detection, depending
756 * on whether we are using PIO or MMIO to talk to the
757 * ATA shadow registers.
758 *
759 * LOCKING:
760 * caller.
761 */
762
763static unsigned int ata_devchk(struct ata_port *ap,
764 unsigned int device)
765{
766 if (ap->flags & ATA_FLAG_MMIO)
767 return ata_mmio_devchk(ap, device);
768 return ata_pio_devchk(ap, device);
769}
770
771/**
772 * ata_dev_classify - determine device type based on ATA-spec signature
773 * @tf: ATA taskfile register set for device to be identified
774 *
775 * Determine from taskfile register contents whether a device is
776 * ATA or ATAPI, as per "Signature and persistence" section
777 * of ATA/PI spec (volume 1, sect 5.14).
778 *
779 * LOCKING:
780 * None.
781 *
782 * RETURNS:
783 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
784 * the event of failure.
785 */
786
057ace5e 787unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 788{
789 /* Apple's open source Darwin code hints that some devices only
790 * put a proper signature into the LBA mid/high registers,
791 * So, we only check those. It's sufficient for uniqueness.
792 */
793
794 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
795 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
796 DPRINTK("found ATA device by sig\n");
797 return ATA_DEV_ATA;
798 }
799
800 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
801 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
802 DPRINTK("found ATAPI device by sig\n");
803 return ATA_DEV_ATAPI;
804 }
805
806 DPRINTK("unknown device\n");
807 return ATA_DEV_UNKNOWN;
808}
809
810/**
811 * ata_dev_try_classify - Parse returned ATA device signature
812 * @ap: ATA channel to examine
813 * @device: Device to examine (starting at zero)
814 *
815 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
816 * an ATA/ATAPI-defined set of values is placed in the ATA
817 * shadow registers, indicating the results of device detection
818 * and diagnostics.
819 *
820 * Select the ATA device, and read the values from the ATA shadow
821 * registers. Then parse according to the Error register value,
822 * and the spec-defined values examined by ata_dev_classify().
823 *
824 * LOCKING:
825 * caller.
826 */
827
828static u8 ata_dev_try_classify(struct ata_port *ap, unsigned int device)
829{
830 struct ata_device *dev = &ap->device[device];
831 struct ata_taskfile tf;
832 unsigned int class;
833 u8 err;
834
835 ap->ops->dev_select(ap, device);
836
837 memset(&tf, 0, sizeof(tf));
838
1da177e4 839 ap->ops->tf_read(ap, &tf);
0169e284 840 err = tf.feature;
1da177e4
LT		 841
842 dev->class = ATA_DEV_NONE;
843
844 /* see if device passed diags */
845 if (err == 1)
846 /* do nothing */ ;
847 else if ((device == 0) && (err == 0x81))
848 /* do nothing */ ;
849 else
850 return err;
851
852 /* determine if device if ATA or ATAPI */
853 class = ata_dev_classify(&tf);
854 if (class == ATA_DEV_UNKNOWN)
855 return err;
856 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
857 return err;
858
859 dev->class = class;
860
861 return err;
862}
863
864/**
865 * ata_dev_id_string - Convert IDENTIFY DEVICE page into string
866 * @id: IDENTIFY DEVICE results we will examine
867 * @s: string into which data is output
868 * @ofs: offset into identify device page
869 * @len: length of string to return. must be an even number.
870 *
871 * The strings in the IDENTIFY DEVICE page are broken up into
872 * 16-bit chunks. Run through the string, and output each
873 * 8-bit chunk linearly, regardless of platform.
874 *
875 * LOCKING:
876 * caller.
877 */
878
057ace5e 879void ata_dev_id_string(const u16 *id, unsigned char *s,
1da177e4
LT		 880 unsigned int ofs, unsigned int len)
881{
882 unsigned int c;
883
884 while (len > 0) {
885 c = id[ofs] >> 8;
886 *s = c;
887 s++;
888
889 c = id[ofs] & 0xff;
890 *s = c;
891 s++;
892
893 ofs++;
894 len -= 2;
895 }
896}
897
0baab86b
EF		 898
899/**
900 * ata_noop_dev_select - Select device 0/1 on ATA bus
901 * @ap: ATA channel to manipulate
902 * @device: ATA device (numbered from zero) to select
903 *
904 * This function performs no actual function.
905 *
906 * May be used as the dev_select() entry in ata_port_operations.
907 *
908 * LOCKING:
909 * caller.
910 */
1da177e4
LT		 911void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
912{
913}
914
0baab86b 915
1da177e4
LT		 916/**
917 * ata_std_dev_select - Select device 0/1 on ATA bus
918 * @ap: ATA channel to manipulate
919 * @device: ATA device (numbered from zero) to select
920 *
921 * Use the method defined in the ATA specification to
922 * make either device 0, or device 1, active on the
0baab86b
EF		 923 * ATA channel. Works with both PIO and MMIO.
924 *
925 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 926 *
927 * LOCKING:
928 * caller.
929 */
930
931void ata_std_dev_select (struct ata_port *ap, unsigned int device)
932{
933 u8 tmp;
934
935 if (device == 0)
936 tmp = ATA_DEVICE_OBS;
937 else
938 tmp = ATA_DEVICE_OBS | ATA_DEV1;
939
940 if (ap->flags & ATA_FLAG_MMIO) {
941 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
942 } else {
943 outb(tmp, ap->ioaddr.device_addr);
944 }
945 ata_pause(ap); /* needed; also flushes, for mmio */
946}
947
948/**
949 * ata_dev_select - Select device 0/1 on ATA bus
950 * @ap: ATA channel to manipulate
951 * @device: ATA device (numbered from zero) to select
952 * @wait: non-zero to wait for Status register BSY bit to clear
953 * @can_sleep: non-zero if context allows sleeping
954 *
955 * Use the method defined in the ATA specification to
956 * make either device 0, or device 1, active on the
957 * ATA channel.
958 *
959 * This is a high-level version of ata_std_dev_select(),
960 * which additionally provides the services of inserting
961 * the proper pauses and status polling, where needed.
962 *
963 * LOCKING:
964 * caller.
965 */
966
967void ata_dev_select(struct ata_port *ap, unsigned int device,
968 unsigned int wait, unsigned int can_sleep)
969{
970 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
971 ap->id, device, wait);
972
973 if (wait)
974 ata_wait_idle(ap);
975
976 ap->ops->dev_select(ap, device);
977
978 if (wait) {
979 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
980 msleep(150);
981 ata_wait_idle(ap);
982 }
983}
984
985/**
986 * ata_dump_id - IDENTIFY DEVICE info debugging output
987 * @dev: Device whose IDENTIFY DEVICE page we will dump
988 *
989 * Dump selected 16-bit words from a detected device's
990 * IDENTIFY PAGE page.
991 *
992 * LOCKING:
993 * caller.
994 */
995
057ace5e 996static inline void ata_dump_id(const struct ata_device *dev)
1da177e4
LT		 997{
998 DPRINTK("49==0x%04x "
999 "53==0x%04x "
1000 "63==0x%04x "
1001 "64==0x%04x "
1002 "75==0x%04x \n",
1003 dev->id[49],
1004 dev->id[53],
1005 dev->id[63],
1006 dev->id[64],
1007 dev->id[75]);
1008 DPRINTK("80==0x%04x "
1009 "81==0x%04x "
1010 "82==0x%04x "
1011 "83==0x%04x "
1012 "84==0x%04x \n",
1013 dev->id[80],
1014 dev->id[81],
1015 dev->id[82],
1016 dev->id[83],
1017 dev->id[84]);
1018 DPRINTK("88==0x%04x "
1019 "93==0x%04x\n",
1020 dev->id[88],
1021 dev->id[93]);
1022}
1023
11e29e21
AC		 1024/*
1025 * Compute the PIO modes available for this device. This is not as
1026 * trivial as it seems if we must consider early devices correctly.
1027 *
1028 * FIXME: pre IDE drive timing (do we care ?).
1029 */
1030
057ace5e 1031static unsigned int ata_pio_modes(const struct ata_device *adev)
11e29e21
AC		 1032{
1033 u16 modes;
1034
1035 /* Usual case. Word 53 indicates word 88 is valid */
1036 if (adev->id[ATA_ID_FIELD_VALID] & (1 << 2)) {
1037 modes = adev->id[ATA_ID_PIO_MODES] & 0x03;
1038 modes <<= 3;
1039 modes |= 0x7;
1040 return modes;
1041 }
1042
1043 /* If word 88 isn't valid then Word 51 holds the PIO timing number
1044 for the maximum. Turn it into a mask and return it */
1045 modes = (2 << (adev->id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
1046 return modes;
1047}
1048
64f043d8
JG		 1049static int ata_qc_wait_err(struct ata_queued_cmd *qc,
1050 struct completion *wait)
1051{
1052 int rc = 0;
1053
1054 if (wait_for_completion_timeout(wait, 30 * HZ) < 1) {
1055 /* timeout handling */
a22e2eb0 1056 qc->err_mask |= ac_err_mask(ata_chk_status(qc->ap));
64f043d8 1057
a22e2eb0 1058 if (!qc->err_mask) {
64f043d8
JG		 1059 printk(KERN_WARNING "ata%u: slow completion (cmd %x)\n",
1060 qc->ap->id, qc->tf.command);
1061 } else {
1062 printk(KERN_WARNING "ata%u: qc timeout (cmd %x)\n",
1063 qc->ap->id, qc->tf.command);
1064 rc = -EIO;
1065 }
1066
a22e2eb0 1067 ata_qc_complete(qc);
64f043d8
JG		 1068 }
1069
1070 return rc;
1071}
1072
1da177e4
LT		 1073/**
1074 * ata_dev_identify - obtain IDENTIFY x DEVICE page
1075 * @ap: port on which device we wish to probe resides
1076 * @device: device bus address, starting at zero
1077 *
1078 * Following bus reset, we issue the IDENTIFY [PACKET] DEVICE
1079 * command, and read back the 512-byte device information page.
1080 * The device information page is fed to us via the standard
1081 * PIO-IN protocol, but we hand-code it here. (TODO: investigate
1082 * using standard PIO-IN paths)
1083 *
1084 * After reading the device information page, we use several
1085 * bits of information from it to initialize data structures
1086 * that will be used during the lifetime of the ata_device.
1087 * Other data from the info page is used to disqualify certain
1088 * older ATA devices we do not wish to support.
1089 *
1090 * LOCKING:
1091 * Inherited from caller. Some functions called by this function
1092 * obtain the host_set lock.
1093 */
1094
1095static void ata_dev_identify(struct ata_port *ap, unsigned int device)
1096{
1097 struct ata_device *dev = &ap->device[device];
8bf62ece 1098 unsigned int major_version;
1da177e4
LT		 1099 u16 tmp;
1100 unsigned long xfer_modes;
1da177e4
LT		 1101 unsigned int using_edd;
1102 DECLARE_COMPLETION(wait);
1103 struct ata_queued_cmd *qc;
1104 unsigned long flags;
1105 int rc;
1106
1107 if (!ata_dev_present(dev)) {
1108 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
1109 ap->id, device);
1110 return;
1111 }
1112
1113 if (ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1114 using_edd = 0;
1115 else
1116 using_edd = 1;
1117
1118 DPRINTK("ENTER, host %u, dev %u\n", ap->id, device);
1119
1120 assert (dev->class == ATA_DEV_ATA || dev->class == ATA_DEV_ATAPI ||
1121 dev->class == ATA_DEV_NONE);
1122
1123 ata_dev_select(ap, device, 1, 1); /* select device 0/1 */
1124
1125 qc = ata_qc_new_init(ap, dev);
1126 BUG_ON(qc == NULL);
1127
1128 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
1129 qc->dma_dir = DMA_FROM_DEVICE;
1130 qc->tf.protocol = ATA_PROT_PIO;
1131 qc->nsect = 1;
1132
1133retry:
1134 if (dev->class == ATA_DEV_ATA) {
1135 qc->tf.command = ATA_CMD_ID_ATA;
1136 DPRINTK("do ATA identify\n");
1137 } else {
1138 qc->tf.command = ATA_CMD_ID_ATAPI;
1139 DPRINTK("do ATAPI identify\n");
1140 }
1141
1142 qc->waiting = &wait;
1143 qc->complete_fn = ata_qc_complete_noop;
1144
1145 spin_lock_irqsave(&ap->host_set->lock, flags);
1146 rc = ata_qc_issue(qc);
1147 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1148
1149 if (rc)
1150 goto err_out;
1151 else
64f043d8 1152 ata_qc_wait_err(qc, &wait);
1da177e4 1153
0169e284
JG		 1154 spin_lock_irqsave(&ap->host_set->lock, flags);
1155 ap->ops->tf_read(ap, &qc->tf);
1156 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1157
1158 if (qc->tf.command & ATA_ERR) {
1da177e4
LT		 1159 /*
1160 * arg! EDD works for all test cases, but seems to return
1161 * the ATA signature for some ATAPI devices. Until the
1162 * reason for this is found and fixed, we fix up the mess
1163 * here. If IDENTIFY DEVICE returns command aborted
1164 * (as ATAPI devices do), then we issue an
1165 * IDENTIFY PACKET DEVICE.
1166 *
1167 * ATA software reset (SRST, the default) does not appear
1168 * to have this problem.
1169 */
7c398335 1170 if ((using_edd) && (dev->class == ATA_DEV_ATA)) {
0169e284 1171 u8 err = qc->tf.feature;
1da177e4
LT		 1172 if (err & ATA_ABORTED) {
1173 dev->class = ATA_DEV_ATAPI;
1174 qc->cursg = 0;
1175 qc->cursg_ofs = 0;
1176 qc->cursect = 0;
1177 qc->nsect = 1;
a22e2eb0 1178 qc->err_mask = 0;
1da177e4
LT		 1179 goto retry;
1180 }
1181 }
1182 goto err_out;
1183 }
1184
1185 swap_buf_le16(dev->id, ATA_ID_WORDS);
1186
1187 /* print device capabilities */
1188 printk(KERN_DEBUG "ata%u: dev %u cfg "
1189 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
1190 ap->id, device, dev->id[49],
1191 dev->id[82], dev->id[83], dev->id[84],
1192 dev->id[85], dev->id[86], dev->id[87],
1193 dev->id[88]);
1194
1195 /*
1196 * common ATA, ATAPI feature tests
1197 */
1198
8bf62ece
AL		 1199 /* we require DMA support (bits 8 of word 49) */
1200 if (!ata_id_has_dma(dev->id)) {
1201 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
1da177e4
LT		 1202 goto err_out_nosup;
1203 }
1204
1205 /* quick-n-dirty find max transfer mode; for printk only */
1206 xfer_modes = dev->id[ATA_ID_UDMA_MODES];
1207 if (!xfer_modes)
1208 xfer_modes = (dev->id[ATA_ID_MWDMA_MODES]) << ATA_SHIFT_MWDMA;
11e29e21
AC		 1209 if (!xfer_modes)
1210 xfer_modes = ata_pio_modes(dev);
1da177e4
LT		 1211
1212 ata_dump_id(dev);
1213
1214 /* ATA-specific feature tests */
1215 if (dev->class == ATA_DEV_ATA) {
1216 if (!ata_id_is_ata(dev->id)) /* sanity check */
1217 goto err_out_nosup;
1218
8bf62ece 1219 /* get major version */
1da177e4 1220 tmp = dev->id[ATA_ID_MAJOR_VER];
8bf62ece
AL		 1221 for (major_version = 14; major_version >= 1; major_version--)
1222 if (tmp & (1 << major_version))
1da177e4
LT		 1223 break;
1224
8bf62ece
AL		 1225 /*
1226 * The exact sequence expected by certain pre-ATA4 drives is:
1227 * SRST RESET
1228 * IDENTIFY
1229 * INITIALIZE DEVICE PARAMETERS
1230 * anything else..
1231 * Some drives were very specific about that exact sequence.
1232 */
59a10b17 1233 if (major_version < 4 || (!ata_id_has_lba(dev->id))) {
8bf62ece
AL		 1234 ata_dev_init_params(ap, dev);
1235
59a10b17
AL		 1236 /* current CHS translation info (id[53-58]) might be
1237 * changed. reread the identify device info.
1238 */
1239 ata_dev_reread_id(ap, dev);
1240 }
1241
8bf62ece
AL		 1242 if (ata_id_has_lba(dev->id)) {
1243 dev->flags |= ATA_DFLAG_LBA;
1244
1245 if (ata_id_has_lba48(dev->id)) {
1246 dev->flags |= ATA_DFLAG_LBA48;
1247 dev->n_sectors = ata_id_u64(dev->id, 100);
1248 } else {
1249 dev->n_sectors = ata_id_u32(dev->id, 60);
1250 }
1251
1252 /* print device info to dmesg */
1253 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors:%s\n",
1254 ap->id, device,
1255 major_version,
1256 ata_mode_string(xfer_modes),
1257 (unsigned long long)dev->n_sectors,
1258 dev->flags & ATA_DFLAG_LBA48 ? " LBA48" : " LBA");
1259 } else {
1260 /* CHS */
1261
1262 /* Default translation */
1263 dev->cylinders = dev->id[1];
1264 dev->heads = dev->id[3];
1265 dev->sectors = dev->id[6];
1266 dev->n_sectors = dev->cylinders * dev->heads * dev->sectors;
1267
1268 if (ata_id_current_chs_valid(dev->id)) {
1269 /* Current CHS translation is valid. */
1270 dev->cylinders = dev->id[54];
1271 dev->heads = dev->id[55];
1272 dev->sectors = dev->id[56];
1273
1274 dev->n_sectors = ata_id_u32(dev->id, 57);
1275 }
1276
1277 /* print device info to dmesg */
1278 printk(KERN_INFO "ata%u: dev %u ATA-%d, max %s, %Lu sectors: CHS %d/%d/%d\n",
1279 ap->id, device,
1280 major_version,
1281 ata_mode_string(xfer_modes),
1282 (unsigned long long)dev->n_sectors,
1283 (int)dev->cylinders, (int)dev->heads, (int)dev->sectors);
1da177e4 1284
1da177e4
LT		 1285 }
1286
1287 ap->host->max_cmd_len = 16;
1da177e4
LT		 1288 }
1289
1290 /* ATAPI-specific feature tests */
2c13b7ce 1291 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1292 if (ata_id_is_ata(dev->id)) /* sanity check */
1293 goto err_out_nosup;
1294
1295 rc = atapi_cdb_len(dev->id);
1296 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1297 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
1298 goto err_out_nosup;
1299 }
1300 ap->cdb_len = (unsigned int) rc;
1301 ap->host->max_cmd_len = (unsigned char) ap->cdb_len;
1302
1303 /* print device info to dmesg */
1304 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
1305 ap->id, device,
1306 ata_mode_string(xfer_modes));
1307 }
1308
1309 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
1310 return;
1311
1312err_out_nosup:
1313 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
1314 ap->id, device);
1315err_out:
1316 dev->class++; /* converts ATA_DEV_xxx into ATA_DEV_xxx_UNSUP */
1317 DPRINTK("EXIT, err\n");
1318}
1319
6f2f3812 1320
057ace5e 1321static inline u8 ata_dev_knobble(const struct ata_port *ap)
6f2f3812
BC		 1322{
1323 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(ap->device->id)));
1324}
1325
1326/**
1327 * ata_dev_config - Run device specific handlers and check for
1328 * SATA->PATA bridges
8a60a071 1329 * @ap: Bus
6f2f3812
BC		 1330 * @i: Device
1331 *
1332 * LOCKING:
1333 */
8a60a071 1334
6f2f3812
BC		 1335void ata_dev_config(struct ata_port *ap, unsigned int i)
1336{
1337 /* limit bridge transfers to udma5, 200 sectors */
1338 if (ata_dev_knobble(ap)) {
1339 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1340 ap->id, ap->device->devno);
1341 ap->udma_mask &= ATA_UDMA5;
1342 ap->host->max_sectors = ATA_MAX_SECTORS;
1343 ap->host->hostt->max_sectors = ATA_MAX_SECTORS;
1344 ap->device->flags |= ATA_DFLAG_LOCK_SECTORS;
1345 }
1346
1347 if (ap->ops->dev_config)
1348 ap->ops->dev_config(ap, &ap->device[i]);
1349}
1350
1da177e4
LT		 1351/**
1352 * ata_bus_probe - Reset and probe ATA bus
1353 * @ap: Bus to probe
1354 *
0cba632b
JG		 1355 * Master ATA bus probing function. Initiates a hardware-dependent
1356 * bus reset, then attempts to identify any devices found on
1357 * the bus.
1358 *
1da177e4 1359 * LOCKING:
0cba632b 1360 * PCI/etc. bus probe sem.
1da177e4
LT		 1361 *
1362 * RETURNS:
1363 * Zero on success, non-zero on error.
1364 */
1365
1366static int ata_bus_probe(struct ata_port *ap)
1367{
1368 unsigned int i, found = 0;
1369
1370 ap->ops->phy_reset(ap);
1371 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1372 goto err_out;
1373
1374 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1375 ata_dev_identify(ap, i);
1376 if (ata_dev_present(&ap->device[i])) {
1377 found = 1;
6f2f3812 1378 ata_dev_config(ap,i);
1da177e4
LT		 1379 }
1380 }
1381
1382 if ((!found) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1383 goto err_out_disable;
1384
1385 ata_set_mode(ap);
1386 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1387 goto err_out_disable;
1388
1389 return 0;
1390
1391err_out_disable:
1392 ap->ops->port_disable(ap);
1393err_out:
1394 return -1;
1395}
1396
1397/**
0cba632b
JG		 1398 * ata_port_probe - Mark port as enabled
1399 * @ap: Port for which we indicate enablement
1da177e4 1400 *
0cba632b
JG		 1401 * Modify @ap data structure such that the system
1402 * thinks that the entire port is enabled.
1403 *
1404 * LOCKING: host_set lock, or some other form of
1405 * serialization.
1da177e4
LT		 1406 */
1407
1408void ata_port_probe(struct ata_port *ap)
1409{
1410 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1411}
1412
1413/**
780a87f7
JG		 1414 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1415 * @ap: SATA port associated with target SATA PHY.
1da177e4 1416 *
780a87f7
JG		 1417 * This function issues commands to standard SATA Sxxx
1418 * PHY registers, to wake up the phy (and device), and
1419 * clear any reset condition.
1da177e4
LT		 1420 *
1421 * LOCKING:
0cba632b 1422 * PCI/etc. bus probe sem.
1da177e4
LT		 1423 *
1424 */
1425void __sata_phy_reset(struct ata_port *ap)
1426{
1427 u32 sstatus;
1428 unsigned long timeout = jiffies + (HZ * 5);
1429
1430 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1431 /* issue phy wake/reset */
1432 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1433 /* Couldn't find anything in SATA I/II specs, but
1434 * AHCI-1.1 10.4.2 says at least 1 ms. */
1435 mdelay(1);
1da177e4 1436 }
cdcca89e 1437 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1438
1439 /* wait for phy to become ready, if necessary */
1440 do {
1441 msleep(200);
1442 sstatus = scr_read(ap, SCR_STATUS);
1443 if ((sstatus & 0xf) != 1)
1444 break;
1445 } while (time_before(jiffies, timeout));
1446
1447 /* TODO: phy layer with polling, timeouts, etc. */
656563e3
JG		 1448 sstatus = scr_read(ap, SCR_STATUS);
1449 if (sata_dev_present(ap)) {
1450 const char *speed;
1451 u32 tmp;
1452
1453 tmp = (sstatus >> 4) & 0xf;
1454 if (tmp & (1 << 0))
1455 speed = "1.5";
1456 else if (tmp & (1 << 1))
1457 speed = "3.0";
1458 else
1459 speed = "<unknown>";
1460 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1461 ap->id, speed, sstatus);
1da177e4 1462 ata_port_probe(ap);
656563e3
JG		 1463 } else {
1464 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1da177e4
LT		 1465 ap->id, sstatus);
1466 ata_port_disable(ap);
1467 }
1468
1469 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1470 return;
1471
1472 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1473 ata_port_disable(ap);
1474 return;
1475 }
1476
1477 ap->cbl = ATA_CBL_SATA;
1478}
1479
1480/**
780a87f7
JG		 1481 * sata_phy_reset - Reset SATA bus.
1482 * @ap: SATA port associated with target SATA PHY.
1da177e4 1483 *
780a87f7
JG		 1484 * This function resets the SATA bus, and then probes
1485 * the bus for devices.
1da177e4
LT		 1486 *
1487 * LOCKING:
0cba632b 1488 * PCI/etc. bus probe sem.
1da177e4
LT		 1489 *
1490 */
1491void sata_phy_reset(struct ata_port *ap)
1492{
1493 __sata_phy_reset(ap);
1494 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1495 return;
1496 ata_bus_reset(ap);
1497}
1498
1499/**
780a87f7
JG		 1500 * ata_port_disable - Disable port.
1501 * @ap: Port to be disabled.
1da177e4 1502 *
780a87f7
JG		 1503 * Modify @ap data structure such that the system
1504 * thinks that the entire port is disabled, and should
1505 * never attempt to probe or communicate with devices
1506 * on this port.
1507 *
1508 * LOCKING: host_set lock, or some other form of
1509 * serialization.
1da177e4
LT		 1510 */
1511
1512void ata_port_disable(struct ata_port *ap)
1513{
1514 ap->device[0].class = ATA_DEV_NONE;
1515 ap->device[1].class = ATA_DEV_NONE;
1516 ap->flags |= ATA_FLAG_PORT_DISABLED;
1517}
1518
452503f9
AC		 1519/*
1520 * This mode timing computation functionality is ported over from
1521 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1522 */
1523/*
1524 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1525 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1526 * for PIO 5, which is a nonstandard extension and UDMA6, which
1527 * is currently supported only by Maxtor drives.
1528 */
1529
1530static const struct ata_timing ata_timing[] = {
1531
1532 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1533 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1534 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1535 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1536
1537 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1538 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1539 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1540
1541/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1542
1543 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1544 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1545 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1546
1547 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1548 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1549 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1550
1551/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1552 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1553 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1554
1555 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1556 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1557 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1558
1559/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1560
1561 { 0xFF }
1562};
1563
1564#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1565#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1566
1567static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1568{
1569 q->setup = EZ(t->setup * 1000, T);
1570 q->act8b = EZ(t->act8b * 1000, T);
1571 q->rec8b = EZ(t->rec8b * 1000, T);
1572 q->cyc8b = EZ(t->cyc8b * 1000, T);
1573 q->active = EZ(t->active * 1000, T);
1574 q->recover = EZ(t->recover * 1000, T);
1575 q->cycle = EZ(t->cycle * 1000, T);
1576 q->udma = EZ(t->udma * 1000, UT);
1577}
1578
1579void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1580 struct ata_timing *m, unsigned int what)
1581{
1582 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1583 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1584 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1585 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1586 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1587 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1588 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1589 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1590}
1591
1592static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1593{
1594 const struct ata_timing *t;
1595
1596 for (t = ata_timing; t->mode != speed; t++)
91190758 1597 if (t->mode == 0xFF)
452503f9
AC		 1598 return NULL;
1599 return t;
1600}
1601
1602int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1603 struct ata_timing *t, int T, int UT)
1604{
1605 const struct ata_timing *s;
1606 struct ata_timing p;
1607
1608 /*
1609 * Find the mode.
75b1f2f8 1610 */
452503f9
AC		 1611
1612 if (!(s = ata_timing_find_mode(speed)))
1613 return -EINVAL;
1614
75b1f2f8
AL		 1615 memcpy(t, s, sizeof(*s));
1616
452503f9
AC		 1617 /*
1618 * If the drive is an EIDE drive, it can tell us it needs extended
1619 * PIO/MW_DMA cycle timing.
1620 */
1621
1622 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1623 memset(&p, 0, sizeof(p));
1624 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1625 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1626 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1627 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1628 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1629 }
1630 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1631 }
1632
1633 /*
1634 * Convert the timing to bus clock counts.
1635 */
1636
75b1f2f8 1637 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1638
1639 /*
1640 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, S.M.A.R.T
1641 * and some other commands. We have to ensure that the DMA cycle timing is
1642 * slower/equal than the fastest PIO timing.
1643 */
1644
1645 if (speed > XFER_PIO_4) {
1646 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1647 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1648 }
1649
1650 /*
1651 * Lenghten active & recovery time so that cycle time is correct.
1652 */
1653
1654 if (t->act8b + t->rec8b < t->cyc8b) {
1655 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1656 t->rec8b = t->cyc8b - t->act8b;
1657 }
1658
1659 if (t->active + t->recover < t->cycle) {
1660 t->active += (t->cycle - (t->active + t->recover)) / 2;
1661 t->recover = t->cycle - t->active;
1662 }
1663
1664 return 0;
1665}
1666
057ace5e 1667static const struct {
1da177e4
LT		 1668 unsigned int shift;
1669 u8 base;
1670} xfer_mode_classes[] = {
1671 { ATA_SHIFT_UDMA, XFER_UDMA_0 },
1672 { ATA_SHIFT_MWDMA, XFER_MW_DMA_0 },
1673 { ATA_SHIFT_PIO, XFER_PIO_0 },
1674};
1675
1676static inline u8 base_from_shift(unsigned int shift)
1677{
1678 int i;
1679
1680 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++)
1681 if (xfer_mode_classes[i].shift == shift)
1682 return xfer_mode_classes[i].base;
1683
1684 return 0xff;
1685}
1686
1687static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1688{
1689 int ofs, idx;
1690 u8 base;
1691
1692 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1693 return;
1694
1695 if (dev->xfer_shift == ATA_SHIFT_PIO)
1696 dev->flags |= ATA_DFLAG_PIO;
1697
1698 ata_dev_set_xfermode(ap, dev);
1699
1700 base = base_from_shift(dev->xfer_shift);
1701 ofs = dev->xfer_mode - base;
1702 idx = ofs + dev->xfer_shift;
1703 WARN_ON(idx >= ARRAY_SIZE(xfer_mode_str));
1704
1705 DPRINTK("idx=%d xfer_shift=%u, xfer_mode=0x%x, base=0x%x, offset=%d\n",
1706 idx, dev->xfer_shift, (int)dev->xfer_mode, (int)base, ofs);
1707
1708 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
1709 ap->id, dev->devno, xfer_mode_str[idx]);
1710}
1711
1712static int ata_host_set_pio(struct ata_port *ap)
1713{
1714 unsigned int mask;
1715 int x, i;
1716 u8 base, xfer_mode;
1717
1718 mask = ata_get_mode_mask(ap, ATA_SHIFT_PIO);
1719 x = fgb(mask);
1720 if (x < 0) {
1721 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1722 return -1;
1723 }
1724
1725 base = base_from_shift(ATA_SHIFT_PIO);
1726 xfer_mode = base + x;
1727
1728 DPRINTK("base 0x%x xfer_mode 0x%x mask 0x%x x %d\n",
1729 (int)base, (int)xfer_mode, mask, x);
1730
1731 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1732 struct ata_device *dev = &ap->device[i];
1733 if (ata_dev_present(dev)) {
1734 dev->pio_mode = xfer_mode;
1735 dev->xfer_mode = xfer_mode;
1736 dev->xfer_shift = ATA_SHIFT_PIO;
1737 if (ap->ops->set_piomode)
1738 ap->ops->set_piomode(ap, dev);
1739 }
1740 }
1741
1742 return 0;
1743}
1744
1745static void ata_host_set_dma(struct ata_port *ap, u8 xfer_mode,
1746 unsigned int xfer_shift)
1747{
1748 int i;
1749
1750 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1751 struct ata_device *dev = &ap->device[i];
1752 if (ata_dev_present(dev)) {
1753 dev->dma_mode = xfer_mode;
1754 dev->xfer_mode = xfer_mode;
1755 dev->xfer_shift = xfer_shift;
1756 if (ap->ops->set_dmamode)
1757 ap->ops->set_dmamode(ap, dev);
1758 }
1759 }
1760}
1761
1762/**
1763 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1764 * @ap: port on which timings will be programmed
1765 *
780a87f7
JG		 1766 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1767 *
1da177e4 1768 * LOCKING:
0cba632b 1769 * PCI/etc. bus probe sem.
1da177e4
LT		 1770 *
1771 */
1772static void ata_set_mode(struct ata_port *ap)
1773{
8cbd6df1 1774 unsigned int xfer_shift;
1da177e4
LT		 1775 u8 xfer_mode;
1776 int rc;
1777
1778 /* step 1: always set host PIO timings */
1779 rc = ata_host_set_pio(ap);
1780 if (rc)
1781 goto err_out;
1782
1783 /* step 2: choose the best data xfer mode */
1784 xfer_mode = xfer_shift = 0;
1785 rc = ata_choose_xfer_mode(ap, &xfer_mode, &xfer_shift);
1786 if (rc)
1787 goto err_out;
1788
1789 /* step 3: if that xfer mode isn't PIO, set host DMA timings */
1790 if (xfer_shift != ATA_SHIFT_PIO)
1791 ata_host_set_dma(ap, xfer_mode, xfer_shift);
1792
1793 /* step 4: update devices' xfer mode */
1794 ata_dev_set_mode(ap, &ap->device[0]);
1795 ata_dev_set_mode(ap, &ap->device[1]);
1796
1797 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1798 return;
1799
1800 if (ap->ops->post_set_mode)
1801 ap->ops->post_set_mode(ap);
1802
1da177e4
LT		 1803 return;
1804
1805err_out:
1806 ata_port_disable(ap);
1807}
1808
1809/**
1810 * ata_busy_sleep - sleep until BSY clears, or timeout
1811 * @ap: port containing status register to be polled
1812 * @tmout_pat: impatience timeout
1813 * @tmout: overall timeout
1814 *
780a87f7
JG		 1815 * Sleep until ATA Status register bit BSY clears,
1816 * or a timeout occurs.
1817 *
1818 * LOCKING: None.
1da177e4
LT		 1819 *
1820 */
1821
1822static unsigned int ata_busy_sleep (struct ata_port *ap,
1823 unsigned long tmout_pat,
1824 unsigned long tmout)
1825{
1826 unsigned long timer_start, timeout;
1827 u8 status;
1828
1829 status = ata_busy_wait(ap, ATA_BUSY, 300);
1830 timer_start = jiffies;
1831 timeout = timer_start + tmout_pat;
1832 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1833 msleep(50);
1834 status = ata_busy_wait(ap, ATA_BUSY, 3);
1835 }
1836
1837 if (status & ATA_BUSY)
1838 printk(KERN_WARNING "ata%u is slow to respond, "
1839 "please be patient\n", ap->id);
1840
1841 timeout = timer_start + tmout;
1842 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1843 msleep(50);
1844 status = ata_chk_status(ap);
1845 }
1846
1847 if (status & ATA_BUSY) {
1848 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1849 ap->id, tmout / HZ);
1850 return 1;
1851 }
1852
1853 return 0;
1854}
1855
1856static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1857{
1858 struct ata_ioports *ioaddr = &ap->ioaddr;
1859 unsigned int dev0 = devmask & (1 << 0);
1860 unsigned int dev1 = devmask & (1 << 1);
1861 unsigned long timeout;
1862
1863 /* if device 0 was found in ata_devchk, wait for its
1864 * BSY bit to clear
1865 */
1866 if (dev0)
1867 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1868
1869 /* if device 1 was found in ata_devchk, wait for
1870 * register access, then wait for BSY to clear
1871 */
1872 timeout = jiffies + ATA_TMOUT_BOOT;
1873 while (dev1) {
1874 u8 nsect, lbal;
1875
1876 ap->ops->dev_select(ap, 1);
1877 if (ap->flags & ATA_FLAG_MMIO) {
1878 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1879 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1880 } else {
1881 nsect = inb(ioaddr->nsect_addr);
1882 lbal = inb(ioaddr->lbal_addr);
1883 }
1884 if ((nsect == 1) && (lbal == 1))
1885 break;
1886 if (time_after(jiffies, timeout)) {
1887 dev1 = 0;
1888 break;
1889 }
1890 msleep(50); /* give drive a breather */
1891 }
1892 if (dev1)
1893 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1894
1895 /* is all this really necessary? */
1896 ap->ops->dev_select(ap, 0);
1897 if (dev1)
1898 ap->ops->dev_select(ap, 1);
1899 if (dev0)
1900 ap->ops->dev_select(ap, 0);
1901}
1902
1903/**
0cba632b
JG		 1904 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1905 * @ap: Port to reset and probe
1906 *
1907 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1908 * probe the bus. Not often used these days.
1da177e4
LT		 1909 *
1910 * LOCKING:
0cba632b 1911 * PCI/etc. bus probe sem.
e5338254 1912 * Obtains host_set lock.
1da177e4
LT		 1913 *
1914 */
1915
1916static unsigned int ata_bus_edd(struct ata_port *ap)
1917{
1918 struct ata_taskfile tf;
e5338254 1919 unsigned long flags;
1da177e4
LT		 1920
1921 /* set up execute-device-diag (bus reset) taskfile */
1922 /* also, take interrupts to a known state (disabled) */
1923 DPRINTK("execute-device-diag\n");
1924 ata_tf_init(ap, &tf, 0);
1925 tf.ctl |= ATA_NIEN;
1926 tf.command = ATA_CMD_EDD;
1927 tf.protocol = ATA_PROT_NODATA;
1928
1929 /* do bus reset */
e5338254 1930 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1931 ata_tf_to_host(ap, &tf);
e5338254 1932 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1933
1934 /* spec says at least 2ms. but who knows with those
1935 * crazy ATAPI devices...
1936 */
1937 msleep(150);
1938
1939 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1940}
1941
1942static unsigned int ata_bus_softreset(struct ata_port *ap,
1943 unsigned int devmask)
1944{
1945 struct ata_ioports *ioaddr = &ap->ioaddr;
1946
1947 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1948
1949 /* software reset. causes dev0 to be selected */
1950 if (ap->flags & ATA_FLAG_MMIO) {
1951 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1952 udelay(20); /* FIXME: flush */
1953 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1954 udelay(20); /* FIXME: flush */
1955 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1956 } else {
1957 outb(ap->ctl, ioaddr->ctl_addr);
1958 udelay(10);
1959 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1960 udelay(10);
1961 outb(ap->ctl, ioaddr->ctl_addr);
1962 }
1963
1964 /* spec mandates ">= 2ms" before checking status.
1965 * We wait 150ms, because that was the magic delay used for
1966 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1967 * between when the ATA command register is written, and then
1968 * status is checked. Because waiting for "a while" before
1969 * checking status is fine, post SRST, we perform this magic
1970 * delay here as well.
1971 */
1972 msleep(150);
1973
1974 ata_bus_post_reset(ap, devmask);
1975
1976 return 0;
1977}
1978
1979/**
1980 * ata_bus_reset - reset host port and associated ATA channel
1981 * @ap: port to reset
1982 *
1983 * This is typically the first time we actually start issuing
1984 * commands to the ATA channel. We wait for BSY to clear, then
1985 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
1986 * result. Determine what devices, if any, are on the channel
1987 * by looking at the device 0/1 error register. Look at the signature
1988 * stored in each device's taskfile registers, to determine if
1989 * the device is ATA or ATAPI.
1990 *
1991 * LOCKING:
0cba632b
JG		 1992 * PCI/etc. bus probe sem.
1993 * Obtains host_set lock.
1da177e4
LT		 1994 *
1995 * SIDE EFFECTS:
1996 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
1997 */
1998
1999void ata_bus_reset(struct ata_port *ap)
2000{
2001 struct ata_ioports *ioaddr = &ap->ioaddr;
2002 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2003 u8 err;
2004 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
2005
2006 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2007
2008 /* determine if device 0/1 are present */
2009 if (ap->flags & ATA_FLAG_SATA_RESET)
2010 dev0 = 1;
2011 else {
2012 dev0 = ata_devchk(ap, 0);
2013 if (slave_possible)
2014 dev1 = ata_devchk(ap, 1);
2015 }
2016
2017 if (dev0)
2018 devmask |= (1 << 0);
2019 if (dev1)
2020 devmask |= (1 << 1);
2021
2022 /* select device 0 again */
2023 ap->ops->dev_select(ap, 0);
2024
2025 /* issue bus reset */
2026 if (ap->flags & ATA_FLAG_SRST)
2027 rc = ata_bus_softreset(ap, devmask);
2028 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
2029 /* set up device control */
2030 if (ap->flags & ATA_FLAG_MMIO)
2031 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2032 else
2033 outb(ap->ctl, ioaddr->ctl_addr);
2034 rc = ata_bus_edd(ap);
2035 }
2036
2037 if (rc)
2038 goto err_out;
2039
2040 /*
2041 * determine by signature whether we have ATA or ATAPI devices
2042 */
2043 err = ata_dev_try_classify(ap, 0);
2044 if ((slave_possible) && (err != 0x81))
2045 ata_dev_try_classify(ap, 1);
2046
2047 /* re-enable interrupts */
2048 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2049 ata_irq_on(ap);
2050
2051 /* is double-select really necessary? */
2052 if (ap->device[1].class != ATA_DEV_NONE)
2053 ap->ops->dev_select(ap, 1);
2054 if (ap->device[0].class != ATA_DEV_NONE)
2055 ap->ops->dev_select(ap, 0);
2056
2057 /* if no devices were detected, disable this port */
2058 if ((ap->device[0].class == ATA_DEV_NONE) &&
2059 (ap->device[1].class == ATA_DEV_NONE))
2060 goto err_out;
2061
2062 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2063 /* set up device control for ATA_FLAG_SATA_RESET */
2064 if (ap->flags & ATA_FLAG_MMIO)
2065 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2066 else
2067 outb(ap->ctl, ioaddr->ctl_addr);
2068 }
2069
2070 DPRINTK("EXIT\n");
2071 return;
2072
2073err_out:
2074 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2075 ap->ops->port_disable(ap);
2076
2077 DPRINTK("EXIT\n");
2078}
2079
057ace5e
JG		 2080static void ata_pr_blacklisted(const struct ata_port *ap,
2081 const struct ata_device *dev)
1da177e4
LT		 2082{
2083 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, disabling DMA\n",
2084 ap->id, dev->devno);
2085}
2086
98ac62de 2087static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2088 "WDC AC11000H",
2089 "WDC AC22100H",
2090 "WDC AC32500H",
2091 "WDC AC33100H",
2092 "WDC AC31600H",
2093 "WDC AC32100H",
2094 "WDC AC23200L",
2095 "Compaq CRD-8241B",
2096 "CRD-8400B",
2097 "CRD-8480B",
2098 "CRD-8482B",
2099 "CRD-84",
2100 "SanDisk SDP3B",
2101 "SanDisk SDP3B-64",
2102 "SANYO CD-ROM CRD",
2103 "HITACHI CDR-8",
2104 "HITACHI CDR-8335",
2105 "HITACHI CDR-8435",
2106 "Toshiba CD-ROM XM-6202B",
e922256a 2107 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2108 "CD-532E-A",
2109 "E-IDE CD-ROM CR-840",
2110 "CD-ROM Drive/F5A",
2111 "WPI CDD-820",
2112 "SAMSUNG CD-ROM SC-148C",
2113 "SAMSUNG CD-ROM SC",
2114 "SanDisk SDP3B-64",
1da177e4
LT		 2115 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2116 "_NEC DV5800A",
2117};
2118
057ace5e 2119static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4
LT		 2120{
2121 unsigned char model_num[40];
2122 char *s;
2123 unsigned int len;
2124 int i;
2125
2126 ata_dev_id_string(dev->id, model_num, ATA_ID_PROD_OFS,
2127 sizeof(model_num));
2128 s = &model_num[0];
2129 len = strnlen(s, sizeof(model_num));
2130
2131 /* ATAPI specifies that empty space is blank-filled; remove blanks */
2132 while ((len > 0) && (s[len - 1] == ' ')) {
2133 len--;
2134 s[len] = 0;
2135 }
2136
2137 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2138 if (!strncmp(ata_dma_blacklist[i], s, len))
2139 return 1;
2140
2141 return 0;
2142}
2143
057ace5e 2144static unsigned int ata_get_mode_mask(const struct ata_port *ap, int shift)
1da177e4 2145{
057ace5e 2146 const struct ata_device *master, *slave;
1da177e4
LT		 2147 unsigned int mask;
2148
2149 master = &ap->device[0];
2150 slave = &ap->device[1];
2151
2152 assert (ata_dev_present(master) || ata_dev_present(slave));
2153
2154 if (shift == ATA_SHIFT_UDMA) {
2155 mask = ap->udma_mask;
2156 if (ata_dev_present(master)) {
2157 mask &= (master->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2158 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2159 mask = 0;
2160 ata_pr_blacklisted(ap, master);
2161 }
2162 }
2163 if (ata_dev_present(slave)) {
2164 mask &= (slave->id[ATA_ID_UDMA_MODES] & 0xff);
057ace5e 2165 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2166 mask = 0;
2167 ata_pr_blacklisted(ap, slave);
2168 }
2169 }
2170 }
2171 else if (shift == ATA_SHIFT_MWDMA) {
2172 mask = ap->mwdma_mask;
2173 if (ata_dev_present(master)) {
2174 mask &= (master->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2175 if (ata_dma_blacklisted(master)) {
1da177e4
LT		 2176 mask = 0;
2177 ata_pr_blacklisted(ap, master);
2178 }
2179 }
2180 if (ata_dev_present(slave)) {
2181 mask &= (slave->id[ATA_ID_MWDMA_MODES] & 0x07);
057ace5e 2182 if (ata_dma_blacklisted(slave)) {
1da177e4
LT		 2183 mask = 0;
2184 ata_pr_blacklisted(ap, slave);
2185 }
2186 }
2187 }
2188 else if (shift == ATA_SHIFT_PIO) {
2189 mask = ap->pio_mask;
2190 if (ata_dev_present(master)) {
2191 /* spec doesn't return explicit support for
2192 * PIO0-2, so we fake it
2193 */
2194 u16 tmp_mode = master->id[ATA_ID_PIO_MODES] & 0x03;
2195 tmp_mode <<= 3;
2196 tmp_mode |= 0x7;
2197 mask &= tmp_mode;
2198 }
2199 if (ata_dev_present(slave)) {
2200 /* spec doesn't return explicit support for
2201 * PIO0-2, so we fake it
2202 */
2203 u16 tmp_mode = slave->id[ATA_ID_PIO_MODES] & 0x03;
2204 tmp_mode <<= 3;
2205 tmp_mode |= 0x7;
2206 mask &= tmp_mode;
2207 }
2208 }
2209 else {
2210 mask = 0xffffffff; /* shut up compiler warning */
2211 BUG();
2212 }
2213
2214 return mask;
2215}
2216
2217/* find greatest bit */
2218static int fgb(u32 bitmap)
2219{
2220 unsigned int i;
2221 int x = -1;
2222
2223 for (i = 0; i < 32; i++)
2224 if (bitmap & (1 << i))
2225 x = i;
2226
2227 return x;
2228}
2229
2230/**
2231 * ata_choose_xfer_mode - attempt to find best transfer mode
2232 * @ap: Port for which an xfer mode will be selected
2233 * @xfer_mode_out: (output) SET FEATURES - XFER MODE code
2234 * @xfer_shift_out: (output) bit shift that selects this mode
2235 *
0cba632b
JG		 2236 * Based on host and device capabilities, determine the
2237 * maximum transfer mode that is amenable to all.
2238 *
1da177e4 2239 * LOCKING:
0cba632b 2240 * PCI/etc. bus probe sem.
1da177e4
LT		 2241 *
2242 * RETURNS:
2243 * Zero on success, negative on error.
2244 */
2245
057ace5e 2246static int ata_choose_xfer_mode(const struct ata_port *ap,
1da177e4
LT		 2247 u8 *xfer_mode_out,
2248 unsigned int *xfer_shift_out)
2249{
2250 unsigned int mask, shift;
2251 int x, i;
2252
2253 for (i = 0; i < ARRAY_SIZE(xfer_mode_classes); i++) {
2254 shift = xfer_mode_classes[i].shift;
2255 mask = ata_get_mode_mask(ap, shift);
2256
2257 x = fgb(mask);
2258 if (x >= 0) {
2259 *xfer_mode_out = xfer_mode_classes[i].base + x;
2260 *xfer_shift_out = shift;
2261 return 0;
2262 }
2263 }
2264
2265 return -1;
2266}
2267
2268/**
2269 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2270 * @ap: Port associated with device @dev
2271 * @dev: Device to which command will be sent
2272 *
780a87f7
JG		 2273 * Issue SET FEATURES - XFER MODE command to device @dev
2274 * on port @ap.
2275 *
1da177e4 2276 * LOCKING:
0cba632b 2277 * PCI/etc. bus probe sem.
1da177e4
LT		 2278 */
2279
2280static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2281{
2282 DECLARE_COMPLETION(wait);
2283 struct ata_queued_cmd *qc;
2284 int rc;
2285 unsigned long flags;
2286
2287 /* set up set-features taskfile */
2288 DPRINTK("set features - xfer mode\n");
2289
2290 qc = ata_qc_new_init(ap, dev);
2291 BUG_ON(qc == NULL);
2292
2293 qc->tf.command = ATA_CMD_SET_FEATURES;
2294 qc->tf.feature = SETFEATURES_XFER;
2295 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2296 qc->tf.protocol = ATA_PROT_NODATA;
2297 qc->tf.nsect = dev->xfer_mode;
2298
2299 qc->waiting = &wait;
2300 qc->complete_fn = ata_qc_complete_noop;
2301
2302 spin_lock_irqsave(&ap->host_set->lock, flags);
2303 rc = ata_qc_issue(qc);
2304 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2305
2306 if (rc)
2307 ata_port_disable(ap);
2308 else
64f043d8 2309 ata_qc_wait_err(qc, &wait);
1da177e4
LT		 2310
2311 DPRINTK("EXIT\n");
2312}
2313
59a10b17
AL		 2314/**
2315 * ata_dev_reread_id - Reread the device identify device info
2316 * @ap: port where the device is
2317 * @dev: device to reread the identify device info
2318 *
2319 * LOCKING:
2320 */
2321
2322static void ata_dev_reread_id(struct ata_port *ap, struct ata_device *dev)
2323{
2324 DECLARE_COMPLETION(wait);
2325 struct ata_queued_cmd *qc;
2326 unsigned long flags;
2327 int rc;
2328
2329 qc = ata_qc_new_init(ap, dev);
2330 BUG_ON(qc == NULL);
2331
2332 ata_sg_init_one(qc, dev->id, sizeof(dev->id));
2333 qc->dma_dir = DMA_FROM_DEVICE;
2334
2335 if (dev->class == ATA_DEV_ATA) {
2336 qc->tf.command = ATA_CMD_ID_ATA;
2337 DPRINTK("do ATA identify\n");
2338 } else {
2339 qc->tf.command = ATA_CMD_ID_ATAPI;
2340 DPRINTK("do ATAPI identify\n");
2341 }
2342
2343 qc->tf.flags |= ATA_TFLAG_DEVICE;
2344 qc->tf.protocol = ATA_PROT_PIO;
2345 qc->nsect = 1;
2346
2347 qc->waiting = &wait;
2348 qc->complete_fn = ata_qc_complete_noop;
2349
2350 spin_lock_irqsave(&ap->host_set->lock, flags);
2351 rc = ata_qc_issue(qc);
2352 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2353
2354 if (rc)
2355 goto err_out;
2356
64f043d8 2357 ata_qc_wait_err(qc, &wait);
59a10b17
AL		 2358
2359 swap_buf_le16(dev->id, ATA_ID_WORDS);
2360
2361 ata_dump_id(dev);
2362
2363 DPRINTK("EXIT\n");
2364
2365 return;
2366err_out:
2367 ata_port_disable(ap);
2368}
2369
8bf62ece
AL		 2370/**
2371 * ata_dev_init_params - Issue INIT DEV PARAMS command
2372 * @ap: Port associated with device @dev
2373 * @dev: Device to which command will be sent
2374 *
2375 * LOCKING:
2376 */
2377
2378static void ata_dev_init_params(struct ata_port *ap, struct ata_device *dev)
2379{
2380 DECLARE_COMPLETION(wait);
2381 struct ata_queued_cmd *qc;
2382 int rc;
2383 unsigned long flags;
2384 u16 sectors = dev->id[6];
2385 u16 heads = dev->id[3];
2386
2387 /* Number of sectors per track 1-255. Number of heads 1-16 */
2388 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
2389 return;
2390
2391 /* set up init dev params taskfile */
2392 DPRINTK("init dev params \n");
2393
2394 qc = ata_qc_new_init(ap, dev);
2395 BUG_ON(qc == NULL);
2396
2397 qc->tf.command = ATA_CMD_INIT_DEV_PARAMS;
2398 qc->tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2399 qc->tf.protocol = ATA_PROT_NODATA;
2400 qc->tf.nsect = sectors;
2401 qc->tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
2402
2403 qc->waiting = &wait;
2404 qc->complete_fn = ata_qc_complete_noop;
2405
2406 spin_lock_irqsave(&ap->host_set->lock, flags);
2407 rc = ata_qc_issue(qc);
2408 spin_unlock_irqrestore(&ap->host_set->lock, flags);
2409
2410 if (rc)
2411 ata_port_disable(ap);
2412 else
64f043d8 2413 ata_qc_wait_err(qc, &wait);
8bf62ece
AL		 2414
2415 DPRINTK("EXIT\n");
2416}
2417
1da177e4 2418/**
0cba632b
JG		 2419 * ata_sg_clean - Unmap DMA memory associated with command
2420 * @qc: Command containing DMA memory to be released
2421 *
2422 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2423 *
2424 * LOCKING:
0cba632b 2425 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2426 */
2427
2428static void ata_sg_clean(struct ata_queued_cmd *qc)
2429{
2430 struct ata_port *ap = qc->ap;
cedc9a47 2431 struct scatterlist *sg = qc->__sg;
1da177e4 2432 int dir = qc->dma_dir;
cedc9a47 2433 void *pad_buf = NULL;
1da177e4
LT		 2434
2435 assert(qc->flags & ATA_QCFLAG_DMAMAP);
2436 assert(sg != NULL);
2437
2438 if (qc->flags & ATA_QCFLAG_SINGLE)
2439 assert(qc->n_elem == 1);
2440
2c13b7ce 2441 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2442
cedc9a47
JG		 2443 /* if we padded the buffer out to 32-bit bound, and data
2444 * xfer direction is from-device, we must copy from the
2445 * pad buffer back into the supplied buffer
2446 */
2447 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2448 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2449
2450 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2451 if (qc->n_elem)
2452 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2453 /* restore last sg */
2454 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2455 if (pad_buf) {
2456 struct scatterlist *psg = &qc->pad_sgent;
2457 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2458 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2459 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2460 }
2461 } else {
e1410f2d
JG		 2462 if (sg_dma_len(&sg[0]) > 0)
2463 dma_unmap_single(ap->host_set->dev,
2464 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2465 dir);
cedc9a47
JG		 2466 /* restore sg */
2467 sg->length += qc->pad_len;
2468 if (pad_buf)
2469 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2470 pad_buf, qc->pad_len);
2471 }
1da177e4
LT		 2472
2473 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2474 qc->__sg = NULL;
1da177e4
LT		 2475}
2476
2477/**
2478 * ata_fill_sg - Fill PCI IDE PRD table
2479 * @qc: Metadata associated with taskfile to be transferred
2480 *
780a87f7
JG		 2481 * Fill PCI IDE PRD (scatter-gather) table with segments
2482 * associated with the current disk command.
2483 *
1da177e4 2484 * LOCKING:
780a87f7 2485 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2486 *
2487 */
2488static void ata_fill_sg(struct ata_queued_cmd *qc)
2489{
1da177e4 2490 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2491 struct scatterlist *sg;
2492 unsigned int idx;
1da177e4 2493
cedc9a47 2494 assert(qc->__sg != NULL);
1da177e4
LT		 2495 assert(qc->n_elem > 0);
2496
2497 idx = 0;
cedc9a47 2498 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2499 u32 addr, offset;
2500 u32 sg_len, len;
2501
2502 /* determine if physical DMA addr spans 64K boundary.
2503 * Note h/w doesn't support 64-bit, so we unconditionally
2504 * truncate dma_addr_t to u32.
2505 */
2506 addr = (u32) sg_dma_address(sg);
2507 sg_len = sg_dma_len(sg);
2508
2509 while (sg_len) {
2510 offset = addr & 0xffff;
2511 len = sg_len;
2512 if ((offset + sg_len) > 0x10000)
2513 len = 0x10000 - offset;
2514
2515 ap->prd[idx].addr = cpu_to_le32(addr);
2516 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2517 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2518
2519 idx++;
2520 sg_len -= len;
2521 addr += len;
2522 }
2523 }
2524
2525 if (idx)
2526 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2527}
2528/**
2529 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2530 * @qc: Metadata associated with taskfile to check
2531 *
780a87f7
JG		 2532 * Allow low-level driver to filter ATA PACKET commands, returning
2533 * a status indicating whether or not it is OK to use DMA for the
2534 * supplied PACKET command.
2535 *
1da177e4 2536 * LOCKING:
0cba632b
JG		 2537 * spin_lock_irqsave(host_set lock)
2538 *
1da177e4
LT		 2539 * RETURNS: 0 when ATAPI DMA can be used
2540 * nonzero otherwise
2541 */
2542int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2543{
2544 struct ata_port *ap = qc->ap;
2545 int rc = 0; /* Assume ATAPI DMA is OK by default */
2546
2547 if (ap->ops->check_atapi_dma)
2548 rc = ap->ops->check_atapi_dma(qc);
2549
2550 return rc;
2551}
2552/**
2553 * ata_qc_prep - Prepare taskfile for submission
2554 * @qc: Metadata associated with taskfile to be prepared
2555 *
780a87f7
JG		 2556 * Prepare ATA taskfile for submission.
2557 *
1da177e4
LT		 2558 * LOCKING:
2559 * spin_lock_irqsave(host_set lock)
2560 */
2561void ata_qc_prep(struct ata_queued_cmd *qc)
2562{
2563 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2564 return;
2565
2566 ata_fill_sg(qc);
2567}
2568
0cba632b
JG		 2569/**
2570 * ata_sg_init_one - Associate command with memory buffer
2571 * @qc: Command to be associated
2572 * @buf: Memory buffer
2573 * @buflen: Length of memory buffer, in bytes.
2574 *
2575 * Initialize the data-related elements of queued_cmd @qc
2576 * to point to a single memory buffer, @buf of byte length @buflen.
2577 *
2578 * LOCKING:
2579 * spin_lock_irqsave(host_set lock)
2580 */
2581
1da177e4
LT		 2582void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2583{
2584 struct scatterlist *sg;
2585
2586 qc->flags |= ATA_QCFLAG_SINGLE;
2587
2588 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2589 qc->__sg = &qc->sgent;
1da177e4 2590 qc->n_elem = 1;
cedc9a47 2591 qc->orig_n_elem = 1;
1da177e4
LT		 2592 qc->buf_virt = buf;
2593
cedc9a47 2594 sg = qc->__sg;
f0612bbc 2595 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2596}
2597
0cba632b
JG		 2598/**
2599 * ata_sg_init - Associate command with scatter-gather table.
2600 * @qc: Command to be associated
2601 * @sg: Scatter-gather table.
2602 * @n_elem: Number of elements in s/g table.
2603 *
2604 * Initialize the data-related elements of queued_cmd @qc
2605 * to point to a scatter-gather table @sg, containing @n_elem
2606 * elements.
2607 *
2608 * LOCKING:
2609 * spin_lock_irqsave(host_set lock)
2610 */
2611
1da177e4
LT		 2612void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2613 unsigned int n_elem)
2614{
2615 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2616 qc->__sg = sg;
1da177e4 2617 qc->n_elem = n_elem;
cedc9a47 2618 qc->orig_n_elem = n_elem;
1da177e4
LT		 2619}
2620
2621/**
0cba632b
JG		 2622 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2623 * @qc: Command with memory buffer to be mapped.
2624 *
2625 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2626 *
2627 * LOCKING:
2628 * spin_lock_irqsave(host_set lock)
2629 *
2630 * RETURNS:
0cba632b 2631 * Zero on success, negative on error.
1da177e4
LT		 2632 */
2633
2634static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2635{
2636 struct ata_port *ap = qc->ap;
2637 int dir = qc->dma_dir;
cedc9a47 2638 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 2639 dma_addr_t dma_address;
2640
cedc9a47
JG		 2641 /* we must lengthen transfers to end on a 32-bit boundary */
2642 qc->pad_len = sg->length & 3;
2643 if (qc->pad_len) {
2644 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2645 struct scatterlist *psg = &qc->pad_sgent;
2646
2647 assert(qc->dev->class == ATA_DEV_ATAPI);
2648
2649 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2650
2651 if (qc->tf.flags & ATA_TFLAG_WRITE)
2652 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2653 qc->pad_len);
2654
2655 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2656 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2657 /* trim sg */
2658 sg->length -= qc->pad_len;
2659
2660 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2661 sg->length, qc->pad_len);
2662 }
2663
e1410f2d
JG		 2664 if (!sg->length) {
2665 sg_dma_address(sg) = 0;
2666 goto skip_map;
2667 }
2668
1da177e4 2669 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2670 sg->length, dir);
537a95d9
TH		 2671 if (dma_mapping_error(dma_address)) {
2672 /* restore sg */
2673 sg->length += qc->pad_len;
1da177e4 2674 return -1;
537a95d9 2675 }
1da177e4
LT		 2676
2677 sg_dma_address(sg) = dma_address;
e1410f2d 2678skip_map:
32529e01 2679 sg_dma_len(sg) = sg->length;
1da177e4
LT		 2680
2681 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2682 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2683
2684 return 0;
2685}
2686
2687/**
0cba632b
JG		 2688 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2689 * @qc: Command with scatter-gather table to be mapped.
2690 *
2691 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2692 *
2693 * LOCKING:
2694 * spin_lock_irqsave(host_set lock)
2695 *
2696 * RETURNS:
0cba632b 2697 * Zero on success, negative on error.
1da177e4
LT		 2698 *
2699 */
2700
2701static int ata_sg_setup(struct ata_queued_cmd *qc)
2702{
2703 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2704 struct scatterlist *sg = qc->__sg;
2705 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 2706 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 2707
2708 VPRINTK("ENTER, ata%u\n", ap->id);
2709 assert(qc->flags & ATA_QCFLAG_SG);
2710
cedc9a47
JG		 2711 /* we must lengthen transfers to end on a 32-bit boundary */
2712 qc->pad_len = lsg->length & 3;
2713 if (qc->pad_len) {
2714 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2715 struct scatterlist *psg = &qc->pad_sgent;
2716 unsigned int offset;
2717
2718 assert(qc->dev->class == ATA_DEV_ATAPI);
2719
2720 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2721
2722 /*
2723 * psg->page/offset are used to copy to-be-written
2724 * data in this function or read data in ata_sg_clean.
2725 */
2726 offset = lsg->offset + lsg->length - qc->pad_len;
2727 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
2728 psg->offset = offset_in_page(offset);
2729
2730 if (qc->tf.flags & ATA_TFLAG_WRITE) {
2731 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2732 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 2733 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2734 }
2735
2736 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2737 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2738 /* trim last sg */
2739 lsg->length -= qc->pad_len;
e1410f2d
JG		 2740 if (lsg->length == 0)
2741 trim_sg = 1;
cedc9a47
JG		 2742
2743 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
2744 qc->n_elem - 1, lsg->length, qc->pad_len);
2745 }
2746
e1410f2d
JG		 2747 pre_n_elem = qc->n_elem;
2748 if (trim_sg && pre_n_elem)
2749 pre_n_elem--;
2750
2751 if (!pre_n_elem) {
2752 n_elem = 0;
2753 goto skip_map;
2754 }
2755
1da177e4 2756 dir = qc->dma_dir;
e1410f2d 2757 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 2758 if (n_elem < 1) {
2759 /* restore last sg */
2760 lsg->length += qc->pad_len;
1da177e4 2761 return -1;
537a95d9 2762 }
1da177e4
LT		 2763
2764 DPRINTK("%d sg elements mapped\n", n_elem);
2765
e1410f2d 2766skip_map:
1da177e4
LT		 2767 qc->n_elem = n_elem;
2768
2769 return 0;
2770}
2771
40e8c82c
TH		 2772/**
2773 * ata_poll_qc_complete - turn irq back on and finish qc
2774 * @qc: Command to complete
8e8b77dd 2775 * @err_mask: ATA status register content
40e8c82c
TH		 2776 *
2777 * LOCKING:
2778 * None. (grabs host lock)
2779 */
2780
a22e2eb0 2781void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 2782{
2783 struct ata_port *ap = qc->ap;
b8f6153e 2784 unsigned long flags;
40e8c82c 2785
b8f6153e 2786 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 2787 ap->flags &= ~ATA_FLAG_NOINTR;
2788 ata_irq_on(ap);
a22e2eb0 2789 ata_qc_complete(qc);
b8f6153e 2790 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 2791}
2792
1da177e4
LT		 2793/**
2794 * ata_pio_poll -
6f0ef4fa 2795 * @ap: the target ata_port
1da177e4
LT		 2796 *
2797 * LOCKING:
0cba632b 2798 * None. (executing in kernel thread context)
1da177e4
LT		 2799 *
2800 * RETURNS:
6f0ef4fa 2801 * timeout value to use
1da177e4
LT		 2802 */
2803
2804static unsigned long ata_pio_poll(struct ata_port *ap)
2805{
c14b8331 2806 struct ata_queued_cmd *qc;
1da177e4 2807 u8 status;
14be71f4
AL		 2808 unsigned int poll_state = HSM_ST_UNKNOWN;
2809 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 2810
c14b8331
AL		 2811 qc = ata_qc_from_tag(ap, ap->active_tag);
2812 assert(qc != NULL);
2813
14be71f4
AL		 2814 switch (ap->hsm_task_state) {
2815 case HSM_ST:
2816 case HSM_ST_POLL:
2817 poll_state = HSM_ST_POLL;
2818 reg_state = HSM_ST;
1da177e4 2819 break;
14be71f4
AL		 2820 case HSM_ST_LAST:
2821 case HSM_ST_LAST_POLL:
2822 poll_state = HSM_ST_LAST_POLL;
2823 reg_state = HSM_ST_LAST;
1da177e4
LT		 2824 break;
2825 default:
2826 BUG();
2827 break;
2828 }
2829
2830 status = ata_chk_status(ap);
2831 if (status & ATA_BUSY) {
2832 if (time_after(jiffies, ap->pio_task_timeout)) {
1c848984 2833 qc->err_mask |= AC_ERR_ATA_BUS;
7c398335 2834 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 2835 return 0;
2836 }
14be71f4 2837 ap->hsm_task_state = poll_state;
1da177e4
LT		 2838 return ATA_SHORT_PAUSE;
2839 }
2840
14be71f4 2841 ap->hsm_task_state = reg_state;
1da177e4
LT		 2842 return 0;
2843}
2844
2845/**
6f0ef4fa
RD		 2846 * ata_pio_complete - check if drive is busy or idle
2847 * @ap: the target ata_port
1da177e4
LT		 2848 *
2849 * LOCKING:
0cba632b 2850 * None. (executing in kernel thread context)
7fb6ec28
JG		 2851 *
2852 * RETURNS:
2853 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 2854 */
2855
7fb6ec28 2856static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 2857{
2858 struct ata_queued_cmd *qc;
2859 u8 drv_stat;
2860
2861 /*
31433ea3
AC		 2862 * This is purely heuristic. This is a fast path. Sometimes when
2863 * we enter, BSY will be cleared in a chk-status or two. If not,
2864 * the drive is probably seeking or something. Snooze for a couple
2865 * msecs, then chk-status again. If still busy, fall back to
14be71f4 2866 * HSM_ST_POLL state.
1da177e4 2867 */
fe79e683
AL		 2868 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2869 if (drv_stat & ATA_BUSY) {
1da177e4 2870 msleep(2);
fe79e683
AL		 2871 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
2872 if (drv_stat & ATA_BUSY) {
14be71f4 2873 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 2874 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 2875 return 0;
1da177e4
LT		 2876 }
2877 }
2878
c14b8331
AL		 2879 qc = ata_qc_from_tag(ap, ap->active_tag);
2880 assert(qc != NULL);
2881
1da177e4
LT		 2882 drv_stat = ata_wait_idle(ap);
2883 if (!ata_ok(drv_stat)) {
1c848984 2884 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 2885 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 2886 return 0;
1da177e4
LT		 2887 }
2888
14be71f4 2889 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 2890
a22e2eb0
AL		 2891 assert(qc->err_mask == 0);
2892 ata_poll_qc_complete(qc);
7fb6ec28
JG		 2893
2894 /* another command may start at this point */
2895
2896 return 1;
1da177e4
LT		 2897}
2898
0baab86b
EF		 2899
2900/**
6f0ef4fa 2901 * swap_buf_le16 - swap halves of 16-words in place
0baab86b
EF		 2902 * @buf: Buffer to swap
2903 * @buf_words: Number of 16-bit words in buffer.
2904 *
2905 * Swap halves of 16-bit words if needed to convert from
2906 * little-endian byte order to native cpu byte order, or
2907 * vice-versa.
2908 *
2909 * LOCKING:
6f0ef4fa 2910 * Inherited from caller.
0baab86b 2911 */
1da177e4
LT		 2912void swap_buf_le16(u16 *buf, unsigned int buf_words)
2913{
2914#ifdef __BIG_ENDIAN
2915 unsigned int i;
2916
2917 for (i = 0; i < buf_words; i++)
2918 buf[i] = le16_to_cpu(buf[i]);
2919#endif /* __BIG_ENDIAN */
2920}
2921
6ae4cfb5
AL		 2922/**
2923 * ata_mmio_data_xfer - Transfer data by MMIO
2924 * @ap: port to read/write
2925 * @buf: data buffer
2926 * @buflen: buffer length
344babaa 2927 * @write_data: read/write
6ae4cfb5
AL		 2928 *
2929 * Transfer data from/to the device data register by MMIO.
2930 *
2931 * LOCKING:
2932 * Inherited from caller.
6ae4cfb5
AL		 2933 */
2934
1da177e4
LT		 2935static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
2936 unsigned int buflen, int write_data)
2937{
2938 unsigned int i;
2939 unsigned int words = buflen >> 1;
2940 u16 *buf16 = (u16 *) buf;
2941 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
2942
6ae4cfb5 2943 /* Transfer multiple of 2 bytes */
1da177e4
LT		 2944 if (write_data) {
2945 for (i = 0; i < words; i++)
2946 writew(le16_to_cpu(buf16[i]), mmio);
2947 } else {
2948 for (i = 0; i < words; i++)
2949 buf16[i] = cpu_to_le16(readw(mmio));
2950 }
6ae4cfb5
AL		 2951
2952 /* Transfer trailing 1 byte, if any. */
2953 if (unlikely(buflen & 0x01)) {
2954 u16 align_buf[1] = { 0 };
2955 unsigned char *trailing_buf = buf + buflen - 1;
2956
2957 if (write_data) {
2958 memcpy(align_buf, trailing_buf, 1);
2959 writew(le16_to_cpu(align_buf[0]), mmio);
2960 } else {
2961 align_buf[0] = cpu_to_le16(readw(mmio));
2962 memcpy(trailing_buf, align_buf, 1);
2963 }
2964 }
1da177e4
LT		 2965}
2966
6ae4cfb5
AL		 2967/**
2968 * ata_pio_data_xfer - Transfer data by PIO
2969 * @ap: port to read/write
2970 * @buf: data buffer
2971 * @buflen: buffer length
344babaa 2972 * @write_data: read/write
6ae4cfb5
AL		 2973 *
2974 * Transfer data from/to the device data register by PIO.
2975 *
2976 * LOCKING:
2977 * Inherited from caller.
6ae4cfb5
AL		 2978 */
2979
1da177e4
LT		 2980static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
2981 unsigned int buflen, int write_data)
2982{
6ae4cfb5 2983 unsigned int words = buflen >> 1;
1da177e4 2984
6ae4cfb5 2985 /* Transfer multiple of 2 bytes */
1da177e4 2986 if (write_data)
6ae4cfb5 2987 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 2988 else
6ae4cfb5
AL		 2989 insw(ap->ioaddr.data_addr, buf, words);
2990
2991 /* Transfer trailing 1 byte, if any. */
2992 if (unlikely(buflen & 0x01)) {
2993 u16 align_buf[1] = { 0 };
2994 unsigned char *trailing_buf = buf + buflen - 1;
2995
2996 if (write_data) {
2997 memcpy(align_buf, trailing_buf, 1);
2998 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
2999 } else {
3000 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3001 memcpy(trailing_buf, align_buf, 1);
3002 }
3003 }
1da177e4
LT		 3004}
3005
6ae4cfb5
AL		 3006/**
3007 * ata_data_xfer - Transfer data from/to the data register.
3008 * @ap: port to read/write
3009 * @buf: data buffer
3010 * @buflen: buffer length
3011 * @do_write: read/write
3012 *
3013 * Transfer data from/to the device data register.
3014 *
3015 * LOCKING:
3016 * Inherited from caller.
6ae4cfb5
AL		 3017 */
3018
1da177e4
LT		 3019static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3020 unsigned int buflen, int do_write)
3021{
3022 if (ap->flags & ATA_FLAG_MMIO)
3023 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3024 else
3025 ata_pio_data_xfer(ap, buf, buflen, do_write);
3026}
3027
6ae4cfb5
AL		 3028/**
3029 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3030 * @qc: Command on going
3031 *
3032 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3033 *
3034 * LOCKING:
3035 * Inherited from caller.
3036 */
3037
1da177e4
LT		 3038static void ata_pio_sector(struct ata_queued_cmd *qc)
3039{
3040 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3041 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3042 struct ata_port *ap = qc->ap;
3043 struct page *page;
3044 unsigned int offset;
3045 unsigned char *buf;
3046
3047 if (qc->cursect == (qc->nsect - 1))
14be71f4 3048 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3049
3050 page = sg[qc->cursg].page;
3051 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3052
3053 /* get the current page and offset */
3054 page = nth_page(page, (offset >> PAGE_SHIFT));
3055 offset %= PAGE_SIZE;
3056
3057 buf = kmap(page) + offset;
3058
3059 qc->cursect++;
3060 qc->cursg_ofs++;
3061
32529e01 3062 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3063 qc->cursg++;
3064 qc->cursg_ofs = 0;
3065 }
3066
3067 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3068
3069 /* do the actual data transfer */
3070 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3071 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3072
3073 kunmap(page);
3074}
3075
6ae4cfb5
AL		 3076/**
3077 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3078 * @qc: Command on going
3079 * @bytes: number of bytes
3080 *
3081 * Transfer Transfer data from/to the ATAPI device.
3082 *
3083 * LOCKING:
3084 * Inherited from caller.
3085 *
3086 */
3087
1da177e4
LT		 3088static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3089{
3090 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3091 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3092 struct ata_port *ap = qc->ap;
3093 struct page *page;
3094 unsigned char *buf;
3095 unsigned int offset, count;
3096
563a6e1f 3097 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3098 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3099
3100next_sg:
563a6e1f 3101 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3102 /*
563a6e1f
AL		 3103 * The end of qc->sg is reached and the device expects
3104 * more data to transfer. In order not to overrun qc->sg
3105 * and fulfill length specified in the byte count register,
3106 * - for read case, discard trailing data from the device
3107 * - for write case, padding zero data to the device
3108 */
3109 u16 pad_buf[1] = { 0 };
3110 unsigned int words = bytes >> 1;
3111 unsigned int i;
3112
3113 if (words) /* warning if bytes > 1 */
7fb6ec28 3114 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3115 ap->id, bytes);
3116
3117 for (i = 0; i < words; i++)
3118 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3119
14be71f4 3120 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3121 return;
3122 }
3123
cedc9a47 3124 sg = &qc->__sg[qc->cursg];
1da177e4 3125
1da177e4
LT		 3126 page = sg->page;
3127 offset = sg->offset + qc->cursg_ofs;
3128
3129 /* get the current page and offset */
3130 page = nth_page(page, (offset >> PAGE_SHIFT));
3131 offset %= PAGE_SIZE;
3132
6952df03 3133 /* don't overrun current sg */
32529e01 3134 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3135
3136 /* don't cross page boundaries */
3137 count = min(count, (unsigned int)PAGE_SIZE - offset);
3138
3139 buf = kmap(page) + offset;
3140
3141 bytes -= count;
3142 qc->curbytes += count;
3143 qc->cursg_ofs += count;
3144
32529e01 3145 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3146 qc->cursg++;
3147 qc->cursg_ofs = 0;
3148 }
3149
3150 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3151
3152 /* do the actual data transfer */
3153 ata_data_xfer(ap, buf, count, do_write);
3154
3155 kunmap(page);
3156
563a6e1f 3157 if (bytes)
1da177e4 3158 goto next_sg;
1da177e4
LT		 3159}
3160
6ae4cfb5
AL		 3161/**
3162 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3163 * @qc: Command on going
3164 *
3165 * Transfer Transfer data from/to the ATAPI device.
3166 *
3167 * LOCKING:
3168 * Inherited from caller.
6ae4cfb5
AL		 3169 */
3170
1da177e4
LT		 3171static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3172{
3173 struct ata_port *ap = qc->ap;
3174 struct ata_device *dev = qc->dev;
3175 unsigned int ireason, bc_lo, bc_hi, bytes;
3176 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3177
3178 ap->ops->tf_read(ap, &qc->tf);
3179 ireason = qc->tf.nsect;
3180 bc_lo = qc->tf.lbam;
3181 bc_hi = qc->tf.lbah;
3182 bytes = (bc_hi << 8) | bc_lo;
3183
3184 /* shall be cleared to zero, indicating xfer of data */
3185 if (ireason & (1 << 0))
3186 goto err_out;
3187
3188 /* make sure transfer direction matches expected */
3189 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3190 if (do_write != i_write)
3191 goto err_out;
3192
3193 __atapi_pio_bytes(qc, bytes);
3194
3195 return;
3196
3197err_out:
3198 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3199 ap->id, dev->devno);
1c848984 3200 qc->err_mask |= AC_ERR_ATA_BUS;
14be71f4 3201 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3202}
3203
3204/**
6f0ef4fa
RD		 3205 * ata_pio_block - start PIO on a block
3206 * @ap: the target ata_port
1da177e4
LT		 3207 *
3208 * LOCKING:
0cba632b 3209 * None. (executing in kernel thread context)
1da177e4
LT		 3210 */
3211
3212static void ata_pio_block(struct ata_port *ap)
3213{
3214 struct ata_queued_cmd *qc;
3215 u8 status;
3216
3217 /*
6f0ef4fa 3218 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3219 * Sometimes when we enter, BSY will be cleared in
3220 * a chk-status or two. If not, the drive is probably seeking
3221 * or something. Snooze for a couple msecs, then
3222 * chk-status again. If still busy, fall back to
14be71f4 3223 * HSM_ST_POLL state.
1da177e4
LT		 3224 */
3225 status = ata_busy_wait(ap, ATA_BUSY, 5);
3226 if (status & ATA_BUSY) {
3227 msleep(2);
3228 status = ata_busy_wait(ap, ATA_BUSY, 10);
3229 if (status & ATA_BUSY) {
14be71f4 3230 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3231 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3232 return;
3233 }
3234 }
3235
3236 qc = ata_qc_from_tag(ap, ap->active_tag);
3237 assert(qc != NULL);
3238
fe79e683
AL		 3239 /* check error */
3240 if (status & (ATA_ERR | ATA_DF)) {
3241 qc->err_mask |= AC_ERR_DEV;
3242 ap->hsm_task_state = HSM_ST_ERR;
3243 return;
3244 }
3245
3246 /* transfer data if any */
1da177e4 3247 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3248 /* DRQ=0 means no more data to transfer */
1da177e4 3249 if ((status & ATA_DRQ) == 0) {
14be71f4 3250 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3251 return;
3252 }
3253
3254 atapi_pio_bytes(qc);
3255 } else {
3256 /* handle BSY=0, DRQ=0 as error */
3257 if ((status & ATA_DRQ) == 0) {
1c848984 3258 qc->err_mask |= AC_ERR_ATA_BUS;
14be71f4 3259 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3260 return;
3261 }
3262
3263 ata_pio_sector(qc);
3264 }
3265}
3266
3267static void ata_pio_error(struct ata_port *ap)
3268{
3269 struct ata_queued_cmd *qc;
a7dac447
JG		 3270
3271 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
1da177e4
LT		 3272
3273 qc = ata_qc_from_tag(ap, ap->active_tag);
3274 assert(qc != NULL);
3275
1c848984
AL		 3276 /* make sure qc->err_mask is available to
3277 * know what's wrong and recover
3278 */
3279 assert(qc->err_mask);
3280
14be71f4 3281 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3282
a22e2eb0 3283 ata_poll_qc_complete(qc);
1da177e4
LT		 3284}
3285
3286static void ata_pio_task(void *_data)
3287{
3288 struct ata_port *ap = _data;
7fb6ec28
JG		 3289 unsigned long timeout;
3290 int qc_completed;
3291
3292fsm_start:
3293 timeout = 0;
3294 qc_completed = 0;
1da177e4 3295
14be71f4
AL		 3296 switch (ap->hsm_task_state) {
3297 case HSM_ST_IDLE:
1da177e4
LT		 3298 return;
3299
14be71f4 3300 case HSM_ST:
1da177e4
LT		 3301 ata_pio_block(ap);
3302 break;
3303
14be71f4 3304 case HSM_ST_LAST:
7fb6ec28 3305 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3306 break;
3307
14be71f4
AL		 3308 case HSM_ST_POLL:
3309 case HSM_ST_LAST_POLL:
1da177e4
LT		 3310 timeout = ata_pio_poll(ap);
3311 break;
3312
14be71f4
AL		 3313 case HSM_ST_TMOUT:
3314 case HSM_ST_ERR:
1da177e4
LT		 3315 ata_pio_error(ap);
3316 return;
3317 }
3318
3319 if (timeout)
7fb6ec28
JG		 3320 queue_delayed_work(ata_wq, &ap->pio_task, timeout);
3321 else if (!qc_completed)
3322 goto fsm_start;
1da177e4
LT		 3323}
3324
1da177e4
LT		 3325/**
3326 * ata_qc_timeout - Handle timeout of queued command
3327 * @qc: Command that timed out
3328 *
3329 * Some part of the kernel (currently, only the SCSI layer)
3330 * has noticed that the active command on port @ap has not
3331 * completed after a specified length of time. Handle this
3332 * condition by disabling DMA (if necessary) and completing
3333 * transactions, with error if necessary.
3334 *
3335 * This also handles the case of the "lost interrupt", where
3336 * for some reason (possibly hardware bug, possibly driver bug)
3337 * an interrupt was not delivered to the driver, even though the
3338 * transaction completed successfully.
3339 *
3340 * LOCKING:
0cba632b 3341 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3342 */
3343
3344static void ata_qc_timeout(struct ata_queued_cmd *qc)
3345{
3346 struct ata_port *ap = qc->ap;
b8f6153e 3347 struct ata_host_set *host_set = ap->host_set;
1da177e4 3348 u8 host_stat = 0, drv_stat;
b8f6153e 3349 unsigned long flags;
1da177e4
LT		 3350
3351 DPRINTK("ENTER\n");
3352
b8f6153e
JG		 3353 spin_lock_irqsave(&host_set->lock, flags);
3354
1da177e4
LT		 3355 /* hack alert! We cannot use the supplied completion
3356 * function from inside the ->eh_strategy_handler() thread.
3357 * libata is the only user of ->eh_strategy_handler() in
3358 * any kernel, so the default scsi_done() assumes it is
3359 * not being called from the SCSI EH.
3360 */
3361 qc->scsidone = scsi_finish_command;
3362
3363 switch (qc->tf.protocol) {
3364
3365 case ATA_PROT_DMA:
3366 case ATA_PROT_ATAPI_DMA:
3367 host_stat = ap->ops->bmdma_status(ap);
3368
3369 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3370 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3371
3372 /* fall through */
3373
3374 default:
3375 ata_altstatus(ap);
3376 drv_stat = ata_chk_status(ap);
3377
3378 /* ack bmdma irq events */
3379 ap->ops->irq_clear(ap);
3380
3381 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3382 ap->id, qc->tf.command, drv_stat, host_stat);
3383
3384 /* complete taskfile transaction */
a22e2eb0
AL		 3385 qc->err_mask |= ac_err_mask(drv_stat);
3386 ata_qc_complete(qc);
1da177e4
LT		 3387 break;
3388 }
b8f6153e
JG		 3389
3390 spin_unlock_irqrestore(&host_set->lock, flags);
3391
1da177e4
LT		 3392 DPRINTK("EXIT\n");
3393}
3394
3395/**
3396 * ata_eng_timeout - Handle timeout of queued command
3397 * @ap: Port on which timed-out command is active
3398 *
3399 * Some part of the kernel (currently, only the SCSI layer)
3400 * has noticed that the active command on port @ap has not
3401 * completed after a specified length of time. Handle this
3402 * condition by disabling DMA (if necessary) and completing
3403 * transactions, with error if necessary.
3404 *
3405 * This also handles the case of the "lost interrupt", where
3406 * for some reason (possibly hardware bug, possibly driver bug)
3407 * an interrupt was not delivered to the driver, even though the
3408 * transaction completed successfully.
3409 *
3410 * LOCKING:
3411 * Inherited from SCSI layer (none, can sleep)
3412 */
3413
3414void ata_eng_timeout(struct ata_port *ap)
3415{
3416 struct ata_queued_cmd *qc;
3417
3418 DPRINTK("ENTER\n");
3419
3420 qc = ata_qc_from_tag(ap, ap->active_tag);
e12669e7
JG		 3421 if (qc)
3422 ata_qc_timeout(qc);
3423 else {
1da177e4
LT		 3424 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
3425 ap->id);
3426 goto out;
3427 }
3428
1da177e4
LT		 3429out:
3430 DPRINTK("EXIT\n");
3431}
3432
3433/**
3434 * ata_qc_new - Request an available ATA command, for queueing
3435 * @ap: Port associated with device @dev
3436 * @dev: Device from whom we request an available command structure
3437 *
3438 * LOCKING:
0cba632b 3439 * None.
1da177e4
LT		 3440 */
3441
3442static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3443{
3444 struct ata_queued_cmd *qc = NULL;
3445 unsigned int i;
3446
3447 for (i = 0; i < ATA_MAX_QUEUE; i++)
3448 if (!test_and_set_bit(i, &ap->qactive)) {
3449 qc = ata_qc_from_tag(ap, i);
3450 break;
3451 }
3452
3453 if (qc)
3454 qc->tag = i;
3455
3456 return qc;
3457}
3458
3459/**
3460 * ata_qc_new_init - Request an available ATA command, and initialize it
3461 * @ap: Port associated with device @dev
3462 * @dev: Device from whom we request an available command structure
3463 *
3464 * LOCKING:
0cba632b 3465 * None.
1da177e4
LT		 3466 */
3467
3468struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3469 struct ata_device *dev)
3470{
3471 struct ata_queued_cmd *qc;
3472
3473 qc = ata_qc_new(ap);
3474 if (qc) {
1da177e4
LT		 3475 qc->scsicmd = NULL;
3476 qc->ap = ap;
3477 qc->dev = dev;
1da177e4 3478
2c13b7ce 3479 ata_qc_reinit(qc);
1da177e4
LT		 3480 }
3481
3482 return qc;
3483}
3484
a22e2eb0 3485int ata_qc_complete_noop(struct ata_queued_cmd *qc)
1da177e4
LT		 3486{
3487 return 0;
3488}
3489
3490static void __ata_qc_complete(struct ata_queued_cmd *qc)
3491{
3492 struct ata_port *ap = qc->ap;
3493 unsigned int tag, do_clear = 0;
3494
3495 qc->flags = 0;
3496 tag = qc->tag;
3497 if (likely(ata_tag_valid(tag))) {
3498 if (tag == ap->active_tag)
3499 ap->active_tag = ATA_TAG_POISON;
3500 qc->tag = ATA_TAG_POISON;
3501 do_clear = 1;
3502 }
3503
3504 if (qc->waiting) {
3505 struct completion *waiting = qc->waiting;
3506 qc->waiting = NULL;
3507 complete(waiting);
3508 }
3509
3510 if (likely(do_clear))
3511 clear_bit(tag, &ap->qactive);
3512}
3513
3514/**
3515 * ata_qc_free - free unused ata_queued_cmd
3516 * @qc: Command to complete
3517 *
3518 * Designed to free unused ata_queued_cmd object
3519 * in case something prevents using it.
3520 *
3521 * LOCKING:
0cba632b 3522 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3523 */
3524void ata_qc_free(struct ata_queued_cmd *qc)
3525{
3526 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3527 assert(qc->waiting == NULL); /* nothing should be waiting */
3528
3529 __ata_qc_complete(qc);
3530}
3531
3532/**
3533 * ata_qc_complete - Complete an active ATA command
3534 * @qc: Command to complete
8e8b77dd 3535 * @err_mask: ATA Status register contents
0cba632b
JG		 3536 *
3537 * Indicate to the mid and upper layers that an ATA
3538 * command has completed, with either an ok or not-ok status.
1da177e4
LT		 3539 *
3540 * LOCKING:
0cba632b 3541 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3542 */
3543
a22e2eb0 3544void ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4
LT		 3545{
3546 int rc;
3547
3548 assert(qc != NULL); /* ata_qc_from_tag _might_ return NULL */
3549 assert(qc->flags & ATA_QCFLAG_ACTIVE);
3550
3551 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3552 ata_sg_clean(qc);
3553
3f3791d3
AL		 3554 /* atapi: mark qc as inactive to prevent the interrupt handler
3555 * from completing the command twice later, before the error handler
3556 * is called. (when rc != 0 and atapi request sense is needed)
3557 */
3558 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3559
1da177e4 3560 /* call completion callback */
a22e2eb0 3561 rc = qc->complete_fn(qc);
1da177e4
LT		 3562
3563 /* if callback indicates not to complete command (non-zero),
3564 * return immediately
3565 */
3566 if (rc != 0)
3567 return;
3568
3569 __ata_qc_complete(qc);
3570
3571 VPRINTK("EXIT\n");
3572}
3573
3574static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3575{
3576 struct ata_port *ap = qc->ap;
3577
3578 switch (qc->tf.protocol) {
3579 case ATA_PROT_DMA:
3580 case ATA_PROT_ATAPI_DMA:
3581 return 1;
3582
3583 case ATA_PROT_ATAPI:
3584 case ATA_PROT_PIO:
3585 case ATA_PROT_PIO_MULT:
3586 if (ap->flags & ATA_FLAG_PIO_DMA)
3587 return 1;
3588
3589 /* fall through */
3590
3591 default:
3592 return 0;
3593 }
3594
3595 /* never reached */
3596}
3597
3598/**
3599 * ata_qc_issue - issue taskfile to device
3600 * @qc: command to issue to device
3601 *
3602 * Prepare an ATA command to submission to device.
3603 * This includes mapping the data into a DMA-able
3604 * area, filling in the S/G table, and finally
3605 * writing the taskfile to hardware, starting the command.
3606 *
3607 * LOCKING:
3608 * spin_lock_irqsave(host_set lock)
3609 *
3610 * RETURNS:
3611 * Zero on success, negative on error.
3612 */
3613
3614int ata_qc_issue(struct ata_queued_cmd *qc)
3615{
3616 struct ata_port *ap = qc->ap;
3617
3618 if (ata_should_dma_map(qc)) {
3619 if (qc->flags & ATA_QCFLAG_SG) {
3620 if (ata_sg_setup(qc))
3621 goto err_out;
3622 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3623 if (ata_sg_setup_one(qc))
3624 goto err_out;
3625 }
3626 } else {
3627 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3628 }
3629
3630 ap->ops->qc_prep(qc);
3631
3632 qc->ap->active_tag = qc->tag;
3633 qc->flags |= ATA_QCFLAG_ACTIVE;
3634
3635 return ap->ops->qc_issue(qc);
3636
3637err_out:
3638 return -1;
3639}
3640
0baab86b 3641
1da177e4
LT		 3642/**
3643 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3644 * @qc: command to issue to device
3645 *
3646 * Using various libata functions and hooks, this function
3647 * starts an ATA command. ATA commands are grouped into
3648 * classes called "protocols", and issuing each type of protocol
3649 * is slightly different.
3650 *
0baab86b
EF		 3651 * May be used as the qc_issue() entry in ata_port_operations.
3652 *
1da177e4
LT		 3653 * LOCKING:
3654 * spin_lock_irqsave(host_set lock)
3655 *
3656 * RETURNS:
3657 * Zero on success, negative on error.
3658 */
3659
3660int ata_qc_issue_prot(struct ata_queued_cmd *qc)
3661{
3662 struct ata_port *ap = qc->ap;
3663
3664 ata_dev_select(ap, qc->dev->devno, 1, 0);
3665
3666 switch (qc->tf.protocol) {
3667 case ATA_PROT_NODATA:
e5338254 3668 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3669 break;
3670
3671 case ATA_PROT_DMA:
3672 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3673 ap->ops->bmdma_setup(qc); /* set up bmdma */
3674 ap->ops->bmdma_start(qc); /* initiate bmdma */
3675 break;
3676
3677 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
3678 ata_qc_set_polling(qc);
e5338254 3679 ata_tf_to_host(ap, &qc->tf);
14be71f4 3680 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 3681 queue_work(ata_wq, &ap->pio_task);
3682 break;
3683
3684 case ATA_PROT_ATAPI:
3685 ata_qc_set_polling(qc);
e5338254 3686 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3687 queue_work(ata_wq, &ap->packet_task);
3688 break;
3689
3690 case ATA_PROT_ATAPI_NODATA:
c1389503 3691 ap->flags |= ATA_FLAG_NOINTR;
e5338254 3692 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3693 queue_work(ata_wq, &ap->packet_task);
3694 break;
3695
3696 case ATA_PROT_ATAPI_DMA:
c1389503 3697 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 3698 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3699 ap->ops->bmdma_setup(qc); /* set up bmdma */
3700 queue_work(ata_wq, &ap->packet_task);
3701 break;
3702
3703 default:
3704 WARN_ON(1);
3705 return -1;
3706 }
3707
3708 return 0;
3709}
3710
3711/**
0baab86b 3712 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 3713 * @qc: Info associated with this ATA transaction.
3714 *
3715 * LOCKING:
3716 * spin_lock_irqsave(host_set lock)
3717 */
3718
3719static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
3720{
3721 struct ata_port *ap = qc->ap;
3722 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3723 u8 dmactl;
3724 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3725
3726 /* load PRD table addr. */
3727 mb(); /* make sure PRD table writes are visible to controller */
3728 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
3729
3730 /* specify data direction, triple-check start bit is clear */
3731 dmactl = readb(mmio + ATA_DMA_CMD);
3732 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3733 if (!rw)
3734 dmactl |= ATA_DMA_WR;
3735 writeb(dmactl, mmio + ATA_DMA_CMD);
3736
3737 /* issue r/w command */
3738 ap->ops->exec_command(ap, &qc->tf);
3739}
3740
3741/**
b73fc89f 3742 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 3743 * @qc: Info associated with this ATA transaction.
3744 *
3745 * LOCKING:
3746 * spin_lock_irqsave(host_set lock)
3747 */
3748
3749static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
3750{
3751 struct ata_port *ap = qc->ap;
3752 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3753 u8 dmactl;
3754
3755 /* start host DMA transaction */
3756 dmactl = readb(mmio + ATA_DMA_CMD);
3757 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
3758
3759 /* Strictly, one may wish to issue a readb() here, to
3760 * flush the mmio write. However, control also passes
3761 * to the hardware at this point, and it will interrupt
3762 * us when we are to resume control. So, in effect,
3763 * we don't care when the mmio write flushes.
3764 * Further, a read of the DMA status register _immediately_
3765 * following the write may not be what certain flaky hardware
3766 * is expected, so I think it is best to not add a readb()
3767 * without first all the MMIO ATA cards/mobos.
3768 * Or maybe I'm just being paranoid.
3769 */
3770}
3771
3772/**
3773 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
3774 * @qc: Info associated with this ATA transaction.
3775 *
3776 * LOCKING:
3777 * spin_lock_irqsave(host_set lock)
3778 */
3779
3780static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
3781{
3782 struct ata_port *ap = qc->ap;
3783 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
3784 u8 dmactl;
3785
3786 /* load PRD table addr. */
3787 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
3788
3789 /* specify data direction, triple-check start bit is clear */
3790 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3791 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
3792 if (!rw)
3793 dmactl |= ATA_DMA_WR;
3794 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3795
3796 /* issue r/w command */
3797 ap->ops->exec_command(ap, &qc->tf);
3798}
3799
3800/**
3801 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
3802 * @qc: Info associated with this ATA transaction.
3803 *
3804 * LOCKING:
3805 * spin_lock_irqsave(host_set lock)
3806 */
3807
3808static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
3809{
3810 struct ata_port *ap = qc->ap;
3811 u8 dmactl;
3812
3813 /* start host DMA transaction */
3814 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3815 outb(dmactl | ATA_DMA_START,
3816 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3817}
3818
0baab86b
EF		 3819
3820/**
3821 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
3822 * @qc: Info associated with this ATA transaction.
3823 *
3824 * Writes the ATA_DMA_START flag to the DMA command register.
3825 *
3826 * May be used as the bmdma_start() entry in ata_port_operations.
3827 *
3828 * LOCKING:
3829 * spin_lock_irqsave(host_set lock)
3830 */
1da177e4
LT		 3831void ata_bmdma_start(struct ata_queued_cmd *qc)
3832{
3833 if (qc->ap->flags & ATA_FLAG_MMIO)
3834 ata_bmdma_start_mmio(qc);
3835 else
3836 ata_bmdma_start_pio(qc);
3837}
3838
0baab86b
EF		 3839
3840/**
3841 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
3842 * @qc: Info associated with this ATA transaction.
3843 *
3844 * Writes address of PRD table to device's PRD Table Address
3845 * register, sets the DMA control register, and calls
3846 * ops->exec_command() to start the transfer.
3847 *
3848 * May be used as the bmdma_setup() entry in ata_port_operations.
3849 *
3850 * LOCKING:
3851 * spin_lock_irqsave(host_set lock)
3852 */
1da177e4
LT		 3853void ata_bmdma_setup(struct ata_queued_cmd *qc)
3854{
3855 if (qc->ap->flags & ATA_FLAG_MMIO)
3856 ata_bmdma_setup_mmio(qc);
3857 else
3858 ata_bmdma_setup_pio(qc);
3859}
3860
0baab86b
EF		 3861
3862/**
3863 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 3864 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3865 *
3866 * Clear interrupt and error flags in DMA status register.
3867 *
3868 * May be used as the irq_clear() entry in ata_port_operations.
3869 *
3870 * LOCKING:
3871 * spin_lock_irqsave(host_set lock)
3872 */
3873
1da177e4
LT		 3874void ata_bmdma_irq_clear(struct ata_port *ap)
3875{
3876 if (ap->flags & ATA_FLAG_MMIO) {
3877 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
3878 writeb(readb(mmio), mmio);
3879 } else {
3880 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
3881 outb(inb(addr), addr);
3882 }
3883
3884}
3885
0baab86b
EF		 3886
3887/**
3888 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 3889 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 3890 *
3891 * Read and return BMDMA status register.
3892 *
3893 * May be used as the bmdma_status() entry in ata_port_operations.
3894 *
3895 * LOCKING:
3896 * spin_lock_irqsave(host_set lock)
3897 */
3898
1da177e4
LT		 3899u8 ata_bmdma_status(struct ata_port *ap)
3900{
3901 u8 host_stat;
3902 if (ap->flags & ATA_FLAG_MMIO) {
3903 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3904 host_stat = readb(mmio + ATA_DMA_STATUS);
3905 } else
ee500aab 3906 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 3907 return host_stat;
3908}
3909
0baab86b
EF		 3910
3911/**
3912 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 3913 * @qc: Command we are ending DMA for
0baab86b
EF		 3914 *
3915 * Clears the ATA_DMA_START flag in the dma control register
3916 *
3917 * May be used as the bmdma_stop() entry in ata_port_operations.
3918 *
3919 * LOCKING:
3920 * spin_lock_irqsave(host_set lock)
3921 */
3922
b73fc89f 3923void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 3924{
b73fc89f 3925 struct ata_port *ap = qc->ap;
1da177e4
LT		 3926 if (ap->flags & ATA_FLAG_MMIO) {
3927 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
3928
3929 /* clear start/stop bit */
3930 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
3931 mmio + ATA_DMA_CMD);
3932 } else {
3933 /* clear start/stop bit */
3934 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
3935 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
3936 }
3937
3938 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
3939 ata_altstatus(ap); /* dummy read */
3940}
3941
3942/**
3943 * ata_host_intr - Handle host interrupt for given (port, task)
3944 * @ap: Port on which interrupt arrived (possibly...)
3945 * @qc: Taskfile currently active in engine
3946 *
3947 * Handle host interrupt for given queued command. Currently,
3948 * only DMA interrupts are handled. All other commands are
3949 * handled via polling with interrupts disabled (nIEN bit).
3950 *
3951 * LOCKING:
3952 * spin_lock_irqsave(host_set lock)
3953 *
3954 * RETURNS:
3955 * One if interrupt was handled, zero if not (shared irq).
3956 */
3957
3958inline unsigned int ata_host_intr (struct ata_port *ap,
3959 struct ata_queued_cmd *qc)
3960{
3961 u8 status, host_stat;
3962
3963 switch (qc->tf.protocol) {
3964
3965 case ATA_PROT_DMA:
3966 case ATA_PROT_ATAPI_DMA:
3967 case ATA_PROT_ATAPI:
3968 /* check status of DMA engine */
3969 host_stat = ap->ops->bmdma_status(ap);
3970 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
3971
3972 /* if it's not our irq... */
3973 if (!(host_stat & ATA_DMA_INTR))
3974 goto idle_irq;
3975
3976 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3977 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3978
3979 /* fall through */
3980
3981 case ATA_PROT_ATAPI_NODATA:
3982 case ATA_PROT_NODATA:
3983 /* check altstatus */
3984 status = ata_altstatus(ap);
3985 if (status & ATA_BUSY)
3986 goto idle_irq;
3987
3988 /* check main status, clearing INTRQ */
3989 status = ata_chk_status(ap);
3990 if (unlikely(status & ATA_BUSY))
3991 goto idle_irq;
3992 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
3993 ap->id, qc->tf.protocol, status);
3994
3995 /* ack bmdma irq events */
3996 ap->ops->irq_clear(ap);
3997
3998 /* complete taskfile transaction */
a22e2eb0
AL		 3999 qc->err_mask |= ac_err_mask(status);
4000 ata_qc_complete(qc);
1da177e4
LT		 4001 break;
4002
4003 default:
4004 goto idle_irq;
4005 }
4006
4007 return 1; /* irq handled */
4008
4009idle_irq:
4010 ap->stats.idle_irq++;
4011
4012#ifdef ATA_IRQ_TRAP
4013 if ((ap->stats.idle_irq % 1000) == 0) {
4014 handled = 1;
4015 ata_irq_ack(ap, 0); /* debug trap */
4016 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4017 }
4018#endif
4019 return 0; /* irq not handled */
4020}
4021
4022/**
4023 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4024 * @irq: irq line (unused)
4025 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4026 * @regs: unused
4027 *
0cba632b
JG		 4028 * Default interrupt handler for PCI IDE devices. Calls
4029 * ata_host_intr() for each port that is not disabled.
4030 *
1da177e4 4031 * LOCKING:
0cba632b 4032 * Obtains host_set lock during operation.
1da177e4
LT		 4033 *
4034 * RETURNS:
0cba632b 4035 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4036 */
4037
4038irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4039{
4040 struct ata_host_set *host_set = dev_instance;
4041 unsigned int i;
4042 unsigned int handled = 0;
4043 unsigned long flags;
4044
4045 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4046 spin_lock_irqsave(&host_set->lock, flags);
4047
4048 for (i = 0; i < host_set->n_ports; i++) {
4049 struct ata_port *ap;
4050
4051 ap = host_set->ports[i];
c1389503
TH		 4052 if (ap &&
4053 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4054 struct ata_queued_cmd *qc;
4055
4056 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4057 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4058 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4059 handled |= ata_host_intr(ap, qc);
4060 }
4061 }
4062
4063 spin_unlock_irqrestore(&host_set->lock, flags);
4064
4065 return IRQ_RETVAL(handled);
4066}
4067
4068/**
4069 * atapi_packet_task - Write CDB bytes to hardware
4070 * @_data: Port to which ATAPI device is attached.
4071 *
4072 * When device has indicated its readiness to accept
4073 * a CDB, this function is called. Send the CDB.
4074 * If DMA is to be performed, exit immediately.
4075 * Otherwise, we are in polling mode, so poll
4076 * status under operation succeeds or fails.
4077 *
4078 * LOCKING:
4079 * Kernel thread context (may sleep)
4080 */
4081
4082static void atapi_packet_task(void *_data)
4083{
4084 struct ata_port *ap = _data;
4085 struct ata_queued_cmd *qc;
4086 u8 status;
4087
4088 qc = ata_qc_from_tag(ap, ap->active_tag);
4089 assert(qc != NULL);
4090 assert(qc->flags & ATA_QCFLAG_ACTIVE);
4091
4092 /* sleep-wait for BSY to clear */
4093 DPRINTK("busy wait\n");
d8fe452b
AL		 4094 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
4095 qc->err_mask |= AC_ERR_ATA_BUS;
4096 goto err_out;
4097 }
1da177e4
LT		 4098
4099 /* make sure DRQ is set */
4100 status = ata_chk_status(ap);
d8fe452b
AL		 4101 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
4102 qc->err_mask |= AC_ERR_ATA_BUS;
1da177e4 4103 goto err_out;
d8fe452b 4104 }
1da177e4
LT		 4105
4106 /* send SCSI cdb */
4107 DPRINTK("send cdb\n");
4108 assert(ap->cdb_len >= 12);
1da177e4 4109
c1389503
TH		 4110 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
4111 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
4112 unsigned long flags;
1da177e4 4113
c1389503
TH		 4114 /* Once we're done issuing command and kicking bmdma,
4115 * irq handler takes over. To not lose irq, we need
4116 * to clear NOINTR flag before sending cdb, but
4117 * interrupt handler shouldn't be invoked before we're
4118 * finished. Hence, the following locking.
4119 */
4120 spin_lock_irqsave(&ap->host_set->lock, flags);
4121 ap->flags &= ~ATA_FLAG_NOINTR;
4122 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
4123 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
4124 ap->ops->bmdma_start(qc); /* initiate bmdma */
4125 spin_unlock_irqrestore(&ap->host_set->lock, flags);
4126 } else {
4127 ata_data_xfer(ap, qc->cdb, ap->cdb_len, 1);
1da177e4 4128
c1389503 4129 /* PIO commands are handled by polling */
14be71f4 4130 ap->hsm_task_state = HSM_ST;
1da177e4
LT		 4131 queue_work(ata_wq, &ap->pio_task);
4132 }
4133
4134 return;
4135
4136err_out:
a22e2eb0 4137 ata_poll_qc_complete(qc);
1da177e4
LT		 4138}
4139
0baab86b
EF		 4140
4141/**
4142 * ata_port_start - Set port up for dma.
4143 * @ap: Port to initialize
4144 *
4145 * Called just after data structures for each port are
4146 * initialized. Allocates space for PRD table.
4147 *
4148 * May be used as the port_start() entry in ata_port_operations.
4149 *
4150 * LOCKING:
6f0ef4fa 4151 * Inherited from caller.
0baab86b
EF		 4152 */
4153
1da177e4
LT		 4154int ata_port_start (struct ata_port *ap)
4155{
4156 struct device *dev = ap->host_set->dev;
6037d6bb 4157 int rc;
1da177e4
LT		 4158
4159 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4160 if (!ap->prd)
4161 return -ENOMEM;
4162
6037d6bb
JG		 4163 rc = ata_pad_alloc(ap, dev);
4164 if (rc) {
cedc9a47 4165 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4166 return rc;
cedc9a47
JG		 4167 }
4168
1da177e4
LT		 4169 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4170
4171 return 0;
4172}
4173
0baab86b
EF		 4174
4175/**
4176 * ata_port_stop - Undo ata_port_start()
4177 * @ap: Port to shut down
4178 *
4179 * Frees the PRD table.
4180 *
4181 * May be used as the port_stop() entry in ata_port_operations.
4182 *
4183 * LOCKING:
6f0ef4fa 4184 * Inherited from caller.
0baab86b
EF		 4185 */
4186
1da177e4
LT		 4187void ata_port_stop (struct ata_port *ap)
4188{
4189 struct device *dev = ap->host_set->dev;
4190
4191 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4192 ata_pad_free(ap, dev);
1da177e4
LT		 4193}
4194
aa8f0dc6
JG		 4195void ata_host_stop (struct ata_host_set *host_set)
4196{
4197 if (host_set->mmio_base)
4198 iounmap(host_set->mmio_base);
4199}
4200
4201
1da177e4
LT		 4202/**
4203 * ata_host_remove - Unregister SCSI host structure with upper layers
4204 * @ap: Port to unregister
4205 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4206 *
4207 * LOCKING:
6f0ef4fa 4208 * Inherited from caller.
1da177e4
LT		 4209 */
4210
4211static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4212{
4213 struct Scsi_Host *sh = ap->host;
4214
4215 DPRINTK("ENTER\n");
4216
4217 if (do_unregister)
4218 scsi_remove_host(sh);
4219
4220 ap->ops->port_stop(ap);
4221}
4222
4223/**
4224 * ata_host_init - Initialize an ata_port structure
4225 * @ap: Structure to initialize
4226 * @host: associated SCSI mid-layer structure
4227 * @host_set: Collection of hosts to which @ap belongs
4228 * @ent: Probe information provided by low-level driver
4229 * @port_no: Port number associated with this ata_port
4230 *
0cba632b
JG		 4231 * Initialize a new ata_port structure, and its associated
4232 * scsi_host.
4233 *
1da177e4 4234 * LOCKING:
0cba632b 4235 * Inherited from caller.
1da177e4
LT		 4236 */
4237
4238static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4239 struct ata_host_set *host_set,
057ace5e 4240 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4241{
4242 unsigned int i;
4243
4244 host->max_id = 16;
4245 host->max_lun = 1;
4246 host->max_channel = 1;
4247 host->unique_id = ata_unique_id++;
4248 host->max_cmd_len = 12;
12413197 4249
1da177e4
LT		 4250 ap->flags = ATA_FLAG_PORT_DISABLED;
4251 ap->id = host->unique_id;
4252 ap->host = host;
4253 ap->ctl = ATA_DEVCTL_OBS;
4254 ap->host_set = host_set;
4255 ap->port_no = port_no;
4256 ap->hard_port_no =
4257 ent->legacy_mode ? ent->hard_port_no : port_no;
4258 ap->pio_mask = ent->pio_mask;
4259 ap->mwdma_mask = ent->mwdma_mask;
4260 ap->udma_mask = ent->udma_mask;
4261 ap->flags |= ent->host_flags;
4262 ap->ops = ent->port_ops;
4263 ap->cbl = ATA_CBL_NONE;
4264 ap->active_tag = ATA_TAG_POISON;
4265 ap->last_ctl = 0xFF;
4266
4267 INIT_WORK(&ap->packet_task, atapi_packet_task, ap);
4268 INIT_WORK(&ap->pio_task, ata_pio_task, ap);
4269
4270 for (i = 0; i < ATA_MAX_DEVICES; i++)
4271 ap->device[i].devno = i;
4272
4273#ifdef ATA_IRQ_TRAP
4274 ap->stats.unhandled_irq = 1;
4275 ap->stats.idle_irq = 1;
4276#endif
4277
4278 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4279}
4280
4281/**
4282 * ata_host_add - Attach low-level ATA driver to system
4283 * @ent: Information provided by low-level driver
4284 * @host_set: Collections of ports to which we add
4285 * @port_no: Port number associated with this host
4286 *
0cba632b
JG		 4287 * Attach low-level ATA driver to system.
4288 *
1da177e4 4289 * LOCKING:
0cba632b 4290 * PCI/etc. bus probe sem.
1da177e4
LT		 4291 *
4292 * RETURNS:
0cba632b 4293 * New ata_port on success, for NULL on error.
1da177e4
LT		 4294 */
4295
057ace5e 4296static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4297 struct ata_host_set *host_set,
4298 unsigned int port_no)
4299{
4300 struct Scsi_Host *host;
4301 struct ata_port *ap;
4302 int rc;
4303
4304 DPRINTK("ENTER\n");
4305 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4306 if (!host)
4307 return NULL;
4308
4309 ap = (struct ata_port *) &host->hostdata[0];
4310
4311 ata_host_init(ap, host, host_set, ent, port_no);
4312
4313 rc = ap->ops->port_start(ap);
4314 if (rc)
4315 goto err_out;
4316
4317 return ap;
4318
4319err_out:
4320 scsi_host_put(host);
4321 return NULL;
4322}
4323
4324/**
0cba632b
JG		 4325 * ata_device_add - Register hardware device with ATA and SCSI layers
4326 * @ent: Probe information describing hardware device to be registered
4327 *
4328 * This function processes the information provided in the probe
4329 * information struct @ent, allocates the necessary ATA and SCSI
4330 * host information structures, initializes them, and registers
4331 * everything with requisite kernel subsystems.
4332 *
4333 * This function requests irqs, probes the ATA bus, and probes
4334 * the SCSI bus.
1da177e4
LT		 4335 *
4336 * LOCKING:
0cba632b 4337 * PCI/etc. bus probe sem.
1da177e4
LT		 4338 *
4339 * RETURNS:
0cba632b 4340 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4341 */
4342
057ace5e 4343int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4344{
4345 unsigned int count = 0, i;
4346 struct device *dev = ent->dev;
4347 struct ata_host_set *host_set;
4348
4349 DPRINTK("ENTER\n");
4350 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4351 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4352 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4353 if (!host_set)
4354 return 0;
1da177e4
LT		 4355 spin_lock_init(&host_set->lock);
4356
4357 host_set->dev = dev;
4358 host_set->n_ports = ent->n_ports;
4359 host_set->irq = ent->irq;
4360 host_set->mmio_base = ent->mmio_base;
4361 host_set->private_data = ent->private_data;
4362 host_set->ops = ent->port_ops;
4363
4364 /* register each port bound to this device */
4365 for (i = 0; i < ent->n_ports; i++) {
4366 struct ata_port *ap;
4367 unsigned long xfer_mode_mask;
4368
4369 ap = ata_host_add(ent, host_set, i);
4370 if (!ap)
4371 goto err_out;
4372
4373 host_set->ports[i] = ap;
4374 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4375 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4376 (ap->pio_mask << ATA_SHIFT_PIO);
4377
4378 /* print per-port info to dmesg */
4379 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4380 "bmdma 0x%lX irq %lu\n",
4381 ap->id,
4382 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4383 ata_mode_string(xfer_mode_mask),
4384 ap->ioaddr.cmd_addr,
4385 ap->ioaddr.ctl_addr,
4386 ap->ioaddr.bmdma_addr,
4387 ent->irq);
4388
4389 ata_chk_status(ap);
4390 host_set->ops->irq_clear(ap);
4391 count++;
4392 }
4393
57f3bda8
RD		 4394 if (!count)
4395 goto err_free_ret;
1da177e4
LT		 4396
4397 /* obtain irq, that is shared between channels */
4398 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4399 DRV_NAME, host_set))
4400 goto err_out;
4401
4402 /* perform each probe synchronously */
4403 DPRINTK("probe begin\n");
4404 for (i = 0; i < count; i++) {
4405 struct ata_port *ap;
4406 int rc;
4407
4408 ap = host_set->ports[i];
4409
4410 DPRINTK("ata%u: probe begin\n", ap->id);
4411 rc = ata_bus_probe(ap);
4412 DPRINTK("ata%u: probe end\n", ap->id);
4413
4414 if (rc) {
4415 /* FIXME: do something useful here?
4416 * Current libata behavior will
4417 * tear down everything when
4418 * the module is removed
4419 * or the h/w is unplugged.
4420 */
4421 }
4422
4423 rc = scsi_add_host(ap->host, dev);
4424 if (rc) {
4425 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4426 ap->id);
4427 /* FIXME: do something useful here */
4428 /* FIXME: handle unconditional calls to
4429 * scsi_scan_host and ata_host_remove, below,
4430 * at the very least
4431 */
4432 }
4433 }
4434
4435 /* probes are done, now scan each port's disk(s) */
4436 DPRINTK("probe begin\n");
4437 for (i = 0; i < count; i++) {
4438 struct ata_port *ap = host_set->ports[i];
4439
644dd0cc 4440 ata_scsi_scan_host(ap);
1da177e4
LT		 4441 }
4442
4443 dev_set_drvdata(dev, host_set);
4444
4445 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4446 return ent->n_ports; /* success */
4447
4448err_out:
4449 for (i = 0; i < count; i++) {
4450 ata_host_remove(host_set->ports[i], 1);
4451 scsi_host_put(host_set->ports[i]->host);
4452 }
57f3bda8 4453err_free_ret:
1da177e4
LT		 4454 kfree(host_set);
4455 VPRINTK("EXIT, returning 0\n");
4456 return 0;
4457}
4458
17b14451
AC		 4459/**
4460 * ata_host_set_remove - PCI layer callback for device removal
4461 * @host_set: ATA host set that was removed
4462 *
4463 * Unregister all objects associated with this host set. Free those
4464 * objects.
4465 *
4466 * LOCKING:
4467 * Inherited from calling layer (may sleep).
4468 */
4469
17b14451
AC		 4470void ata_host_set_remove(struct ata_host_set *host_set)
4471{
4472 struct ata_port *ap;
4473 unsigned int i;
4474
4475 for (i = 0; i < host_set->n_ports; i++) {
4476 ap = host_set->ports[i];
4477 scsi_remove_host(ap->host);
4478 }
4479
4480 free_irq(host_set->irq, host_set);
4481
4482 for (i = 0; i < host_set->n_ports; i++) {
4483 ap = host_set->ports[i];
4484
4485 ata_scsi_release(ap->host);
4486
4487 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4488 struct ata_ioports *ioaddr = &ap->ioaddr;
4489
4490 if (ioaddr->cmd_addr == 0x1f0)
4491 release_region(0x1f0, 8);
4492 else if (ioaddr->cmd_addr == 0x170)
4493 release_region(0x170, 8);
4494 }
4495
4496 scsi_host_put(ap->host);
4497 }
4498
4499 if (host_set->ops->host_stop)
4500 host_set->ops->host_stop(host_set);
4501
4502 kfree(host_set);
4503}
4504
1da177e4
LT		 4505/**
4506 * ata_scsi_release - SCSI layer callback hook for host unload
4507 * @host: libata host to be unloaded
4508 *
4509 * Performs all duties necessary to shut down a libata port...
4510 * Kill port kthread, disable port, and release resources.
4511 *
4512 * LOCKING:
4513 * Inherited from SCSI layer.
4514 *
4515 * RETURNS:
4516 * One.
4517 */
4518
4519int ata_scsi_release(struct Scsi_Host *host)
4520{
4521 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
4522
4523 DPRINTK("ENTER\n");
4524
4525 ap->ops->port_disable(ap);
4526 ata_host_remove(ap, 0);
4527
4528 DPRINTK("EXIT\n");
4529 return 1;
4530}
4531
4532/**
4533 * ata_std_ports - initialize ioaddr with standard port offsets.
4534 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4535 *
4536 * Utility function which initializes data_addr, error_addr,
4537 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4538 * device_addr, status_addr, and command_addr to standard offsets
4539 * relative to cmd_addr.
4540 *
4541 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4542 */
0baab86b 4543
1da177e4
LT		 4544void ata_std_ports(struct ata_ioports *ioaddr)
4545{
4546 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4547 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4548 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4549 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4550 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4551 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4552 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4553 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4554 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4555 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4556}
4557
4558static struct ata_probe_ent *
057ace5e 4559ata_probe_ent_alloc(struct device *dev, const struct ata_port_info *port)
1da177e4
LT		 4560{
4561 struct ata_probe_ent *probe_ent;
4562
57f3bda8 4563 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1da177e4
LT		 4564 if (!probe_ent) {
4565 printk(KERN_ERR DRV_NAME "(%s): out of memory\n",
4566 kobject_name(&(dev->kobj)));
4567 return NULL;
4568 }
4569
1da177e4
LT		 4570 INIT_LIST_HEAD(&probe_ent->node);
4571 probe_ent->dev = dev;
4572
4573 probe_ent->sht = port->sht;
4574 probe_ent->host_flags = port->host_flags;
4575 probe_ent->pio_mask = port->pio_mask;
4576 probe_ent->mwdma_mask = port->mwdma_mask;
4577 probe_ent->udma_mask = port->udma_mask;
4578 probe_ent->port_ops = port->port_ops;
4579
4580 return probe_ent;
4581}
4582
0baab86b
EF		 4583
4584
374b1873
JG		 4585#ifdef CONFIG_PCI
4586
4587void ata_pci_host_stop (struct ata_host_set *host_set)
4588{
4589 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4590
4591 pci_iounmap(pdev, host_set->mmio_base);
4592}
4593
0baab86b
EF		 4594/**
4595 * ata_pci_init_native_mode - Initialize native-mode driver
4596 * @pdev: pci device to be initialized
4597 * @port: array[2] of pointers to port info structures.
47a86593 4598 * @ports: bitmap of ports present
0baab86b
EF		 4599 *
4600 * Utility function which allocates and initializes an
4601 * ata_probe_ent structure for a standard dual-port
4602 * PIO-based IDE controller. The returned ata_probe_ent
4603 * structure can be passed to ata_device_add(). The returned
4604 * ata_probe_ent structure should then be freed with kfree().
47a86593
AC		 4605 *
4606 * The caller need only pass the address of the primary port, the
4607 * secondary will be deduced automatically. If the device has non
4608 * standard secondary port mappings this function can be called twice,
4609 * once for each interface.
0baab86b
EF		 4610 */
4611
1da177e4 4612struct ata_probe_ent *
47a86593 4613ata_pci_init_native_mode(struct pci_dev *pdev, struct ata_port_info **port, int ports)
1da177e4
LT		 4614{
4615 struct ata_probe_ent *probe_ent =
4616 ata_probe_ent_alloc(pci_dev_to_dev(pdev), port[0]);
47a86593
AC		 4617 int p = 0;
4618
1da177e4
LT		 4619 if (!probe_ent)
4620 return NULL;
4621
1da177e4
LT		 4622 probe_ent->irq = pdev->irq;
4623 probe_ent->irq_flags = SA_SHIRQ;
e99f8b5e 4624 probe_ent->private_data = port[0]->private_data;
1da177e4 4625
47a86593
AC		 4626 if (ports & ATA_PORT_PRIMARY) {
4627 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 0);
4628 probe_ent->port[p].altstatus_addr =
4629 probe_ent->port[p].ctl_addr =
4630 pci_resource_start(pdev, 1) | ATA_PCI_CTL_OFS;
4631 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4);
4632 ata_std_ports(&probe_ent->port[p]);
4633 p++;
4634 }
1da177e4 4635
47a86593
AC		 4636 if (ports & ATA_PORT_SECONDARY) {
4637 probe_ent->port[p].cmd_addr = pci_resource_start(pdev, 2);
4638 probe_ent->port[p].altstatus_addr =
4639 probe_ent->port[p].ctl_addr =
4640 pci_resource_start(pdev, 3) | ATA_PCI_CTL_OFS;
4641 probe_ent->port[p].bmdma_addr = pci_resource_start(pdev, 4) + 8;
4642 ata_std_ports(&probe_ent->port[p]);
4643 p++;
4644 }
1da177e4 4645
47a86593 4646 probe_ent->n_ports = p;
1da177e4
LT		 4647 return probe_ent;
4648}
4649
0f0d5192 4650static struct ata_probe_ent *ata_pci_init_legacy_port(struct pci_dev *pdev, struct ata_port_info *port, int port_num)
1da177e4 4651{
47a86593 4652 struct ata_probe_ent *probe_ent;
1da177e4 4653
0f0d5192 4654 probe_ent = ata_probe_ent_alloc(pci_dev_to_dev(pdev), port);
1da177e4
LT		 4655 if (!probe_ent)
4656 return NULL;
1da177e4 4657
1da177e4 4658 probe_ent->legacy_mode = 1;
47a86593
AC		 4659 probe_ent->n_ports = 1;
4660 probe_ent->hard_port_no = port_num;
e99f8b5e 4661 probe_ent->private_data = port->private_data;
47a86593
AC		 4662
4663 switch(port_num)
4664 {
4665 case 0:
4666 probe_ent->irq = 14;
4667 probe_ent->port[0].cmd_addr = 0x1f0;
4668 probe_ent->port[0].altstatus_addr =
4669 probe_ent->port[0].ctl_addr = 0x3f6;
4670 break;
4671 case 1:
4672 probe_ent->irq = 15;
4673 probe_ent->port[0].cmd_addr = 0x170;
4674 probe_ent->port[0].altstatus_addr =
4675 probe_ent->port[0].ctl_addr = 0x376;
4676 break;
4677 }
4678 probe_ent->port[0].bmdma_addr = pci_resource_start(pdev, 4) + 8 * port_num;
1da177e4 4679 ata_std_ports(&probe_ent->port[0]);
1da177e4
LT		 4680 return probe_ent;
4681}
4682
4683/**
4684 * ata_pci_init_one - Initialize/register PCI IDE host controller
4685 * @pdev: Controller to be initialized
4686 * @port_info: Information from low-level host driver
4687 * @n_ports: Number of ports attached to host controller
4688 *
0baab86b
EF		 4689 * This is a helper function which can be called from a driver's
4690 * xxx_init_one() probe function if the hardware uses traditional
4691 * IDE taskfile registers.
4692 *
4693 * This function calls pci_enable_device(), reserves its register
4694 * regions, sets the dma mask, enables bus master mode, and calls
4695 * ata_device_add()
4696 *
1da177e4
LT		 4697 * LOCKING:
4698 * Inherited from PCI layer (may sleep).
4699 *
4700 * RETURNS:
0cba632b 4701 * Zero on success, negative on errno-based value on error.
1da177e4
LT		 4702 */
4703
4704int ata_pci_init_one (struct pci_dev *pdev, struct ata_port_info **port_info,
4705 unsigned int n_ports)
4706{
47a86593 4707 struct ata_probe_ent *probe_ent = NULL, *probe_ent2 = NULL;
1da177e4
LT		 4708 struct ata_port_info *port[2];
4709 u8 tmp8, mask;
4710 unsigned int legacy_mode = 0;
4711 int disable_dev_on_err = 1;
4712 int rc;
4713
4714 DPRINTK("ENTER\n");
4715
4716 port[0] = port_info[0];
4717 if (n_ports > 1)
4718 port[1] = port_info[1];
4719 else
4720 port[1] = port[0];
4721
4722 if ((port[0]->host_flags & ATA_FLAG_NO_LEGACY) == 0
4723 && (pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
47a86593 4724 /* TODO: What if one channel is in native mode ... */
1da177e4
LT		 4725 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
4726 mask = (1 << 2) | (1 << 0);
4727 if ((tmp8 & mask) != mask)
4728 legacy_mode = (1 << 3);
4729 }
4730
4731 /* FIXME... */
47a86593
AC		 4732 if ((!legacy_mode) && (n_ports > 2)) {
4733 printk(KERN_ERR "ata: BUG: native mode, n_ports > 2\n");
4734 n_ports = 2;
4735 /* For now */
1da177e4
LT		 4736 }
4737
47a86593
AC		 4738 /* FIXME: Really for ATA it isn't safe because the device may be
4739 multi-purpose and we want to leave it alone if it was already
4740 enabled. Secondly for shared use as Arjan says we want refcounting
4741
4742 Checking dev->is_enabled is insufficient as this is not set at
4743 boot for the primary video which is BIOS enabled
4744 */
4745
1da177e4
LT		 4746 rc = pci_enable_device(pdev);
4747 if (rc)
4748 return rc;
4749
4750 rc = pci_request_regions(pdev, DRV_NAME);
4751 if (rc) {
4752 disable_dev_on_err = 0;
4753 goto err_out;
4754 }
4755
47a86593 4756 /* FIXME: Should use platform specific mappers for legacy port ranges */
1da177e4
LT		 4757 if (legacy_mode) {
4758 if (!request_region(0x1f0, 8, "libata")) {
4759 struct resource *conflict, res;
4760 res.start = 0x1f0;
4761 res.end = 0x1f0 + 8 - 1;
4762 conflict = ____request_resource(&ioport_resource, &res);
4763 if (!strcmp(conflict->name, "libata"))
4764 legacy_mode |= (1 << 0);
4765 else {
4766 disable_dev_on_err = 0;
4767 printk(KERN_WARNING "ata: 0x1f0 IDE port busy\n");
4768 }
4769 } else
4770 legacy_mode |= (1 << 0);
4771
4772 if (!request_region(0x170, 8, "libata")) {
4773 struct resource *conflict, res;
4774 res.start = 0x170;
4775 res.end = 0x170 + 8 - 1;
4776 conflict = ____request_resource(&ioport_resource, &res);
4777 if (!strcmp(conflict->name, "libata"))
4778 legacy_mode |= (1 << 1);
4779 else {
4780 disable_dev_on_err = 0;
4781 printk(KERN_WARNING "ata: 0x170 IDE port busy\n");
4782 }
4783 } else
4784 legacy_mode |= (1 << 1);
4785 }
4786
4787 /* we have legacy mode, but all ports are unavailable */
4788 if (legacy_mode == (1 << 3)) {
4789 rc = -EBUSY;
4790 goto err_out_regions;
4791 }
4792
4793 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
4794 if (rc)
4795 goto err_out_regions;
4796 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
4797 if (rc)
4798 goto err_out_regions;
4799
4800 if (legacy_mode) {
47a86593 4801 if (legacy_mode & (1 << 0))
0f0d5192 4802 probe_ent = ata_pci_init_legacy_port(pdev, port[0], 0);
47a86593 4803 if (legacy_mode & (1 << 1))
0f0d5192 4804 probe_ent2 = ata_pci_init_legacy_port(pdev, port[1], 1);
47a86593
AC		 4805 } else {
4806 if (n_ports == 2)
4807 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
4808 else
4809 probe_ent = ata_pci_init_native_mode(pdev, port, ATA_PORT_PRIMARY);
4810 }
4811 if (!probe_ent && !probe_ent2) {
1da177e4
LT		 4812 rc = -ENOMEM;
4813 goto err_out_regions;
4814 }
4815
4816 pci_set_master(pdev);
4817
4818 /* FIXME: check ata_device_add return */
4819 if (legacy_mode) {
4820 if (legacy_mode & (1 << 0))
4821 ata_device_add(probe_ent);
4822 if (legacy_mode & (1 << 1))
4823 ata_device_add(probe_ent2);
4824 } else
4825 ata_device_add(probe_ent);
4826
4827 kfree(probe_ent);
4828 kfree(probe_ent2);
4829
4830 return 0;
4831
4832err_out_regions:
4833 if (legacy_mode & (1 << 0))
4834 release_region(0x1f0, 8);
4835 if (legacy_mode & (1 << 1))
4836 release_region(0x170, 8);
4837 pci_release_regions(pdev);
4838err_out:
4839 if (disable_dev_on_err)
4840 pci_disable_device(pdev);
4841 return rc;
4842}
4843
4844/**
4845 * ata_pci_remove_one - PCI layer callback for device removal
4846 * @pdev: PCI device that was removed
4847 *
4848 * PCI layer indicates to libata via this hook that
6f0ef4fa 4849 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4850 * Handle this by unregistering all objects associated
4851 * with this PCI device. Free those objects. Then finally
4852 * release PCI resources and disable device.
4853 *
4854 * LOCKING:
4855 * Inherited from PCI layer (may sleep).
4856 */
4857
4858void ata_pci_remove_one (struct pci_dev *pdev)
4859{
4860 struct device *dev = pci_dev_to_dev(pdev);
4861 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4862
17b14451 4863 ata_host_set_remove(host_set);
1da177e4
LT		 4864 pci_release_regions(pdev);
4865 pci_disable_device(pdev);
4866 dev_set_drvdata(dev, NULL);
4867}
4868
4869/* move to PCI subsystem */
057ace5e 4870int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4871{
4872 unsigned long tmp = 0;
4873
4874 switch (bits->width) {
4875 case 1: {
4876 u8 tmp8 = 0;
4877 pci_read_config_byte(pdev, bits->reg, &tmp8);
4878 tmp = tmp8;
4879 break;
4880 }
4881 case 2: {
4882 u16 tmp16 = 0;
4883 pci_read_config_word(pdev, bits->reg, &tmp16);
4884 tmp = tmp16;
4885 break;
4886 }
4887 case 4: {
4888 u32 tmp32 = 0;
4889 pci_read_config_dword(pdev, bits->reg, &tmp32);
4890 tmp = tmp32;
4891 break;
4892 }
4893
4894 default:
4895 return -EINVAL;
4896 }
4897
4898 tmp &= bits->mask;
4899
4900 return (tmp == bits->val) ? 1 : 0;
4901}
4902#endif /* CONFIG_PCI */
4903
4904
1da177e4
LT		 4905static int __init ata_init(void)
4906{
4907 ata_wq = create_workqueue("ata");
4908 if (!ata_wq)
4909 return -ENOMEM;
4910
4911 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
4912 return 0;
4913}
4914
4915static void __exit ata_exit(void)
4916{
4917 destroy_workqueue(ata_wq);
4918}
4919
4920module_init(ata_init);
4921module_exit(ata_exit);
4922
67846b30
JG		 4923static unsigned long ratelimit_time;
4924static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
4925
4926int ata_ratelimit(void)
4927{
4928 int rc;
4929 unsigned long flags;
4930
4931 spin_lock_irqsave(&ata_ratelimit_lock, flags);
4932
4933 if (time_after(jiffies, ratelimit_time)) {
4934 rc = 1;
4935 ratelimit_time = jiffies + (HZ/5);
4936 } else
4937 rc = 0;
4938
4939 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
4940
4941 return rc;
4942}
4943
1da177e4
LT		 4944/*
4945 * libata is essentially a library of internal helper functions for
4946 * low-level ATA host controller drivers. As such, the API/ABI is
4947 * likely to change as new drivers are added and updated.
4948 * Do not depend on ABI/API stability.
4949 */
4950
4951EXPORT_SYMBOL_GPL(ata_std_bios_param);
4952EXPORT_SYMBOL_GPL(ata_std_ports);
4953EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 4954EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 4955EXPORT_SYMBOL_GPL(ata_sg_init);
4956EXPORT_SYMBOL_GPL(ata_sg_init_one);
4957EXPORT_SYMBOL_GPL(ata_qc_complete);
4958EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
4959EXPORT_SYMBOL_GPL(ata_eng_timeout);
4960EXPORT_SYMBOL_GPL(ata_tf_load);
4961EXPORT_SYMBOL_GPL(ata_tf_read);
4962EXPORT_SYMBOL_GPL(ata_noop_dev_select);
4963EXPORT_SYMBOL_GPL(ata_std_dev_select);
4964EXPORT_SYMBOL_GPL(ata_tf_to_fis);
4965EXPORT_SYMBOL_GPL(ata_tf_from_fis);
4966EXPORT_SYMBOL_GPL(ata_check_status);
4967EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 4968EXPORT_SYMBOL_GPL(ata_exec_command);
4969EXPORT_SYMBOL_GPL(ata_port_start);
4970EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 4971EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 4972EXPORT_SYMBOL_GPL(ata_interrupt);
4973EXPORT_SYMBOL_GPL(ata_qc_prep);
4974EXPORT_SYMBOL_GPL(ata_bmdma_setup);
4975EXPORT_SYMBOL_GPL(ata_bmdma_start);
4976EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
4977EXPORT_SYMBOL_GPL(ata_bmdma_status);
4978EXPORT_SYMBOL_GPL(ata_bmdma_stop);
4979EXPORT_SYMBOL_GPL(ata_port_probe);
4980EXPORT_SYMBOL_GPL(sata_phy_reset);
4981EXPORT_SYMBOL_GPL(__sata_phy_reset);
4982EXPORT_SYMBOL_GPL(ata_bus_reset);
4983EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 4984EXPORT_SYMBOL_GPL(ata_ratelimit);
1da177e4
LT		 4985EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
4986EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
4987EXPORT_SYMBOL_GPL(ata_scsi_error);
4988EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
4989EXPORT_SYMBOL_GPL(ata_scsi_release);
4990EXPORT_SYMBOL_GPL(ata_host_intr);
4991EXPORT_SYMBOL_GPL(ata_dev_classify);
4992EXPORT_SYMBOL_GPL(ata_dev_id_string);
6f2f3812 4993EXPORT_SYMBOL_GPL(ata_dev_config);
1da177e4
LT		 4994EXPORT_SYMBOL_GPL(ata_scsi_simulate);
4995
452503f9
AC		 4996EXPORT_SYMBOL_GPL(ata_timing_compute);
4997EXPORT_SYMBOL_GPL(ata_timing_merge);
4998
1da177e4
LT		 4999#ifdef CONFIG_PCI
5000EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5001EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5002EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5003EXPORT_SYMBOL_GPL(ata_pci_init_one);
5004EXPORT_SYMBOL_GPL(ata_pci_remove_one);
5005#endif /* CONFIG_PCI */
Clone of davem's net-next-2.6 tree