[net-next-2.6.git] / drivers / scsi / cyberstormII.c

/* cyberstormII.c: Driver for CyberStorm SCSI Mk II
 *
 * Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
 *
 * This driver is based on cyberstorm.c
 */

/* TODO:
 *
 * 1) Figure out how to make a cleaner merge with the sparc driver with regard
 *    to the caches and the Sparc MMU mapping.
 * 2) Make as few routines required outside the generic driver. A lot of the
 *    routines in this file used to be inline!
 */

#include <linux/module.h>

#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/blkdev.h>
#include <linux/proc_fs.h>
#include <linux/stat.h>
#include <linux/interrupt.h>

#include "scsi.h"
#include <scsi/scsi_host.h>
#include "NCR53C9x.h"

#include <linux/zorro.h>
#include <asm/irq.h>
#include <asm/amigaints.h>
#include <asm/amigahw.h>

#include <asm/pgtable.h>

/* The controller registers can be found in the Z2 config area at these
 * offsets:
 */
#define CYBERII_ESP_ADDR 0x1ff03
#define CYBERII_DMA_ADDR 0x1ff43


/* The CyberStorm II DMA interface */
struct cyberII_dma_registers {
	volatile unsigned char cond_reg;        /* DMA cond    (ro)  [0x000] */
#define ctrl_reg  cond_reg			/* DMA control (wo)  [0x000] */
	unsigned char dmapad4[0x3f];
	volatile unsigned char dma_addr0;	/* DMA address (MSB) [0x040] */
	unsigned char dmapad1[3];
	volatile unsigned char dma_addr1;	/* DMA address       [0x044] */
	unsigned char dmapad2[3];
	volatile unsigned char dma_addr2;	/* DMA address       [0x048] */
	unsigned char dmapad3[3];
	volatile unsigned char dma_addr3;	/* DMA address (LSB) [0x04c] */
};

/* DMA control bits */
#define CYBERII_DMA_LED    0x02	/* HD led control 1 = on */

static int  dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
static int  dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp);
static void dma_dump_state(struct NCR_ESP *esp);
static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
static void dma_ints_off(struct NCR_ESP *esp);
static void dma_ints_on(struct NCR_ESP *esp);
static int  dma_irq_p(struct NCR_ESP *esp);
static void dma_led_off(struct NCR_ESP *esp);
static void dma_led_on(struct NCR_ESP *esp);
static int  dma_ports_p(struct NCR_ESP *esp);
static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);

static volatile unsigned char cmd_buffer[16];
				/* This is where all commands are put
				 * before they are transferred to the ESP chip
				 * via PIO.
				 */

/***************************************************************** Detection */
int __init cyberII_esp_detect(struct scsi_host_template *tpnt)
{
	struct NCR_ESP *esp;
	struct zorro_dev *z = NULL;
	unsigned long address;
	struct ESP_regs *eregs;

	if ((z = zorro_find_device(ZORRO_PROD_PHASE5_CYBERSTORM_MK_II, z))) {
	    unsigned long board = z->resource.start;
	    if (request_mem_region(board+CYBERII_ESP_ADDR,
				   sizeof(struct ESP_regs), "NCR53C9x")) {
		/* Do some magic to figure out if the CyberStorm Mk II
		 * is equipped with a SCSI controller
		 */
		address = (unsigned long)ZTWO_VADDR(board);
		eregs = (struct ESP_regs *)(address + CYBERII_ESP_ADDR);

		esp = esp_allocate(tpnt, (void *)board + CYBERII_ESP_ADDR, 0);

		esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE | 7));
		udelay(5);
		if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE | 7)) {
			esp_deallocate(esp);
			scsi_unregister(esp->ehost);
			release_mem_region(board+CYBERII_ESP_ADDR,
					   sizeof(struct ESP_regs));
			return 0; /* Bail out if address did not hold data */
		}

		/* Do command transfer with programmed I/O */
		esp->do_pio_cmds = 1;

		/* Required functions */
		esp->dma_bytes_sent = &dma_bytes_sent;
		esp->dma_can_transfer = &dma_can_transfer;
		esp->dma_dump_state = &dma_dump_state;
		esp->dma_init_read = &dma_init_read;
		esp->dma_init_write = &dma_init_write;
		esp->dma_ints_off = &dma_ints_off;
		esp->dma_ints_on = &dma_ints_on;
		esp->dma_irq_p = &dma_irq_p;
		esp->dma_ports_p = &dma_ports_p;
		esp->dma_setup = &dma_setup;

		/* Optional functions */
		esp->dma_barrier = 0;
		esp->dma_drain = 0;
		esp->dma_invalidate = 0;
		esp->dma_irq_entry = 0;
		esp->dma_irq_exit = 0;
		esp->dma_led_on = &dma_led_on;
		esp->dma_led_off = &dma_led_off;
		esp->dma_poll = 0;
		esp->dma_reset = 0;

		/* SCSI chip speed */
		esp->cfreq = 40000000;

		/* The DMA registers on the CyberStorm are mapped
		 * relative to the device (i.e. in the same Zorro
		 * I/O block).
		 */
		esp->dregs = (void *)(address + CYBERII_DMA_ADDR);

		/* ESP register base */
		esp->eregs = eregs;
		
		/* Set the command buffer */
		esp->esp_command = cmd_buffer;
		esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);

		esp->irq = IRQ_AMIGA_PORTS;
		request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
			    "CyberStorm SCSI Mk II", esp->ehost);

		/* Figure out our scsi ID on the bus */
		esp->scsi_id = 7;
		
		/* We don't have a differential SCSI-bus. */
		esp->diff = 0;

		esp_initialize(esp);

		printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
		esps_running = esps_in_use;
		return esps_in_use;
	    }
	}
	return 0;
}

/************************************************************* DMA Functions */
static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
{
	/* Since the CyberStorm DMA is fully dedicated to the ESP chip,
	 * the number of bytes sent (to the ESP chip) equals the number
	 * of bytes in the FIFO - there is no buffering in the DMA controller.
	 * XXXX Do I read this right? It is from host to ESP, right?
	 */
	return fifo_count;
}

static int dma_can_transfer(struct NCR_ESP *esp, Scsi_Cmnd *sp)
{
	/* I don't think there's any limit on the CyberDMA. So we use what
	 * the ESP chip can handle (24 bit).
	 */
	unsigned long sz = sp->SCp.this_residual;
	if(sz > 0x1000000)
		sz = 0x1000000;
	return sz;
}

static void dma_dump_state(struct NCR_ESP *esp)
{
	ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
		esp->esp_id, ((struct cyberII_dma_registers *)
			      (esp->dregs))->cond_reg));
	ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
		amiga_custom.intreqr, amiga_custom.intenar));
}

static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
{
	struct cyberII_dma_registers *dregs = 
		(struct cyberII_dma_registers *) esp->dregs;

	cache_clear(addr, length);

	addr &= ~(1);
	dregs->dma_addr0 = (addr >> 24) & 0xff;
	dregs->dma_addr1 = (addr >> 16) & 0xff;
	dregs->dma_addr2 = (addr >>  8) & 0xff;
	dregs->dma_addr3 = (addr      ) & 0xff;
}

static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
{
	struct cyberII_dma_registers *dregs = 
		(struct cyberII_dma_registers *) esp->dregs;

	cache_push(addr, length);

	addr |= 1;
	dregs->dma_addr0 = (addr >> 24) & 0xff;
	dregs->dma_addr1 = (addr >> 16) & 0xff;
	dregs->dma_addr2 = (addr >>  8) & 0xff;
	dregs->dma_addr3 = (addr      ) & 0xff;
}

static void dma_ints_off(struct NCR_ESP *esp)
{
	disable_irq(esp->irq);
}

static void dma_ints_on(struct NCR_ESP *esp)
{
	enable_irq(esp->irq);
}

static int dma_irq_p(struct NCR_ESP *esp)
{
	/* It's important to check the DMA IRQ bit in the correct way! */
	return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
}

static void dma_led_off(struct NCR_ESP *esp)
{
	((struct cyberII_dma_registers *)(esp->dregs))->ctrl_reg &= ~CYBERII_DMA_LED;
}

static void dma_led_on(struct NCR_ESP *esp)
{
	((struct cyberII_dma_registers *)(esp->dregs))->ctrl_reg |= CYBERII_DMA_LED;
}

static int dma_ports_p(struct NCR_ESP *esp)
{
	return ((amiga_custom.intenar) & IF_PORTS);
}

static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
{
	/* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
	 * so when (write) is true, it actually means READ!
	 */
	if(write){
		dma_init_read(esp, addr, count);
	} else {
		dma_init_write(esp, addr, count);
	}
}

#define HOSTS_C

int cyberII_esp_release(struct Scsi_Host *instance)
{
#ifdef MODULE
	unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;

	esp_deallocate((struct NCR_ESP *)instance->hostdata); 
	esp_release();
	release_mem_region(address, sizeof(struct ESP_regs));
	free_irq(IRQ_AMIGA_PORTS, esp_intr);
#endif
	return 1;
}


static struct scsi_host_template driver_template = {
	.proc_name		= "esp-cyberstormII",
	.proc_info		= esp_proc_info,
	.name			= "CyberStorm Mk II SCSI",
	.detect			= cyberII_esp_detect,
	.slave_alloc		= esp_slave_alloc,
	.slave_destroy		= esp_slave_destroy,
	.release		= cyberII_esp_release,
	.queuecommand		= esp_queue,
	.eh_abort_handler	= esp_abort,
	.eh_bus_reset_handler	= esp_reset,
	.can_queue		= 7,
	.this_id		= 7,
	.sg_tablesize		= SG_ALL,
	.cmd_per_lun		= 1,
	.use_clustering		= ENABLE_CLUSTERING
};


#include "scsi_module.c"

MODULE_LICENSE("GPL");
Commit	Line	Data
1da177e4 LT	1	/* cyberstormII.c: Driver for CyberStorm SCSI Mk II
	2	*
	3	* Copyright (C) 1996 Jesper Skov (jskov@cygnus.co.uk)
	4	*
	5	* This driver is based on cyberstorm.c
	6	*/
	7
	8	/* TODO:
	9	*
	10	* 1) Figure out how to make a cleaner merge with the sparc driver with regard
	11	* to the caches and the Sparc MMU mapping.
	12	* 2) Make as few routines required outside the generic driver. A lot of the
	13	* routines in this file used to be inline!
	14	*/
	15
	16	#include <linux/module.h>
	17
	18	#include <linux/init.h>
	19	#include <linux/kernel.h>
	20	#include <linux/delay.h>
	21	#include <linux/types.h>
	22	#include <linux/string.h>
	23	#include <linux/slab.h>
	24	#include <linux/blkdev.h>
	25	#include <linux/proc_fs.h>
	26	#include <linux/stat.h>
	27	#include <linux/interrupt.h>
	28
	29	#include "scsi.h"
	30	#include <scsi/scsi_host.h>
	31	#include "NCR53C9x.h"
	32
	33	#include <linux/zorro.h>
	34	#include <asm/irq.h>
	35	#include <asm/amigaints.h>
	36	#include <asm/amigahw.h>
	37
	38	#include <asm/pgtable.h>
	39
	40	/* The controller registers can be found in the Z2 config area at these
	41	* offsets:
	42	*/
	43	#define CYBERII_ESP_ADDR 0x1ff03
	44	#define CYBERII_DMA_ADDR 0x1ff43
	45
	46
	47	/* The CyberStorm II DMA interface */
	48	struct cyberII_dma_registers {
	49	volatile unsigned char cond_reg; /* DMA cond (ro) [0x000] */
	50	#define ctrl_reg cond_reg /* DMA control (wo) [0x000] */
	51	unsigned char dmapad4[0x3f];
	52	volatile unsigned char dma_addr0; /* DMA address (MSB) [0x040] */
	53	unsigned char dmapad1[3];
	54	volatile unsigned char dma_addr1; /* DMA address [0x044] */
	55	unsigned char dmapad2[3];
	56	volatile unsigned char dma_addr2; /* DMA address [0x048] */
	57	unsigned char dmapad3[3];
	58	volatile unsigned char dma_addr3; /* DMA address (LSB) [0x04c] */
	59	};
	60
	61	/* DMA control bits */
	62	#define CYBERII_DMA_LED 0x02 /* HD led control 1 = on */
	63
	64	static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count);
65	static int dma_can_transfer(struct NCR_ESP esp, Scsi_Cmnd sp);
66	static void dma_dump_state(struct NCR_ESP *esp);
67	static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length);
68	static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length);
69	static void dma_ints_off(struct NCR_ESP *esp);
70	static void dma_ints_on(struct NCR_ESP *esp);
71	static int dma_irq_p(struct NCR_ESP *esp);
72	static void dma_led_off(struct NCR_ESP *esp);
73	static void dma_led_on(struct NCR_ESP *esp);
74	static int dma_ports_p(struct NCR_ESP *esp);
75	static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write);
76
77	static volatile unsigned char cmd_buffer[16];
78	/* This is where all commands are put
79	* before they are transferred to the ESP chip
80	* via PIO.
81	*/
82
83	/***************************************************************** Detection */
d0be4a7d	84	int __init cyberII_esp_detect(struct scsi_host_template *tpnt)
1da177e4 LT	85	{
	86	struct NCR_ESP *esp;
	87	struct zorro_dev *z = NULL;
	88	unsigned long address;
	89	struct ESP_regs *eregs;
	90
	91	if ((z = zorro_find_device(ZORRO_PROD_PHASE5_CYBERSTORM_MK_II, z))) {
	92	unsigned long board = z->resource.start;
	93	if (request_mem_region(board+CYBERII_ESP_ADDR,
	94	sizeof(struct ESP_regs), "NCR53C9x")) {
	95	/* Do some magic to figure out if the CyberStorm Mk II
	96	* is equipped with a SCSI controller
	97	*/
	98	address = (unsigned long)ZTWO_VADDR(board);
	99	eregs = (struct ESP_regs *)(address + CYBERII_ESP_ADDR);
	100
4df4db5c	101	esp = esp_allocate(tpnt, (void *)board + CYBERII_ESP_ADDR, 0);
1da177e4 LT	102
	103	esp_write(eregs->esp_cfg1, (ESP_CONFIG1_PENABLE \| 7));
	104	udelay(5);
	105	if(esp_read(eregs->esp_cfg1) != (ESP_CONFIG1_PENABLE \| 7)) {
	106	esp_deallocate(esp);
	107	scsi_unregister(esp->ehost);
	108	release_mem_region(board+CYBERII_ESP_ADDR,
	109	sizeof(struct ESP_regs));
	110	return 0; /* Bail out if address did not hold data */
	111	}
	112
	113	/* Do command transfer with programmed I/O */
	114	esp->do_pio_cmds = 1;
	115
	116	/* Required functions */
	117	esp->dma_bytes_sent = &dma_bytes_sent;
	118	esp->dma_can_transfer = &dma_can_transfer;
	119	esp->dma_dump_state = &dma_dump_state;
	120	esp->dma_init_read = &dma_init_read;
	121	esp->dma_init_write = &dma_init_write;
	122	esp->dma_ints_off = &dma_ints_off;
	123	esp->dma_ints_on = &dma_ints_on;
	124	esp->dma_irq_p = &dma_irq_p;
	125	esp->dma_ports_p = &dma_ports_p;
	126	esp->dma_setup = &dma_setup;
	127
	128	/* Optional functions */
	129	esp->dma_barrier = 0;
	130	esp->dma_drain = 0;
	131	esp->dma_invalidate = 0;
	132	esp->dma_irq_entry = 0;
	133	esp->dma_irq_exit = 0;
	134	esp->dma_led_on = &dma_led_on;
	135	esp->dma_led_off = &dma_led_off;
	136	esp->dma_poll = 0;
	137	esp->dma_reset = 0;
	138
	139	/* SCSI chip speed */
	140	esp->cfreq = 40000000;
	141
	142	/* The DMA registers on the CyberStorm are mapped
	143	* relative to the device (i.e. in the same Zorro
	144	* I/O block).
	145	*/
	146	esp->dregs = (void *)(address + CYBERII_DMA_ADDR);
	147
	148	/* ESP register base */
	149	esp->eregs = eregs;
	150
	151	/* Set the command buffer */
	152	esp->esp_command = cmd_buffer;
	153	esp->esp_command_dvma = virt_to_bus((void *)cmd_buffer);
	154
	155	esp->irq = IRQ_AMIGA_PORTS;
1d6f359a	156	request_irq(IRQ_AMIGA_PORTS, esp_intr, IRQF_SHARED,
1da177e4 LT	157	"CyberStorm SCSI Mk II", esp->ehost);
	158
	159	/* Figure out our scsi ID on the bus */
	160	esp->scsi_id = 7;
	161
	162	/* We don't have a differential SCSI-bus. */
	163	esp->diff = 0;
	164
	165	esp_initialize(esp);
	166
	167	printk("ESP: Total of %d ESP hosts found, %d actually in use.\n", nesps, esps_in_use);
	168	esps_running = esps_in_use;
	169	return esps_in_use;
	170	}
	171	}
	172	return 0;
	173	}
	174
	175	/************************************************************* DMA Functions */
	176	static int dma_bytes_sent(struct NCR_ESP *esp, int fifo_count)
	177	{
	178	/* Since the CyberStorm DMA is fully dedicated to the ESP chip,
	179	* the number of bytes sent (to the ESP chip) equals the number
	180	* of bytes in the FIFO - there is no buffering in the DMA controller.
	181	* XXXX Do I read this right? It is from host to ESP, right?
	182	*/
	183	return fifo_count;
	184	}
	185
	186	static int dma_can_transfer(struct NCR_ESP esp, Scsi_Cmnd sp)
	187	{
	188	/* I don't think there's any limit on the CyberDMA. So we use what
	189	* the ESP chip can handle (24 bit).
	190	*/
	191	unsigned long sz = sp->SCp.this_residual;
	192	if(sz > 0x1000000)
	193	sz = 0x1000000;
	194	return sz;
	195	}
	196
	197	static void dma_dump_state(struct NCR_ESP *esp)
	198	{
	199	ESPLOG(("esp%d: dma -- cond_reg<%02x>\n",
	200	esp->esp_id, ((struct cyberII_dma_registers *)
	201	(esp->dregs))->cond_reg));
	202	ESPLOG(("intreq:<%04x>, intena:<%04x>\n",
b4290a23	203	amiga_custom.intreqr, amiga_custom.intenar));
1da177e4 LT	204	}
	205
	206	static void dma_init_read(struct NCR_ESP *esp, __u32 addr, int length)
	207	{
	208	struct cyberII_dma_registers *dregs =
	209	(struct cyberII_dma_registers *) esp->dregs;
	210
	211	cache_clear(addr, length);
	212
	213	addr &= ~(1);
	214	dregs->dma_addr0 = (addr >> 24) & 0xff;
	215	dregs->dma_addr1 = (addr >> 16) & 0xff;
	216	dregs->dma_addr2 = (addr >> 8) & 0xff;
	217	dregs->dma_addr3 = (addr ) & 0xff;
	218	}
	219
	220	static void dma_init_write(struct NCR_ESP *esp, __u32 addr, int length)
	221	{
	222	struct cyberII_dma_registers *dregs =
	223	(struct cyberII_dma_registers *) esp->dregs;
	224
	225	cache_push(addr, length);
	226
	227	addr \|= 1;
	228	dregs->dma_addr0 = (addr >> 24) & 0xff;
	229	dregs->dma_addr1 = (addr >> 16) & 0xff;
	230	dregs->dma_addr2 = (addr >> 8) & 0xff;
	231	dregs->dma_addr3 = (addr ) & 0xff;
	232	}
	233
	234	static void dma_ints_off(struct NCR_ESP *esp)
	235	{
	236	disable_irq(esp->irq);
	237	}
	238
	239	static void dma_ints_on(struct NCR_ESP *esp)
	240	{
	241	enable_irq(esp->irq);
	242	}
	243
	244	static int dma_irq_p(struct NCR_ESP *esp)
	245	{
	246	/* It's important to check the DMA IRQ bit in the correct way! */
	247	return (esp_read(esp->eregs->esp_status) & ESP_STAT_INTR);
	248	}
	249
	250	static void dma_led_off(struct NCR_ESP *esp)
	251	{
	252	((struct cyberII_dma_registers *)(esp->dregs))->ctrl_reg &= ~CYBERII_DMA_LED;
	253	}
	254
	255	static void dma_led_on(struct NCR_ESP *esp)
	256	{
	257	((struct cyberII_dma_registers *)(esp->dregs))->ctrl_reg \|= CYBERII_DMA_LED;
	258	}
	259
	260	static int dma_ports_p(struct NCR_ESP *esp)
	261	{
b4290a23	262	return ((amiga_custom.intenar) & IF_PORTS);
1da177e4 LT	263	}
	264
	265	static void dma_setup(struct NCR_ESP *esp, __u32 addr, int count, int write)
	266	{
	267	/* On the Sparc, DMA_ST_WRITE means "move data from device to memory"
	268	* so when (write) is true, it actually means READ!
	269	*/
	270	if(write){
	271	dma_init_read(esp, addr, count);
	272	} else {
	273	dma_init_write(esp, addr, count);
	274	}
	275	}
	276
	277	#define HOSTS_C
	278
	279	int cyberII_esp_release(struct Scsi_Host *instance)
	280	{
	281	#ifdef MODULE
	282	unsigned long address = (unsigned long)((struct NCR_ESP *)instance->hostdata)->edev;
	283
	284	esp_deallocate((struct NCR_ESP *)instance->hostdata);
	285	esp_release();
	286	release_mem_region(address, sizeof(struct ESP_regs));
	287	free_irq(IRQ_AMIGA_PORTS, esp_intr);
	288	#endif
	289	return 1;
	290	}
	291
	292
d0be4a7d	293	static struct scsi_host_template driver_template = {
1da177e4 LT	294	.proc_name = "esp-cyberstormII",
	295	.proc_info = esp_proc_info,
	296	.name = "CyberStorm Mk II SCSI",
	297	.detect = cyberII_esp_detect,
	298	.slave_alloc = esp_slave_alloc,
	299	.slave_destroy = esp_slave_destroy,
	300	.release = cyberII_esp_release,
	301	.queuecommand = esp_queue,
	302	.eh_abort_handler = esp_abort,
	303	.eh_bus_reset_handler = esp_reset,
	304	.can_queue = 7,
	305	.this_id = 7,
	306	.sg_tablesize = SG_ALL,
	307	.cmd_per_lun = 1,
	308	.use_clustering = ENABLE_CLUSTERING
	309	};
	310
	311
	312	#include "scsi_module.c"
	313
	314	MODULE_LICENSE("GPL");